1/*
  2 * Rockchip timer support
  3 *
  4 * Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 */
 10#include <linux/clk.h>
 11#include <linux/clockchips.h>
 12#include <linux/init.h>
 13#include <linux/interrupt.h>
 14#include <linux/of.h>
 15#include <linux/of_address.h>
 16#include <linux/of_irq.h>
 17
 18#define TIMER_NAME "rk_timer"
 19
 20#define TIMER_LOAD_COUNT0	0x00
 21#define TIMER_LOAD_COUNT1	0x04
 22#define TIMER_CONTROL_REG3288	0x10
 23#define TIMER_CONTROL_REG3399	0x1c
 24#define TIMER_INT_STATUS	0x18
 25
 26#define TIMER_DISABLE		0x0
 27#define TIMER_ENABLE		0x1
 28#define TIMER_MODE_FREE_RUNNING			(0 << 1)
 29#define TIMER_MODE_USER_DEFINED_COUNT		(1 << 1)
 30#define TIMER_INT_UNMASK			(1 << 2)
 31
 32struct bc_timer {
 33	struct clock_event_device ce;
 34	void __iomem *base;
 35	void __iomem *ctrl;
 36	u32 freq;
 37};
 38
 39static struct bc_timer bc_timer;
 40
 41static inline struct bc_timer *rk_timer(struct clock_event_device *ce)
 42{
 43	return container_of(ce, struct bc_timer, ce);
 44}
 45
 46static inline void __iomem *rk_base(struct clock_event_device *ce)
 47{
 48	return rk_timer(ce)->base;
 49}
 50
 51static inline void __iomem *rk_ctrl(struct clock_event_device *ce)
 52{
 53	return rk_timer(ce)->ctrl;
 54}
 55
 56static inline void rk_timer_disable(struct clock_event_device *ce)
 57{
 58	writel_relaxed(TIMER_DISABLE, rk_ctrl(ce));
 59}
 60
 61static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
 62{
 63	writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
 64		       rk_ctrl(ce));
 65}
 66
 67static void rk_timer_update_counter(unsigned long cycles,
 68				    struct clock_event_device *ce)
 69{
 70	writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
 71	writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
 72}
 73
 74static void rk_timer_interrupt_clear(struct clock_event_device *ce)
 75{
 76	writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
 77}
 78
 79static inline int rk_timer_set_next_event(unsigned long cycles,
 80					  struct clock_event_device *ce)
 81{
 82	rk_timer_disable(ce);
 83	rk_timer_update_counter(cycles, ce);
 84	rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
 85	return 0;
 86}
 87
 88static int rk_timer_shutdown(struct clock_event_device *ce)
 89{
 90	rk_timer_disable(ce);
 91	return 0;
 92}
 93
 94static int rk_timer_set_periodic(struct clock_event_device *ce)
 95{
 96	rk_timer_disable(ce);
 97	rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
 98	rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING);
 99	return 0;
100}
101
102static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
103{
104	struct clock_event_device *ce = dev_id;
105
106	rk_timer_interrupt_clear(ce);
107
108	if (clockevent_state_oneshot(ce))
109		rk_timer_disable(ce);
110
111	ce->event_handler(ce);
112
113	return IRQ_HANDLED;
114}
115
116static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
117{
118	struct clock_event_device *ce = &bc_timer.ce;
119	struct clk *timer_clk;
120	struct clk *pclk;
121	int ret = -EINVAL, irq;
122
123	bc_timer.base = of_iomap(np, 0);
124	if (!bc_timer.base) {
125		pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
126		return -ENXIO;
127	}
128	bc_timer.ctrl = bc_timer.base + ctrl_reg;
129
130	pclk = of_clk_get_by_name(np, "pclk");
131	if (IS_ERR(pclk)) {
132		ret = PTR_ERR(pclk);
133		pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
134		goto out_unmap;
135	}
136
137	ret = clk_prepare_enable(pclk);
138	if (ret) {
139		pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
140		goto out_unmap;
141	}
142
143	timer_clk = of_clk_get_by_name(np, "timer");
144	if (IS_ERR(timer_clk)) {
145		ret = PTR_ERR(timer_clk);
146		pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
147		goto out_timer_clk;
148	}
149
150	ret = clk_prepare_enable(timer_clk);
151	if (ret) {
152		pr_err("Failed to enable timer clock\n");
153		goto out_timer_clk;
154	}
155
156	bc_timer.freq = clk_get_rate(timer_clk);
157
158	irq = irq_of_parse_and_map(np, 0);
159	if (!irq) {
160		ret = -EINVAL;
161		pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
162		goto out_irq;
163	}
164
165	ce->name = TIMER_NAME;
166	ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
167		       CLOCK_EVT_FEAT_DYNIRQ;
168	ce->set_next_event = rk_timer_set_next_event;
169	ce->set_state_shutdown = rk_timer_shutdown;
170	ce->set_state_periodic = rk_timer_set_periodic;
171	ce->irq = irq;
172	ce->cpumask = cpu_possible_mask;
173	ce->rating = 250;
174
175	rk_timer_interrupt_clear(ce);
176	rk_timer_disable(ce);
177
178	ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
179	if (ret) {
180		pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
181		goto out_irq;
182	}
183
184	clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
185
186	return 0;
187
188out_irq:
189	clk_disable_unprepare(timer_clk);
190out_timer_clk:
191	clk_disable_unprepare(pclk);
192out_unmap:
193	iounmap(bc_timer.base);
194
195	return ret;
196}
197
198static int __init rk3288_timer_init(struct device_node *np)
199{
200	return rk_timer_init(np, TIMER_CONTROL_REG3288);
201}
202
203static int __init rk3399_timer_init(struct device_node *np)
204{
205	return rk_timer_init(np, TIMER_CONTROL_REG3399);
206}
207
208CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer",
209		       rk3288_timer_init);
210CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer",
211		       rk3399_timer_init);