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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Low-level direct PCI config space access via ECAM - common code between
4 * i386 and x86-64.
5 *
6 * This code does:
7 * - known chipset handling
8 * - ACPI decoding and validation
9 *
10 * Per-architecture code takes care of the mappings and accesses
11 * themselves.
12 */
13
14#define pr_fmt(fmt) "PCI: " fmt
15
16#include <linux/acpi.h>
17#include <linux/efi.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/bitmap.h>
21#include <linux/dmi.h>
22#include <linux/slab.h>
23#include <linux/mutex.h>
24#include <linux/rculist.h>
25#include <asm/e820/api.h>
26#include <asm/pci_x86.h>
27#include <asm/acpi.h>
28
29/* Indicate if the ECAM resources have been placed into the resource table */
30static bool pci_mmcfg_running_state;
31static bool pci_mmcfg_arch_init_failed;
32static DEFINE_MUTEX(pci_mmcfg_lock);
33#define pci_mmcfg_lock_held() lock_is_held(&(pci_mmcfg_lock).dep_map)
34
35LIST_HEAD(pci_mmcfg_list);
36
37static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
38{
39 if (cfg->res.parent)
40 release_resource(&cfg->res);
41 list_del(&cfg->list);
42 kfree(cfg);
43}
44
45static void __init free_all_mmcfg(void)
46{
47 struct pci_mmcfg_region *cfg, *tmp;
48
49 pci_mmcfg_arch_free();
50 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
51 pci_mmconfig_remove(cfg);
52}
53
54static void list_add_sorted(struct pci_mmcfg_region *new)
55{
56 struct pci_mmcfg_region *cfg;
57
58 /* keep list sorted by segment and starting bus number */
59 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) {
60 if (cfg->segment > new->segment ||
61 (cfg->segment == new->segment &&
62 cfg->start_bus >= new->start_bus)) {
63 list_add_tail_rcu(&new->list, &cfg->list);
64 return;
65 }
66 }
67 list_add_tail_rcu(&new->list, &pci_mmcfg_list);
68}
69
70static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
71 int end, u64 addr)
72{
73 struct pci_mmcfg_region *new;
74 struct resource *res;
75
76 if (addr == 0)
77 return NULL;
78
79 new = kzalloc(sizeof(*new), GFP_KERNEL);
80 if (!new)
81 return NULL;
82
83 new->address = addr;
84 new->segment = segment;
85 new->start_bus = start;
86 new->end_bus = end;
87
88 res = &new->res;
89 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
90 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
91 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
92 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
93 "PCI ECAM %04x [bus %02x-%02x]", segment, start, end);
94 res->name = new->name;
95
96 return new;
97}
98
99struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
100 int end, u64 addr)
101{
102 struct pci_mmcfg_region *new;
103
104 new = pci_mmconfig_alloc(segment, start, end, addr);
105 if (!new)
106 return NULL;
107
108 mutex_lock(&pci_mmcfg_lock);
109 list_add_sorted(new);
110 mutex_unlock(&pci_mmcfg_lock);
111
112 pr_info("ECAM %pR (base %#lx) for domain %04x [bus %02x-%02x]\n",
113 &new->res, (unsigned long)addr, segment, start, end);
114
115 return new;
116}
117
118struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
119{
120 struct pci_mmcfg_region *cfg;
121
122 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held())
123 if (cfg->segment == segment &&
124 cfg->start_bus <= bus && bus <= cfg->end_bus)
125 return cfg;
126
127 return NULL;
128}
129
130static const char *__init pci_mmcfg_e7520(void)
131{
132 u32 win;
133 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
134
135 win = win & 0xf000;
136 if (win == 0x0000 || win == 0xf000)
137 return NULL;
138
139 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
140 return NULL;
141
142 return "Intel Corporation E7520 Memory Controller Hub";
143}
144
145static const char *__init pci_mmcfg_intel_945(void)
146{
147 u32 pciexbar, mask = 0, len = 0;
148
149 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
150
151 /* Enable bit */
152 if (!(pciexbar & 1))
153 return NULL;
154
155 /* Size bits */
156 switch ((pciexbar >> 1) & 3) {
157 case 0:
158 mask = 0xf0000000U;
159 len = 0x10000000U;
160 break;
161 case 1:
162 mask = 0xf8000000U;
163 len = 0x08000000U;
164 break;
165 case 2:
166 mask = 0xfc000000U;
167 len = 0x04000000U;
168 break;
169 default:
170 return NULL;
171 }
172
173 /* Errata #2, things break when not aligned on a 256Mb boundary */
174 /* Can only happen in 64M/128M mode */
175
176 if ((pciexbar & mask) & 0x0fffffffU)
177 return NULL;
178
179 /* Don't hit the APIC registers and their friends */
180 if ((pciexbar & mask) >= 0xf0000000U)
181 return NULL;
182
183 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
184 return NULL;
185
186 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
187}
188
189static const char *__init pci_mmcfg_amd_fam10h(void)
190{
191 u32 low, high, address;
192 u64 base, msr;
193 int i;
194 unsigned segnbits = 0, busnbits, end_bus;
195
196 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
197 return NULL;
198
199 address = MSR_FAM10H_MMIO_CONF_BASE;
200 if (rdmsr_safe(address, &low, &high))
201 return NULL;
202
203 msr = high;
204 msr <<= 32;
205 msr |= low;
206
207 /* ECAM is not enabled */
208 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
209 return NULL;
210
211 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
212
213 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
214 FAM10H_MMIO_CONF_BUSRANGE_MASK;
215
216 /*
217 * only handle bus 0 ?
218 * need to skip it
219 */
220 if (!busnbits)
221 return NULL;
222
223 if (busnbits > 8) {
224 segnbits = busnbits - 8;
225 busnbits = 8;
226 }
227
228 end_bus = (1 << busnbits) - 1;
229 for (i = 0; i < (1 << segnbits); i++)
230 if (pci_mmconfig_add(i, 0, end_bus,
231 base + (1<<28) * i) == NULL) {
232 free_all_mmcfg();
233 return NULL;
234 }
235
236 return "AMD Family 10h NB";
237}
238
239static bool __initdata mcp55_checked;
240static const char *__init pci_mmcfg_nvidia_mcp55(void)
241{
242 int bus;
243 int mcp55_mmconf_found = 0;
244
245 static const u32 extcfg_regnum __initconst = 0x90;
246 static const u32 extcfg_regsize __initconst = 4;
247 static const u32 extcfg_enable_mask __initconst = 1 << 31;
248 static const u32 extcfg_start_mask __initconst = 0xff << 16;
249 static const int extcfg_start_shift __initconst = 16;
250 static const u32 extcfg_size_mask __initconst = 0x3 << 28;
251 static const int extcfg_size_shift __initconst = 28;
252 static const int extcfg_sizebus[] __initconst = {
253 0x100, 0x80, 0x40, 0x20
254 };
255 static const u32 extcfg_base_mask[] __initconst = {
256 0x7ff8, 0x7ffc, 0x7ffe, 0x7fff
257 };
258 static const int extcfg_base_lshift __initconst = 25;
259
260 /*
261 * do check if amd fam10h already took over
262 */
263 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
264 return NULL;
265
266 mcp55_checked = true;
267 for (bus = 0; bus < 256; bus++) {
268 u64 base;
269 u32 l, extcfg;
270 u16 vendor, device;
271 int start, size_index, end;
272
273 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
274 vendor = l & 0xffff;
275 device = (l >> 16) & 0xffff;
276
277 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
278 continue;
279
280 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
281 extcfg_regsize, &extcfg);
282
283 if (!(extcfg & extcfg_enable_mask))
284 continue;
285
286 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
287 base = extcfg & extcfg_base_mask[size_index];
288 /* base could > 4G */
289 base <<= extcfg_base_lshift;
290 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
291 end = start + extcfg_sizebus[size_index] - 1;
292 if (pci_mmconfig_add(0, start, end, base) == NULL)
293 continue;
294 mcp55_mmconf_found++;
295 }
296
297 if (!mcp55_mmconf_found)
298 return NULL;
299
300 return "nVidia MCP55";
301}
302
303struct pci_mmcfg_hostbridge_probe {
304 u32 bus;
305 u32 devfn;
306 u32 vendor;
307 u32 device;
308 const char *(*probe)(void);
309};
310
311static const struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initconst = {
312 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
313 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
314 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
315 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
316 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
317 0x1200, pci_mmcfg_amd_fam10h },
318 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
319 0x1200, pci_mmcfg_amd_fam10h },
320 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
321 0x0369, pci_mmcfg_nvidia_mcp55 },
322};
323
324static void __init pci_mmcfg_check_end_bus_number(void)
325{
326 struct pci_mmcfg_region *cfg, *cfgx;
327
328 /* Fixup overlaps */
329 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
330 if (cfg->end_bus < cfg->start_bus)
331 cfg->end_bus = 255;
332
333 /* Don't access the list head ! */
334 if (cfg->list.next == &pci_mmcfg_list)
335 break;
336
337 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
338 if (cfg->end_bus >= cfgx->start_bus)
339 cfg->end_bus = cfgx->start_bus - 1;
340 }
341}
342
343static int __init pci_mmcfg_check_hostbridge(void)
344{
345 u32 l;
346 u32 bus, devfn;
347 u16 vendor, device;
348 int i;
349 const char *name;
350
351 if (!raw_pci_ops)
352 return 0;
353
354 free_all_mmcfg();
355
356 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
357 bus = pci_mmcfg_probes[i].bus;
358 devfn = pci_mmcfg_probes[i].devfn;
359 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
360 vendor = l & 0xffff;
361 device = (l >> 16) & 0xffff;
362
363 name = NULL;
364 if (pci_mmcfg_probes[i].vendor == vendor &&
365 pci_mmcfg_probes[i].device == device)
366 name = pci_mmcfg_probes[i].probe();
367
368 if (name)
369 pr_info("%s with ECAM support\n", name);
370 }
371
372 /* some end_bus_number is crazy, fix it */
373 pci_mmcfg_check_end_bus_number();
374
375 return !list_empty(&pci_mmcfg_list);
376}
377
378static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data)
379{
380 struct resource *mcfg_res = data;
381 struct acpi_resource_address64 address;
382 acpi_status status;
383
384 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
385 struct acpi_resource_fixed_memory32 *fixmem32 =
386 &res->data.fixed_memory32;
387 if (!fixmem32)
388 return AE_OK;
389 if ((mcfg_res->start >= fixmem32->address) &&
390 (mcfg_res->end < (fixmem32->address +
391 fixmem32->address_length))) {
392 mcfg_res->flags = 1;
393 return AE_CTRL_TERMINATE;
394 }
395 }
396 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
397 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
398 return AE_OK;
399
400 status = acpi_resource_to_address64(res, &address);
401 if (ACPI_FAILURE(status) ||
402 (address.address.address_length <= 0) ||
403 (address.resource_type != ACPI_MEMORY_RANGE))
404 return AE_OK;
405
406 if ((mcfg_res->start >= address.address.minimum) &&
407 (mcfg_res->end < (address.address.minimum + address.address.address_length))) {
408 mcfg_res->flags = 1;
409 return AE_CTRL_TERMINATE;
410 }
411 return AE_OK;
412}
413
414static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl,
415 void *context, void **rv)
416{
417 struct resource *mcfg_res = context;
418
419 acpi_walk_resources(handle, METHOD_NAME__CRS,
420 check_mcfg_resource, context);
421
422 if (mcfg_res->flags)
423 return AE_CTRL_TERMINATE;
424
425 return AE_OK;
426}
427
428static bool is_acpi_reserved(u64 start, u64 end, enum e820_type not_used)
429{
430 struct resource mcfg_res;
431
432 mcfg_res.start = start;
433 mcfg_res.end = end - 1;
434 mcfg_res.flags = 0;
435
436 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
437
438 if (!mcfg_res.flags)
439 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
440 NULL);
441
442 return mcfg_res.flags;
443}
444
445static bool is_efi_mmio(struct resource *res)
446{
447#ifdef CONFIG_EFI
448 u64 start = res->start;
449 u64 end = res->start + resource_size(res);
450 efi_memory_desc_t *md;
451 u64 size, mmio_start, mmio_end;
452
453 for_each_efi_memory_desc(md) {
454 if (md->type == EFI_MEMORY_MAPPED_IO) {
455 size = md->num_pages << EFI_PAGE_SHIFT;
456 mmio_start = md->phys_addr;
457 mmio_end = mmio_start + size;
458
459 if (mmio_start <= start && end <= mmio_end)
460 return true;
461 }
462 }
463#endif
464
465 return false;
466}
467
468typedef bool (*check_reserved_t)(u64 start, u64 end, enum e820_type type);
469
470static bool __ref is_mmconf_reserved(check_reserved_t is_reserved,
471 struct pci_mmcfg_region *cfg,
472 struct device *dev, const char *method)
473{
474 u64 addr = cfg->res.start;
475 u64 size = resource_size(&cfg->res);
476 u64 old_size = size;
477 int num_buses;
478
479 while (!is_reserved(addr, addr + size, E820_TYPE_RESERVED)) {
480 size >>= 1;
481 if (size < (16UL<<20))
482 break;
483 }
484
485 if (size < (16UL<<20) && size != old_size)
486 return false;
487
488 if (dev)
489 dev_info(dev, "ECAM %pR reserved as %s\n",
490 &cfg->res, method);
491 else
492 pr_info("ECAM %pR reserved as %s\n", &cfg->res, method);
493
494 if (old_size != size) {
495 /* update end_bus */
496 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
497 num_buses = cfg->end_bus - cfg->start_bus + 1;
498 cfg->res.end = cfg->res.start +
499 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
500 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
501 "PCI ECAM %04x [bus %02x-%02x]",
502 cfg->segment, cfg->start_bus, cfg->end_bus);
503
504 if (dev)
505 dev_info(dev, "ECAM %pR (base %#lx) (size reduced!)\n",
506 &cfg->res, (unsigned long) cfg->address);
507 else
508 pr_info("ECAM %pR (base %#lx) for %04x [bus%02x-%02x] (size reduced!)\n",
509 &cfg->res, (unsigned long) cfg->address,
510 cfg->segment, cfg->start_bus, cfg->end_bus);
511 }
512
513 return true;
514}
515
516static bool __ref pci_mmcfg_reserved(struct device *dev,
517 struct pci_mmcfg_region *cfg, int early)
518{
519 struct resource *conflict;
520
521 if (!early && !acpi_disabled) {
522 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev,
523 "ACPI motherboard resource"))
524 return true;
525
526 if (dev)
527 dev_info(dev, FW_INFO "ECAM %pR not reserved in ACPI motherboard resources\n",
528 &cfg->res);
529 else
530 pr_info(FW_INFO "ECAM %pR not reserved in ACPI motherboard resources\n",
531 &cfg->res);
532
533 if (is_efi_mmio(&cfg->res)) {
534 pr_info("ECAM %pR is EfiMemoryMappedIO; assuming valid\n",
535 &cfg->res);
536 conflict = insert_resource_conflict(&iomem_resource,
537 &cfg->res);
538 if (conflict)
539 pr_warn("ECAM %pR conflicts with %s %pR\n",
540 &cfg->res, conflict->name, conflict);
541 else
542 pr_info("ECAM %pR reserved to work around lack of ACPI motherboard _CRS\n",
543 &cfg->res);
544 return true;
545 }
546 }
547
548 /*
549 * e820__mapped_all() is marked as __init.
550 * All entries from ACPI MCFG table have been checked at boot time.
551 * For MCFG information constructed from hotpluggable host bridge's
552 * _CBA method, just assume it's reserved.
553 */
554 if (pci_mmcfg_running_state)
555 return true;
556
557 /* Don't try to do this check unless configuration
558 type 1 is available. how about type 2 ?*/
559 if (raw_pci_ops)
560 return is_mmconf_reserved(e820__mapped_all, cfg, dev,
561 "E820 entry");
562
563 return false;
564}
565
566static void __init pci_mmcfg_reject_broken(int early)
567{
568 struct pci_mmcfg_region *cfg;
569
570 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
571 if (!pci_mmcfg_reserved(NULL, cfg, early)) {
572 pr_info("not using ECAM (%pR not reserved)\n",
573 &cfg->res);
574 free_all_mmcfg();
575 return;
576 }
577 }
578}
579
580static bool __init acpi_mcfg_valid_entry(struct acpi_table_mcfg *mcfg,
581 struct acpi_mcfg_allocation *cfg)
582{
583 if (cfg->address < 0xFFFFFFFF)
584 return true;
585
586 if (!strncmp(mcfg->header.oem_id, "SGI", 3))
587 return true;
588
589 if ((mcfg->header.revision >= 1) && (dmi_get_bios_year() >= 2010))
590 return true;
591
592 pr_err("ECAM at %#llx for %04x [bus %02x-%02x] is above 4GB, ignored\n",
593 cfg->address, cfg->pci_segment, cfg->start_bus_number,
594 cfg->end_bus_number);
595 return false;
596}
597
598static int __init pci_parse_mcfg(struct acpi_table_header *header)
599{
600 struct acpi_table_mcfg *mcfg;
601 struct acpi_mcfg_allocation *cfg_table, *cfg;
602 unsigned long i;
603 int entries;
604
605 if (!header)
606 return -EINVAL;
607
608 mcfg = (struct acpi_table_mcfg *)header;
609
610 /* how many config structures do we have */
611 free_all_mmcfg();
612 entries = 0;
613 i = header->length - sizeof(struct acpi_table_mcfg);
614 while (i >= sizeof(struct acpi_mcfg_allocation)) {
615 entries++;
616 i -= sizeof(struct acpi_mcfg_allocation);
617 }
618 if (entries == 0) {
619 pr_err("MCFG has no entries\n");
620 return -ENODEV;
621 }
622
623 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
624 for (i = 0; i < entries; i++) {
625 cfg = &cfg_table[i];
626 if (!acpi_mcfg_valid_entry(mcfg, cfg)) {
627 free_all_mmcfg();
628 return -ENODEV;
629 }
630
631 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
632 cfg->end_bus_number, cfg->address) == NULL) {
633 pr_warn("no memory for MCFG entries\n");
634 free_all_mmcfg();
635 return -ENOMEM;
636 }
637 }
638
639 return 0;
640}
641
642#ifdef CONFIG_ACPI_APEI
643extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size,
644 void *data), void *data);
645
646static int pci_mmcfg_for_each_region(int (*func)(__u64 start, __u64 size,
647 void *data), void *data)
648{
649 struct pci_mmcfg_region *cfg;
650 int rc;
651
652 if (list_empty(&pci_mmcfg_list))
653 return 0;
654
655 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
656 rc = func(cfg->res.start, resource_size(&cfg->res), data);
657 if (rc)
658 return rc;
659 }
660
661 return 0;
662}
663#define set_apei_filter() (arch_apei_filter_addr = pci_mmcfg_for_each_region)
664#else
665#define set_apei_filter()
666#endif
667
668static void __init __pci_mmcfg_init(int early)
669{
670 pr_debug("%s(%s)\n", __func__, early ? "early" : "late");
671
672 pci_mmcfg_reject_broken(early);
673 if (list_empty(&pci_mmcfg_list))
674 return;
675
676 if (pcibios_last_bus < 0) {
677 const struct pci_mmcfg_region *cfg;
678
679 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
680 if (cfg->segment)
681 break;
682 pcibios_last_bus = cfg->end_bus;
683 }
684 }
685
686 if (pci_mmcfg_arch_init())
687 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
688 else {
689 free_all_mmcfg();
690 pci_mmcfg_arch_init_failed = true;
691 }
692}
693
694static int __initdata known_bridge;
695
696void __init pci_mmcfg_early_init(void)
697{
698 pr_debug("%s() pci_probe %#x\n", __func__, pci_probe);
699
700 if (pci_probe & PCI_PROBE_MMCONF) {
701 if (pci_mmcfg_check_hostbridge())
702 known_bridge = 1;
703 else
704 acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
705 __pci_mmcfg_init(1);
706
707 set_apei_filter();
708 }
709}
710
711void __init pci_mmcfg_late_init(void)
712{
713 pr_debug("%s() pci_probe %#x\n", __func__, pci_probe);
714
715 /* ECAM disabled */
716 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
717 return;
718
719 if (known_bridge)
720 return;
721
722 /* ECAM hasn't been enabled yet, try again */
723 if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
724 acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
725 __pci_mmcfg_init(0);
726 }
727}
728
729static int __init pci_mmcfg_late_insert_resources(void)
730{
731 struct pci_mmcfg_region *cfg;
732
733 pci_mmcfg_running_state = true;
734
735 pr_debug("%s() pci_probe %#x\n", __func__, pci_probe);
736
737 /* If we are not using ECAM, don't insert the resources. */
738 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
739 return 1;
740
741 /*
742 * Attempt to insert the mmcfg resources but not with the busy flag
743 * marked so it won't cause request errors when __request_region is
744 * called.
745 */
746 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
747 if (!cfg->res.parent) {
748 pr_debug("%s() insert %pR\n", __func__, &cfg->res);
749 insert_resource(&iomem_resource, &cfg->res);
750 }
751 }
752
753 return 0;
754}
755
756/*
757 * Perform ECAM resource insertion after PCI initialization to allow for
758 * misprogrammed MCFG tables that state larger sizes but actually conflict
759 * with other system resources.
760 */
761late_initcall(pci_mmcfg_late_insert_resources);
762
763/* Add ECAM information for host bridges */
764int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
765 phys_addr_t addr)
766{
767 int rc;
768 struct resource *tmp = NULL;
769 struct pci_mmcfg_region *cfg;
770
771 dev_dbg(dev, "%s(%04x [bus %02x-%02x])\n", __func__, seg, start, end);
772
773 if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
774 return -ENODEV;
775
776 if (start > end)
777 return -EINVAL;
778
779 mutex_lock(&pci_mmcfg_lock);
780 cfg = pci_mmconfig_lookup(seg, start);
781 if (cfg) {
782 if (cfg->end_bus < end)
783 dev_info(dev, FW_INFO "ECAM %pR for domain %04x [bus %02x-%02x] only partially covers this bridge\n",
784 &cfg->res, cfg->segment, cfg->start_bus,
785 cfg->end_bus);
786 mutex_unlock(&pci_mmcfg_lock);
787 return -EEXIST;
788 }
789
790 /*
791 * Don't move earlier; we must return -EEXIST, not -EINVAL, if
792 * pci_mmconfig_lookup() finds something
793 */
794 if (!addr) {
795 mutex_unlock(&pci_mmcfg_lock);
796 return -EINVAL;
797 }
798
799 rc = -EBUSY;
800 cfg = pci_mmconfig_alloc(seg, start, end, addr);
801 if (cfg == NULL) {
802 dev_warn(dev, "fail to add ECAM (out of memory)\n");
803 rc = -ENOMEM;
804 } else if (!pci_mmcfg_reserved(dev, cfg, 0)) {
805 dev_warn(dev, FW_BUG "ECAM %pR isn't reserved\n",
806 &cfg->res);
807 } else {
808 /* Insert resource if it's not in boot stage */
809 if (pci_mmcfg_running_state)
810 tmp = insert_resource_conflict(&iomem_resource,
811 &cfg->res);
812
813 if (tmp) {
814 dev_warn(dev, "ECAM %pR conflicts with %s %pR\n",
815 &cfg->res, tmp->name, tmp);
816 } else if (pci_mmcfg_arch_map(cfg)) {
817 dev_warn(dev, "fail to map ECAM %pR\n", &cfg->res);
818 } else {
819 list_add_sorted(cfg);
820 dev_info(dev, "ECAM %pR (base %#lx)\n",
821 &cfg->res, (unsigned long)addr);
822 cfg = NULL;
823 rc = 0;
824 }
825 }
826
827 if (cfg) {
828 if (cfg->res.parent)
829 release_resource(&cfg->res);
830 kfree(cfg);
831 }
832
833 mutex_unlock(&pci_mmcfg_lock);
834
835 return rc;
836}
837
838/* Delete ECAM information for host bridges */
839int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
840{
841 struct pci_mmcfg_region *cfg;
842
843 mutex_lock(&pci_mmcfg_lock);
844 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
845 if (cfg->segment == seg && cfg->start_bus == start &&
846 cfg->end_bus == end) {
847 list_del_rcu(&cfg->list);
848 synchronize_rcu();
849 pci_mmcfg_arch_unmap(cfg);
850 if (cfg->res.parent)
851 release_resource(&cfg->res);
852 mutex_unlock(&pci_mmcfg_lock);
853 kfree(cfg);
854 return 0;
855 }
856 mutex_unlock(&pci_mmcfg_lock);
857
858 return -ENOENT;
859}
1/*
2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
4 *
5 * This code does:
6 * - known chipset handling
7 * - ACPI decoding and validation
8 *
9 * Per-architecture code takes care of the mappings and accesses
10 * themselves.
11 */
12
13#include <linux/pci.h>
14#include <linux/init.h>
15#include <linux/sfi_acpi.h>
16#include <linux/bitmap.h>
17#include <linux/dmi.h>
18#include <linux/slab.h>
19#include <linux/mutex.h>
20#include <linux/rculist.h>
21#include <asm/e820.h>
22#include <asm/pci_x86.h>
23#include <asm/acpi.h>
24
25#define PREFIX "PCI: "
26
27/* Indicate if the mmcfg resources have been placed into the resource table. */
28static bool pci_mmcfg_running_state;
29static bool pci_mmcfg_arch_init_failed;
30static DEFINE_MUTEX(pci_mmcfg_lock);
31
32LIST_HEAD(pci_mmcfg_list);
33
34static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
35{
36 if (cfg->res.parent)
37 release_resource(&cfg->res);
38 list_del(&cfg->list);
39 kfree(cfg);
40}
41
42static void __init free_all_mmcfg(void)
43{
44 struct pci_mmcfg_region *cfg, *tmp;
45
46 pci_mmcfg_arch_free();
47 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
48 pci_mmconfig_remove(cfg);
49}
50
51static void list_add_sorted(struct pci_mmcfg_region *new)
52{
53 struct pci_mmcfg_region *cfg;
54
55 /* keep list sorted by segment and starting bus number */
56 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
57 if (cfg->segment > new->segment ||
58 (cfg->segment == new->segment &&
59 cfg->start_bus >= new->start_bus)) {
60 list_add_tail_rcu(&new->list, &cfg->list);
61 return;
62 }
63 }
64 list_add_tail_rcu(&new->list, &pci_mmcfg_list);
65}
66
67static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
68 int end, u64 addr)
69{
70 struct pci_mmcfg_region *new;
71 struct resource *res;
72
73 if (addr == 0)
74 return NULL;
75
76 new = kzalloc(sizeof(*new), GFP_KERNEL);
77 if (!new)
78 return NULL;
79
80 new->address = addr;
81 new->segment = segment;
82 new->start_bus = start;
83 new->end_bus = end;
84
85 res = &new->res;
86 res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
87 res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
88 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
89 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
90 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
91 res->name = new->name;
92
93 return new;
94}
95
96static struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
97 int end, u64 addr)
98{
99 struct pci_mmcfg_region *new;
100
101 new = pci_mmconfig_alloc(segment, start, end, addr);
102 if (new) {
103 mutex_lock(&pci_mmcfg_lock);
104 list_add_sorted(new);
105 mutex_unlock(&pci_mmcfg_lock);
106
107 pr_info(PREFIX
108 "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
109 "(base %#lx)\n",
110 segment, start, end, &new->res, (unsigned long)addr);
111 }
112
113 return new;
114}
115
116struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
117{
118 struct pci_mmcfg_region *cfg;
119
120 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
121 if (cfg->segment == segment &&
122 cfg->start_bus <= bus && bus <= cfg->end_bus)
123 return cfg;
124
125 return NULL;
126}
127
128static const char *__init pci_mmcfg_e7520(void)
129{
130 u32 win;
131 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
132
133 win = win & 0xf000;
134 if (win == 0x0000 || win == 0xf000)
135 return NULL;
136
137 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
138 return NULL;
139
140 return "Intel Corporation E7520 Memory Controller Hub";
141}
142
143static const char *__init pci_mmcfg_intel_945(void)
144{
145 u32 pciexbar, mask = 0, len = 0;
146
147 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
148
149 /* Enable bit */
150 if (!(pciexbar & 1))
151 return NULL;
152
153 /* Size bits */
154 switch ((pciexbar >> 1) & 3) {
155 case 0:
156 mask = 0xf0000000U;
157 len = 0x10000000U;
158 break;
159 case 1:
160 mask = 0xf8000000U;
161 len = 0x08000000U;
162 break;
163 case 2:
164 mask = 0xfc000000U;
165 len = 0x04000000U;
166 break;
167 default:
168 return NULL;
169 }
170
171 /* Errata #2, things break when not aligned on a 256Mb boundary */
172 /* Can only happen in 64M/128M mode */
173
174 if ((pciexbar & mask) & 0x0fffffffU)
175 return NULL;
176
177 /* Don't hit the APIC registers and their friends */
178 if ((pciexbar & mask) >= 0xf0000000U)
179 return NULL;
180
181 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
182 return NULL;
183
184 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
185}
186
187static const char *__init pci_mmcfg_amd_fam10h(void)
188{
189 u32 low, high, address;
190 u64 base, msr;
191 int i;
192 unsigned segnbits = 0, busnbits, end_bus;
193
194 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
195 return NULL;
196
197 address = MSR_FAM10H_MMIO_CONF_BASE;
198 if (rdmsr_safe(address, &low, &high))
199 return NULL;
200
201 msr = high;
202 msr <<= 32;
203 msr |= low;
204
205 /* mmconfig is not enable */
206 if (!(msr & FAM10H_MMIO_CONF_ENABLE))
207 return NULL;
208
209 base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
210
211 busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
212 FAM10H_MMIO_CONF_BUSRANGE_MASK;
213
214 /*
215 * only handle bus 0 ?
216 * need to skip it
217 */
218 if (!busnbits)
219 return NULL;
220
221 if (busnbits > 8) {
222 segnbits = busnbits - 8;
223 busnbits = 8;
224 }
225
226 end_bus = (1 << busnbits) - 1;
227 for (i = 0; i < (1 << segnbits); i++)
228 if (pci_mmconfig_add(i, 0, end_bus,
229 base + (1<<28) * i) == NULL) {
230 free_all_mmcfg();
231 return NULL;
232 }
233
234 return "AMD Family 10h NB";
235}
236
237static bool __initdata mcp55_checked;
238static const char *__init pci_mmcfg_nvidia_mcp55(void)
239{
240 int bus;
241 int mcp55_mmconf_found = 0;
242
243 static const u32 extcfg_regnum __initconst = 0x90;
244 static const u32 extcfg_regsize __initconst = 4;
245 static const u32 extcfg_enable_mask __initconst = 1 << 31;
246 static const u32 extcfg_start_mask __initconst = 0xff << 16;
247 static const int extcfg_start_shift __initconst = 16;
248 static const u32 extcfg_size_mask __initconst = 0x3 << 28;
249 static const int extcfg_size_shift __initconst = 28;
250 static const int extcfg_sizebus[] __initconst = {
251 0x100, 0x80, 0x40, 0x20
252 };
253 static const u32 extcfg_base_mask[] __initconst = {
254 0x7ff8, 0x7ffc, 0x7ffe, 0x7fff
255 };
256 static const int extcfg_base_lshift __initconst = 25;
257
258 /*
259 * do check if amd fam10h already took over
260 */
261 if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
262 return NULL;
263
264 mcp55_checked = true;
265 for (bus = 0; bus < 256; bus++) {
266 u64 base;
267 u32 l, extcfg;
268 u16 vendor, device;
269 int start, size_index, end;
270
271 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
272 vendor = l & 0xffff;
273 device = (l >> 16) & 0xffff;
274
275 if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
276 continue;
277
278 raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
279 extcfg_regsize, &extcfg);
280
281 if (!(extcfg & extcfg_enable_mask))
282 continue;
283
284 size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
285 base = extcfg & extcfg_base_mask[size_index];
286 /* base could > 4G */
287 base <<= extcfg_base_lshift;
288 start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
289 end = start + extcfg_sizebus[size_index] - 1;
290 if (pci_mmconfig_add(0, start, end, base) == NULL)
291 continue;
292 mcp55_mmconf_found++;
293 }
294
295 if (!mcp55_mmconf_found)
296 return NULL;
297
298 return "nVidia MCP55";
299}
300
301struct pci_mmcfg_hostbridge_probe {
302 u32 bus;
303 u32 devfn;
304 u32 vendor;
305 u32 device;
306 const char *(*probe)(void);
307};
308
309static const struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initconst = {
310 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
311 PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
312 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
313 PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
314 { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
315 0x1200, pci_mmcfg_amd_fam10h },
316 { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
317 0x1200, pci_mmcfg_amd_fam10h },
318 { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
319 0x0369, pci_mmcfg_nvidia_mcp55 },
320};
321
322static void __init pci_mmcfg_check_end_bus_number(void)
323{
324 struct pci_mmcfg_region *cfg, *cfgx;
325
326 /* Fixup overlaps */
327 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
328 if (cfg->end_bus < cfg->start_bus)
329 cfg->end_bus = 255;
330
331 /* Don't access the list head ! */
332 if (cfg->list.next == &pci_mmcfg_list)
333 break;
334
335 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
336 if (cfg->end_bus >= cfgx->start_bus)
337 cfg->end_bus = cfgx->start_bus - 1;
338 }
339}
340
341static int __init pci_mmcfg_check_hostbridge(void)
342{
343 u32 l;
344 u32 bus, devfn;
345 u16 vendor, device;
346 int i;
347 const char *name;
348
349 if (!raw_pci_ops)
350 return 0;
351
352 free_all_mmcfg();
353
354 for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
355 bus = pci_mmcfg_probes[i].bus;
356 devfn = pci_mmcfg_probes[i].devfn;
357 raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
358 vendor = l & 0xffff;
359 device = (l >> 16) & 0xffff;
360
361 name = NULL;
362 if (pci_mmcfg_probes[i].vendor == vendor &&
363 pci_mmcfg_probes[i].device == device)
364 name = pci_mmcfg_probes[i].probe();
365
366 if (name)
367 pr_info(PREFIX "%s with MMCONFIG support\n", name);
368 }
369
370 /* some end_bus_number is crazy, fix it */
371 pci_mmcfg_check_end_bus_number();
372
373 return !list_empty(&pci_mmcfg_list);
374}
375
376static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data)
377{
378 struct resource *mcfg_res = data;
379 struct acpi_resource_address64 address;
380 acpi_status status;
381
382 if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
383 struct acpi_resource_fixed_memory32 *fixmem32 =
384 &res->data.fixed_memory32;
385 if (!fixmem32)
386 return AE_OK;
387 if ((mcfg_res->start >= fixmem32->address) &&
388 (mcfg_res->end < (fixmem32->address +
389 fixmem32->address_length))) {
390 mcfg_res->flags = 1;
391 return AE_CTRL_TERMINATE;
392 }
393 }
394 if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
395 (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
396 return AE_OK;
397
398 status = acpi_resource_to_address64(res, &address);
399 if (ACPI_FAILURE(status) ||
400 (address.address.address_length <= 0) ||
401 (address.resource_type != ACPI_MEMORY_RANGE))
402 return AE_OK;
403
404 if ((mcfg_res->start >= address.address.minimum) &&
405 (mcfg_res->end < (address.address.minimum + address.address.address_length))) {
406 mcfg_res->flags = 1;
407 return AE_CTRL_TERMINATE;
408 }
409 return AE_OK;
410}
411
412static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl,
413 void *context, void **rv)
414{
415 struct resource *mcfg_res = context;
416
417 acpi_walk_resources(handle, METHOD_NAME__CRS,
418 check_mcfg_resource, context);
419
420 if (mcfg_res->flags)
421 return AE_CTRL_TERMINATE;
422
423 return AE_OK;
424}
425
426static int is_acpi_reserved(u64 start, u64 end, unsigned not_used)
427{
428 struct resource mcfg_res;
429
430 mcfg_res.start = start;
431 mcfg_res.end = end - 1;
432 mcfg_res.flags = 0;
433
434 acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
435
436 if (!mcfg_res.flags)
437 acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
438 NULL);
439
440 return mcfg_res.flags;
441}
442
443typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
444
445static int __ref is_mmconf_reserved(check_reserved_t is_reserved,
446 struct pci_mmcfg_region *cfg,
447 struct device *dev, int with_e820)
448{
449 u64 addr = cfg->res.start;
450 u64 size = resource_size(&cfg->res);
451 u64 old_size = size;
452 int num_buses;
453 char *method = with_e820 ? "E820" : "ACPI motherboard resources";
454
455 while (!is_reserved(addr, addr + size, E820_RESERVED)) {
456 size >>= 1;
457 if (size < (16UL<<20))
458 break;
459 }
460
461 if (size < (16UL<<20) && size != old_size)
462 return 0;
463
464 if (dev)
465 dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
466 &cfg->res, method);
467 else
468 pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
469 &cfg->res, method);
470
471 if (old_size != size) {
472 /* update end_bus */
473 cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
474 num_buses = cfg->end_bus - cfg->start_bus + 1;
475 cfg->res.end = cfg->res.start +
476 PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
477 snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
478 "PCI MMCONFIG %04x [bus %02x-%02x]",
479 cfg->segment, cfg->start_bus, cfg->end_bus);
480
481 if (dev)
482 dev_info(dev,
483 "MMCONFIG "
484 "at %pR (base %#lx) (size reduced!)\n",
485 &cfg->res, (unsigned long) cfg->address);
486 else
487 pr_info(PREFIX
488 "MMCONFIG for %04x [bus%02x-%02x] "
489 "at %pR (base %#lx) (size reduced!)\n",
490 cfg->segment, cfg->start_bus, cfg->end_bus,
491 &cfg->res, (unsigned long) cfg->address);
492 }
493
494 return 1;
495}
496
497static int __ref pci_mmcfg_check_reserved(struct device *dev,
498 struct pci_mmcfg_region *cfg, int early)
499{
500 if (!early && !acpi_disabled) {
501 if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
502 return 1;
503
504 if (dev)
505 dev_info(dev, FW_INFO
506 "MMCONFIG at %pR not reserved in "
507 "ACPI motherboard resources\n",
508 &cfg->res);
509 else
510 pr_info(FW_INFO PREFIX
511 "MMCONFIG at %pR not reserved in "
512 "ACPI motherboard resources\n",
513 &cfg->res);
514 }
515
516 /*
517 * e820_all_mapped() is marked as __init.
518 * All entries from ACPI MCFG table have been checked at boot time.
519 * For MCFG information constructed from hotpluggable host bridge's
520 * _CBA method, just assume it's reserved.
521 */
522 if (pci_mmcfg_running_state)
523 return 1;
524
525 /* Don't try to do this check unless configuration
526 type 1 is available. how about type 2 ?*/
527 if (raw_pci_ops)
528 return is_mmconf_reserved(e820_all_mapped, cfg, dev, 1);
529
530 return 0;
531}
532
533static void __init pci_mmcfg_reject_broken(int early)
534{
535 struct pci_mmcfg_region *cfg;
536
537 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
538 if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
539 pr_info(PREFIX "not using MMCONFIG\n");
540 free_all_mmcfg();
541 return;
542 }
543 }
544}
545
546static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
547 struct acpi_mcfg_allocation *cfg)
548{
549 int year;
550
551 if (cfg->address < 0xFFFFFFFF)
552 return 0;
553
554 if (!strncmp(mcfg->header.oem_id, "SGI", 3))
555 return 0;
556
557 if (mcfg->header.revision >= 1) {
558 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
559 year >= 2010)
560 return 0;
561 }
562
563 pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
564 "is above 4GB, ignored\n", cfg->pci_segment,
565 cfg->start_bus_number, cfg->end_bus_number, cfg->address);
566 return -EINVAL;
567}
568
569static int __init pci_parse_mcfg(struct acpi_table_header *header)
570{
571 struct acpi_table_mcfg *mcfg;
572 struct acpi_mcfg_allocation *cfg_table, *cfg;
573 unsigned long i;
574 int entries;
575
576 if (!header)
577 return -EINVAL;
578
579 mcfg = (struct acpi_table_mcfg *)header;
580
581 /* how many config structures do we have */
582 free_all_mmcfg();
583 entries = 0;
584 i = header->length - sizeof(struct acpi_table_mcfg);
585 while (i >= sizeof(struct acpi_mcfg_allocation)) {
586 entries++;
587 i -= sizeof(struct acpi_mcfg_allocation);
588 }
589 if (entries == 0) {
590 pr_err(PREFIX "MMCONFIG has no entries\n");
591 return -ENODEV;
592 }
593
594 cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
595 for (i = 0; i < entries; i++) {
596 cfg = &cfg_table[i];
597 if (acpi_mcfg_check_entry(mcfg, cfg)) {
598 free_all_mmcfg();
599 return -ENODEV;
600 }
601
602 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
603 cfg->end_bus_number, cfg->address) == NULL) {
604 pr_warn(PREFIX "no memory for MCFG entries\n");
605 free_all_mmcfg();
606 return -ENOMEM;
607 }
608 }
609
610 return 0;
611}
612
613#ifdef CONFIG_ACPI_APEI
614extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size,
615 void *data), void *data);
616
617static int pci_mmcfg_for_each_region(int (*func)(__u64 start, __u64 size,
618 void *data), void *data)
619{
620 struct pci_mmcfg_region *cfg;
621 int rc;
622
623 if (list_empty(&pci_mmcfg_list))
624 return 0;
625
626 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
627 rc = func(cfg->res.start, resource_size(&cfg->res), data);
628 if (rc)
629 return rc;
630 }
631
632 return 0;
633}
634#define set_apei_filter() (arch_apei_filter_addr = pci_mmcfg_for_each_region)
635#else
636#define set_apei_filter()
637#endif
638
639static void __init __pci_mmcfg_init(int early)
640{
641 pci_mmcfg_reject_broken(early);
642 if (list_empty(&pci_mmcfg_list))
643 return;
644
645 if (pcibios_last_bus < 0) {
646 const struct pci_mmcfg_region *cfg;
647
648 list_for_each_entry(cfg, &pci_mmcfg_list, list) {
649 if (cfg->segment)
650 break;
651 pcibios_last_bus = cfg->end_bus;
652 }
653 }
654
655 if (pci_mmcfg_arch_init())
656 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
657 else {
658 free_all_mmcfg();
659 pci_mmcfg_arch_init_failed = true;
660 }
661}
662
663static int __initdata known_bridge;
664
665void __init pci_mmcfg_early_init(void)
666{
667 if (pci_probe & PCI_PROBE_MMCONF) {
668 if (pci_mmcfg_check_hostbridge())
669 known_bridge = 1;
670 else
671 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
672 __pci_mmcfg_init(1);
673
674 set_apei_filter();
675 }
676}
677
678void __init pci_mmcfg_late_init(void)
679{
680 /* MMCONFIG disabled */
681 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
682 return;
683
684 if (known_bridge)
685 return;
686
687 /* MMCONFIG hasn't been enabled yet, try again */
688 if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
689 acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
690 __pci_mmcfg_init(0);
691 }
692}
693
694static int __init pci_mmcfg_late_insert_resources(void)
695{
696 struct pci_mmcfg_region *cfg;
697
698 pci_mmcfg_running_state = true;
699
700 /* If we are not using MMCONFIG, don't insert the resources. */
701 if ((pci_probe & PCI_PROBE_MMCONF) == 0)
702 return 1;
703
704 /*
705 * Attempt to insert the mmcfg resources but not with the busy flag
706 * marked so it won't cause request errors when __request_region is
707 * called.
708 */
709 list_for_each_entry(cfg, &pci_mmcfg_list, list)
710 if (!cfg->res.parent)
711 insert_resource(&iomem_resource, &cfg->res);
712
713 return 0;
714}
715
716/*
717 * Perform MMCONFIG resource insertion after PCI initialization to allow for
718 * misprogrammed MCFG tables that state larger sizes but actually conflict
719 * with other system resources.
720 */
721late_initcall(pci_mmcfg_late_insert_resources);
722
723/* Add MMCFG information for host bridges */
724int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
725 phys_addr_t addr)
726{
727 int rc;
728 struct resource *tmp = NULL;
729 struct pci_mmcfg_region *cfg;
730
731 if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
732 return -ENODEV;
733
734 if (start > end)
735 return -EINVAL;
736
737 mutex_lock(&pci_mmcfg_lock);
738 cfg = pci_mmconfig_lookup(seg, start);
739 if (cfg) {
740 if (cfg->end_bus < end)
741 dev_info(dev, FW_INFO
742 "MMCONFIG for "
743 "domain %04x [bus %02x-%02x] "
744 "only partially covers this bridge\n",
745 cfg->segment, cfg->start_bus, cfg->end_bus);
746 mutex_unlock(&pci_mmcfg_lock);
747 return -EEXIST;
748 }
749
750 if (!addr) {
751 mutex_unlock(&pci_mmcfg_lock);
752 return -EINVAL;
753 }
754
755 rc = -EBUSY;
756 cfg = pci_mmconfig_alloc(seg, start, end, addr);
757 if (cfg == NULL) {
758 dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
759 rc = -ENOMEM;
760 } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
761 dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
762 &cfg->res);
763 } else {
764 /* Insert resource if it's not in boot stage */
765 if (pci_mmcfg_running_state)
766 tmp = insert_resource_conflict(&iomem_resource,
767 &cfg->res);
768
769 if (tmp) {
770 dev_warn(dev,
771 "MMCONFIG %pR conflicts with "
772 "%s %pR\n",
773 &cfg->res, tmp->name, tmp);
774 } else if (pci_mmcfg_arch_map(cfg)) {
775 dev_warn(dev, "fail to map MMCONFIG %pR.\n",
776 &cfg->res);
777 } else {
778 list_add_sorted(cfg);
779 dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
780 &cfg->res, (unsigned long)addr);
781 cfg = NULL;
782 rc = 0;
783 }
784 }
785
786 if (cfg) {
787 if (cfg->res.parent)
788 release_resource(&cfg->res);
789 kfree(cfg);
790 }
791
792 mutex_unlock(&pci_mmcfg_lock);
793
794 return rc;
795}
796
797/* Delete MMCFG information for host bridges */
798int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
799{
800 struct pci_mmcfg_region *cfg;
801
802 mutex_lock(&pci_mmcfg_lock);
803 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
804 if (cfg->segment == seg && cfg->start_bus == start &&
805 cfg->end_bus == end) {
806 list_del_rcu(&cfg->list);
807 synchronize_rcu();
808 pci_mmcfg_arch_unmap(cfg);
809 if (cfg->res.parent)
810 release_resource(&cfg->res);
811 mutex_unlock(&pci_mmcfg_lock);
812 kfree(cfg);
813 return 0;
814 }
815 mutex_unlock(&pci_mmcfg_lock);
816
817 return -ENOENT;
818}