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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
7 *
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
10 *
11 * Most of this originates from head_64.S and thus has the same
12 * copyright history.
13 *
14 */
15
16#include <linux/linkage.h>
17#include <asm/hw_irq.h>
18#include <asm/exception-64s.h>
19#include <asm/ptrace.h>
20#include <asm/cpuidle.h>
21#include <asm/head-64.h>
22#include <asm/feature-fixups.h>
23#include <asm/kup.h>
24
25/*
26 * Following are fixed section helper macros.
27 *
28 * EXC_REAL_BEGIN/END - real, unrelocated exception vectors
29 * EXC_VIRT_BEGIN/END - virt (AIL), unrelocated exception vectors
30 * TRAMP_REAL_BEGIN - real, unrelocated helpers (virt may call these)
31 * TRAMP_VIRT_BEGIN - virt, unreloc helpers (in practice, real can use)
32 * EXC_COMMON - After switching to virtual, relocated mode.
33 */
34
35#define EXC_REAL_BEGIN(name, start, size) \
36 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
37
38#define EXC_REAL_END(name, start, size) \
39 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##name, start, size)
40
41#define EXC_VIRT_BEGIN(name, start, size) \
42 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
43
44#define EXC_VIRT_END(name, start, size) \
45 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##name, start, size)
46
47#define EXC_COMMON_BEGIN(name) \
48 USE_TEXT_SECTION(); \
49 .balign IFETCH_ALIGN_BYTES; \
50 .global name; \
51 _ASM_NOKPROBE_SYMBOL(name); \
52 DEFINE_FIXED_SYMBOL(name, text); \
53name:
54
55#define TRAMP_REAL_BEGIN(name) \
56 FIXED_SECTION_ENTRY_BEGIN(real_trampolines, name)
57
58#define TRAMP_VIRT_BEGIN(name) \
59 FIXED_SECTION_ENTRY_BEGIN(virt_trampolines, name)
60
61#define EXC_REAL_NONE(start, size) \
62 FIXED_SECTION_ENTRY_BEGIN_LOCATION(real_vectors, exc_real_##start##_##unused, start, size); \
63 FIXED_SECTION_ENTRY_END_LOCATION(real_vectors, exc_real_##start##_##unused, start, size)
64
65#define EXC_VIRT_NONE(start, size) \
66 FIXED_SECTION_ENTRY_BEGIN_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size); \
67 FIXED_SECTION_ENTRY_END_LOCATION(virt_vectors, exc_virt_##start##_##unused, start, size)
68
69/*
70 * We're short on space and time in the exception prolog, so we can't
71 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
72 * Instead we get the base of the kernel from paca->kernelbase and or in the low
73 * part of label. This requires that the label be within 64KB of kernelbase, and
74 * that kernelbase be 64K aligned.
75 */
76#define LOAD_HANDLER(reg, label) \
77 ld reg,PACAKBASE(r13); /* get high part of &label */ \
78 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
79
80#define __LOAD_HANDLER(reg, label, section) \
81 ld reg,PACAKBASE(r13); \
82 ori reg,reg,(ABS_ADDR(label, section))@l
83
84/*
85 * Branches from unrelocated code (e.g., interrupts) to labels outside
86 * head-y require >64K offsets.
87 */
88#define __LOAD_FAR_HANDLER(reg, label, section) \
89 ld reg,PACAKBASE(r13); \
90 ori reg,reg,(ABS_ADDR(label, section))@l; \
91 addis reg,reg,(ABS_ADDR(label, section))@h
92
93/*
94 * Interrupt code generation macros
95 */
96#define IVEC .L_IVEC_\name\() /* Interrupt vector address */
97#define IHSRR .L_IHSRR_\name\() /* Sets SRR or HSRR registers */
98#define IHSRR_IF_HVMODE .L_IHSRR_IF_HVMODE_\name\() /* HSRR if HV else SRR */
99#define IAREA .L_IAREA_\name\() /* PACA save area */
100#define IVIRT .L_IVIRT_\name\() /* Has virt mode entry point */
101#define IISIDE .L_IISIDE_\name\() /* Uses SRR0/1 not DAR/DSISR */
102#define ICFAR .L_ICFAR_\name\() /* Uses CFAR */
103#define ICFAR_IF_HVMODE .L_ICFAR_IF_HVMODE_\name\() /* Uses CFAR if HV */
104#define IDAR .L_IDAR_\name\() /* Uses DAR (or SRR0) */
105#define IDSISR .L_IDSISR_\name\() /* Uses DSISR (or SRR1) */
106#define IBRANCH_TO_COMMON .L_IBRANCH_TO_COMMON_\name\() /* ENTRY branch to common */
107#define IREALMODE_COMMON .L_IREALMODE_COMMON_\name\() /* Common runs in realmode */
108#define IMASK .L_IMASK_\name\() /* IRQ soft-mask bit */
109#define IKVM_REAL .L_IKVM_REAL_\name\() /* Real entry tests KVM */
110#define __IKVM_REAL(name) .L_IKVM_REAL_ ## name
111#define IKVM_VIRT .L_IKVM_VIRT_\name\() /* Virt entry tests KVM */
112#define ISTACK .L_ISTACK_\name\() /* Set regular kernel stack */
113#define __ISTACK(name) .L_ISTACK_ ## name
114#define IKUAP .L_IKUAP_\name\() /* Do KUAP lock */
115#define IMSR_R12 .L_IMSR_R12_\name\() /* Assumes MSR saved to r12 */
116
117#define INT_DEFINE_BEGIN(n) \
118.macro int_define_ ## n name
119
120#define INT_DEFINE_END(n) \
121.endm ; \
122int_define_ ## n n ; \
123do_define_int n
124
125.macro do_define_int name
126 .ifndef IVEC
127 .error "IVEC not defined"
128 .endif
129 .ifndef IHSRR
130 IHSRR=0
131 .endif
132 .ifndef IHSRR_IF_HVMODE
133 IHSRR_IF_HVMODE=0
134 .endif
135 .ifndef IAREA
136 IAREA=PACA_EXGEN
137 .endif
138 .ifndef IVIRT
139 IVIRT=1
140 .endif
141 .ifndef IISIDE
142 IISIDE=0
143 .endif
144 .ifndef ICFAR
145 ICFAR=1
146 .endif
147 .ifndef ICFAR_IF_HVMODE
148 ICFAR_IF_HVMODE=0
149 .endif
150 .ifndef IDAR
151 IDAR=0
152 .endif
153 .ifndef IDSISR
154 IDSISR=0
155 .endif
156 .ifndef IBRANCH_TO_COMMON
157 IBRANCH_TO_COMMON=1
158 .endif
159 .ifndef IREALMODE_COMMON
160 IREALMODE_COMMON=0
161 .else
162 .if ! IBRANCH_TO_COMMON
163 .error "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0"
164 .endif
165 .endif
166 .ifndef IMASK
167 IMASK=0
168 .endif
169 .ifndef IKVM_REAL
170 IKVM_REAL=0
171 .endif
172 .ifndef IKVM_VIRT
173 IKVM_VIRT=0
174 .endif
175 .ifndef ISTACK
176 ISTACK=1
177 .endif
178 .ifndef IKUAP
179 IKUAP=1
180 .endif
181 .ifndef IMSR_R12
182 IMSR_R12=0
183 .endif
184.endm
185
186/*
187 * All interrupts which set HSRR registers, as well as SRESET and MCE and
188 * syscall when invoked with "sc 1" switch to MSR[HV]=1 (HVMODE) to be taken,
189 * so they all generally need to test whether they were taken in guest context.
190 *
191 * Note: SRESET and MCE may also be sent to the guest by the hypervisor, and be
192 * taken with MSR[HV]=0.
193 *
194 * Interrupts which set SRR registers (with the above exceptions) do not
195 * elevate to MSR[HV]=1 mode, though most can be taken when running with
196 * MSR[HV]=1 (e.g., bare metal kernel and userspace). So these interrupts do
197 * not need to test whether a guest is running because they get delivered to
198 * the guest directly, including nested HV KVM guests.
199 *
200 * The exception is PR KVM, where the guest runs with MSR[PR]=1 and the host
201 * runs with MSR[HV]=0, so the host takes all interrupts on behalf of the
202 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be
203 * delivered to the real-mode entry point, therefore such interrupts only test
204 * KVM in their real mode handlers, and only when PR KVM is possible.
205 *
206 * Interrupts that are taken in MSR[HV]=0 and escalate to MSR[HV]=1 are always
207 * delivered in real-mode when the MMU is in hash mode because the MMU
208 * registers are not set appropriately to translate host addresses. In nested
209 * radix mode these can be delivered in virt-mode as the host translations are
210 * used implicitly (see: effective LPID, effective PID).
211 */
212
213/*
214 * If an interrupt is taken while a guest is running, it is immediately routed
215 * to KVM to handle.
216 */
217
218.macro KVMTEST name handler
219#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
220 lbz r10,HSTATE_IN_GUEST(r13)
221 cmpwi r10,0
222 /* HSRR variants have the 0x2 bit added to their trap number */
223 .if IHSRR_IF_HVMODE
224 BEGIN_FTR_SECTION
225 li r10,(IVEC + 0x2)
226 FTR_SECTION_ELSE
227 li r10,(IVEC)
228 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
229 .elseif IHSRR
230 li r10,(IVEC + 0x2)
231 .else
232 li r10,(IVEC)
233 .endif
234 bne \handler
235#endif
236.endm
237
238/*
239 * This is the BOOK3S interrupt entry code macro.
240 *
241 * This can result in one of several things happening:
242 * - Branch to the _common handler, relocated, in virtual mode.
243 * These are normal interrupts (synchronous and asynchronous) handled by
244 * the kernel.
245 * - Branch to KVM, relocated but real mode interrupts remain in real mode.
246 * These occur when HSTATE_IN_GUEST is set. The interrupt may be caused by
247 * / intended for host or guest kernel, but KVM must always be involved
248 * because the machine state is set for guest execution.
249 * - Branch to the masked handler, unrelocated.
250 * These occur when maskable asynchronous interrupts are taken with the
251 * irq_soft_mask set.
252 * - Branch to an "early" handler in real mode but relocated.
253 * This is done if early=1. MCE and HMI use these to handle errors in real
254 * mode.
255 * - Fall through and continue executing in real, unrelocated mode.
256 * This is done if early=2.
257 */
258
259.macro GEN_BRANCH_TO_COMMON name, virt
260 .if IREALMODE_COMMON
261 LOAD_HANDLER(r10, \name\()_common)
262 mtctr r10
263 bctr
264 .else
265 .if \virt
266#ifndef CONFIG_RELOCATABLE
267 b \name\()_common_virt
268#else
269 LOAD_HANDLER(r10, \name\()_common_virt)
270 mtctr r10
271 bctr
272#endif
273 .else
274 LOAD_HANDLER(r10, \name\()_common_real)
275 mtctr r10
276 bctr
277 .endif
278 .endif
279.endm
280
281.macro GEN_INT_ENTRY name, virt, ool=0
282 SET_SCRATCH0(r13) /* save r13 */
283 GET_PACA(r13)
284 std r9,IAREA+EX_R9(r13) /* save r9 */
285BEGIN_FTR_SECTION
286 mfspr r9,SPRN_PPR
287END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
288 HMT_MEDIUM
289 std r10,IAREA+EX_R10(r13) /* save r10 */
290 .if ICFAR
291BEGIN_FTR_SECTION
292 mfspr r10,SPRN_CFAR
293END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
294 .elseif ICFAR_IF_HVMODE
295BEGIN_FTR_SECTION
296 BEGIN_FTR_SECTION_NESTED(69)
297 mfspr r10,SPRN_CFAR
298 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 69)
299FTR_SECTION_ELSE
300 BEGIN_FTR_SECTION_NESTED(69)
301 li r10,0
302 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 69)
303ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
304 .endif
305 .if \ool
306 .if !\virt
307 b tramp_real_\name
308 .pushsection .text
309 TRAMP_REAL_BEGIN(tramp_real_\name)
310 .else
311 b tramp_virt_\name
312 .pushsection .text
313 TRAMP_VIRT_BEGIN(tramp_virt_\name)
314 .endif
315 .endif
316
317BEGIN_FTR_SECTION
318 std r9,IAREA+EX_PPR(r13)
319END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
320 .if ICFAR || ICFAR_IF_HVMODE
321BEGIN_FTR_SECTION
322 std r10,IAREA+EX_CFAR(r13)
323END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
324 .endif
325 INTERRUPT_TO_KERNEL
326 mfctr r10
327 std r10,IAREA+EX_CTR(r13)
328 mfcr r9
329 std r11,IAREA+EX_R11(r13) /* save r11 - r12 */
330 std r12,IAREA+EX_R12(r13)
331
332 /*
333 * DAR/DSISR, SCRATCH0 must be read before setting MSR[RI],
334 * because a d-side MCE will clobber those registers so is
335 * not recoverable if they are live.
336 */
337 GET_SCRATCH0(r10)
338 std r10,IAREA+EX_R13(r13)
339 .if IDAR && !IISIDE
340 .if IHSRR
341 mfspr r10,SPRN_HDAR
342 .else
343 mfspr r10,SPRN_DAR
344 .endif
345 std r10,IAREA+EX_DAR(r13)
346 .endif
347 .if IDSISR && !IISIDE
348 .if IHSRR
349 mfspr r10,SPRN_HDSISR
350 .else
351 mfspr r10,SPRN_DSISR
352 .endif
353 stw r10,IAREA+EX_DSISR(r13)
354 .endif
355
356 .if IHSRR_IF_HVMODE
357 BEGIN_FTR_SECTION
358 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
359 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
360 FTR_SECTION_ELSE
361 mfspr r11,SPRN_SRR0 /* save SRR0 */
362 mfspr r12,SPRN_SRR1 /* and SRR1 */
363 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
364 .elseif IHSRR
365 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
366 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
367 .else
368 mfspr r11,SPRN_SRR0 /* save SRR0 */
369 mfspr r12,SPRN_SRR1 /* and SRR1 */
370 .endif
371
372 .if IBRANCH_TO_COMMON
373 GEN_BRANCH_TO_COMMON \name \virt
374 .endif
375
376 .if \ool
377 .popsection
378 .endif
379.endm
380
381/*
382 * __GEN_COMMON_ENTRY is required to receive the branch from interrupt
383 * entry, except in the case of the real-mode handlers which require
384 * __GEN_REALMODE_COMMON_ENTRY.
385 *
386 * This switches to virtual mode and sets MSR[RI].
387 */
388.macro __GEN_COMMON_ENTRY name
389DEFINE_FIXED_SYMBOL(\name\()_common_real, text)
390\name\()_common_real:
391 .if IKVM_REAL
392 KVMTEST \name kvm_interrupt
393 .endif
394
395 ld r10,PACAKMSR(r13) /* get MSR value for kernel */
396 /* MSR[RI] is clear iff using SRR regs */
397 .if IHSRR_IF_HVMODE
398 BEGIN_FTR_SECTION
399 xori r10,r10,MSR_RI
400 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
401 .elseif ! IHSRR
402 xori r10,r10,MSR_RI
403 .endif
404 mtmsrd r10
405
406 .if IVIRT
407 .if IKVM_VIRT
408 b 1f /* skip the virt test coming from real */
409 .endif
410
411 .balign IFETCH_ALIGN_BYTES
412DEFINE_FIXED_SYMBOL(\name\()_common_virt, text)
413\name\()_common_virt:
414 .if IKVM_VIRT
415 KVMTEST \name kvm_interrupt
4161:
417 .endif
418 .endif /* IVIRT */
419.endm
420
421/*
422 * Don't switch to virt mode. Used for early MCE and HMI handlers that
423 * want to run in real mode.
424 */
425.macro __GEN_REALMODE_COMMON_ENTRY name
426DEFINE_FIXED_SYMBOL(\name\()_common_real, text)
427\name\()_common_real:
428 .if IKVM_REAL
429 KVMTEST \name kvm_interrupt
430 .endif
431.endm
432
433.macro __GEN_COMMON_BODY name
434 .if IMASK
435 .if ! ISTACK
436 .error "No support for masked interrupt to use custom stack"
437 .endif
438
439 /* If coming from user, skip soft-mask tests. */
440 andi. r10,r12,MSR_PR
441 bne 3f
442
443 /*
444 * Kernel code running below __end_soft_masked may be
445 * implicitly soft-masked if it is within the regions
446 * in the soft mask table.
447 */
448 LOAD_HANDLER(r10, __end_soft_masked)
449 cmpld r11,r10
450 bge+ 1f
451
452 /* SEARCH_SOFT_MASK_TABLE clobbers r9,r10,r12 */
453 mtctr r12
454 stw r9,PACA_EXGEN+EX_CCR(r13)
455 SEARCH_SOFT_MASK_TABLE
456 cmpdi r12,0
457 mfctr r12 /* Restore r12 to SRR1 */
458 lwz r9,PACA_EXGEN+EX_CCR(r13)
459 beq 1f /* Not in soft-mask table */
460 li r10,IMASK
461 b 2f /* In soft-mask table, always mask */
462
463 /* Test the soft mask state against our interrupt's bit */
4641: lbz r10,PACAIRQSOFTMASK(r13)
4652: andi. r10,r10,IMASK
466 /* Associate vector numbers with bits in paca->irq_happened */
467 .if IVEC == 0x500 || IVEC == 0xea0
468 li r10,PACA_IRQ_EE
469 .elseif IVEC == 0x900
470 li r10,PACA_IRQ_DEC
471 .elseif IVEC == 0xa00 || IVEC == 0xe80
472 li r10,PACA_IRQ_DBELL
473 .elseif IVEC == 0xe60
474 li r10,PACA_IRQ_HMI
475 .elseif IVEC == 0xf00
476 li r10,PACA_IRQ_PMI
477 .else
478 .abort "Bad maskable vector"
479 .endif
480
481 .if IHSRR_IF_HVMODE
482 BEGIN_FTR_SECTION
483 bne masked_Hinterrupt
484 FTR_SECTION_ELSE
485 bne masked_interrupt
486 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
487 .elseif IHSRR
488 bne masked_Hinterrupt
489 .else
490 bne masked_interrupt
491 .endif
492 .endif
493
494 .if ISTACK
495 andi. r10,r12,MSR_PR /* See if coming from user */
4963: mr r10,r1 /* Save r1 */
497 subi r1,r1,INT_FRAME_SIZE /* alloc frame on kernel stack */
498 beq- 100f
499 ld r1,PACAKSAVE(r13) /* kernel stack to use */
500100: tdgei r1,-INT_FRAME_SIZE /* trap if r1 is in userspace */
501 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
502 .endif
503
504 std r9,_CCR(r1) /* save CR in stackframe */
505 std r11,_NIP(r1) /* save SRR0 in stackframe */
506 std r12,_MSR(r1) /* save SRR1 in stackframe */
507 std r10,0(r1) /* make stack chain pointer */
508 std r0,GPR0(r1) /* save r0 in stackframe */
509 std r10,GPR1(r1) /* save r1 in stackframe */
510 SANITIZE_GPR(0)
511
512 /* Mark our [H]SRRs valid for return */
513 li r10,1
514 .if IHSRR_IF_HVMODE
515 BEGIN_FTR_SECTION
516 stb r10,PACAHSRR_VALID(r13)
517 FTR_SECTION_ELSE
518 stb r10,PACASRR_VALID(r13)
519 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
520 .elseif IHSRR
521 stb r10,PACAHSRR_VALID(r13)
522 .else
523 stb r10,PACASRR_VALID(r13)
524 .endif
525
526 .if ISTACK
527 .if IKUAP
528 kuap_save_amr_and_lock r9, r10, cr1, cr0
529 .endif
530 beq 101f /* if from kernel mode */
531BEGIN_FTR_SECTION
532 ld r9,IAREA+EX_PPR(r13) /* Read PPR from paca */
533 std r9,_PPR(r1)
534END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
535101:
536 .else
537 .if IKUAP
538 kuap_save_amr_and_lock r9, r10, cr1
539 .endif
540 .endif
541
542 /* Save original regs values from save area to stack frame. */
543 ld r9,IAREA+EX_R9(r13) /* move r9, r10 to stackframe */
544 ld r10,IAREA+EX_R10(r13)
545 std r9,GPR9(r1)
546 std r10,GPR10(r1)
547 ld r9,IAREA+EX_R11(r13) /* move r11 - r13 to stackframe */
548 ld r10,IAREA+EX_R12(r13)
549 ld r11,IAREA+EX_R13(r13)
550 std r9,GPR11(r1)
551 std r10,GPR12(r1)
552 std r11,GPR13(r1)
553 .if !IMSR_R12
554 SANITIZE_GPRS(9, 12)
555 .else
556 SANITIZE_GPRS(9, 11)
557 .endif
558
559 SAVE_NVGPRS(r1)
560 SANITIZE_NVGPRS()
561
562 .if IDAR
563 .if IISIDE
564 ld r10,_NIP(r1)
565 .else
566 ld r10,IAREA+EX_DAR(r13)
567 .endif
568 std r10,_DAR(r1)
569 .endif
570
571 .if IDSISR
572 .if IISIDE
573 ld r10,_MSR(r1)
574 lis r11,DSISR_SRR1_MATCH_64S@h
575 and r10,r10,r11
576 .else
577 lwz r10,IAREA+EX_DSISR(r13)
578 .endif
579 std r10,_DSISR(r1)
580 .endif
581
582BEGIN_FTR_SECTION
583 .if ICFAR || ICFAR_IF_HVMODE
584 ld r10,IAREA+EX_CFAR(r13)
585 .else
586 li r10,0
587 .endif
588 std r10,ORIG_GPR3(r1)
589END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
590 ld r10,IAREA+EX_CTR(r13)
591 std r10,_CTR(r1)
592 SAVE_GPRS(2, 8, r1) /* save r2 - r8 in stackframe */
593 SANITIZE_GPRS(2, 8)
594 mflr r9 /* Get LR, later save to stack */
595 LOAD_PACA_TOC() /* get kernel TOC into r2 */
596 std r9,_LINK(r1)
597 lbz r10,PACAIRQSOFTMASK(r13)
598 mfspr r11,SPRN_XER /* save XER in stackframe */
599 std r10,SOFTE(r1)
600 std r11,_XER(r1)
601 li r9,IVEC
602 std r9,_TRAP(r1) /* set trap number */
603 li r10,0
604 LOAD_REG_IMMEDIATE(r11, STACK_FRAME_REGS_MARKER)
605 std r10,RESULT(r1) /* clear regs->result */
606 std r11,STACK_INT_FRAME_MARKER(r1) /* mark the frame */
607.endm
608
609/*
610 * On entry r13 points to the paca, r9-r13 are saved in the paca,
611 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
612 * SRR1, and relocation is on.
613 *
614 * If stack=0, then the stack is already set in r1, and r1 is saved in r10.
615 * PPR save and CPU accounting is not done for the !stack case (XXX why not?)
616 */
617.macro GEN_COMMON name
618 __GEN_COMMON_ENTRY \name
619 __GEN_COMMON_BODY \name
620.endm
621
622.macro SEARCH_RESTART_TABLE
623#ifdef CONFIG_RELOCATABLE
624 mr r12,r2
625 LOAD_PACA_TOC()
626 LOAD_REG_ADDR(r9, __start___restart_table)
627 LOAD_REG_ADDR(r10, __stop___restart_table)
628 mr r2,r12
629#else
630 LOAD_REG_IMMEDIATE_SYM(r9, r12, __start___restart_table)
631 LOAD_REG_IMMEDIATE_SYM(r10, r12, __stop___restart_table)
632#endif
633300:
634 cmpd r9,r10
635 beq 302f
636 ld r12,0(r9)
637 cmpld r11,r12
638 blt 301f
639 ld r12,8(r9)
640 cmpld r11,r12
641 bge 301f
642 ld r12,16(r9)
643 b 303f
644301:
645 addi r9,r9,24
646 b 300b
647302:
648 li r12,0
649303:
650.endm
651
652.macro SEARCH_SOFT_MASK_TABLE
653#ifdef CONFIG_RELOCATABLE
654 mr r12,r2
655 LOAD_PACA_TOC()
656 LOAD_REG_ADDR(r9, __start___soft_mask_table)
657 LOAD_REG_ADDR(r10, __stop___soft_mask_table)
658 mr r2,r12
659#else
660 LOAD_REG_IMMEDIATE_SYM(r9, r12, __start___soft_mask_table)
661 LOAD_REG_IMMEDIATE_SYM(r10, r12, __stop___soft_mask_table)
662#endif
663300:
664 cmpd r9,r10
665 beq 302f
666 ld r12,0(r9)
667 cmpld r11,r12
668 blt 301f
669 ld r12,8(r9)
670 cmpld r11,r12
671 bge 301f
672 li r12,1
673 b 303f
674301:
675 addi r9,r9,16
676 b 300b
677302:
678 li r12,0
679303:
680.endm
681
682/*
683 * Restore all registers including H/SRR0/1 saved in a stack frame of a
684 * standard exception.
685 */
686.macro EXCEPTION_RESTORE_REGS hsrr=0
687 /* Move original SRR0 and SRR1 into the respective regs */
688 ld r9,_MSR(r1)
689 li r10,0
690 .if \hsrr
691 mtspr SPRN_HSRR1,r9
692 stb r10,PACAHSRR_VALID(r13)
693 .else
694 mtspr SPRN_SRR1,r9
695 stb r10,PACASRR_VALID(r13)
696 .endif
697 ld r9,_NIP(r1)
698 .if \hsrr
699 mtspr SPRN_HSRR0,r9
700 .else
701 mtspr SPRN_SRR0,r9
702 .endif
703 ld r9,_CTR(r1)
704 mtctr r9
705 ld r9,_XER(r1)
706 mtxer r9
707 ld r9,_LINK(r1)
708 mtlr r9
709 ld r9,_CCR(r1)
710 mtcr r9
711 SANITIZE_RESTORE_NVGPRS()
712 REST_GPRS(2, 13, r1)
713 REST_GPR(0, r1)
714 /* restore original r1. */
715 ld r1,GPR1(r1)
716.endm
717
718/*
719 * EARLY_BOOT_FIXUP - Fix real-mode interrupt with wrong endian in early boot.
720 *
721 * There's a short window during boot where although the kernel is running
722 * little endian, any exceptions will cause the CPU to switch back to big
723 * endian. For example a WARN() boils down to a trap instruction, which will
724 * cause a program check, and we end up here but with the CPU in big endian
725 * mode. The first instruction of the program check handler (in GEN_INT_ENTRY
726 * below) is an mtsprg, which when executed in the wrong endian is an lhzu with
727 * a ~3GB displacement from r3. The content of r3 is random, so that is a load
728 * from some random location, and depending on the system can easily lead to a
729 * checkstop, or an infinitely recursive page fault.
730 *
731 * So to handle that case we have a trampoline here that can detect we are in
732 * the wrong endian and flip us back to the correct endian. We can't flip
733 * MSR[LE] using mtmsr, so we have to use rfid. That requires backing up SRR0/1
734 * as well as a GPR. To do that we use SPRG0/2/3, as SPRG1 is already used for
735 * the paca. SPRG3 is user readable, but this trampoline is only active very
736 * early in boot, and SPRG3 will be reinitialised in vdso_getcpu_init() before
737 * userspace starts.
738 */
739.macro EARLY_BOOT_FIXUP
740BEGIN_FTR_SECTION
741#ifdef CONFIG_CPU_LITTLE_ENDIAN
742 tdi 0,0,0x48 // Trap never, or in reverse endian: b . + 8
743 b 2f // Skip trampoline if endian is correct
744 .long 0xa643707d // mtsprg 0, r11 Backup r11
745 .long 0xa6027a7d // mfsrr0 r11
746 .long 0xa643727d // mtsprg 2, r11 Backup SRR0 in SPRG2
747 .long 0xa6027b7d // mfsrr1 r11
748 .long 0xa643737d // mtsprg 3, r11 Backup SRR1 in SPRG3
749 .long 0xa600607d // mfmsr r11
750 .long 0x01006b69 // xori r11, r11, 1 Invert MSR[LE]
751 .long 0xa6037b7d // mtsrr1 r11
752 /*
753 * This is 'li r11,1f' where 1f is the absolute address of that
754 * label, byteswapped into the SI field of the instruction.
755 */
756 .long 0x00006039 | \
757 ((ABS_ADDR(1f, real_vectors) & 0x00ff) << 24) | \
758 ((ABS_ADDR(1f, real_vectors) & 0xff00) << 8)
759 .long 0xa6037a7d // mtsrr0 r11
760 .long 0x2400004c // rfid
7611:
762 mfsprg r11, 3
763 mtsrr1 r11 // Restore SRR1
764 mfsprg r11, 2
765 mtsrr0 r11 // Restore SRR0
766 mfsprg r11, 0 // Restore r11
7672:
768#endif
769 /*
770 * program check could hit at any time, and pseries can not block
771 * MSR[ME] in early boot. So check if there is anything useful in r13
772 * yet, and spin forever if not.
773 */
774 mtsprg 0, r11
775 mfcr r11
776 cmpdi r13, 0
777 beq .
778 mtcr r11
779 mfsprg r11, 0
780END_FTR_SECTION(0, 1) // nop out after boot
781.endm
782
783/*
784 * There are a few constraints to be concerned with.
785 * - Real mode exceptions code/data must be located at their physical location.
786 * - Virtual mode exceptions must be mapped at their 0xc000... location.
787 * - Fixed location code must not call directly beyond the __end_interrupts
788 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
789 * must be used.
790 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
791 * virtual 0xc00...
792 * - Conditional branch targets must be within +/-32K of caller.
793 *
794 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
795 * therefore don't have to run in physically located code or rfid to
796 * virtual mode kernel code. However on relocatable kernels they do have
797 * to branch to KERNELBASE offset because the rest of the kernel (outside
798 * the exception vectors) may be located elsewhere.
799 *
800 * Virtual exceptions correspond with physical, except their entry points
801 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
802 * offset applied. Virtual exceptions are enabled with the Alternate
803 * Interrupt Location (AIL) bit set in the LPCR. However this does not
804 * guarantee they will be delivered virtually. Some conditions (see the ISA)
805 * cause exceptions to be delivered in real mode.
806 *
807 * The scv instructions are a special case. They get a 0x3000 offset applied.
808 * scv exceptions have unique reentrancy properties, see below.
809 *
810 * It's impossible to receive interrupts below 0x300 via AIL.
811 *
812 * KVM: None of the virtual exceptions are from the guest. Anything that
813 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
814 *
815 *
816 * We layout physical memory as follows:
817 * 0x0000 - 0x00ff : Secondary processor spin code
818 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
819 * 0x1900 - 0x2fff : Real mode trampolines
820 * 0x3000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
821 * 0x5900 - 0x6fff : Relon mode trampolines
822 * 0x7000 - 0x7fff : FWNMI data area
823 * 0x8000 - .... : Common interrupt handlers, remaining early
824 * setup code, rest of kernel.
825 *
826 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
827 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
828 * vectors there.
829 */
830OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
831OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x3000)
832OPEN_FIXED_SECTION(virt_vectors, 0x3000, 0x5900)
833OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
834
835#ifdef CONFIG_PPC_POWERNV
836 .globl start_real_trampolines
837 .globl end_real_trampolines
838 .globl start_virt_trampolines
839 .globl end_virt_trampolines
840#endif
841
842#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
843/*
844 * Data area reserved for FWNMI option.
845 * This address (0x7000) is fixed by the RPA.
846 * pseries and powernv need to keep the whole page from
847 * 0x7000 to 0x8000 free for use by the firmware
848 */
849ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
850OPEN_TEXT_SECTION(0x8000)
851#else
852OPEN_TEXT_SECTION(0x7000)
853#endif
854
855USE_FIXED_SECTION(real_vectors)
856
857/*
858 * This is the start of the interrupt handlers for pSeries
859 * This code runs with relocation off.
860 * Code from here to __end_interrupts gets copied down to real
861 * address 0x100 when we are running a relocatable kernel.
862 * Therefore any relative branches in this section must only
863 * branch to labels in this section.
864 */
865 .globl __start_interrupts
866__start_interrupts:
867
868/**
869 * Interrupt 0x3000 - System Call Vectored Interrupt (syscall).
870 * This is a synchronous interrupt invoked with the "scv" instruction. The
871 * system call does not alter the HV bit, so it is directed to the OS.
872 *
873 * Handling:
874 * scv instructions enter the kernel without changing EE, RI, ME, or HV.
875 * In particular, this means we can take a maskable interrupt at any point
876 * in the scv handler, which is unlike any other interrupt. This is solved
877 * by treating the instruction addresses in the handler as being soft-masked,
878 * by adding a SOFT_MASK_TABLE entry for them.
879 *
880 * AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and
881 * ensure scv is never executed with relocation off, which means AIL-0
882 * should never happen.
883 *
884 * Before leaving the following inside-__end_soft_masked text, at least of the
885 * following must be true:
886 * - MSR[PR]=1 (i.e., return to userspace)
887 * - MSR_EE|MSR_RI is clear (no reentrant exceptions)
888 * - Standard kernel environment is set up (stack, paca, etc)
889 *
890 * KVM:
891 * These interrupts do not elevate HV 0->1, so HV is not involved. PR KVM
892 * ensures that FSCR[SCV] is disabled whenever it has to force AIL off.
893 *
894 * Call convention:
895 *
896 * syscall register convention is in Documentation/arch/powerpc/syscall64-abi.rst
897 */
898EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000)
899 /* SCV 0 */
900 mr r9,r13
901 GET_PACA(r13)
902 mflr r11
903 mfctr r12
904 li r10,IRQS_ALL_DISABLED
905 stb r10,PACAIRQSOFTMASK(r13)
906#ifdef CONFIG_RELOCATABLE
907 b system_call_vectored_tramp
908#else
909 b system_call_vectored_common
910#endif
911 nop
912
913 /* SCV 1 - 127 */
914 .rept 127
915 mr r9,r13
916 GET_PACA(r13)
917 mflr r11
918 mfctr r12
919 li r10,IRQS_ALL_DISABLED
920 stb r10,PACAIRQSOFTMASK(r13)
921 li r0,-1 /* cause failure */
922#ifdef CONFIG_RELOCATABLE
923 b system_call_vectored_sigill_tramp
924#else
925 b system_call_vectored_sigill
926#endif
927 .endr
928EXC_VIRT_END(system_call_vectored, 0x3000, 0x1000)
929
930// Treat scv vectors as soft-masked, see comment above.
931// Use absolute values rather than labels here, so they don't get relocated,
932// because this code runs unrelocated.
933SOFT_MASK_TABLE(0xc000000000003000, 0xc000000000004000)
934
935#ifdef CONFIG_RELOCATABLE
936TRAMP_VIRT_BEGIN(system_call_vectored_tramp)
937 __LOAD_HANDLER(r10, system_call_vectored_common, virt_trampolines)
938 mtctr r10
939 bctr
940
941TRAMP_VIRT_BEGIN(system_call_vectored_sigill_tramp)
942 __LOAD_HANDLER(r10, system_call_vectored_sigill, virt_trampolines)
943 mtctr r10
944 bctr
945#endif
946
947
948/* No virt vectors corresponding with 0x0..0x100 */
949EXC_VIRT_NONE(0x4000, 0x100)
950
951
952/**
953 * Interrupt 0x100 - System Reset Interrupt (SRESET aka NMI).
954 * This is a non-maskable, asynchronous interrupt always taken in real-mode.
955 * It is caused by:
956 * - Wake from power-saving state, on powernv.
957 * - An NMI from another CPU, triggered by firmware or hypercall.
958 * - As crash/debug signal injected from BMC, firmware or hypervisor.
959 *
960 * Handling:
961 * Power-save wakeup is the only performance critical path, so this is
962 * determined quickly as possible first. In this case volatile registers
963 * can be discarded and SPRs like CFAR don't need to be read.
964 *
965 * If not a powersave wakeup, then it's run as a regular interrupt, however
966 * it uses its own stack and PACA save area to preserve the regular kernel
967 * environment for debugging.
968 *
969 * This interrupt is not maskable, so triggering it when MSR[RI] is clear,
970 * or SCRATCH0 is in use, etc. may cause a crash. It's also not entirely
971 * correct to switch to virtual mode to run the regular interrupt handler
972 * because it might be interrupted when the MMU is in a bad state (e.g., SLB
973 * is clear).
974 *
975 * FWNMI:
976 * PAPR specifies a "fwnmi" facility which sends the sreset to a different
977 * entry point with a different register set up. Some hypervisors will
978 * send the sreset to 0x100 in the guest if it is not fwnmi capable.
979 *
980 * KVM:
981 * Unlike most SRR interrupts, this may be taken by the host while executing
982 * in a guest, so a KVM test is required. KVM will pull the CPU out of guest
983 * mode and then raise the sreset.
984 */
985INT_DEFINE_BEGIN(system_reset)
986 IVEC=0x100
987 IAREA=PACA_EXNMI
988 IVIRT=0 /* no virt entry point */
989 ISTACK=0
990 IKVM_REAL=1
991INT_DEFINE_END(system_reset)
992
993EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
994#ifdef CONFIG_PPC_P7_NAP
995 /*
996 * If running native on arch 2.06 or later, check if we are waking up
997 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
998 * bits 46:47. A non-0 value indicates that we are coming from a power
999 * saving state. The idle wakeup handler initially runs in real mode,
1000 * but we branch to the 0xc000... address so we can turn on relocation
1001 * with mtmsrd later, after SPRs are restored.
1002 *
1003 * Careful to minimise cost for the fast path (idle wakeup) while
1004 * also avoiding clobbering CFAR for the debug path (non-idle).
1005 *
1006 * For the idle wake case volatile registers can be clobbered, which
1007 * is why we use those initially. If it turns out to not be an idle
1008 * wake, carefully put everything back the way it was, so we can use
1009 * common exception macros to handle it.
1010 */
1011BEGIN_FTR_SECTION
1012 SET_SCRATCH0(r13)
1013 GET_PACA(r13)
1014 std r3,PACA_EXNMI+0*8(r13)
1015 std r4,PACA_EXNMI+1*8(r13)
1016 std r5,PACA_EXNMI+2*8(r13)
1017 mfspr r3,SPRN_SRR1
1018 mfocrf r4,0x80
1019 rlwinm. r5,r3,47-31,30,31
1020 bne+ system_reset_idle_wake
1021 /* Not powersave wakeup. Restore regs for regular interrupt handler. */
1022 mtocrf 0x80,r4
1023 ld r3,PACA_EXNMI+0*8(r13)
1024 ld r4,PACA_EXNMI+1*8(r13)
1025 ld r5,PACA_EXNMI+2*8(r13)
1026 GET_SCRATCH0(r13)
1027END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1028#endif
1029
1030 GEN_INT_ENTRY system_reset, virt=0
1031 /*
1032 * In theory, we should not enable relocation here if it was disabled
1033 * in SRR1, because the MMU may not be configured to support it (e.g.,
1034 * SLB may have been cleared). In practice, there should only be a few
1035 * small windows where that's the case, and sreset is considered to
1036 * be dangerous anyway.
1037 */
1038EXC_REAL_END(system_reset, 0x100, 0x100)
1039EXC_VIRT_NONE(0x4100, 0x100)
1040
1041#ifdef CONFIG_PPC_P7_NAP
1042TRAMP_REAL_BEGIN(system_reset_idle_wake)
1043 /* We are waking up from idle, so may clobber any volatile register */
1044 cmpwi cr1,r5,2
1045 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
1046 __LOAD_FAR_HANDLER(r12, DOTSYM(idle_return_gpr_loss), real_trampolines)
1047 mtctr r12
1048 bctr
1049#endif
1050
1051#ifdef CONFIG_PPC_PSERIES
1052/*
1053 * Vectors for the FWNMI option. Share common code.
1054 */
1055TRAMP_REAL_BEGIN(system_reset_fwnmi)
1056 GEN_INT_ENTRY system_reset, virt=0
1057
1058#endif /* CONFIG_PPC_PSERIES */
1059
1060EXC_COMMON_BEGIN(system_reset_common)
1061 __GEN_COMMON_ENTRY system_reset
1062 /*
1063 * Increment paca->in_nmi. When the interrupt entry wrapper later
1064 * enable MSR_RI, then SLB or MCE will be able to recover, but a nested
1065 * NMI will notice in_nmi and not recover because of the use of the NMI
1066 * stack. in_nmi reentrancy is tested in system_reset_exception.
1067 */
1068 lhz r10,PACA_IN_NMI(r13)
1069 addi r10,r10,1
1070 sth r10,PACA_IN_NMI(r13)
1071
1072 mr r10,r1
1073 ld r1,PACA_NMI_EMERG_SP(r13)
1074 subi r1,r1,INT_FRAME_SIZE
1075 __GEN_COMMON_BODY system_reset
1076
1077 addi r3,r1,STACK_INT_FRAME_REGS
1078 bl CFUNC(system_reset_exception)
1079
1080 /* Clear MSR_RI before setting SRR0 and SRR1. */
1081 li r9,0
1082 mtmsrd r9,1
1083
1084 /*
1085 * MSR_RI is clear, now we can decrement paca->in_nmi.
1086 */
1087 lhz r10,PACA_IN_NMI(r13)
1088 subi r10,r10,1
1089 sth r10,PACA_IN_NMI(r13)
1090
1091 kuap_kernel_restore r9, r10
1092 EXCEPTION_RESTORE_REGS
1093 RFI_TO_USER_OR_KERNEL
1094
1095
1096/**
1097 * Interrupt 0x200 - Machine Check Interrupt (MCE).
1098 * This is a non-maskable interrupt always taken in real-mode. It can be
1099 * synchronous or asynchronous, caused by hardware or software, and it may be
1100 * taken in a power-saving state.
1101 *
1102 * Handling:
1103 * Similarly to system reset, this uses its own stack and PACA save area,
1104 * the difference is re-entrancy is allowed on the machine check stack.
1105 *
1106 * machine_check_early is run in real mode, and carefully decodes the
1107 * machine check and tries to handle it (e.g., flush the SLB if there was an
1108 * error detected there), determines if it was recoverable and logs the
1109 * event.
1110 *
1111 * This early code does not "reconcile" irq soft-mask state like SRESET or
1112 * regular interrupts do, so irqs_disabled() among other things may not work
1113 * properly (irq disable/enable already doesn't work because irq tracing can
1114 * not work in real mode).
1115 *
1116 * Then, depending on the execution context when the interrupt is taken, there
1117 * are 3 main actions:
1118 * - Executing in kernel mode. The event is queued with irq_work, which means
1119 * it is handled when it is next safe to do so (i.e., the kernel has enabled
1120 * interrupts), which could be immediately when the interrupt returns. This
1121 * avoids nasty issues like switching to virtual mode when the MMU is in a
1122 * bad state, or when executing OPAL code. (SRESET is exposed to such issues,
1123 * but it has different priorities). Check to see if the CPU was in power
1124 * save, and return via the wake up code if it was.
1125 *
1126 * - Executing in user mode. machine_check_exception is run like a normal
1127 * interrupt handler, which processes the data generated by the early handler.
1128 *
1129 * - Executing in guest mode. The interrupt is run with its KVM test, and
1130 * branches to KVM to deal with. KVM may queue the event for the host
1131 * to report later.
1132 *
1133 * This interrupt is not maskable, so if it triggers when MSR[RI] is clear,
1134 * or SCRATCH0 is in use, it may cause a crash.
1135 *
1136 * KVM:
1137 * See SRESET.
1138 */
1139INT_DEFINE_BEGIN(machine_check_early)
1140 IVEC=0x200
1141 IAREA=PACA_EXMC
1142 IVIRT=0 /* no virt entry point */
1143 IREALMODE_COMMON=1
1144 ISTACK=0
1145 IDAR=1
1146 IDSISR=1
1147 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
1148INT_DEFINE_END(machine_check_early)
1149
1150INT_DEFINE_BEGIN(machine_check)
1151 IVEC=0x200
1152 IAREA=PACA_EXMC
1153 IVIRT=0 /* no virt entry point */
1154 IDAR=1
1155 IDSISR=1
1156 IKVM_REAL=1
1157INT_DEFINE_END(machine_check)
1158
1159EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
1160 EARLY_BOOT_FIXUP
1161 GEN_INT_ENTRY machine_check_early, virt=0
1162EXC_REAL_END(machine_check, 0x200, 0x100)
1163EXC_VIRT_NONE(0x4200, 0x100)
1164
1165#ifdef CONFIG_PPC_PSERIES
1166TRAMP_REAL_BEGIN(machine_check_fwnmi)
1167 /* See comment at machine_check exception, don't turn on RI */
1168 GEN_INT_ENTRY machine_check_early, virt=0
1169#endif
1170
1171#define MACHINE_CHECK_HANDLER_WINDUP \
1172 /* Clear MSR_RI before setting SRR0 and SRR1. */\
1173 li r9,0; \
1174 mtmsrd r9,1; /* Clear MSR_RI */ \
1175 /* Decrement paca->in_mce now RI is clear. */ \
1176 lhz r12,PACA_IN_MCE(r13); \
1177 subi r12,r12,1; \
1178 sth r12,PACA_IN_MCE(r13); \
1179 EXCEPTION_RESTORE_REGS
1180
1181EXC_COMMON_BEGIN(machine_check_early_common)
1182 __GEN_REALMODE_COMMON_ENTRY machine_check_early
1183
1184 /*
1185 * Switch to mc_emergency stack and handle re-entrancy (we limit
1186 * the nested MCE upto level 4 to avoid stack overflow).
1187 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
1188 *
1189 * We use paca->in_mce to check whether this is the first entry or
1190 * nested machine check. We increment paca->in_mce to track nested
1191 * machine checks.
1192 *
1193 * If this is the first entry then set stack pointer to
1194 * paca->mc_emergency_sp, otherwise r1 is already pointing to
1195 * stack frame on mc_emergency stack.
1196 *
1197 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
1198 * checkstop if we get another machine check exception before we do
1199 * rfid with MSR_ME=1.
1200 *
1201 * This interrupt can wake directly from idle. If that is the case,
1202 * the machine check is handled then the idle wakeup code is called
1203 * to restore state.
1204 */
1205 lhz r10,PACA_IN_MCE(r13)
1206 cmpwi r10,0 /* Are we in nested machine check */
1207 cmpwi cr1,r10,MAX_MCE_DEPTH /* Are we at maximum nesting */
1208 addi r10,r10,1 /* increment paca->in_mce */
1209 sth r10,PACA_IN_MCE(r13)
1210
1211 mr r10,r1 /* Save r1 */
1212 bne 1f
1213 /* First machine check entry */
1214 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
12151: /* Limit nested MCE to level 4 to avoid stack overflow */
1216 bgt cr1,unrecoverable_mce /* Check if we hit limit of 4 */
1217 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1218
1219 __GEN_COMMON_BODY machine_check_early
1220
1221BEGIN_FTR_SECTION
1222 bl enable_machine_check
1223END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1224 addi r3,r1,STACK_INT_FRAME_REGS
1225BEGIN_FTR_SECTION
1226 bl CFUNC(machine_check_early_boot)
1227END_FTR_SECTION(0, 1) // nop out after boot
1228 bl CFUNC(machine_check_early)
1229 std r3,RESULT(r1) /* Save result */
1230 ld r12,_MSR(r1)
1231
1232#ifdef CONFIG_PPC_P7_NAP
1233 /*
1234 * Check if thread was in power saving mode. We come here when any
1235 * of the following is true:
1236 * a. thread wasn't in power saving mode
1237 * b. thread was in power saving mode with no state loss,
1238 * supervisor state loss or hypervisor state loss.
1239 *
1240 * Go back to nap/sleep/winkle mode again if (b) is true.
1241 */
1242BEGIN_FTR_SECTION
1243 rlwinm. r11,r12,47-31,30,31
1244 bne machine_check_idle_common
1245END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1246#endif
1247
1248#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1249 /*
1250 * Check if we are coming from guest. If yes, then run the normal
1251 * exception handler which will take the
1252 * machine_check_kvm->kvm_interrupt branch to deliver the MC event
1253 * to guest.
1254 */
1255 lbz r11,HSTATE_IN_GUEST(r13)
1256 cmpwi r11,0 /* Check if coming from guest */
1257 bne mce_deliver /* continue if we are. */
1258#endif
1259
1260 /*
1261 * Check if we are coming from userspace. If yes, then run the normal
1262 * exception handler which will deliver the MC event to this kernel.
1263 */
1264 andi. r11,r12,MSR_PR /* See if coming from user. */
1265 bne mce_deliver /* continue in V mode if we are. */
1266
1267 /*
1268 * At this point we are coming from kernel context.
1269 * Queue up the MCE event and return from the interrupt.
1270 * But before that, check if this is an un-recoverable exception.
1271 * If yes, then stay on emergency stack and panic.
1272 */
1273 andi. r11,r12,MSR_RI
1274 beq unrecoverable_mce
1275
1276 /*
1277 * Check if we have successfully handled/recovered from error, if not
1278 * then stay on emergency stack and panic.
1279 */
1280 ld r3,RESULT(r1) /* Load result */
1281 cmpdi r3,0 /* see if we handled MCE successfully */
1282 beq unrecoverable_mce /* if !handled then panic */
1283
1284 /*
1285 * Return from MC interrupt.
1286 * Queue up the MCE event so that we can log it later, while
1287 * returning from kernel or opal call.
1288 */
1289 bl CFUNC(machine_check_queue_event)
1290 MACHINE_CHECK_HANDLER_WINDUP
1291 RFI_TO_KERNEL
1292
1293mce_deliver:
1294 /*
1295 * This is a host user or guest MCE. Restore all registers, then
1296 * run the "late" handler. For host user, this will run the
1297 * machine_check_exception handler in virtual mode like a normal
1298 * interrupt handler. For guest, this will trigger the KVM test
1299 * and branch to the KVM interrupt similarly to other interrupts.
1300 */
1301BEGIN_FTR_SECTION
1302 ld r10,ORIG_GPR3(r1)
1303 mtspr SPRN_CFAR,r10
1304END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1305 MACHINE_CHECK_HANDLER_WINDUP
1306 GEN_INT_ENTRY machine_check, virt=0
1307
1308EXC_COMMON_BEGIN(machine_check_common)
1309 /*
1310 * Machine check is different because we use a different
1311 * save area: PACA_EXMC instead of PACA_EXGEN.
1312 */
1313 GEN_COMMON machine_check
1314 addi r3,r1,STACK_INT_FRAME_REGS
1315 bl CFUNC(machine_check_exception_async)
1316 b interrupt_return_srr
1317
1318
1319#ifdef CONFIG_PPC_P7_NAP
1320/*
1321 * This is an idle wakeup. Low level machine check has already been
1322 * done. Queue the event then call the idle code to do the wake up.
1323 */
1324EXC_COMMON_BEGIN(machine_check_idle_common)
1325 bl CFUNC(machine_check_queue_event)
1326
1327 /*
1328 * GPR-loss wakeups are relatively straightforward, because the
1329 * idle sleep code has saved all non-volatile registers on its
1330 * own stack, and r1 in PACAR1.
1331 *
1332 * For no-loss wakeups the r1 and lr registers used by the
1333 * early machine check handler have to be restored first. r2 is
1334 * the kernel TOC, so no need to restore it.
1335 *
1336 * Then decrement MCE nesting after finishing with the stack.
1337 */
1338 ld r3,_MSR(r1)
1339 ld r4,_LINK(r1)
1340 ld r1,GPR1(r1)
1341
1342 lhz r11,PACA_IN_MCE(r13)
1343 subi r11,r11,1
1344 sth r11,PACA_IN_MCE(r13)
1345
1346 mtlr r4
1347 rlwinm r10,r3,47-31,30,31
1348 cmpwi cr1,r10,2
1349 bltlr cr1 /* no state loss, return to idle caller with r3=SRR1 */
1350 b idle_return_gpr_loss
1351#endif
1352
1353EXC_COMMON_BEGIN(unrecoverable_mce)
1354 /*
1355 * We are going down. But there are chances that we might get hit by
1356 * another MCE during panic path and we may run into unstable state
1357 * with no way out. Hence, turn ME bit off while going down, so that
1358 * when another MCE is hit during panic path, system will checkstop
1359 * and hypervisor will get restarted cleanly by SP.
1360 */
1361BEGIN_FTR_SECTION
1362 li r10,0 /* clear MSR_RI */
1363 mtmsrd r10,1
1364 bl CFUNC(disable_machine_check)
1365END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1366 ld r10,PACAKMSR(r13)
1367 li r3,MSR_ME
1368 andc r10,r10,r3
1369 mtmsrd r10
1370
1371 lhz r12,PACA_IN_MCE(r13)
1372 subi r12,r12,1
1373 sth r12,PACA_IN_MCE(r13)
1374
1375 /*
1376 * Invoke machine_check_exception to print MCE event and panic.
1377 * This is the NMI version of the handler because we are called from
1378 * the early handler which is a true NMI.
1379 */
1380 addi r3,r1,STACK_INT_FRAME_REGS
1381 bl CFUNC(machine_check_exception)
1382
1383 /*
1384 * We will not reach here. Even if we did, there is no way out.
1385 * Call unrecoverable_exception and die.
1386 */
1387 addi r3,r1,STACK_INT_FRAME_REGS
1388 bl CFUNC(unrecoverable_exception)
1389 b .
1390
1391
1392/**
1393 * Interrupt 0x300 - Data Storage Interrupt (DSI).
1394 * This is a synchronous interrupt generated due to a data access exception,
1395 * e.g., a load orstore which does not have a valid page table entry with
1396 * permissions. DAWR matches also fault here, as do RC updates, and minor misc
1397 * errors e.g., copy/paste, AMO, certain invalid CI accesses, etc.
1398 *
1399 * Handling:
1400 * - Hash MMU
1401 * Go to do_hash_fault, which attempts to fill the HPT from an entry in the
1402 * Linux page table. Hash faults can hit in kernel mode in a fairly
1403 * arbitrary state (e.g., interrupts disabled, locks held) when accessing
1404 * "non-bolted" regions, e.g., vmalloc space. However these should always be
1405 * backed by Linux page table entries.
1406 *
1407 * If no entry is found the Linux page fault handler is invoked (by
1408 * do_hash_fault). Linux page faults can happen in kernel mode due to user
1409 * copy operations of course.
1410 *
1411 * KVM: The KVM HDSI handler may perform a load with MSR[DR]=1 in guest
1412 * MMU context, which may cause a DSI in the host, which must go to the
1413 * KVM handler. MSR[IR] is not enabled, so the real-mode handler will
1414 * always be used regardless of AIL setting.
1415 *
1416 * - Radix MMU
1417 * The hardware loads from the Linux page table directly, so a fault goes
1418 * immediately to Linux page fault.
1419 *
1420 * Conditions like DAWR match are handled on the way in to Linux page fault.
1421 */
1422INT_DEFINE_BEGIN(data_access)
1423 IVEC=0x300
1424 IDAR=1
1425 IDSISR=1
1426 IKVM_REAL=1
1427INT_DEFINE_END(data_access)
1428
1429EXC_REAL_BEGIN(data_access, 0x300, 0x80)
1430 GEN_INT_ENTRY data_access, virt=0
1431EXC_REAL_END(data_access, 0x300, 0x80)
1432EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
1433 GEN_INT_ENTRY data_access, virt=1
1434EXC_VIRT_END(data_access, 0x4300, 0x80)
1435EXC_COMMON_BEGIN(data_access_common)
1436 GEN_COMMON data_access
1437 ld r4,_DSISR(r1)
1438 addi r3,r1,STACK_INT_FRAME_REGS
1439 andis. r0,r4,DSISR_DABRMATCH@h
1440 bne- 1f
1441#ifdef CONFIG_PPC_64S_HASH_MMU
1442BEGIN_MMU_FTR_SECTION
1443 bl CFUNC(do_hash_fault)
1444MMU_FTR_SECTION_ELSE
1445 bl CFUNC(do_page_fault)
1446ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1447#else
1448 bl CFUNC(do_page_fault)
1449#endif
1450 b interrupt_return_srr
1451
14521: bl CFUNC(do_break)
1453 /*
1454 * do_break() may have changed the NV GPRS while handling a breakpoint.
1455 * If so, we need to restore them with their updated values.
1456 */
1457 HANDLER_RESTORE_NVGPRS()
1458 b interrupt_return_srr
1459
1460
1461/**
1462 * Interrupt 0x380 - Data Segment Interrupt (DSLB).
1463 * This is a synchronous interrupt in response to an MMU fault missing SLB
1464 * entry for HPT, or an address outside RPT translation range.
1465 *
1466 * Handling:
1467 * - HPT:
1468 * This refills the SLB, or reports an access fault similarly to a bad page
1469 * fault. When coming from user-mode, the SLB handler may access any kernel
1470 * data, though it may itself take a DSLB. When coming from kernel mode,
1471 * recursive faults must be avoided so access is restricted to the kernel
1472 * image text/data, kernel stack, and any data allocated below
1473 * ppc64_bolted_size (first segment). The kernel handler must avoid stomping
1474 * on user-handler data structures.
1475 *
1476 * KVM: Same as 0x300, DSLB must test for KVM guest.
1477 */
1478INT_DEFINE_BEGIN(data_access_slb)
1479 IVEC=0x380
1480 IDAR=1
1481 IKVM_REAL=1
1482INT_DEFINE_END(data_access_slb)
1483
1484EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
1485 GEN_INT_ENTRY data_access_slb, virt=0
1486EXC_REAL_END(data_access_slb, 0x380, 0x80)
1487EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
1488 GEN_INT_ENTRY data_access_slb, virt=1
1489EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
1490EXC_COMMON_BEGIN(data_access_slb_common)
1491 GEN_COMMON data_access_slb
1492#ifdef CONFIG_PPC_64S_HASH_MMU
1493BEGIN_MMU_FTR_SECTION
1494 /* HPT case, do SLB fault */
1495 addi r3,r1,STACK_INT_FRAME_REGS
1496 bl CFUNC(do_slb_fault)
1497 cmpdi r3,0
1498 bne- 1f
1499 b fast_interrupt_return_srr
15001: /* Error case */
1501MMU_FTR_SECTION_ELSE
1502 /* Radix case, access is outside page table range */
1503 li r3,-EFAULT
1504ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1505#else
1506 li r3,-EFAULT
1507#endif
1508 std r3,RESULT(r1)
1509 addi r3,r1,STACK_INT_FRAME_REGS
1510 bl CFUNC(do_bad_segment_interrupt)
1511 b interrupt_return_srr
1512
1513
1514/**
1515 * Interrupt 0x400 - Instruction Storage Interrupt (ISI).
1516 * This is a synchronous interrupt in response to an MMU fault due to an
1517 * instruction fetch.
1518 *
1519 * Handling:
1520 * Similar to DSI, though in response to fetch. The faulting address is found
1521 * in SRR0 (rather than DAR), and status in SRR1 (rather than DSISR).
1522 */
1523INT_DEFINE_BEGIN(instruction_access)
1524 IVEC=0x400
1525 IISIDE=1
1526 IDAR=1
1527 IDSISR=1
1528#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1529 IKVM_REAL=1
1530#endif
1531INT_DEFINE_END(instruction_access)
1532
1533EXC_REAL_BEGIN(instruction_access, 0x400, 0x80)
1534 GEN_INT_ENTRY instruction_access, virt=0
1535EXC_REAL_END(instruction_access, 0x400, 0x80)
1536EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80)
1537 GEN_INT_ENTRY instruction_access, virt=1
1538EXC_VIRT_END(instruction_access, 0x4400, 0x80)
1539EXC_COMMON_BEGIN(instruction_access_common)
1540 GEN_COMMON instruction_access
1541 addi r3,r1,STACK_INT_FRAME_REGS
1542#ifdef CONFIG_PPC_64S_HASH_MMU
1543BEGIN_MMU_FTR_SECTION
1544 bl CFUNC(do_hash_fault)
1545MMU_FTR_SECTION_ELSE
1546 bl CFUNC(do_page_fault)
1547ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1548#else
1549 bl CFUNC(do_page_fault)
1550#endif
1551 b interrupt_return_srr
1552
1553
1554/**
1555 * Interrupt 0x480 - Instruction Segment Interrupt (ISLB).
1556 * This is a synchronous interrupt in response to an MMU fault due to an
1557 * instruction fetch.
1558 *
1559 * Handling:
1560 * Similar to DSLB, though in response to fetch. The faulting address is found
1561 * in SRR0 (rather than DAR).
1562 */
1563INT_DEFINE_BEGIN(instruction_access_slb)
1564 IVEC=0x480
1565 IISIDE=1
1566 IDAR=1
1567#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1568 IKVM_REAL=1
1569#endif
1570INT_DEFINE_END(instruction_access_slb)
1571
1572EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
1573 GEN_INT_ENTRY instruction_access_slb, virt=0
1574EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
1575EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
1576 GEN_INT_ENTRY instruction_access_slb, virt=1
1577EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
1578EXC_COMMON_BEGIN(instruction_access_slb_common)
1579 GEN_COMMON instruction_access_slb
1580#ifdef CONFIG_PPC_64S_HASH_MMU
1581BEGIN_MMU_FTR_SECTION
1582 /* HPT case, do SLB fault */
1583 addi r3,r1,STACK_INT_FRAME_REGS
1584 bl CFUNC(do_slb_fault)
1585 cmpdi r3,0
1586 bne- 1f
1587 b fast_interrupt_return_srr
15881: /* Error case */
1589MMU_FTR_SECTION_ELSE
1590 /* Radix case, access is outside page table range */
1591 li r3,-EFAULT
1592ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1593#else
1594 li r3,-EFAULT
1595#endif
1596 std r3,RESULT(r1)
1597 addi r3,r1,STACK_INT_FRAME_REGS
1598 bl CFUNC(do_bad_segment_interrupt)
1599 b interrupt_return_srr
1600
1601
1602/**
1603 * Interrupt 0x500 - External Interrupt.
1604 * This is an asynchronous maskable interrupt in response to an "external
1605 * exception" from the interrupt controller or hypervisor (e.g., device
1606 * interrupt). It is maskable in hardware by clearing MSR[EE], and
1607 * soft-maskable with IRQS_DISABLED mask (i.e., local_irq_disable()).
1608 *
1609 * When running in HV mode, Linux sets up the LPCR[LPES] bit such that
1610 * interrupts are delivered with HSRR registers, guests use SRRs, which
1611 * reqiures IHSRR_IF_HVMODE.
1612 *
1613 * On bare metal POWER9 and later, Linux sets the LPCR[HVICE] bit such that
1614 * external interrupts are delivered as Hypervisor Virtualization Interrupts
1615 * rather than External Interrupts.
1616 *
1617 * Handling:
1618 * This calls into Linux IRQ handler. NVGPRs are not saved to reduce overhead,
1619 * because registers at the time of the interrupt are not so important as it is
1620 * asynchronous.
1621 *
1622 * If soft masked, the masked handler will note the pending interrupt for
1623 * replay, and clear MSR[EE] in the interrupted context.
1624 *
1625 * CFAR is not required because this is an asynchronous interrupt that in
1626 * general won't have much bearing on the state of the CPU, with the possible
1627 * exception of crash/debug IPIs, but those are generally moving to use SRESET
1628 * IPIs. Unless this is an HV interrupt and KVM HV is possible, in which case
1629 * it may be exiting the guest and need CFAR to be saved.
1630 */
1631INT_DEFINE_BEGIN(hardware_interrupt)
1632 IVEC=0x500
1633 IHSRR_IF_HVMODE=1
1634 IMASK=IRQS_DISABLED
1635 IKVM_REAL=1
1636 IKVM_VIRT=1
1637 ICFAR=0
1638#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
1639 ICFAR_IF_HVMODE=1
1640#endif
1641INT_DEFINE_END(hardware_interrupt)
1642
1643EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
1644 GEN_INT_ENTRY hardware_interrupt, virt=0
1645EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
1646EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
1647 GEN_INT_ENTRY hardware_interrupt, virt=1
1648EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
1649EXC_COMMON_BEGIN(hardware_interrupt_common)
1650 GEN_COMMON hardware_interrupt
1651 addi r3,r1,STACK_INT_FRAME_REGS
1652 bl CFUNC(do_IRQ)
1653 BEGIN_FTR_SECTION
1654 b interrupt_return_hsrr
1655 FTR_SECTION_ELSE
1656 b interrupt_return_srr
1657 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1658
1659
1660/**
1661 * Interrupt 0x600 - Alignment Interrupt
1662 * This is a synchronous interrupt in response to data alignment fault.
1663 */
1664INT_DEFINE_BEGIN(alignment)
1665 IVEC=0x600
1666 IDAR=1
1667 IDSISR=1
1668#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1669 IKVM_REAL=1
1670#endif
1671INT_DEFINE_END(alignment)
1672
1673EXC_REAL_BEGIN(alignment, 0x600, 0x100)
1674 GEN_INT_ENTRY alignment, virt=0
1675EXC_REAL_END(alignment, 0x600, 0x100)
1676EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
1677 GEN_INT_ENTRY alignment, virt=1
1678EXC_VIRT_END(alignment, 0x4600, 0x100)
1679EXC_COMMON_BEGIN(alignment_common)
1680 GEN_COMMON alignment
1681 addi r3,r1,STACK_INT_FRAME_REGS
1682 bl CFUNC(alignment_exception)
1683 HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
1684 b interrupt_return_srr
1685
1686
1687/**
1688 * Interrupt 0x700 - Program Interrupt (program check).
1689 * This is a synchronous interrupt in response to various instruction faults:
1690 * traps, privilege errors, TM errors, floating point exceptions.
1691 *
1692 * Handling:
1693 * This interrupt may use the "emergency stack" in some cases when being taken
1694 * from kernel context, which complicates handling.
1695 */
1696INT_DEFINE_BEGIN(program_check)
1697 IVEC=0x700
1698#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1699 IKVM_REAL=1
1700#endif
1701INT_DEFINE_END(program_check)
1702
1703EXC_REAL_BEGIN(program_check, 0x700, 0x100)
1704 EARLY_BOOT_FIXUP
1705 GEN_INT_ENTRY program_check, virt=0
1706EXC_REAL_END(program_check, 0x700, 0x100)
1707EXC_VIRT_BEGIN(program_check, 0x4700, 0x100)
1708 GEN_INT_ENTRY program_check, virt=1
1709EXC_VIRT_END(program_check, 0x4700, 0x100)
1710EXC_COMMON_BEGIN(program_check_common)
1711 __GEN_COMMON_ENTRY program_check
1712
1713 /*
1714 * It's possible to receive a TM Bad Thing type program check with
1715 * userspace register values (in particular r1), but with SRR1 reporting
1716 * that we came from the kernel. Normally that would confuse the bad
1717 * stack logic, and we would report a bad kernel stack pointer. Instead
1718 * we switch to the emergency stack if we're taking a TM Bad Thing from
1719 * the kernel.
1720 */
1721
1722 andi. r10,r12,MSR_PR
1723 bne .Lnormal_stack /* If userspace, go normal path */
1724
1725 andis. r10,r12,(SRR1_PROGTM)@h
1726 bne .Lemergency_stack /* If TM, emergency */
1727
1728 cmpdi r1,-INT_FRAME_SIZE /* check if r1 is in userspace */
1729 blt .Lnormal_stack /* normal path if not */
1730
1731 /* Use the emergency stack */
1732.Lemergency_stack:
1733 andi. r10,r12,MSR_PR /* Set CR0 correctly for label */
1734 /* 3 in EXCEPTION_PROLOG_COMMON */
1735 mr r10,r1 /* Save r1 */
1736 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1737 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1738 __ISTACK(program_check)=0
1739 __GEN_COMMON_BODY program_check
1740 b .Ldo_program_check
1741
1742.Lnormal_stack:
1743 __ISTACK(program_check)=1
1744 __GEN_COMMON_BODY program_check
1745
1746.Ldo_program_check:
1747 addi r3,r1,STACK_INT_FRAME_REGS
1748 bl CFUNC(program_check_exception)
1749 HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
1750 b interrupt_return_srr
1751
1752
1753/*
1754 * Interrupt 0x800 - Floating-Point Unavailable Interrupt.
1755 * This is a synchronous interrupt in response to executing an fp instruction
1756 * with MSR[FP]=0.
1757 *
1758 * Handling:
1759 * This will load FP registers and enable the FP bit if coming from userspace,
1760 * otherwise report a bad kernel use of FP.
1761 */
1762INT_DEFINE_BEGIN(fp_unavailable)
1763 IVEC=0x800
1764#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1765 IKVM_REAL=1
1766#endif
1767 IMSR_R12=1
1768INT_DEFINE_END(fp_unavailable)
1769
1770EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100)
1771 GEN_INT_ENTRY fp_unavailable, virt=0
1772EXC_REAL_END(fp_unavailable, 0x800, 0x100)
1773EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100)
1774 GEN_INT_ENTRY fp_unavailable, virt=1
1775EXC_VIRT_END(fp_unavailable, 0x4800, 0x100)
1776EXC_COMMON_BEGIN(fp_unavailable_common)
1777 GEN_COMMON fp_unavailable
1778 bne 1f /* if from user, just load it up */
1779 addi r3,r1,STACK_INT_FRAME_REGS
1780 bl CFUNC(kernel_fp_unavailable_exception)
17810: trap
1782 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
17831:
1784#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1785BEGIN_FTR_SECTION
1786 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1787 * transaction), go do TM stuff
1788 */
1789 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1790 bne- 2f
1791END_FTR_SECTION_IFSET(CPU_FTR_TM)
1792#endif
1793 bl CFUNC(load_up_fpu)
1794 b fast_interrupt_return_srr
1795#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
17962: /* User process was in a transaction */
1797 addi r3,r1,STACK_INT_FRAME_REGS
1798 bl CFUNC(fp_unavailable_tm)
1799 b interrupt_return_srr
1800#endif
1801
1802
1803/**
1804 * Interrupt 0x900 - Decrementer Interrupt.
1805 * This is an asynchronous interrupt in response to a decrementer exception
1806 * (e.g., DEC has wrapped below zero). It is maskable in hardware by clearing
1807 * MSR[EE], and soft-maskable with IRQS_DISABLED mask (i.e.,
1808 * local_irq_disable()).
1809 *
1810 * Handling:
1811 * This calls into Linux timer handler. NVGPRs are not saved (see 0x500).
1812 *
1813 * If soft masked, the masked handler will note the pending interrupt for
1814 * replay, and bump the decrementer to a high value, leaving MSR[EE] enabled
1815 * in the interrupted context.
1816 * If PPC_WATCHDOG is configured, the soft masked handler will actually set
1817 * things back up to run soft_nmi_interrupt as a regular interrupt handler
1818 * on the emergency stack.
1819 *
1820 * CFAR is not required because this is asynchronous (see hardware_interrupt).
1821 * A watchdog interrupt may like to have CFAR, but usually the interesting
1822 * branch is long gone by that point (e.g., infinite loop).
1823 */
1824INT_DEFINE_BEGIN(decrementer)
1825 IVEC=0x900
1826 IMASK=IRQS_DISABLED
1827#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1828 IKVM_REAL=1
1829#endif
1830 ICFAR=0
1831INT_DEFINE_END(decrementer)
1832
1833EXC_REAL_BEGIN(decrementer, 0x900, 0x80)
1834 GEN_INT_ENTRY decrementer, virt=0
1835EXC_REAL_END(decrementer, 0x900, 0x80)
1836EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80)
1837 GEN_INT_ENTRY decrementer, virt=1
1838EXC_VIRT_END(decrementer, 0x4900, 0x80)
1839EXC_COMMON_BEGIN(decrementer_common)
1840 GEN_COMMON decrementer
1841 addi r3,r1,STACK_INT_FRAME_REGS
1842 bl CFUNC(timer_interrupt)
1843 b interrupt_return_srr
1844
1845
1846/**
1847 * Interrupt 0x980 - Hypervisor Decrementer Interrupt.
1848 * This is an asynchronous interrupt, similar to 0x900 but for the HDEC
1849 * register.
1850 *
1851 * Handling:
1852 * Linux does not use this outside KVM where it's used to keep a host timer
1853 * while the guest is given control of DEC. It should normally be caught by
1854 * the KVM test and routed there.
1855 */
1856INT_DEFINE_BEGIN(hdecrementer)
1857 IVEC=0x980
1858 IHSRR=1
1859 ISTACK=0
1860 IKVM_REAL=1
1861 IKVM_VIRT=1
1862INT_DEFINE_END(hdecrementer)
1863
1864EXC_REAL_BEGIN(hdecrementer, 0x980, 0x80)
1865 GEN_INT_ENTRY hdecrementer, virt=0
1866EXC_REAL_END(hdecrementer, 0x980, 0x80)
1867EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80)
1868 GEN_INT_ENTRY hdecrementer, virt=1
1869EXC_VIRT_END(hdecrementer, 0x4980, 0x80)
1870EXC_COMMON_BEGIN(hdecrementer_common)
1871 __GEN_COMMON_ENTRY hdecrementer
1872 /*
1873 * Hypervisor decrementer interrupts not caught by the KVM test
1874 * shouldn't occur but are sometimes left pending on exit from a KVM
1875 * guest. We don't need to do anything to clear them, as they are
1876 * edge-triggered.
1877 *
1878 * Be careful to avoid touching the kernel stack.
1879 */
1880 li r10,0
1881 stb r10,PACAHSRR_VALID(r13)
1882 ld r10,PACA_EXGEN+EX_CTR(r13)
1883 mtctr r10
1884 mtcrf 0x80,r9
1885 ld r9,PACA_EXGEN+EX_R9(r13)
1886 ld r10,PACA_EXGEN+EX_R10(r13)
1887 ld r11,PACA_EXGEN+EX_R11(r13)
1888 ld r12,PACA_EXGEN+EX_R12(r13)
1889 ld r13,PACA_EXGEN+EX_R13(r13)
1890 HRFI_TO_KERNEL
1891
1892
1893/**
1894 * Interrupt 0xa00 - Directed Privileged Doorbell Interrupt.
1895 * This is an asynchronous interrupt in response to a msgsndp doorbell.
1896 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
1897 * IRQS_DISABLED mask (i.e., local_irq_disable()).
1898 *
1899 * Handling:
1900 * Guests may use this for IPIs between threads in a core if the
1901 * hypervisor supports it. NVGPRS are not saved (see 0x500).
1902 *
1903 * If soft masked, the masked handler will note the pending interrupt for
1904 * replay, leaving MSR[EE] enabled in the interrupted context because the
1905 * doorbells are edge triggered.
1906 *
1907 * CFAR is not required, similarly to hardware_interrupt.
1908 */
1909INT_DEFINE_BEGIN(doorbell_super)
1910 IVEC=0xa00
1911 IMASK=IRQS_DISABLED
1912#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1913 IKVM_REAL=1
1914#endif
1915 ICFAR=0
1916INT_DEFINE_END(doorbell_super)
1917
1918EXC_REAL_BEGIN(doorbell_super, 0xa00, 0x100)
1919 GEN_INT_ENTRY doorbell_super, virt=0
1920EXC_REAL_END(doorbell_super, 0xa00, 0x100)
1921EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100)
1922 GEN_INT_ENTRY doorbell_super, virt=1
1923EXC_VIRT_END(doorbell_super, 0x4a00, 0x100)
1924EXC_COMMON_BEGIN(doorbell_super_common)
1925 GEN_COMMON doorbell_super
1926 addi r3,r1,STACK_INT_FRAME_REGS
1927#ifdef CONFIG_PPC_DOORBELL
1928 bl CFUNC(doorbell_exception)
1929#else
1930 bl CFUNC(unknown_async_exception)
1931#endif
1932 b interrupt_return_srr
1933
1934
1935EXC_REAL_NONE(0xb00, 0x100)
1936EXC_VIRT_NONE(0x4b00, 0x100)
1937
1938/**
1939 * Interrupt 0xc00 - System Call Interrupt (syscall, hcall).
1940 * This is a synchronous interrupt invoked with the "sc" instruction. The
1941 * system call is invoked with "sc 0" and does not alter the HV bit, so it
1942 * is directed to the currently running OS. The hypercall is invoked with
1943 * "sc 1" and it sets HV=1, so it elevates to hypervisor.
1944 *
1945 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
1946 * 0x4c00 virtual mode.
1947 *
1948 * Handling:
1949 * If the KVM test fires then it was due to a hypercall and is accordingly
1950 * routed to KVM. Otherwise this executes a normal Linux system call.
1951 *
1952 * Call convention:
1953 *
1954 * syscall and hypercalls register conventions are documented in
1955 * Documentation/arch/powerpc/syscall64-abi.rst and
1956 * Documentation/arch/powerpc/papr_hcalls.rst respectively.
1957 *
1958 * The intersection of volatile registers that don't contain possible
1959 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
1960 * without saving, though xer is not a good idea to use, as hardware may
1961 * interpret some bits so it may be costly to change them.
1962 */
1963INT_DEFINE_BEGIN(system_call)
1964 IVEC=0xc00
1965 IKVM_REAL=1
1966 IKVM_VIRT=1
1967 ICFAR=0
1968INT_DEFINE_END(system_call)
1969
1970.macro SYSTEM_CALL virt
1971#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1972 /*
1973 * There is a little bit of juggling to get syscall and hcall
1974 * working well. Save r13 in ctr to avoid using SPRG scratch
1975 * register.
1976 *
1977 * Userspace syscalls have already saved the PPR, hcalls must save
1978 * it before setting HMT_MEDIUM.
1979 */
1980 mtctr r13
1981 GET_PACA(r13)
1982 std r10,PACA_EXGEN+EX_R10(r13)
1983 INTERRUPT_TO_KERNEL
1984 KVMTEST system_call kvm_hcall /* uses r10, branch to kvm_hcall */
1985 mfctr r9
1986#else
1987 mr r9,r13
1988 GET_PACA(r13)
1989 INTERRUPT_TO_KERNEL
1990#endif
1991
1992#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1993BEGIN_FTR_SECTION
1994 cmpdi r0,0x1ebe
1995 beq- 1f
1996END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
1997#endif
1998
1999 /* We reach here with PACA in r13, r13 in r9. */
2000 mfspr r11,SPRN_SRR0
2001 mfspr r12,SPRN_SRR1
2002
2003 HMT_MEDIUM
2004
2005 .if ! \virt
2006 __LOAD_HANDLER(r10, system_call_common_real, real_vectors)
2007 mtctr r10
2008 bctr
2009 .else
2010#ifdef CONFIG_RELOCATABLE
2011 __LOAD_HANDLER(r10, system_call_common, virt_vectors)
2012 mtctr r10
2013 bctr
2014#else
2015 b system_call_common
2016#endif
2017 .endif
2018
2019#ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
2020 /* Fast LE/BE switch system call */
20211: mfspr r12,SPRN_SRR1
2022 xori r12,r12,MSR_LE
2023 mtspr SPRN_SRR1,r12
2024 mr r13,r9
2025 RFI_TO_USER /* return to userspace */
2026 b . /* prevent speculative execution */
2027#endif
2028.endm
2029
2030EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
2031 SYSTEM_CALL 0
2032EXC_REAL_END(system_call, 0xc00, 0x100)
2033EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
2034 SYSTEM_CALL 1
2035EXC_VIRT_END(system_call, 0x4c00, 0x100)
2036
2037#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
2038TRAMP_REAL_BEGIN(kvm_hcall)
2039 std r9,PACA_EXGEN+EX_R9(r13)
2040 std r11,PACA_EXGEN+EX_R11(r13)
2041 std r12,PACA_EXGEN+EX_R12(r13)
2042 mfcr r9
2043 mfctr r10
2044 std r10,PACA_EXGEN+EX_R13(r13)
2045 li r10,0
2046 std r10,PACA_EXGEN+EX_CFAR(r13)
2047 std r10,PACA_EXGEN+EX_CTR(r13)
2048 /*
2049 * Save the PPR (on systems that support it) before changing to
2050 * HMT_MEDIUM. That allows the KVM code to save that value into the
2051 * guest state (it is the guest's PPR value).
2052 */
2053BEGIN_FTR_SECTION
2054 mfspr r10,SPRN_PPR
2055 std r10,PACA_EXGEN+EX_PPR(r13)
2056END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
2057
2058 HMT_MEDIUM
2059
2060#ifdef CONFIG_RELOCATABLE
2061 /*
2062 * Requires __LOAD_FAR_HANDLER beause kvmppc_hcall lives
2063 * outside the head section.
2064 */
2065 __LOAD_FAR_HANDLER(r10, kvmppc_hcall, real_trampolines)
2066 mtctr r10
2067 bctr
2068#else
2069 b kvmppc_hcall
2070#endif
2071#endif
2072
2073/**
2074 * Interrupt 0xd00 - Trace Interrupt.
2075 * This is a synchronous interrupt in response to instruction step or
2076 * breakpoint faults.
2077 */
2078INT_DEFINE_BEGIN(single_step)
2079 IVEC=0xd00
2080#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2081 IKVM_REAL=1
2082#endif
2083INT_DEFINE_END(single_step)
2084
2085EXC_REAL_BEGIN(single_step, 0xd00, 0x100)
2086 GEN_INT_ENTRY single_step, virt=0
2087EXC_REAL_END(single_step, 0xd00, 0x100)
2088EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100)
2089 GEN_INT_ENTRY single_step, virt=1
2090EXC_VIRT_END(single_step, 0x4d00, 0x100)
2091EXC_COMMON_BEGIN(single_step_common)
2092 GEN_COMMON single_step
2093 addi r3,r1,STACK_INT_FRAME_REGS
2094 bl CFUNC(single_step_exception)
2095 b interrupt_return_srr
2096
2097
2098/**
2099 * Interrupt 0xe00 - Hypervisor Data Storage Interrupt (HDSI).
2100 * This is a synchronous interrupt in response to an MMU fault caused by a
2101 * guest data access.
2102 *
2103 * Handling:
2104 * This should always get routed to KVM. In radix MMU mode, this is caused
2105 * by a guest nested radix access that can't be performed due to the
2106 * partition scope page table. In hash mode, this can be caused by guests
2107 * running with translation disabled (virtual real mode) or with VPM enabled.
2108 * KVM will update the page table structures or disallow the access.
2109 */
2110INT_DEFINE_BEGIN(h_data_storage)
2111 IVEC=0xe00
2112 IHSRR=1
2113 IDAR=1
2114 IDSISR=1
2115 IKVM_REAL=1
2116 IKVM_VIRT=1
2117INT_DEFINE_END(h_data_storage)
2118
2119EXC_REAL_BEGIN(h_data_storage, 0xe00, 0x20)
2120 GEN_INT_ENTRY h_data_storage, virt=0, ool=1
2121EXC_REAL_END(h_data_storage, 0xe00, 0x20)
2122EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20)
2123 GEN_INT_ENTRY h_data_storage, virt=1, ool=1
2124EXC_VIRT_END(h_data_storage, 0x4e00, 0x20)
2125EXC_COMMON_BEGIN(h_data_storage_common)
2126 GEN_COMMON h_data_storage
2127 addi r3,r1,STACK_INT_FRAME_REGS
2128BEGIN_MMU_FTR_SECTION
2129 bl CFUNC(do_bad_page_fault_segv)
2130MMU_FTR_SECTION_ELSE
2131 bl CFUNC(unknown_exception)
2132ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
2133 b interrupt_return_hsrr
2134
2135
2136/**
2137 * Interrupt 0xe20 - Hypervisor Instruction Storage Interrupt (HISI).
2138 * This is a synchronous interrupt in response to an MMU fault caused by a
2139 * guest instruction fetch, similar to HDSI.
2140 */
2141INT_DEFINE_BEGIN(h_instr_storage)
2142 IVEC=0xe20
2143 IHSRR=1
2144 IKVM_REAL=1
2145 IKVM_VIRT=1
2146INT_DEFINE_END(h_instr_storage)
2147
2148EXC_REAL_BEGIN(h_instr_storage, 0xe20, 0x20)
2149 GEN_INT_ENTRY h_instr_storage, virt=0, ool=1
2150EXC_REAL_END(h_instr_storage, 0xe20, 0x20)
2151EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20)
2152 GEN_INT_ENTRY h_instr_storage, virt=1, ool=1
2153EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20)
2154EXC_COMMON_BEGIN(h_instr_storage_common)
2155 GEN_COMMON h_instr_storage
2156 addi r3,r1,STACK_INT_FRAME_REGS
2157 bl CFUNC(unknown_exception)
2158 b interrupt_return_hsrr
2159
2160
2161/**
2162 * Interrupt 0xe40 - Hypervisor Emulation Assistance Interrupt.
2163 */
2164INT_DEFINE_BEGIN(emulation_assist)
2165 IVEC=0xe40
2166 IHSRR=1
2167 IKVM_REAL=1
2168 IKVM_VIRT=1
2169INT_DEFINE_END(emulation_assist)
2170
2171EXC_REAL_BEGIN(emulation_assist, 0xe40, 0x20)
2172 GEN_INT_ENTRY emulation_assist, virt=0, ool=1
2173EXC_REAL_END(emulation_assist, 0xe40, 0x20)
2174EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20)
2175 GEN_INT_ENTRY emulation_assist, virt=1, ool=1
2176EXC_VIRT_END(emulation_assist, 0x4e40, 0x20)
2177EXC_COMMON_BEGIN(emulation_assist_common)
2178 GEN_COMMON emulation_assist
2179 addi r3,r1,STACK_INT_FRAME_REGS
2180 bl CFUNC(emulation_assist_interrupt)
2181 HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
2182 b interrupt_return_hsrr
2183
2184
2185/**
2186 * Interrupt 0xe60 - Hypervisor Maintenance Interrupt (HMI).
2187 * This is an asynchronous interrupt caused by a Hypervisor Maintenance
2188 * Exception. It is always taken in real mode but uses HSRR registers
2189 * unlike SRESET and MCE.
2190 *
2191 * It is maskable in hardware by clearing MSR[EE], and partially soft-maskable
2192 * with IRQS_DISABLED mask (i.e., local_irq_disable()).
2193 *
2194 * Handling:
2195 * This is a special case, this is handled similarly to machine checks, with an
2196 * initial real mode handler that is not soft-masked, which attempts to fix the
2197 * problem. Then a regular handler which is soft-maskable and reports the
2198 * problem.
2199 *
2200 * The emergency stack is used for the early real mode handler.
2201 *
2202 * XXX: unclear why MCE and HMI schemes could not be made common, e.g.,
2203 * either use soft-masking for the MCE, or use irq_work for the HMI.
2204 *
2205 * KVM:
2206 * Unlike MCE, this calls into KVM without calling the real mode handler
2207 * first.
2208 */
2209INT_DEFINE_BEGIN(hmi_exception_early)
2210 IVEC=0xe60
2211 IHSRR=1
2212 IREALMODE_COMMON=1
2213 ISTACK=0
2214 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
2215 IKVM_REAL=1
2216INT_DEFINE_END(hmi_exception_early)
2217
2218INT_DEFINE_BEGIN(hmi_exception)
2219 IVEC=0xe60
2220 IHSRR=1
2221 IMASK=IRQS_DISABLED
2222 IKVM_REAL=1
2223INT_DEFINE_END(hmi_exception)
2224
2225EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20)
2226 GEN_INT_ENTRY hmi_exception_early, virt=0, ool=1
2227EXC_REAL_END(hmi_exception, 0xe60, 0x20)
2228EXC_VIRT_NONE(0x4e60, 0x20)
2229
2230EXC_COMMON_BEGIN(hmi_exception_early_common)
2231 __GEN_REALMODE_COMMON_ENTRY hmi_exception_early
2232
2233 mr r10,r1 /* Save r1 */
2234 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
2235 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
2236
2237 __GEN_COMMON_BODY hmi_exception_early
2238
2239 addi r3,r1,STACK_INT_FRAME_REGS
2240 bl CFUNC(hmi_exception_realmode)
2241 cmpdi cr0,r3,0
2242 bne 1f
2243
2244 EXCEPTION_RESTORE_REGS hsrr=1
2245 HRFI_TO_USER_OR_KERNEL
2246
22471:
2248 /*
2249 * Go to virtual mode and pull the HMI event information from
2250 * firmware.
2251 */
2252 EXCEPTION_RESTORE_REGS hsrr=1
2253 GEN_INT_ENTRY hmi_exception, virt=0
2254
2255EXC_COMMON_BEGIN(hmi_exception_common)
2256 GEN_COMMON hmi_exception
2257 addi r3,r1,STACK_INT_FRAME_REGS
2258 bl CFUNC(handle_hmi_exception)
2259 b interrupt_return_hsrr
2260
2261
2262/**
2263 * Interrupt 0xe80 - Directed Hypervisor Doorbell Interrupt.
2264 * This is an asynchronous interrupt in response to a msgsnd doorbell.
2265 * Similar to the 0xa00 doorbell but for host rather than guest.
2266 *
2267 * CFAR is not required (similar to doorbell_interrupt), unless KVM HV
2268 * is enabled, in which case it may be a guest exit. Most PowerNV kernels
2269 * include KVM support so it would be nice if this could be dynamically
2270 * patched out if KVM was not currently running any guests.
2271 */
2272INT_DEFINE_BEGIN(h_doorbell)
2273 IVEC=0xe80
2274 IHSRR=1
2275 IMASK=IRQS_DISABLED
2276 IKVM_REAL=1
2277 IKVM_VIRT=1
2278#ifndef CONFIG_KVM_BOOK3S_HV_POSSIBLE
2279 ICFAR=0
2280#endif
2281INT_DEFINE_END(h_doorbell)
2282
2283EXC_REAL_BEGIN(h_doorbell, 0xe80, 0x20)
2284 GEN_INT_ENTRY h_doorbell, virt=0, ool=1
2285EXC_REAL_END(h_doorbell, 0xe80, 0x20)
2286EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20)
2287 GEN_INT_ENTRY h_doorbell, virt=1, ool=1
2288EXC_VIRT_END(h_doorbell, 0x4e80, 0x20)
2289EXC_COMMON_BEGIN(h_doorbell_common)
2290 GEN_COMMON h_doorbell
2291 addi r3,r1,STACK_INT_FRAME_REGS
2292#ifdef CONFIG_PPC_DOORBELL
2293 bl CFUNC(doorbell_exception)
2294#else
2295 bl CFUNC(unknown_async_exception)
2296#endif
2297 b interrupt_return_hsrr
2298
2299
2300/**
2301 * Interrupt 0xea0 - Hypervisor Virtualization Interrupt.
2302 * This is an asynchronous interrupt in response to an "external exception".
2303 * Similar to 0x500 but for host only.
2304 *
2305 * Like h_doorbell, CFAR is only required for KVM HV because this can be
2306 * a guest exit.
2307 */
2308INT_DEFINE_BEGIN(h_virt_irq)
2309 IVEC=0xea0
2310 IHSRR=1
2311 IMASK=IRQS_DISABLED
2312 IKVM_REAL=1
2313 IKVM_VIRT=1
2314#ifndef CONFIG_KVM_BOOK3S_HV_POSSIBLE
2315 ICFAR=0
2316#endif
2317INT_DEFINE_END(h_virt_irq)
2318
2319EXC_REAL_BEGIN(h_virt_irq, 0xea0, 0x20)
2320 GEN_INT_ENTRY h_virt_irq, virt=0, ool=1
2321EXC_REAL_END(h_virt_irq, 0xea0, 0x20)
2322EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20)
2323 GEN_INT_ENTRY h_virt_irq, virt=1, ool=1
2324EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20)
2325EXC_COMMON_BEGIN(h_virt_irq_common)
2326 GEN_COMMON h_virt_irq
2327 addi r3,r1,STACK_INT_FRAME_REGS
2328 bl CFUNC(do_IRQ)
2329 b interrupt_return_hsrr
2330
2331
2332EXC_REAL_NONE(0xec0, 0x20)
2333EXC_VIRT_NONE(0x4ec0, 0x20)
2334EXC_REAL_NONE(0xee0, 0x20)
2335EXC_VIRT_NONE(0x4ee0, 0x20)
2336
2337
2338/*
2339 * Interrupt 0xf00 - Performance Monitor Interrupt (PMI, PMU).
2340 * This is an asynchronous interrupt in response to a PMU exception.
2341 * It is maskable in hardware by clearing MSR[EE], and soft-maskable with
2342 * IRQS_PMI_DISABLED mask (NOTE: NOT local_irq_disable()).
2343 *
2344 * Handling:
2345 * This calls into the perf subsystem.
2346 *
2347 * Like the watchdog soft-nmi, it appears an NMI interrupt to Linux, in that it
2348 * runs under local_irq_disable. However it may be soft-masked in
2349 * powerpc-specific code.
2350 *
2351 * If soft masked, the masked handler will note the pending interrupt for
2352 * replay, and clear MSR[EE] in the interrupted context.
2353 *
2354 * CFAR is not used by perf interrupts so not required.
2355 */
2356INT_DEFINE_BEGIN(performance_monitor)
2357 IVEC=0xf00
2358 IMASK=IRQS_PMI_DISABLED
2359#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2360 IKVM_REAL=1
2361#endif
2362 ICFAR=0
2363INT_DEFINE_END(performance_monitor)
2364
2365EXC_REAL_BEGIN(performance_monitor, 0xf00, 0x20)
2366 GEN_INT_ENTRY performance_monitor, virt=0, ool=1
2367EXC_REAL_END(performance_monitor, 0xf00, 0x20)
2368EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20)
2369 GEN_INT_ENTRY performance_monitor, virt=1, ool=1
2370EXC_VIRT_END(performance_monitor, 0x4f00, 0x20)
2371EXC_COMMON_BEGIN(performance_monitor_common)
2372 GEN_COMMON performance_monitor
2373 addi r3,r1,STACK_INT_FRAME_REGS
2374 lbz r4,PACAIRQSOFTMASK(r13)
2375 cmpdi r4,IRQS_ENABLED
2376 bne 1f
2377 bl CFUNC(performance_monitor_exception_async)
2378 b interrupt_return_srr
23791:
2380 bl CFUNC(performance_monitor_exception_nmi)
2381 /* Clear MSR_RI before setting SRR0 and SRR1. */
2382 li r9,0
2383 mtmsrd r9,1
2384
2385 kuap_kernel_restore r9, r10
2386
2387 EXCEPTION_RESTORE_REGS hsrr=0
2388 RFI_TO_KERNEL
2389
2390/**
2391 * Interrupt 0xf20 - Vector Unavailable Interrupt.
2392 * This is a synchronous interrupt in response to
2393 * executing a vector (or altivec) instruction with MSR[VEC]=0.
2394 * Similar to FP unavailable.
2395 */
2396INT_DEFINE_BEGIN(altivec_unavailable)
2397 IVEC=0xf20
2398#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2399 IKVM_REAL=1
2400#endif
2401 IMSR_R12=1
2402INT_DEFINE_END(altivec_unavailable)
2403
2404EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20)
2405 GEN_INT_ENTRY altivec_unavailable, virt=0, ool=1
2406EXC_REAL_END(altivec_unavailable, 0xf20, 0x20)
2407EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20)
2408 GEN_INT_ENTRY altivec_unavailable, virt=1, ool=1
2409EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20)
2410EXC_COMMON_BEGIN(altivec_unavailable_common)
2411 GEN_COMMON altivec_unavailable
2412#ifdef CONFIG_ALTIVEC
2413BEGIN_FTR_SECTION
2414 beq 1f
2415#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2416 BEGIN_FTR_SECTION_NESTED(69)
2417 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2418 * transaction), go do TM stuff
2419 */
2420 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2421 bne- 2f
2422 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2423#endif
2424 bl CFUNC(load_up_altivec)
2425 b fast_interrupt_return_srr
2426#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
24272: /* User process was in a transaction */
2428 addi r3,r1,STACK_INT_FRAME_REGS
2429 bl CFUNC(altivec_unavailable_tm)
2430 b interrupt_return_srr
2431#endif
24321:
2433END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2434#endif
2435 addi r3,r1,STACK_INT_FRAME_REGS
2436 bl CFUNC(altivec_unavailable_exception)
2437 b interrupt_return_srr
2438
2439
2440/**
2441 * Interrupt 0xf40 - VSX Unavailable Interrupt.
2442 * This is a synchronous interrupt in response to
2443 * executing a VSX instruction with MSR[VSX]=0.
2444 * Similar to FP unavailable.
2445 */
2446INT_DEFINE_BEGIN(vsx_unavailable)
2447 IVEC=0xf40
2448#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2449 IKVM_REAL=1
2450#endif
2451 IMSR_R12=1
2452INT_DEFINE_END(vsx_unavailable)
2453
2454EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20)
2455 GEN_INT_ENTRY vsx_unavailable, virt=0, ool=1
2456EXC_REAL_END(vsx_unavailable, 0xf40, 0x20)
2457EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20)
2458 GEN_INT_ENTRY vsx_unavailable, virt=1, ool=1
2459EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20)
2460EXC_COMMON_BEGIN(vsx_unavailable_common)
2461 GEN_COMMON vsx_unavailable
2462#ifdef CONFIG_VSX
2463BEGIN_FTR_SECTION
2464 beq 1f
2465#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2466 BEGIN_FTR_SECTION_NESTED(69)
2467 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
2468 * transaction), go do TM stuff
2469 */
2470 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
2471 bne- 2f
2472 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2473#endif
2474 b load_up_vsx
2475#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
24762: /* User process was in a transaction */
2477 addi r3,r1,STACK_INT_FRAME_REGS
2478 bl CFUNC(vsx_unavailable_tm)
2479 b interrupt_return_srr
2480#endif
24811:
2482END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2483#endif
2484 addi r3,r1,STACK_INT_FRAME_REGS
2485 bl CFUNC(vsx_unavailable_exception)
2486 b interrupt_return_srr
2487
2488
2489/**
2490 * Interrupt 0xf60 - Facility Unavailable Interrupt.
2491 * This is a synchronous interrupt in response to
2492 * executing an instruction without access to the facility that can be
2493 * resolved by the OS (e.g., FSCR, MSR).
2494 * Similar to FP unavailable.
2495 */
2496INT_DEFINE_BEGIN(facility_unavailable)
2497 IVEC=0xf60
2498#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2499 IKVM_REAL=1
2500#endif
2501INT_DEFINE_END(facility_unavailable)
2502
2503EXC_REAL_BEGIN(facility_unavailable, 0xf60, 0x20)
2504 GEN_INT_ENTRY facility_unavailable, virt=0, ool=1
2505EXC_REAL_END(facility_unavailable, 0xf60, 0x20)
2506EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20)
2507 GEN_INT_ENTRY facility_unavailable, virt=1, ool=1
2508EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20)
2509EXC_COMMON_BEGIN(facility_unavailable_common)
2510 GEN_COMMON facility_unavailable
2511 addi r3,r1,STACK_INT_FRAME_REGS
2512 bl CFUNC(facility_unavailable_exception)
2513 HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
2514 b interrupt_return_srr
2515
2516
2517/**
2518 * Interrupt 0xf60 - Hypervisor Facility Unavailable Interrupt.
2519 * This is a synchronous interrupt in response to
2520 * executing an instruction without access to the facility that can only
2521 * be resolved in HV mode (e.g., HFSCR).
2522 * Similar to FP unavailable.
2523 */
2524INT_DEFINE_BEGIN(h_facility_unavailable)
2525 IVEC=0xf80
2526 IHSRR=1
2527 IKVM_REAL=1
2528 IKVM_VIRT=1
2529INT_DEFINE_END(h_facility_unavailable)
2530
2531EXC_REAL_BEGIN(h_facility_unavailable, 0xf80, 0x20)
2532 GEN_INT_ENTRY h_facility_unavailable, virt=0, ool=1
2533EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20)
2534EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20)
2535 GEN_INT_ENTRY h_facility_unavailable, virt=1, ool=1
2536EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20)
2537EXC_COMMON_BEGIN(h_facility_unavailable_common)
2538 GEN_COMMON h_facility_unavailable
2539 addi r3,r1,STACK_INT_FRAME_REGS
2540 bl CFUNC(facility_unavailable_exception)
2541 /* XXX Shouldn't be necessary in practice */
2542 HANDLER_RESTORE_NVGPRS()
2543 b interrupt_return_hsrr
2544
2545
2546EXC_REAL_NONE(0xfa0, 0x20)
2547EXC_VIRT_NONE(0x4fa0, 0x20)
2548EXC_REAL_NONE(0xfc0, 0x20)
2549EXC_VIRT_NONE(0x4fc0, 0x20)
2550EXC_REAL_NONE(0xfe0, 0x20)
2551EXC_VIRT_NONE(0x4fe0, 0x20)
2552
2553EXC_REAL_NONE(0x1000, 0x100)
2554EXC_VIRT_NONE(0x5000, 0x100)
2555EXC_REAL_NONE(0x1100, 0x100)
2556EXC_VIRT_NONE(0x5100, 0x100)
2557
2558#ifdef CONFIG_CBE_RAS
2559INT_DEFINE_BEGIN(cbe_system_error)
2560 IVEC=0x1200
2561 IHSRR=1
2562INT_DEFINE_END(cbe_system_error)
2563
2564EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100)
2565 GEN_INT_ENTRY cbe_system_error, virt=0
2566EXC_REAL_END(cbe_system_error, 0x1200, 0x100)
2567EXC_VIRT_NONE(0x5200, 0x100)
2568EXC_COMMON_BEGIN(cbe_system_error_common)
2569 GEN_COMMON cbe_system_error
2570 addi r3,r1,STACK_INT_FRAME_REGS
2571 bl CFUNC(cbe_system_error_exception)
2572 b interrupt_return_hsrr
2573
2574#else /* CONFIG_CBE_RAS */
2575EXC_REAL_NONE(0x1200, 0x100)
2576EXC_VIRT_NONE(0x5200, 0x100)
2577#endif
2578
2579/**
2580 * Interrupt 0x1300 - Instruction Address Breakpoint Interrupt.
2581 * This has been removed from the ISA before 2.01, which is the earliest
2582 * 64-bit BookS ISA supported, however the G5 / 970 implements this
2583 * interrupt with a non-architected feature available through the support
2584 * processor interface.
2585 */
2586INT_DEFINE_BEGIN(instruction_breakpoint)
2587 IVEC=0x1300
2588#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2589 IKVM_REAL=1
2590#endif
2591INT_DEFINE_END(instruction_breakpoint)
2592
2593EXC_REAL_BEGIN(instruction_breakpoint, 0x1300, 0x100)
2594 GEN_INT_ENTRY instruction_breakpoint, virt=0
2595EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100)
2596EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100)
2597 GEN_INT_ENTRY instruction_breakpoint, virt=1
2598EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100)
2599EXC_COMMON_BEGIN(instruction_breakpoint_common)
2600 GEN_COMMON instruction_breakpoint
2601 addi r3,r1,STACK_INT_FRAME_REGS
2602 bl CFUNC(instruction_breakpoint_exception)
2603 b interrupt_return_srr
2604
2605
2606EXC_REAL_NONE(0x1400, 0x100)
2607EXC_VIRT_NONE(0x5400, 0x100)
2608
2609/**
2610 * Interrupt 0x1500 - Soft Patch Interrupt
2611 *
2612 * Handling:
2613 * This is an implementation specific interrupt which can be used for a
2614 * range of exceptions.
2615 *
2616 * This interrupt handler is unique in that it runs the denormal assist
2617 * code even for guests (and even in guest context) without going to KVM,
2618 * for speed. POWER9 does not raise denorm exceptions, so this special case
2619 * could be phased out in future to reduce special cases.
2620 */
2621INT_DEFINE_BEGIN(denorm_exception)
2622 IVEC=0x1500
2623 IHSRR=1
2624 IBRANCH_TO_COMMON=0
2625 IKVM_REAL=1
2626INT_DEFINE_END(denorm_exception)
2627
2628EXC_REAL_BEGIN(denorm_exception, 0x1500, 0x100)
2629 GEN_INT_ENTRY denorm_exception, virt=0
2630#ifdef CONFIG_PPC_DENORMALISATION
2631 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2632 bne+ denorm_assist
2633#endif
2634 GEN_BRANCH_TO_COMMON denorm_exception, virt=0
2635EXC_REAL_END(denorm_exception, 0x1500, 0x100)
2636#ifdef CONFIG_PPC_DENORMALISATION
2637EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
2638 GEN_INT_ENTRY denorm_exception, virt=1
2639 andis. r10,r12,(HSRR1_DENORM)@h /* denorm? */
2640 bne+ denorm_assist
2641 GEN_BRANCH_TO_COMMON denorm_exception, virt=1
2642EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
2643#else
2644EXC_VIRT_NONE(0x5500, 0x100)
2645#endif
2646
2647#ifdef CONFIG_PPC_DENORMALISATION
2648TRAMP_REAL_BEGIN(denorm_assist)
2649BEGIN_FTR_SECTION
2650/*
2651 * To denormalise we need to move a copy of the register to itself.
2652 * For POWER6 do that here for all FP regs.
2653 */
2654 mfmsr r10
2655 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
2656 xori r10,r10,(MSR_FE0|MSR_FE1)
2657 mtmsrd r10
2658 sync
2659
2660 .Lreg=0
2661 .rept 32
2662 fmr .Lreg,.Lreg
2663 .Lreg=.Lreg+1
2664 .endr
2665
2666FTR_SECTION_ELSE
2667/*
2668 * To denormalise we need to move a copy of the register to itself.
2669 * For POWER7 do that here for the first 32 VSX registers only.
2670 */
2671 mfmsr r10
2672 oris r10,r10,MSR_VSX@h
2673 mtmsrd r10
2674 sync
2675
2676 .Lreg=0
2677 .rept 32
2678 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2679 .Lreg=.Lreg+1
2680 .endr
2681
2682ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
2683
2684BEGIN_FTR_SECTION
2685 b denorm_done
2686END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
2687/*
2688 * To denormalise we need to move a copy of the register to itself.
2689 * For POWER8 we need to do that for all 64 VSX registers
2690 */
2691 .Lreg=32
2692 .rept 32
2693 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2694 .Lreg=.Lreg+1
2695 .endr
2696
2697denorm_done:
2698 mfspr r11,SPRN_HSRR0
2699 subi r11,r11,4
2700 mtspr SPRN_HSRR0,r11
2701 mtcrf 0x80,r9
2702 ld r9,PACA_EXGEN+EX_R9(r13)
2703BEGIN_FTR_SECTION
2704 ld r10,PACA_EXGEN+EX_PPR(r13)
2705 mtspr SPRN_PPR,r10
2706END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
2707BEGIN_FTR_SECTION
2708 ld r10,PACA_EXGEN+EX_CFAR(r13)
2709 mtspr SPRN_CFAR,r10
2710END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
2711 li r10,0
2712 stb r10,PACAHSRR_VALID(r13)
2713 ld r10,PACA_EXGEN+EX_R10(r13)
2714 ld r11,PACA_EXGEN+EX_R11(r13)
2715 ld r12,PACA_EXGEN+EX_R12(r13)
2716 ld r13,PACA_EXGEN+EX_R13(r13)
2717 HRFI_TO_UNKNOWN
2718 b .
2719#endif
2720
2721EXC_COMMON_BEGIN(denorm_exception_common)
2722 GEN_COMMON denorm_exception
2723 addi r3,r1,STACK_INT_FRAME_REGS
2724 bl CFUNC(unknown_exception)
2725 b interrupt_return_hsrr
2726
2727
2728#ifdef CONFIG_CBE_RAS
2729INT_DEFINE_BEGIN(cbe_maintenance)
2730 IVEC=0x1600
2731 IHSRR=1
2732INT_DEFINE_END(cbe_maintenance)
2733
2734EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100)
2735 GEN_INT_ENTRY cbe_maintenance, virt=0
2736EXC_REAL_END(cbe_maintenance, 0x1600, 0x100)
2737EXC_VIRT_NONE(0x5600, 0x100)
2738EXC_COMMON_BEGIN(cbe_maintenance_common)
2739 GEN_COMMON cbe_maintenance
2740 addi r3,r1,STACK_INT_FRAME_REGS
2741 bl CFUNC(cbe_maintenance_exception)
2742 b interrupt_return_hsrr
2743
2744#else /* CONFIG_CBE_RAS */
2745EXC_REAL_NONE(0x1600, 0x100)
2746EXC_VIRT_NONE(0x5600, 0x100)
2747#endif
2748
2749
2750INT_DEFINE_BEGIN(altivec_assist)
2751 IVEC=0x1700
2752#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
2753 IKVM_REAL=1
2754#endif
2755INT_DEFINE_END(altivec_assist)
2756
2757EXC_REAL_BEGIN(altivec_assist, 0x1700, 0x100)
2758 GEN_INT_ENTRY altivec_assist, virt=0
2759EXC_REAL_END(altivec_assist, 0x1700, 0x100)
2760EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100)
2761 GEN_INT_ENTRY altivec_assist, virt=1
2762EXC_VIRT_END(altivec_assist, 0x5700, 0x100)
2763EXC_COMMON_BEGIN(altivec_assist_common)
2764 GEN_COMMON altivec_assist
2765 addi r3,r1,STACK_INT_FRAME_REGS
2766#ifdef CONFIG_ALTIVEC
2767 bl CFUNC(altivec_assist_exception)
2768 HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
2769#else
2770 bl CFUNC(unknown_exception)
2771#endif
2772 b interrupt_return_srr
2773
2774
2775#ifdef CONFIG_CBE_RAS
2776INT_DEFINE_BEGIN(cbe_thermal)
2777 IVEC=0x1800
2778 IHSRR=1
2779INT_DEFINE_END(cbe_thermal)
2780
2781EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100)
2782 GEN_INT_ENTRY cbe_thermal, virt=0
2783EXC_REAL_END(cbe_thermal, 0x1800, 0x100)
2784EXC_VIRT_NONE(0x5800, 0x100)
2785EXC_COMMON_BEGIN(cbe_thermal_common)
2786 GEN_COMMON cbe_thermal
2787 addi r3,r1,STACK_INT_FRAME_REGS
2788 bl CFUNC(cbe_thermal_exception)
2789 b interrupt_return_hsrr
2790
2791#else /* CONFIG_CBE_RAS */
2792EXC_REAL_NONE(0x1800, 0x100)
2793EXC_VIRT_NONE(0x5800, 0x100)
2794#endif
2795
2796
2797#ifdef CONFIG_PPC_WATCHDOG
2798
2799INT_DEFINE_BEGIN(soft_nmi)
2800 IVEC=0x900
2801 ISTACK=0
2802 ICFAR=0
2803INT_DEFINE_END(soft_nmi)
2804
2805/*
2806 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
2807 * stack is one that is usable by maskable interrupts so long as MSR_EE
2808 * remains off. It is used for recovery when something has corrupted the
2809 * normal kernel stack, for example. The "soft NMI" must not use the process
2810 * stack because we want irq disabled sections to avoid touching the stack
2811 * at all (other than PMU interrupts), so use the emergency stack for this,
2812 * and run it entirely with interrupts hard disabled.
2813 */
2814EXC_COMMON_BEGIN(soft_nmi_common)
2815 mr r10,r1
2816 ld r1,PACAEMERGSP(r13)
2817 subi r1,r1,INT_FRAME_SIZE
2818 __GEN_COMMON_BODY soft_nmi
2819
2820 addi r3,r1,STACK_INT_FRAME_REGS
2821 bl CFUNC(soft_nmi_interrupt)
2822
2823 /* Clear MSR_RI before setting SRR0 and SRR1. */
2824 li r9,0
2825 mtmsrd r9,1
2826
2827 kuap_kernel_restore r9, r10
2828
2829 EXCEPTION_RESTORE_REGS hsrr=0
2830 RFI_TO_KERNEL
2831
2832#endif /* CONFIG_PPC_WATCHDOG */
2833
2834/*
2835 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
2836 * - If it was a decrementer interrupt, we bump the dec to max and return.
2837 * - If it was a doorbell we return immediately since doorbells are edge
2838 * triggered and won't automatically refire.
2839 * - If it was a HMI we return immediately since we handled it in realmode
2840 * and it won't refire.
2841 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
2842 * This is called with r10 containing the value to OR to the paca field.
2843 */
2844.macro MASKED_INTERRUPT hsrr=0
2845 .if \hsrr
2846masked_Hinterrupt:
2847 .else
2848masked_interrupt:
2849 .endif
2850 stw r9,PACA_EXGEN+EX_CCR(r13)
2851#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
2852 /*
2853 * Ensure there was no previous MUST_HARD_MASK interrupt or
2854 * HARD_DIS setting. If this does fire, the interrupt is still
2855 * masked and MSR[EE] will be cleared on return, so no need to
2856 * panic, but somebody probably enabled MSR[EE] under
2857 * PACA_IRQ_HARD_DIS, mtmsr(mfmsr() | MSR_x) being a common
2858 * cause.
2859 */
2860 lbz r9,PACAIRQHAPPENED(r13)
2861 andi. r9,r9,(PACA_IRQ_MUST_HARD_MASK|PACA_IRQ_HARD_DIS)
28620: tdnei r9,0
2863 EMIT_WARN_ENTRY 0b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
2864#endif
2865 lbz r9,PACAIRQHAPPENED(r13)
2866 or r9,r9,r10
2867 stb r9,PACAIRQHAPPENED(r13)
2868
2869 .if ! \hsrr
2870 cmpwi r10,PACA_IRQ_DEC
2871 bne 1f
2872 LOAD_REG_IMMEDIATE(r9, 0x7fffffff)
2873 mtspr SPRN_DEC,r9
2874#ifdef CONFIG_PPC_WATCHDOG
2875 lwz r9,PACA_EXGEN+EX_CCR(r13)
2876 b soft_nmi_common
2877#else
2878 b 2f
2879#endif
2880 .endif
2881
28821: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK
2883 beq 2f
2884 xori r12,r12,MSR_EE /* clear MSR_EE */
2885 .if \hsrr
2886 mtspr SPRN_HSRR1,r12
2887 .else
2888 mtspr SPRN_SRR1,r12
2889 .endif
2890 ori r9,r9,PACA_IRQ_HARD_DIS
2891 stb r9,PACAIRQHAPPENED(r13)
28922: /* done */
2893 li r9,0
2894 .if \hsrr
2895 stb r9,PACAHSRR_VALID(r13)
2896 .else
2897 stb r9,PACASRR_VALID(r13)
2898 .endif
2899
2900 SEARCH_RESTART_TABLE
2901 cmpdi r12,0
2902 beq 3f
2903 .if \hsrr
2904 mtspr SPRN_HSRR0,r12
2905 .else
2906 mtspr SPRN_SRR0,r12
2907 .endif
29083:
2909
2910 ld r9,PACA_EXGEN+EX_CTR(r13)
2911 mtctr r9
2912 lwz r9,PACA_EXGEN+EX_CCR(r13)
2913 mtcrf 0x80,r9
2914 std r1,PACAR1(r13)
2915 ld r9,PACA_EXGEN+EX_R9(r13)
2916 ld r10,PACA_EXGEN+EX_R10(r13)
2917 ld r11,PACA_EXGEN+EX_R11(r13)
2918 ld r12,PACA_EXGEN+EX_R12(r13)
2919 ld r13,PACA_EXGEN+EX_R13(r13)
2920 /* May return to masked low address where r13 is not set up */
2921 .if \hsrr
2922 HRFI_TO_KERNEL
2923 .else
2924 RFI_TO_KERNEL
2925 .endif
2926 b .
2927.endm
2928
2929TRAMP_REAL_BEGIN(stf_barrier_fallback)
2930 std r9,PACA_EXRFI+EX_R9(r13)
2931 std r10,PACA_EXRFI+EX_R10(r13)
2932 sync
2933 ld r9,PACA_EXRFI+EX_R9(r13)
2934 ld r10,PACA_EXRFI+EX_R10(r13)
2935 ori 31,31,0
2936 .rept 14
2937 b 1f
29381:
2939 .endr
2940 blr
2941
2942/* Clobbers r10, r11, ctr */
2943.macro L1D_DISPLACEMENT_FLUSH
2944 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2945 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2946 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2947 mtctr r11
2948 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2949
2950 /* order ld/st prior to dcbt stop all streams with flushing */
2951 sync
2952
2953 /*
2954 * The load addresses are at staggered offsets within cachelines,
2955 * which suits some pipelines better (on others it should not
2956 * hurt).
2957 */
29581:
2959 ld r11,(0x80 + 8)*0(r10)
2960 ld r11,(0x80 + 8)*1(r10)
2961 ld r11,(0x80 + 8)*2(r10)
2962 ld r11,(0x80 + 8)*3(r10)
2963 ld r11,(0x80 + 8)*4(r10)
2964 ld r11,(0x80 + 8)*5(r10)
2965 ld r11,(0x80 + 8)*6(r10)
2966 ld r11,(0x80 + 8)*7(r10)
2967 addi r10,r10,0x80*8
2968 bdnz 1b
2969.endm
2970
2971TRAMP_REAL_BEGIN(entry_flush_fallback)
2972 std r9,PACA_EXRFI+EX_R9(r13)
2973 std r10,PACA_EXRFI+EX_R10(r13)
2974 std r11,PACA_EXRFI+EX_R11(r13)
2975 mfctr r9
2976 L1D_DISPLACEMENT_FLUSH
2977 mtctr r9
2978 ld r9,PACA_EXRFI+EX_R9(r13)
2979 ld r10,PACA_EXRFI+EX_R10(r13)
2980 ld r11,PACA_EXRFI+EX_R11(r13)
2981 blr
2982
2983/*
2984 * The SCV entry flush happens with interrupts enabled, so it must disable
2985 * to prevent EXRFI being clobbered by NMIs (e.g., soft_nmi_common). r10
2986 * (containing LR) does not need to be preserved here because scv entry
2987 * puts 0 in the pt_regs, CTR can be clobbered for the same reason.
2988 */
2989TRAMP_REAL_BEGIN(scv_entry_flush_fallback)
2990 li r10,0
2991 mtmsrd r10,1
2992 lbz r10,PACAIRQHAPPENED(r13)
2993 ori r10,r10,PACA_IRQ_HARD_DIS
2994 stb r10,PACAIRQHAPPENED(r13)
2995 std r11,PACA_EXRFI+EX_R11(r13)
2996 L1D_DISPLACEMENT_FLUSH
2997 ld r11,PACA_EXRFI+EX_R11(r13)
2998 li r10,MSR_RI
2999 mtmsrd r10,1
3000 blr
3001
3002TRAMP_REAL_BEGIN(rfi_flush_fallback)
3003 SET_SCRATCH0(r13);
3004 GET_PACA(r13);
3005 std r1,PACA_EXRFI+EX_R12(r13)
3006 ld r1,PACAKSAVE(r13)
3007 std r9,PACA_EXRFI+EX_R9(r13)
3008 std r10,PACA_EXRFI+EX_R10(r13)
3009 std r11,PACA_EXRFI+EX_R11(r13)
3010 mfctr r9
3011 L1D_DISPLACEMENT_FLUSH
3012 mtctr r9
3013 ld r9,PACA_EXRFI+EX_R9(r13)
3014 ld r10,PACA_EXRFI+EX_R10(r13)
3015 ld r11,PACA_EXRFI+EX_R11(r13)
3016 ld r1,PACA_EXRFI+EX_R12(r13)
3017 GET_SCRATCH0(r13);
3018 rfid
3019
3020TRAMP_REAL_BEGIN(hrfi_flush_fallback)
3021 SET_SCRATCH0(r13);
3022 GET_PACA(r13);
3023 std r1,PACA_EXRFI+EX_R12(r13)
3024 ld r1,PACAKSAVE(r13)
3025 std r9,PACA_EXRFI+EX_R9(r13)
3026 std r10,PACA_EXRFI+EX_R10(r13)
3027 std r11,PACA_EXRFI+EX_R11(r13)
3028 mfctr r9
3029 L1D_DISPLACEMENT_FLUSH
3030 mtctr r9
3031 ld r9,PACA_EXRFI+EX_R9(r13)
3032 ld r10,PACA_EXRFI+EX_R10(r13)
3033 ld r11,PACA_EXRFI+EX_R11(r13)
3034 ld r1,PACA_EXRFI+EX_R12(r13)
3035 GET_SCRATCH0(r13);
3036 hrfid
3037
3038TRAMP_REAL_BEGIN(rfscv_flush_fallback)
3039 /* system call volatile */
3040 mr r7,r13
3041 GET_PACA(r13);
3042 mr r8,r1
3043 ld r1,PACAKSAVE(r13)
3044 mfctr r9
3045 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
3046 ld r11,PACA_L1D_FLUSH_SIZE(r13)
3047 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
3048 mtctr r11
3049 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
3050
3051 /* order ld/st prior to dcbt stop all streams with flushing */
3052 sync
3053
3054 /*
3055 * The load adresses are at staggered offsets within cachelines,
3056 * which suits some pipelines better (on others it should not
3057 * hurt).
3058 */
30591:
3060 ld r11,(0x80 + 8)*0(r10)
3061 ld r11,(0x80 + 8)*1(r10)
3062 ld r11,(0x80 + 8)*2(r10)
3063 ld r11,(0x80 + 8)*3(r10)
3064 ld r11,(0x80 + 8)*4(r10)
3065 ld r11,(0x80 + 8)*5(r10)
3066 ld r11,(0x80 + 8)*6(r10)
3067 ld r11,(0x80 + 8)*7(r10)
3068 addi r10,r10,0x80*8
3069 bdnz 1b
3070
3071 mtctr r9
3072 li r9,0
3073 li r10,0
3074 li r11,0
3075 mr r1,r8
3076 mr r13,r7
3077 RFSCV
3078
3079USE_TEXT_SECTION()
3080
3081#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
3082kvm_interrupt:
3083 /*
3084 * The conditional branch in KVMTEST can't reach all the way,
3085 * make a stub.
3086 */
3087 b kvmppc_interrupt
3088#endif
3089
3090_GLOBAL(do_uaccess_flush)
3091 UACCESS_FLUSH_FIXUP_SECTION
3092 nop
3093 nop
3094 nop
3095 blr
3096 L1D_DISPLACEMENT_FLUSH
3097 blr
3098_ASM_NOKPROBE_SYMBOL(do_uaccess_flush)
3099EXPORT_SYMBOL(do_uaccess_flush)
3100
3101
3102MASKED_INTERRUPT
3103MASKED_INTERRUPT hsrr=1
3104
3105USE_FIXED_SECTION(virt_trampolines)
3106 /*
3107 * All code below __end_soft_masked is treated as soft-masked. If
3108 * any code runs here with MSR[EE]=1, it must then cope with pending
3109 * soft interrupt being raised (i.e., by ensuring it is replayed).
3110 *
3111 * The __end_interrupts marker must be past the out-of-line (OOL)
3112 * handlers, so that they are copied to real address 0x100 when running
3113 * a relocatable kernel. This ensures they can be reached from the short
3114 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
3115 * directly, without using LOAD_HANDLER().
3116 */
3117 .align 7
3118 .globl __end_interrupts
3119__end_interrupts:
3120DEFINE_FIXED_SYMBOL(__end_interrupts, virt_trampolines)
3121
3122CLOSE_FIXED_SECTION(real_vectors);
3123CLOSE_FIXED_SECTION(real_trampolines);
3124CLOSE_FIXED_SECTION(virt_vectors);
3125CLOSE_FIXED_SECTION(virt_trampolines);
3126
3127USE_TEXT_SECTION()
3128
3129/* MSR[RI] should be clear because this uses SRR[01] */
3130_GLOBAL(enable_machine_check)
3131 mflr r0
3132 bcl 20,31,$+4
31330: mflr r3
3134 addi r3,r3,(1f - 0b)
3135 mtspr SPRN_SRR0,r3
3136 mfmsr r3
3137 ori r3,r3,MSR_ME
3138 mtspr SPRN_SRR1,r3
3139 RFI_TO_KERNEL
31401: mtlr r0
3141 blr
3142
3143/* MSR[RI] should be clear because this uses SRR[01] */
3144SYM_FUNC_START_LOCAL(disable_machine_check)
3145 mflr r0
3146 bcl 20,31,$+4
31470: mflr r3
3148 addi r3,r3,(1f - 0b)
3149 mtspr SPRN_SRR0,r3
3150 mfmsr r3
3151 li r4,MSR_ME
3152 andc r3,r3,r4
3153 mtspr SPRN_SRR1,r3
3154 RFI_TO_KERNEL
31551: mtlr r0
3156 blr
3157SYM_FUNC_END(disable_machine_check)
1/*
2 * This file contains the 64-bit "server" PowerPC variant
3 * of the low level exception handling including exception
4 * vectors, exception return, part of the slb and stab
5 * handling and other fixed offset specific things.
6 *
7 * This file is meant to be #included from head_64.S due to
8 * position dependent assembly.
9 *
10 * Most of this originates from head_64.S and thus has the same
11 * copyright history.
12 *
13 */
14
15#include <asm/hw_irq.h>
16#include <asm/exception-64s.h>
17#include <asm/ptrace.h>
18#include <asm/cpuidle.h>
19#include <asm/head-64.h>
20
21/*
22 * There are a few constraints to be concerned with.
23 * - Real mode exceptions code/data must be located at their physical location.
24 * - Virtual mode exceptions must be mapped at their 0xc000... location.
25 * - Fixed location code must not call directly beyond the __end_interrupts
26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
27 * must be used.
28 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
29 * virtual 0xc00...
30 * - Conditional branch targets must be within +/-32K of caller.
31 *
32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
33 * therefore don't have to run in physically located code or rfid to
34 * virtual mode kernel code. However on relocatable kernels they do have
35 * to branch to KERNELBASE offset because the rest of the kernel (outside
36 * the exception vectors) may be located elsewhere.
37 *
38 * Virtual exceptions correspond with physical, except their entry points
39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
40 * offset applied. Virtual exceptions are enabled with the Alternate
41 * Interrupt Location (AIL) bit set in the LPCR. However this does not
42 * guarantee they will be delivered virtually. Some conditions (see the ISA)
43 * cause exceptions to be delivered in real mode.
44 *
45 * It's impossible to receive interrupts below 0x300 via AIL.
46 *
47 * KVM: None of the virtual exceptions are from the guest. Anything that
48 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
49 *
50 *
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
54 * 0x1900 - 0x3fff : Real mode trampolines
55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
56 * 0x5900 - 0x6fff : Relon mode trampolines
57 * 0x7000 - 0x7fff : FWNMI data area
58 * 0x8000 - .... : Common interrupt handlers, remaining early
59 * setup code, rest of kernel.
60 *
61 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
62 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
63 * vectors there.
64 */
65OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
66OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
67OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
68OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
69#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
70/*
71 * Data area reserved for FWNMI option.
72 * This address (0x7000) is fixed by the RPA.
73 * pseries and powernv need to keep the whole page from
74 * 0x7000 to 0x8000 free for use by the firmware
75 */
76ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
77OPEN_TEXT_SECTION(0x8000)
78#else
79OPEN_TEXT_SECTION(0x7000)
80#endif
81
82USE_FIXED_SECTION(real_vectors)
83
84/*
85 * This is the start of the interrupt handlers for pSeries
86 * This code runs with relocation off.
87 * Code from here to __end_interrupts gets copied down to real
88 * address 0x100 when we are running a relocatable kernel.
89 * Therefore any relative branches in this section must only
90 * branch to labels in this section.
91 */
92 .globl __start_interrupts
93__start_interrupts:
94
95/* No virt vectors corresponding with 0x0..0x100 */
96EXC_VIRT_NONE(0x4000, 0x4100)
97
98
99#ifdef CONFIG_PPC_P7_NAP
100 /*
101 * If running native on arch 2.06 or later, check if we are waking up
102 * from nap/sleep/winkle, and branch to idle handler.
103 */
104#define IDLETEST(n) \
105 BEGIN_FTR_SECTION ; \
106 mfspr r10,SPRN_SRR1 ; \
107 rlwinm. r10,r10,47-31,30,31 ; \
108 beq- 1f ; \
109 cmpwi cr3,r10,2 ; \
110 BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \
1111: \
112 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
113#else
114#define IDLETEST NOTEST
115#endif
116
117EXC_REAL_BEGIN(system_reset, 0x100, 0x200)
118 SET_SCRATCH0(r13)
119 GET_PACA(r13)
120 clrrdi r13,r13,1 /* Last bit of HSPRG0 is set if waking from winkle */
121 EXCEPTION_PROLOG_PSERIES_PACA(PACA_EXGEN, system_reset_common, EXC_STD,
122 IDLETEST, 0x100)
123
124EXC_REAL_END(system_reset, 0x100, 0x200)
125EXC_VIRT_NONE(0x4100, 0x4200)
126
127#ifdef CONFIG_PPC_P7_NAP
128EXC_COMMON_BEGIN(system_reset_idle_common)
129BEGIN_FTR_SECTION
130 GET_PACA(r13) /* Restore HSPRG0 to get the winkle bit in r13 */
131END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
132 bl pnv_restore_hyp_resource
133
134 li r0,PNV_THREAD_RUNNING
135 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
136
137#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
138 li r0,KVM_HWTHREAD_IN_KERNEL
139 stb r0,HSTATE_HWTHREAD_STATE(r13)
140 /* Order setting hwthread_state vs. testing hwthread_req */
141 sync
142 lbz r0,HSTATE_HWTHREAD_REQ(r13)
143 cmpwi r0,0
144 beq 1f
145 b kvm_start_guest
1461:
147#endif
148
149 /* Return SRR1 from power7_nap() */
150 mfspr r3,SPRN_SRR1
151 blt cr3,2f
152 b pnv_wakeup_loss
1532: b pnv_wakeup_noloss
154#endif
155
156EXC_COMMON(system_reset_common, 0x100, system_reset_exception)
157
158#ifdef CONFIG_PPC_PSERIES
159/*
160 * Vectors for the FWNMI option. Share common code.
161 */
162TRAMP_REAL_BEGIN(system_reset_fwnmi)
163 SET_SCRATCH0(r13) /* save r13 */
164 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
165 NOTEST, 0x100)
166#endif /* CONFIG_PPC_PSERIES */
167
168
169EXC_REAL_BEGIN(machine_check, 0x200, 0x300)
170 /* This is moved out of line as it can be patched by FW, but
171 * some code path might still want to branch into the original
172 * vector
173 */
174 SET_SCRATCH0(r13) /* save r13 */
175 /*
176 * Running native on arch 2.06 or later, we may wakeup from winkle
177 * inside machine check. If yes, then last bit of HSPRG0 would be set
178 * to 1. Hence clear it unconditionally.
179 */
180 GET_PACA(r13)
181 clrrdi r13,r13,1
182 SET_PACA(r13)
183 EXCEPTION_PROLOG_0(PACA_EXMC)
184BEGIN_FTR_SECTION
185 b machine_check_powernv_early
186FTR_SECTION_ELSE
187 b machine_check_pSeries_0
188ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
189EXC_REAL_END(machine_check, 0x200, 0x300)
190EXC_VIRT_NONE(0x4200, 0x4300)
191TRAMP_REAL_BEGIN(machine_check_powernv_early)
192BEGIN_FTR_SECTION
193 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
194 /*
195 * Register contents:
196 * R13 = PACA
197 * R9 = CR
198 * Original R9 to R13 is saved on PACA_EXMC
199 *
200 * Switch to mc_emergency stack and handle re-entrancy (we limit
201 * the nested MCE upto level 4 to avoid stack overflow).
202 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
203 *
204 * We use paca->in_mce to check whether this is the first entry or
205 * nested machine check. We increment paca->in_mce to track nested
206 * machine checks.
207 *
208 * If this is the first entry then set stack pointer to
209 * paca->mc_emergency_sp, otherwise r1 is already pointing to
210 * stack frame on mc_emergency stack.
211 *
212 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
213 * checkstop if we get another machine check exception before we do
214 * rfid with MSR_ME=1.
215 */
216 mr r11,r1 /* Save r1 */
217 lhz r10,PACA_IN_MCE(r13)
218 cmpwi r10,0 /* Are we in nested machine check */
219 bne 0f /* Yes, we are. */
220 /* First machine check entry */
221 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
2220: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
223 addi r10,r10,1 /* increment paca->in_mce */
224 sth r10,PACA_IN_MCE(r13)
225 /* Limit nested MCE to level 4 to avoid stack overflow */
226 cmpwi r10,4
227 bgt 2f /* Check if we hit limit of 4 */
228 std r11,GPR1(r1) /* Save r1 on the stack. */
229 std r11,0(r1) /* make stack chain pointer */
230 mfspr r11,SPRN_SRR0 /* Save SRR0 */
231 std r11,_NIP(r1)
232 mfspr r11,SPRN_SRR1 /* Save SRR1 */
233 std r11,_MSR(r1)
234 mfspr r11,SPRN_DAR /* Save DAR */
235 std r11,_DAR(r1)
236 mfspr r11,SPRN_DSISR /* Save DSISR */
237 std r11,_DSISR(r1)
238 std r9,_CCR(r1) /* Save CR in stackframe */
239 /* Save r9 through r13 from EXMC save area to stack frame. */
240 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
241 mfmsr r11 /* get MSR value */
242 ori r11,r11,MSR_ME /* turn on ME bit */
243 ori r11,r11,MSR_RI /* turn on RI bit */
244 LOAD_HANDLER(r12, machine_check_handle_early)
2451: mtspr SPRN_SRR0,r12
246 mtspr SPRN_SRR1,r11
247 rfid
248 b . /* prevent speculative execution */
2492:
250 /* Stack overflow. Stay on emergency stack and panic.
251 * Keep the ME bit off while panic-ing, so that if we hit
252 * another machine check we checkstop.
253 */
254 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
255 ld r11,PACAKMSR(r13)
256 LOAD_HANDLER(r12, unrecover_mce)
257 li r10,MSR_ME
258 andc r11,r11,r10 /* Turn off MSR_ME */
259 b 1b
260 b . /* prevent speculative execution */
261END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
262
263TRAMP_REAL_BEGIN(machine_check_pSeries)
264 .globl machine_check_fwnmi
265machine_check_fwnmi:
266 SET_SCRATCH0(r13) /* save r13 */
267 EXCEPTION_PROLOG_0(PACA_EXMC)
268machine_check_pSeries_0:
269 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
270 /*
271 * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the
272 * difference that MSR_RI is not enabled, because PACA_EXMC is being
273 * used, so nested machine check corrupts it. machine_check_common
274 * enables MSR_RI.
275 */
276 ld r10,PACAKMSR(r13)
277 xori r10,r10,MSR_RI
278 mfspr r11,SPRN_SRR0
279 LOAD_HANDLER(r12, machine_check_common)
280 mtspr SPRN_SRR0,r12
281 mfspr r12,SPRN_SRR1
282 mtspr SPRN_SRR1,r10
283 rfid
284 b . /* prevent speculative execution */
285
286TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
287
288EXC_COMMON_BEGIN(machine_check_common)
289 /*
290 * Machine check is different because we use a different
291 * save area: PACA_EXMC instead of PACA_EXGEN.
292 */
293 mfspr r10,SPRN_DAR
294 std r10,PACA_EXMC+EX_DAR(r13)
295 mfspr r10,SPRN_DSISR
296 stw r10,PACA_EXMC+EX_DSISR(r13)
297 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
298 FINISH_NAP
299 RECONCILE_IRQ_STATE(r10, r11)
300 ld r3,PACA_EXMC+EX_DAR(r13)
301 lwz r4,PACA_EXMC+EX_DSISR(r13)
302 /* Enable MSR_RI when finished with PACA_EXMC */
303 li r10,MSR_RI
304 mtmsrd r10,1
305 std r3,_DAR(r1)
306 std r4,_DSISR(r1)
307 bl save_nvgprs
308 addi r3,r1,STACK_FRAME_OVERHEAD
309 bl machine_check_exception
310 b ret_from_except
311
312#define MACHINE_CHECK_HANDLER_WINDUP \
313 /* Clear MSR_RI before setting SRR0 and SRR1. */\
314 li r0,MSR_RI; \
315 mfmsr r9; /* get MSR value */ \
316 andc r9,r9,r0; \
317 mtmsrd r9,1; /* Clear MSR_RI */ \
318 /* Move original SRR0 and SRR1 into the respective regs */ \
319 ld r9,_MSR(r1); \
320 mtspr SPRN_SRR1,r9; \
321 ld r3,_NIP(r1); \
322 mtspr SPRN_SRR0,r3; \
323 ld r9,_CTR(r1); \
324 mtctr r9; \
325 ld r9,_XER(r1); \
326 mtxer r9; \
327 ld r9,_LINK(r1); \
328 mtlr r9; \
329 REST_GPR(0, r1); \
330 REST_8GPRS(2, r1); \
331 REST_GPR(10, r1); \
332 ld r11,_CCR(r1); \
333 mtcr r11; \
334 /* Decrement paca->in_mce. */ \
335 lhz r12,PACA_IN_MCE(r13); \
336 subi r12,r12,1; \
337 sth r12,PACA_IN_MCE(r13); \
338 REST_GPR(11, r1); \
339 REST_2GPRS(12, r1); \
340 /* restore original r1. */ \
341 ld r1,GPR1(r1)
342
343 /*
344 * Handle machine check early in real mode. We come here with
345 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
346 */
347EXC_COMMON_BEGIN(machine_check_handle_early)
348 std r0,GPR0(r1) /* Save r0 */
349 EXCEPTION_PROLOG_COMMON_3(0x200)
350 bl save_nvgprs
351 addi r3,r1,STACK_FRAME_OVERHEAD
352 bl machine_check_early
353 std r3,RESULT(r1) /* Save result */
354 ld r12,_MSR(r1)
355#ifdef CONFIG_PPC_P7_NAP
356 /*
357 * Check if thread was in power saving mode. We come here when any
358 * of the following is true:
359 * a. thread wasn't in power saving mode
360 * b. thread was in power saving mode with no state loss,
361 * supervisor state loss or hypervisor state loss.
362 *
363 * Go back to nap/sleep/winkle mode again if (b) is true.
364 */
365 rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */
366 beq 4f /* No, it wasn;t */
367 /* Thread was in power saving mode. Go back to nap again. */
368 cmpwi r11,2
369 blt 3f
370 /* Supervisor/Hypervisor state loss */
371 li r0,1
372 stb r0,PACA_NAPSTATELOST(r13)
3733: bl machine_check_queue_event
374 MACHINE_CHECK_HANDLER_WINDUP
375 GET_PACA(r13)
376 ld r1,PACAR1(r13)
377 /*
378 * Check what idle state this CPU was in and go back to same mode
379 * again.
380 */
381 lbz r3,PACA_THREAD_IDLE_STATE(r13)
382 cmpwi r3,PNV_THREAD_NAP
383 bgt 10f
384 IDLE_STATE_ENTER_SEQ(PPC_NAP)
385 /* No return */
38610:
387 cmpwi r3,PNV_THREAD_SLEEP
388 bgt 2f
389 IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
390 /* No return */
391
3922:
393 /*
394 * Go back to winkle. Please note that this thread was woken up in
395 * machine check from winkle and have not restored the per-subcore
396 * state. Hence before going back to winkle, set last bit of HSPRG0
397 * to 1. This will make sure that if this thread gets woken up
398 * again at reset vector 0x100 then it will get chance to restore
399 * the subcore state.
400 */
401 ori r13,r13,1
402 SET_PACA(r13)
403 IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
404 /* No return */
4054:
406#endif
407 /*
408 * Check if we are coming from hypervisor userspace. If yes then we
409 * continue in host kernel in V mode to deliver the MC event.
410 */
411 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
412 beq 5f
413 andi. r11,r12,MSR_PR /* See if coming from user. */
414 bne 9f /* continue in V mode if we are. */
415
4165:
417#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
418 /*
419 * We are coming from kernel context. Check if we are coming from
420 * guest. if yes, then we can continue. We will fall through
421 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
422 */
423 lbz r11,HSTATE_IN_GUEST(r13)
424 cmpwi r11,0 /* Check if coming from guest */
425 bne 9f /* continue if we are. */
426#endif
427 /*
428 * At this point we are not sure about what context we come from.
429 * Queue up the MCE event and return from the interrupt.
430 * But before that, check if this is an un-recoverable exception.
431 * If yes, then stay on emergency stack and panic.
432 */
433 andi. r11,r12,MSR_RI
434 bne 2f
4351: mfspr r11,SPRN_SRR0
436 LOAD_HANDLER(r10,unrecover_mce)
437 mtspr SPRN_SRR0,r10
438 ld r10,PACAKMSR(r13)
439 /*
440 * We are going down. But there are chances that we might get hit by
441 * another MCE during panic path and we may run into unstable state
442 * with no way out. Hence, turn ME bit off while going down, so that
443 * when another MCE is hit during panic path, system will checkstop
444 * and hypervisor will get restarted cleanly by SP.
445 */
446 li r3,MSR_ME
447 andc r10,r10,r3 /* Turn off MSR_ME */
448 mtspr SPRN_SRR1,r10
449 rfid
450 b .
4512:
452 /*
453 * Check if we have successfully handled/recovered from error, if not
454 * then stay on emergency stack and panic.
455 */
456 ld r3,RESULT(r1) /* Load result */
457 cmpdi r3,0 /* see if we handled MCE successfully */
458
459 beq 1b /* if !handled then panic */
460 /*
461 * Return from MC interrupt.
462 * Queue up the MCE event so that we can log it later, while
463 * returning from kernel or opal call.
464 */
465 bl machine_check_queue_event
466 MACHINE_CHECK_HANDLER_WINDUP
467 rfid
4689:
469 /* Deliver the machine check to host kernel in V mode. */
470 MACHINE_CHECK_HANDLER_WINDUP
471 b machine_check_pSeries
472
473EXC_COMMON_BEGIN(unrecover_mce)
474 /* Invoke machine_check_exception to print MCE event and panic. */
475 addi r3,r1,STACK_FRAME_OVERHEAD
476 bl machine_check_exception
477 /*
478 * We will not reach here. Even if we did, there is no way out. Call
479 * unrecoverable_exception and die.
480 */
4811: addi r3,r1,STACK_FRAME_OVERHEAD
482 bl unrecoverable_exception
483 b 1b
484
485
486EXC_REAL(data_access, 0x300, 0x380)
487EXC_VIRT(data_access, 0x4300, 0x4380, 0x300)
488TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
489
490EXC_COMMON_BEGIN(data_access_common)
491 /*
492 * Here r13 points to the paca, r9 contains the saved CR,
493 * SRR0 and SRR1 are saved in r11 and r12,
494 * r9 - r13 are saved in paca->exgen.
495 */
496 mfspr r10,SPRN_DAR
497 std r10,PACA_EXGEN+EX_DAR(r13)
498 mfspr r10,SPRN_DSISR
499 stw r10,PACA_EXGEN+EX_DSISR(r13)
500 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
501 RECONCILE_IRQ_STATE(r10, r11)
502 ld r12,_MSR(r1)
503 ld r3,PACA_EXGEN+EX_DAR(r13)
504 lwz r4,PACA_EXGEN+EX_DSISR(r13)
505 li r5,0x300
506 std r3,_DAR(r1)
507 std r4,_DSISR(r1)
508BEGIN_MMU_FTR_SECTION
509 b do_hash_page /* Try to handle as hpte fault */
510MMU_FTR_SECTION_ELSE
511 b handle_page_fault
512ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
513
514
515EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400)
516 SET_SCRATCH0(r13)
517 EXCEPTION_PROLOG_0(PACA_EXSLB)
518 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
519 std r3,PACA_EXSLB+EX_R3(r13)
520 mfspr r3,SPRN_DAR
521 mfspr r12,SPRN_SRR1
522 crset 4*cr6+eq
523#ifndef CONFIG_RELOCATABLE
524 b slb_miss_realmode
525#else
526 /*
527 * We can't just use a direct branch to slb_miss_realmode
528 * because the distance from here to there depends on where
529 * the kernel ends up being put.
530 */
531 mfctr r11
532 LOAD_HANDLER(r10, slb_miss_realmode)
533 mtctr r10
534 bctr
535#endif
536EXC_REAL_END(data_access_slb, 0x380, 0x400)
537
538EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400)
539 SET_SCRATCH0(r13)
540 EXCEPTION_PROLOG_0(PACA_EXSLB)
541 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
542 std r3,PACA_EXSLB+EX_R3(r13)
543 mfspr r3,SPRN_DAR
544 mfspr r12,SPRN_SRR1
545 crset 4*cr6+eq
546#ifndef CONFIG_RELOCATABLE
547 b slb_miss_realmode
548#else
549 /*
550 * We can't just use a direct branch to slb_miss_realmode
551 * because the distance from here to there depends on where
552 * the kernel ends up being put.
553 */
554 mfctr r11
555 LOAD_HANDLER(r10, slb_miss_realmode)
556 mtctr r10
557 bctr
558#endif
559EXC_VIRT_END(data_access_slb, 0x4380, 0x4400)
560TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
561
562
563EXC_REAL(instruction_access, 0x400, 0x480)
564EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400)
565TRAMP_KVM(PACA_EXGEN, 0x400)
566
567EXC_COMMON_BEGIN(instruction_access_common)
568 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
569 RECONCILE_IRQ_STATE(r10, r11)
570 ld r12,_MSR(r1)
571 ld r3,_NIP(r1)
572 andis. r4,r12,0x5820
573 li r5,0x400
574 std r3,_DAR(r1)
575 std r4,_DSISR(r1)
576BEGIN_MMU_FTR_SECTION
577 b do_hash_page /* Try to handle as hpte fault */
578MMU_FTR_SECTION_ELSE
579 b handle_page_fault
580ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
581
582
583EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500)
584 SET_SCRATCH0(r13)
585 EXCEPTION_PROLOG_0(PACA_EXSLB)
586 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
587 std r3,PACA_EXSLB+EX_R3(r13)
588 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
589 mfspr r12,SPRN_SRR1
590 crclr 4*cr6+eq
591#ifndef CONFIG_RELOCATABLE
592 b slb_miss_realmode
593#else
594 mfctr r11
595 LOAD_HANDLER(r10, slb_miss_realmode)
596 mtctr r10
597 bctr
598#endif
599EXC_REAL_END(instruction_access_slb, 0x480, 0x500)
600
601EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500)
602 SET_SCRATCH0(r13)
603 EXCEPTION_PROLOG_0(PACA_EXSLB)
604 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
605 std r3,PACA_EXSLB+EX_R3(r13)
606 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
607 mfspr r12,SPRN_SRR1
608 crclr 4*cr6+eq
609#ifndef CONFIG_RELOCATABLE
610 b slb_miss_realmode
611#else
612 mfctr r11
613 LOAD_HANDLER(r10, slb_miss_realmode)
614 mtctr r10
615 bctr
616#endif
617EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500)
618TRAMP_KVM(PACA_EXSLB, 0x480)
619
620
621/* This handler is used by both 0x380 and 0x480 slb miss interrupts */
622EXC_COMMON_BEGIN(slb_miss_realmode)
623 /*
624 * r13 points to the PACA, r9 contains the saved CR,
625 * r12 contain the saved SRR1, SRR0 is still ready for return
626 * r3 has the faulting address
627 * r9 - r13 are saved in paca->exslb.
628 * r3 is saved in paca->slb_r3
629 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
630 * We assume we aren't going to take any exceptions during this
631 * procedure.
632 */
633 mflr r10
634#ifdef CONFIG_RELOCATABLE
635 mtctr r11
636#endif
637
638 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
639 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
640 std r3,PACA_EXSLB+EX_DAR(r13)
641
642 crset 4*cr0+eq
643#ifdef CONFIG_PPC_STD_MMU_64
644BEGIN_MMU_FTR_SECTION
645 bl slb_allocate_realmode
646END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
647#endif
648
649 ld r10,PACA_EXSLB+EX_LR(r13)
650 ld r3,PACA_EXSLB+EX_R3(r13)
651 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
652 mtlr r10
653
654 beq 8f /* if bad address, make full stack frame */
655
656 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
657 beq- 2f
658
659 /* All done -- return from exception. */
660
661.machine push
662.machine "power4"
663 mtcrf 0x80,r9
664 mtcrf 0x02,r9 /* I/D indication is in cr6 */
665 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
666.machine pop
667
668 RESTORE_PPR_PACA(PACA_EXSLB, r9)
669 ld r9,PACA_EXSLB+EX_R9(r13)
670 ld r10,PACA_EXSLB+EX_R10(r13)
671 ld r11,PACA_EXSLB+EX_R11(r13)
672 ld r12,PACA_EXSLB+EX_R12(r13)
673 ld r13,PACA_EXSLB+EX_R13(r13)
674 rfid
675 b . /* prevent speculative execution */
676
6772: mfspr r11,SPRN_SRR0
678 LOAD_HANDLER(r10,unrecov_slb)
679 mtspr SPRN_SRR0,r10
680 ld r10,PACAKMSR(r13)
681 mtspr SPRN_SRR1,r10
682 rfid
683 b .
684
6858: mfspr r11,SPRN_SRR0
686 LOAD_HANDLER(r10,bad_addr_slb)
687 mtspr SPRN_SRR0,r10
688 ld r10,PACAKMSR(r13)
689 mtspr SPRN_SRR1,r10
690 rfid
691 b .
692
693EXC_COMMON_BEGIN(unrecov_slb)
694 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
695 RECONCILE_IRQ_STATE(r10, r11)
696 bl save_nvgprs
6971: addi r3,r1,STACK_FRAME_OVERHEAD
698 bl unrecoverable_exception
699 b 1b
700
701EXC_COMMON_BEGIN(bad_addr_slb)
702 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
703 RECONCILE_IRQ_STATE(r10, r11)
704 ld r3, PACA_EXSLB+EX_DAR(r13)
705 std r3, _DAR(r1)
706 beq cr6, 2f
707 li r10, 0x480 /* fix trap number for I-SLB miss */
708 std r10, _TRAP(r1)
7092: bl save_nvgprs
710 addi r3, r1, STACK_FRAME_OVERHEAD
711 bl slb_miss_bad_addr
712 b ret_from_except
713
714EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600)
715 .globl hardware_interrupt_hv;
716hardware_interrupt_hv:
717 BEGIN_FTR_SECTION
718 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
719 EXC_HV, SOFTEN_TEST_HV)
720do_kvm_H0x500:
721 KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502)
722 FTR_SECTION_ELSE
723 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
724 EXC_STD, SOFTEN_TEST_PR)
725do_kvm_0x500:
726 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500)
727 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
728EXC_REAL_END(hardware_interrupt, 0x500, 0x600)
729
730EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600)
731 .globl hardware_interrupt_relon_hv;
732hardware_interrupt_relon_hv:
733 BEGIN_FTR_SECTION
734 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV)
735 FTR_SECTION_ELSE
736 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR)
737 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
738EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600)
739
740EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
741
742
743EXC_REAL(alignment, 0x600, 0x700)
744EXC_VIRT(alignment, 0x4600, 0x4700, 0x600)
745TRAMP_KVM(PACA_EXGEN, 0x600)
746EXC_COMMON_BEGIN(alignment_common)
747 mfspr r10,SPRN_DAR
748 std r10,PACA_EXGEN+EX_DAR(r13)
749 mfspr r10,SPRN_DSISR
750 stw r10,PACA_EXGEN+EX_DSISR(r13)
751 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
752 ld r3,PACA_EXGEN+EX_DAR(r13)
753 lwz r4,PACA_EXGEN+EX_DSISR(r13)
754 std r3,_DAR(r1)
755 std r4,_DSISR(r1)
756 bl save_nvgprs
757 RECONCILE_IRQ_STATE(r10, r11)
758 addi r3,r1,STACK_FRAME_OVERHEAD
759 bl alignment_exception
760 b ret_from_except
761
762
763EXC_REAL(program_check, 0x700, 0x800)
764EXC_VIRT(program_check, 0x4700, 0x4800, 0x700)
765TRAMP_KVM(PACA_EXGEN, 0x700)
766EXC_COMMON_BEGIN(program_check_common)
767 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
768 bl save_nvgprs
769 RECONCILE_IRQ_STATE(r10, r11)
770 addi r3,r1,STACK_FRAME_OVERHEAD
771 bl program_check_exception
772 b ret_from_except
773
774
775EXC_REAL(fp_unavailable, 0x800, 0x900)
776EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800)
777TRAMP_KVM(PACA_EXGEN, 0x800)
778EXC_COMMON_BEGIN(fp_unavailable_common)
779 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
780 bne 1f /* if from user, just load it up */
781 bl save_nvgprs
782 RECONCILE_IRQ_STATE(r10, r11)
783 addi r3,r1,STACK_FRAME_OVERHEAD
784 bl kernel_fp_unavailable_exception
785 BUG_OPCODE
7861:
787#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
788BEGIN_FTR_SECTION
789 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
790 * transaction), go do TM stuff
791 */
792 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
793 bne- 2f
794END_FTR_SECTION_IFSET(CPU_FTR_TM)
795#endif
796 bl load_up_fpu
797 b fast_exception_return
798#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
7992: /* User process was in a transaction */
800 bl save_nvgprs
801 RECONCILE_IRQ_STATE(r10, r11)
802 addi r3,r1,STACK_FRAME_OVERHEAD
803 bl fp_unavailable_tm
804 b ret_from_except
805#endif
806
807
808EXC_REAL_MASKABLE(decrementer, 0x900, 0x980)
809EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900)
810TRAMP_KVM(PACA_EXGEN, 0x900)
811EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
812
813
814EXC_REAL_HV(hdecrementer, 0x980, 0xa00)
815EXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980)
816TRAMP_KVM_HV(PACA_EXGEN, 0x980)
817EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
818
819
820EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00)
821EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00)
822TRAMP_KVM(PACA_EXGEN, 0xa00)
823#ifdef CONFIG_PPC_DOORBELL
824EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
825#else
826EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
827#endif
828
829
830EXC_REAL(trap_0b, 0xb00, 0xc00)
831EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00)
832TRAMP_KVM(PACA_EXGEN, 0xb00)
833EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
834
835#define LOAD_SYSCALL_HANDLER(reg) \
836 __LOAD_HANDLER(reg, system_call_common)
837
838/* Syscall routine is used twice, in reloc-off and reloc-on paths */
839#define SYSCALL_PSERIES_1 \
840BEGIN_FTR_SECTION \
841 cmpdi r0,0x1ebe ; \
842 beq- 1f ; \
843END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
844 mr r9,r13 ; \
845 GET_PACA(r13) ; \
846 mfspr r11,SPRN_SRR0 ; \
8470:
848
849#define SYSCALL_PSERIES_2_RFID \
850 mfspr r12,SPRN_SRR1 ; \
851 LOAD_SYSCALL_HANDLER(r10) ; \
852 mtspr SPRN_SRR0,r10 ; \
853 ld r10,PACAKMSR(r13) ; \
854 mtspr SPRN_SRR1,r10 ; \
855 rfid ; \
856 b . ; /* prevent speculative execution */
857
858#define SYSCALL_PSERIES_3 \
859 /* Fast LE/BE switch system call */ \
8601: mfspr r12,SPRN_SRR1 ; \
861 xori r12,r12,MSR_LE ; \
862 mtspr SPRN_SRR1,r12 ; \
863 rfid ; /* return to userspace */ \
864 b . ; /* prevent speculative execution */
865
866#if defined(CONFIG_RELOCATABLE)
867 /*
868 * We can't branch directly so we do it via the CTR which
869 * is volatile across system calls.
870 */
871#define SYSCALL_PSERIES_2_DIRECT \
872 LOAD_SYSCALL_HANDLER(r12) ; \
873 mtctr r12 ; \
874 mfspr r12,SPRN_SRR1 ; \
875 li r10,MSR_RI ; \
876 mtmsrd r10,1 ; \
877 bctr ;
878#else
879 /* We can branch directly */
880#define SYSCALL_PSERIES_2_DIRECT \
881 mfspr r12,SPRN_SRR1 ; \
882 li r10,MSR_RI ; \
883 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
884 b system_call_common ;
885#endif
886
887EXC_REAL_BEGIN(system_call, 0xc00, 0xd00)
888 /*
889 * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems
890 * that support it) before changing to HMT_MEDIUM. That allows the KVM
891 * code to save that value into the guest state (it is the guest's PPR
892 * value). Otherwise just change to HMT_MEDIUM as userspace has
893 * already saved the PPR.
894 */
895#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
896 SET_SCRATCH0(r13)
897 GET_PACA(r13)
898 std r9,PACA_EXGEN+EX_R9(r13)
899 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR);
900 HMT_MEDIUM;
901 std r10,PACA_EXGEN+EX_R10(r13)
902 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR);
903 mfcr r9
904 KVMTEST_PR(0xc00)
905 GET_SCRATCH0(r13)
906#else
907 HMT_MEDIUM;
908#endif
909 SYSCALL_PSERIES_1
910 SYSCALL_PSERIES_2_RFID
911 SYSCALL_PSERIES_3
912EXC_REAL_END(system_call, 0xc00, 0xd00)
913
914EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00)
915 HMT_MEDIUM
916 SYSCALL_PSERIES_1
917 SYSCALL_PSERIES_2_DIRECT
918 SYSCALL_PSERIES_3
919EXC_VIRT_END(system_call, 0x4c00, 0x4d00)
920
921TRAMP_KVM(PACA_EXGEN, 0xc00)
922
923
924EXC_REAL(single_step, 0xd00, 0xe00)
925EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00)
926TRAMP_KVM(PACA_EXGEN, 0xd00)
927EXC_COMMON(single_step_common, 0xd00, single_step_exception)
928
929EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20)
930EXC_VIRT_NONE(0x4e00, 0x4e20)
931TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
932EXC_COMMON_BEGIN(h_data_storage_common)
933 mfspr r10,SPRN_HDAR
934 std r10,PACA_EXGEN+EX_DAR(r13)
935 mfspr r10,SPRN_HDSISR
936 stw r10,PACA_EXGEN+EX_DSISR(r13)
937 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
938 bl save_nvgprs
939 RECONCILE_IRQ_STATE(r10, r11)
940 addi r3,r1,STACK_FRAME_OVERHEAD
941 bl unknown_exception
942 b ret_from_except
943
944
945EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40)
946EXC_VIRT_NONE(0x4e20, 0x4e40)
947TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
948EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
949
950
951EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60)
952EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60, 0xe40)
953TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
954EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
955
956
957/*
958 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
959 * first, and then eventaully from there to the trampoline to get into virtual
960 * mode.
961 */
962__EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early)
963__TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60)
964EXC_VIRT_NONE(0x4e60, 0x4e80)
965TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
966TRAMP_REAL_BEGIN(hmi_exception_early)
967 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
968 mr r10,r1 /* Save r1 */
969 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
970 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
971 std r9,_CCR(r1) /* save CR in stackframe */
972 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
973 std r11,_NIP(r1) /* save HSRR0 in stackframe */
974 mfspr r12,SPRN_HSRR1 /* Save SRR1 */
975 std r12,_MSR(r1) /* save SRR1 in stackframe */
976 std r10,0(r1) /* make stack chain pointer */
977 std r0,GPR0(r1) /* save r0 in stackframe */
978 std r10,GPR1(r1) /* save r1 in stackframe */
979 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
980 EXCEPTION_PROLOG_COMMON_3(0xe60)
981 addi r3,r1,STACK_FRAME_OVERHEAD
982 bl hmi_exception_realmode
983 /* Windup the stack. */
984 /* Move original HSRR0 and HSRR1 into the respective regs */
985 ld r9,_MSR(r1)
986 mtspr SPRN_HSRR1,r9
987 ld r3,_NIP(r1)
988 mtspr SPRN_HSRR0,r3
989 ld r9,_CTR(r1)
990 mtctr r9
991 ld r9,_XER(r1)
992 mtxer r9
993 ld r9,_LINK(r1)
994 mtlr r9
995 REST_GPR(0, r1)
996 REST_8GPRS(2, r1)
997 REST_GPR(10, r1)
998 ld r11,_CCR(r1)
999 mtcr r11
1000 REST_GPR(11, r1)
1001 REST_2GPRS(12, r1)
1002 /* restore original r1. */
1003 ld r1,GPR1(r1)
1004
1005 /*
1006 * Go to virtual mode and pull the HMI event information from
1007 * firmware.
1008 */
1009 .globl hmi_exception_after_realmode
1010hmi_exception_after_realmode:
1011 SET_SCRATCH0(r13)
1012 EXCEPTION_PROLOG_0(PACA_EXGEN)
1013 b tramp_real_hmi_exception
1014
1015EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception)
1016
1017
1018EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0)
1019EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0, 0xe80)
1020TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1021#ifdef CONFIG_PPC_DOORBELL
1022EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1023#else
1024EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1025#endif
1026
1027
1028EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0)
1029EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0, 0xea0)
1030TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1031EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1032
1033
1034EXC_REAL_NONE(0xec0, 0xf00)
1035EXC_VIRT_NONE(0x4ec0, 0x4f00)
1036
1037
1038EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20)
1039EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20, 0xf00)
1040TRAMP_KVM(PACA_EXGEN, 0xf00)
1041EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1042
1043
1044EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40)
1045EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40, 0xf20)
1046TRAMP_KVM(PACA_EXGEN, 0xf20)
1047EXC_COMMON_BEGIN(altivec_unavailable_common)
1048 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1049#ifdef CONFIG_ALTIVEC
1050BEGIN_FTR_SECTION
1051 beq 1f
1052#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1053 BEGIN_FTR_SECTION_NESTED(69)
1054 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1055 * transaction), go do TM stuff
1056 */
1057 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1058 bne- 2f
1059 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1060#endif
1061 bl load_up_altivec
1062 b fast_exception_return
1063#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
10642: /* User process was in a transaction */
1065 bl save_nvgprs
1066 RECONCILE_IRQ_STATE(r10, r11)
1067 addi r3,r1,STACK_FRAME_OVERHEAD
1068 bl altivec_unavailable_tm
1069 b ret_from_except
1070#endif
10711:
1072END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1073#endif
1074 bl save_nvgprs
1075 RECONCILE_IRQ_STATE(r10, r11)
1076 addi r3,r1,STACK_FRAME_OVERHEAD
1077 bl altivec_unavailable_exception
1078 b ret_from_except
1079
1080
1081EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60)
1082EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60, 0xf40)
1083TRAMP_KVM(PACA_EXGEN, 0xf40)
1084EXC_COMMON_BEGIN(vsx_unavailable_common)
1085 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1086#ifdef CONFIG_VSX
1087BEGIN_FTR_SECTION
1088 beq 1f
1089#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1090 BEGIN_FTR_SECTION_NESTED(69)
1091 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1092 * transaction), go do TM stuff
1093 */
1094 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1095 bne- 2f
1096 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1097#endif
1098 b load_up_vsx
1099#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
11002: /* User process was in a transaction */
1101 bl save_nvgprs
1102 RECONCILE_IRQ_STATE(r10, r11)
1103 addi r3,r1,STACK_FRAME_OVERHEAD
1104 bl vsx_unavailable_tm
1105 b ret_from_except
1106#endif
11071:
1108END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1109#endif
1110 bl save_nvgprs
1111 RECONCILE_IRQ_STATE(r10, r11)
1112 addi r3,r1,STACK_FRAME_OVERHEAD
1113 bl vsx_unavailable_exception
1114 b ret_from_except
1115
1116
1117EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80)
1118EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80, 0xf60)
1119TRAMP_KVM(PACA_EXGEN, 0xf60)
1120EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1121
1122
1123EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0)
1124EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0, 0xf80)
1125TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1126EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1127
1128
1129EXC_REAL_NONE(0xfa0, 0x1200)
1130EXC_VIRT_NONE(0x4fa0, 0x5200)
1131
1132#ifdef CONFIG_CBE_RAS
1133EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300)
1134EXC_VIRT_NONE(0x5200, 0x5300)
1135TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1136EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1137#else /* CONFIG_CBE_RAS */
1138EXC_REAL_NONE(0x1200, 0x1300)
1139EXC_VIRT_NONE(0x5200, 0x5300)
1140#endif
1141
1142
1143EXC_REAL(instruction_breakpoint, 0x1300, 0x1400)
1144EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300)
1145TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1146EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1147
1148EXC_REAL_NONE(0x1400, 0x1500)
1149EXC_VIRT_NONE(0x5400, 0x5500)
1150
1151EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600)
1152 mtspr SPRN_SPRG_HSCRATCH0,r13
1153 EXCEPTION_PROLOG_0(PACA_EXGEN)
1154 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1155
1156#ifdef CONFIG_PPC_DENORMALISATION
1157 mfspr r10,SPRN_HSRR1
1158 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
1159 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1160 addi r11,r11,-4 /* HSRR0 is next instruction */
1161 bne+ denorm_assist
1162#endif
1163
1164 KVMTEST_PR(0x1500)
1165 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1166EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600)
1167
1168#ifdef CONFIG_PPC_DENORMALISATION
1169EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600)
1170 b exc_real_0x1500_denorm_exception_hv
1171EXC_VIRT_END(denorm_exception, 0x5500, 0x5600)
1172#else
1173EXC_VIRT_NONE(0x5500, 0x5600)
1174#endif
1175
1176TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
1177
1178#ifdef CONFIG_PPC_DENORMALISATION
1179TRAMP_REAL_BEGIN(denorm_assist)
1180BEGIN_FTR_SECTION
1181/*
1182 * To denormalise we need to move a copy of the register to itself.
1183 * For POWER6 do that here for all FP regs.
1184 */
1185 mfmsr r10
1186 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1187 xori r10,r10,(MSR_FE0|MSR_FE1)
1188 mtmsrd r10
1189 sync
1190
1191#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
1192#define FMR4(n) FMR2(n) ; FMR2(n+2)
1193#define FMR8(n) FMR4(n) ; FMR4(n+4)
1194#define FMR16(n) FMR8(n) ; FMR8(n+8)
1195#define FMR32(n) FMR16(n) ; FMR16(n+16)
1196 FMR32(0)
1197
1198FTR_SECTION_ELSE
1199/*
1200 * To denormalise we need to move a copy of the register to itself.
1201 * For POWER7 do that here for the first 32 VSX registers only.
1202 */
1203 mfmsr r10
1204 oris r10,r10,MSR_VSX@h
1205 mtmsrd r10
1206 sync
1207
1208#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1209#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1210#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1211#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1212#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1213 XVCPSGNDP32(0)
1214
1215ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1216
1217BEGIN_FTR_SECTION
1218 b denorm_done
1219END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1220/*
1221 * To denormalise we need to move a copy of the register to itself.
1222 * For POWER8 we need to do that for all 64 VSX registers
1223 */
1224 XVCPSGNDP32(32)
1225denorm_done:
1226 mtspr SPRN_HSRR0,r11
1227 mtcrf 0x80,r9
1228 ld r9,PACA_EXGEN+EX_R9(r13)
1229 RESTORE_PPR_PACA(PACA_EXGEN, r10)
1230BEGIN_FTR_SECTION
1231 ld r10,PACA_EXGEN+EX_CFAR(r13)
1232 mtspr SPRN_CFAR,r10
1233END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1234 ld r10,PACA_EXGEN+EX_R10(r13)
1235 ld r11,PACA_EXGEN+EX_R11(r13)
1236 ld r12,PACA_EXGEN+EX_R12(r13)
1237 ld r13,PACA_EXGEN+EX_R13(r13)
1238 HRFID
1239 b .
1240#endif
1241
1242EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception)
1243
1244
1245#ifdef CONFIG_CBE_RAS
1246EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700)
1247EXC_VIRT_NONE(0x5600, 0x5700)
1248TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1249EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1250#else /* CONFIG_CBE_RAS */
1251EXC_REAL_NONE(0x1600, 0x1700)
1252EXC_VIRT_NONE(0x5600, 0x5700)
1253#endif
1254
1255
1256EXC_REAL(altivec_assist, 0x1700, 0x1800)
1257EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700)
1258TRAMP_KVM(PACA_EXGEN, 0x1700)
1259#ifdef CONFIG_ALTIVEC
1260EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1261#else
1262EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1263#endif
1264
1265
1266#ifdef CONFIG_CBE_RAS
1267EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900)
1268EXC_VIRT_NONE(0x5800, 0x5900)
1269TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1270EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1271#else /* CONFIG_CBE_RAS */
1272EXC_REAL_NONE(0x1800, 0x1900)
1273EXC_VIRT_NONE(0x5800, 0x5900)
1274#endif
1275
1276
1277/*
1278 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1279 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1280 * - If it was a doorbell we return immediately since doorbells are edge
1281 * triggered and won't automatically refire.
1282 * - If it was a HMI we return immediately since we handled it in realmode
1283 * and it won't refire.
1284 * - else we hard disable and return.
1285 * This is called with r10 containing the value to OR to the paca field.
1286 */
1287#define MASKED_INTERRUPT(_H) \
1288masked_##_H##interrupt: \
1289 std r11,PACA_EXGEN+EX_R11(r13); \
1290 lbz r11,PACAIRQHAPPENED(r13); \
1291 or r11,r11,r10; \
1292 stb r11,PACAIRQHAPPENED(r13); \
1293 cmpwi r10,PACA_IRQ_DEC; \
1294 bne 1f; \
1295 lis r10,0x7fff; \
1296 ori r10,r10,0xffff; \
1297 mtspr SPRN_DEC,r10; \
1298 b 2f; \
12991: cmpwi r10,PACA_IRQ_DBELL; \
1300 beq 2f; \
1301 cmpwi r10,PACA_IRQ_HMI; \
1302 beq 2f; \
1303 mfspr r10,SPRN_##_H##SRR1; \
1304 rldicl r10,r10,48,1; /* clear MSR_EE */ \
1305 rotldi r10,r10,16; \
1306 mtspr SPRN_##_H##SRR1,r10; \
13072: mtcrf 0x80,r9; \
1308 ld r9,PACA_EXGEN+EX_R9(r13); \
1309 ld r10,PACA_EXGEN+EX_R10(r13); \
1310 ld r11,PACA_EXGEN+EX_R11(r13); \
1311 GET_SCRATCH0(r13); \
1312 ##_H##rfid; \
1313 b .
1314
1315/*
1316 * Real mode exceptions actually use this too, but alternate
1317 * instruction code patches (which end up in the common .text area)
1318 * cannot reach these if they are put there.
1319 */
1320USE_FIXED_SECTION(virt_trampolines)
1321 MASKED_INTERRUPT()
1322 MASKED_INTERRUPT(H)
1323
1324#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1325TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1326 /*
1327 * Here all GPRs are unchanged from when the interrupt happened
1328 * except for r13, which is saved in SPRG_SCRATCH0.
1329 */
1330 mfspr r13, SPRN_SRR0
1331 addi r13, r13, 4
1332 mtspr SPRN_SRR0, r13
1333 GET_SCRATCH0(r13)
1334 rfid
1335 b .
1336
1337TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1338 /*
1339 * Here all GPRs are unchanged from when the interrupt happened
1340 * except for r13, which is saved in SPRG_SCRATCH0.
1341 */
1342 mfspr r13, SPRN_HSRR0
1343 addi r13, r13, 4
1344 mtspr SPRN_HSRR0, r13
1345 GET_SCRATCH0(r13)
1346 hrfid
1347 b .
1348#endif
1349
1350/*
1351 * Ensure that any handlers that get invoked from the exception prologs
1352 * above are below the first 64KB (0x10000) of the kernel image because
1353 * the prologs assemble the addresses of these handlers using the
1354 * LOAD_HANDLER macro, which uses an ori instruction.
1355 */
1356
1357/*** Common interrupt handlers ***/
1358
1359
1360 /*
1361 * Relocation-on interrupts: A subset of the interrupts can be delivered
1362 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1363 * it. Addresses are the same as the original interrupt addresses, but
1364 * offset by 0xc000000000004000.
1365 * It's impossible to receive interrupts below 0x300 via this mechanism.
1366 * KVM: None of these traps are from the guest ; anything that escalated
1367 * to HV=1 from HV=0 is delivered via real mode handlers.
1368 */
1369
1370 /*
1371 * This uses the standard macro, since the original 0x300 vector
1372 * only has extra guff for STAB-based processors -- which never
1373 * come here.
1374 */
1375
1376EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1377 b __ppc64_runlatch_on
1378
1379USE_FIXED_SECTION(virt_trampolines)
1380 /*
1381 * The __end_interrupts marker must be past the out-of-line (OOL)
1382 * handlers, so that they are copied to real address 0x100 when running
1383 * a relocatable kernel. This ensures they can be reached from the short
1384 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1385 * directly, without using LOAD_HANDLER().
1386 */
1387 .align 7
1388 .globl __end_interrupts
1389__end_interrupts:
1390DEFINE_FIXED_SYMBOL(__end_interrupts)
1391
1392#ifdef CONFIG_PPC_970_NAP
1393EXC_COMMON_BEGIN(power4_fixup_nap)
1394 andc r9,r9,r10
1395 std r9,TI_LOCAL_FLAGS(r11)
1396 ld r10,_LINK(r1) /* make idle task do the */
1397 std r10,_NIP(r1) /* equivalent of a blr */
1398 blr
1399#endif
1400
1401CLOSE_FIXED_SECTION(real_vectors);
1402CLOSE_FIXED_SECTION(real_trampolines);
1403CLOSE_FIXED_SECTION(virt_vectors);
1404CLOSE_FIXED_SECTION(virt_trampolines);
1405
1406USE_TEXT_SECTION()
1407
1408/*
1409 * Hash table stuff
1410 */
1411 .balign IFETCH_ALIGN_BYTES
1412do_hash_page:
1413#ifdef CONFIG_PPC_STD_MMU_64
1414 andis. r0,r4,0xa410 /* weird error? */
1415 bne- handle_page_fault /* if not, try to insert a HPTE */
1416 andis. r0,r4,DSISR_DABRMATCH@h
1417 bne- handle_dabr_fault
1418 CURRENT_THREAD_INFO(r11, r1)
1419 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1420 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1421 bne 77f /* then don't call hash_page now */
1422
1423 /*
1424 * r3 contains the faulting address
1425 * r4 msr
1426 * r5 contains the trap number
1427 * r6 contains dsisr
1428 *
1429 * at return r3 = 0 for success, 1 for page fault, negative for error
1430 */
1431 mr r4,r12
1432 ld r6,_DSISR(r1)
1433 bl __hash_page /* build HPTE if possible */
1434 cmpdi r3,0 /* see if __hash_page succeeded */
1435
1436 /* Success */
1437 beq fast_exc_return_irq /* Return from exception on success */
1438
1439 /* Error */
1440 blt- 13f
1441#endif /* CONFIG_PPC_STD_MMU_64 */
1442
1443/* Here we have a page fault that hash_page can't handle. */
1444handle_page_fault:
144511: ld r4,_DAR(r1)
1446 ld r5,_DSISR(r1)
1447 addi r3,r1,STACK_FRAME_OVERHEAD
1448 bl do_page_fault
1449 cmpdi r3,0
1450 beq+ 12f
1451 bl save_nvgprs
1452 mr r5,r3
1453 addi r3,r1,STACK_FRAME_OVERHEAD
1454 lwz r4,_DAR(r1)
1455 bl bad_page_fault
1456 b ret_from_except
1457
1458/* We have a data breakpoint exception - handle it */
1459handle_dabr_fault:
1460 bl save_nvgprs
1461 ld r4,_DAR(r1)
1462 ld r5,_DSISR(r1)
1463 addi r3,r1,STACK_FRAME_OVERHEAD
1464 bl do_break
146512: b ret_from_except_lite
1466
1467
1468#ifdef CONFIG_PPC_STD_MMU_64
1469/* We have a page fault that hash_page could handle but HV refused
1470 * the PTE insertion
1471 */
147213: bl save_nvgprs
1473 mr r5,r3
1474 addi r3,r1,STACK_FRAME_OVERHEAD
1475 ld r4,_DAR(r1)
1476 bl low_hash_fault
1477 b ret_from_except
1478#endif
1479
1480/*
1481 * We come here as a result of a DSI at a point where we don't want
1482 * to call hash_page, such as when we are accessing memory (possibly
1483 * user memory) inside a PMU interrupt that occurred while interrupts
1484 * were soft-disabled. We want to invoke the exception handler for
1485 * the access, or panic if there isn't a handler.
1486 */
148777: bl save_nvgprs
1488 mr r4,r3
1489 addi r3,r1,STACK_FRAME_OVERHEAD
1490 li r5,SIGSEGV
1491 bl bad_page_fault
1492 b ret_from_except
1493
1494/*
1495 * Here we have detected that the kernel stack pointer is bad.
1496 * R9 contains the saved CR, r13 points to the paca,
1497 * r10 contains the (bad) kernel stack pointer,
1498 * r11 and r12 contain the saved SRR0 and SRR1.
1499 * We switch to using an emergency stack, save the registers there,
1500 * and call kernel_bad_stack(), which panics.
1501 */
1502bad_stack:
1503 ld r1,PACAEMERGSP(r13)
1504 subi r1,r1,64+INT_FRAME_SIZE
1505 std r9,_CCR(r1)
1506 std r10,GPR1(r1)
1507 std r11,_NIP(r1)
1508 std r12,_MSR(r1)
1509 mfspr r11,SPRN_DAR
1510 mfspr r12,SPRN_DSISR
1511 std r11,_DAR(r1)
1512 std r12,_DSISR(r1)
1513 mflr r10
1514 mfctr r11
1515 mfxer r12
1516 std r10,_LINK(r1)
1517 std r11,_CTR(r1)
1518 std r12,_XER(r1)
1519 SAVE_GPR(0,r1)
1520 SAVE_GPR(2,r1)
1521 ld r10,EX_R3(r3)
1522 std r10,GPR3(r1)
1523 SAVE_GPR(4,r1)
1524 SAVE_4GPRS(5,r1)
1525 ld r9,EX_R9(r3)
1526 ld r10,EX_R10(r3)
1527 SAVE_2GPRS(9,r1)
1528 ld r9,EX_R11(r3)
1529 ld r10,EX_R12(r3)
1530 ld r11,EX_R13(r3)
1531 std r9,GPR11(r1)
1532 std r10,GPR12(r1)
1533 std r11,GPR13(r1)
1534BEGIN_FTR_SECTION
1535 ld r10,EX_CFAR(r3)
1536 std r10,ORIG_GPR3(r1)
1537END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1538 SAVE_8GPRS(14,r1)
1539 SAVE_10GPRS(22,r1)
1540 lhz r12,PACA_TRAP_SAVE(r13)
1541 std r12,_TRAP(r1)
1542 addi r11,r1,INT_FRAME_SIZE
1543 std r11,0(r1)
1544 li r12,0
1545 std r12,0(r11)
1546 ld r2,PACATOC(r13)
1547 ld r11,exception_marker@toc(r2)
1548 std r12,RESULT(r1)
1549 std r11,STACK_FRAME_OVERHEAD-16(r1)
15501: addi r3,r1,STACK_FRAME_OVERHEAD
1551 bl kernel_bad_stack
1552 b 1b
1553
1554/*
1555 * Called from arch_local_irq_enable when an interrupt needs
1556 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1557 * which kind of interrupt. MSR:EE is already off. We generate a
1558 * stackframe like if a real interrupt had happened.
1559 *
1560 * Note: While MSR:EE is off, we need to make sure that _MSR
1561 * in the generated frame has EE set to 1 or the exception
1562 * handler will not properly re-enable them.
1563 */
1564_GLOBAL(__replay_interrupt)
1565 /* We are going to jump to the exception common code which
1566 * will retrieve various register values from the PACA which
1567 * we don't give a damn about, so we don't bother storing them.
1568 */
1569 mfmsr r12
1570 mflr r11
1571 mfcr r9
1572 ori r12,r12,MSR_EE
1573 cmpwi r3,0x900
1574 beq decrementer_common
1575 cmpwi r3,0x500
1576 beq hardware_interrupt_common
1577BEGIN_FTR_SECTION
1578 cmpwi r3,0xe80
1579 beq h_doorbell_common
1580 cmpwi r3,0xea0
1581 beq h_virt_irq_common
1582 cmpwi r3,0xe60
1583 beq hmi_exception_common
1584FTR_SECTION_ELSE
1585 cmpwi r3,0xa00
1586 beq doorbell_super_common
1587ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1588 blr