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1/*
2 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __MV_UDC_H
11#define __MV_UDC_H
12
13#define VUSBHS_MAX_PORTS 8
14
15#define DQH_ALIGNMENT 2048
16#define DTD_ALIGNMENT 64
17#define DMA_BOUNDARY 4096
18
19#define EP_DIR_IN 1
20#define EP_DIR_OUT 0
21
22#define DMA_ADDR_INVALID (~(dma_addr_t)0)
23
24#define EP0_MAX_PKT_SIZE 64
25/* ep0 transfer state */
26#define WAIT_FOR_SETUP 0
27#define DATA_STATE_XMIT 1
28#define DATA_STATE_NEED_ZLP 2
29#define WAIT_FOR_OUT_STATUS 3
30#define DATA_STATE_RECV 4
31
32#define CAPLENGTH_MASK (0xff)
33#define DCCPARAMS_DEN_MASK (0x1f)
34
35#define HCSPARAMS_PPC (0x10)
36
37/* Frame Index Register Bit Masks */
38#define USB_FRINDEX_MASKS 0x3fff
39
40/* Command Register Bit Masks */
41#define USBCMD_RUN_STOP (0x00000001)
42#define USBCMD_CTRL_RESET (0x00000002)
43#define USBCMD_SETUP_TRIPWIRE_SET (0x00002000)
44#define USBCMD_SETUP_TRIPWIRE_CLEAR (~USBCMD_SETUP_TRIPWIRE_SET)
45
46#define USBCMD_ATDTW_TRIPWIRE_SET (0x00004000)
47#define USBCMD_ATDTW_TRIPWIRE_CLEAR (~USBCMD_ATDTW_TRIPWIRE_SET)
48
49/* bit 15,3,2 are for frame list size */
50#define USBCMD_FRAME_SIZE_1024 (0x00000000) /* 000 */
51#define USBCMD_FRAME_SIZE_512 (0x00000004) /* 001 */
52#define USBCMD_FRAME_SIZE_256 (0x00000008) /* 010 */
53#define USBCMD_FRAME_SIZE_128 (0x0000000C) /* 011 */
54#define USBCMD_FRAME_SIZE_64 (0x00008000) /* 100 */
55#define USBCMD_FRAME_SIZE_32 (0x00008004) /* 101 */
56#define USBCMD_FRAME_SIZE_16 (0x00008008) /* 110 */
57#define USBCMD_FRAME_SIZE_8 (0x0000800C) /* 111 */
58
59#define EPCTRL_TX_ALL_MASK (0xFFFF0000)
60#define EPCTRL_RX_ALL_MASK (0x0000FFFF)
61
62#define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000)
63#define EPCTRL_TX_EP_STALL (0x00010000)
64#define EPCTRL_RX_EP_STALL (0x00000001)
65#define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040)
66#define EPCTRL_RX_ENABLE (0x00000080)
67#define EPCTRL_TX_ENABLE (0x00800000)
68#define EPCTRL_CONTROL (0x00000000)
69#define EPCTRL_ISOCHRONOUS (0x00040000)
70#define EPCTRL_BULK (0x00080000)
71#define EPCTRL_INT (0x000C0000)
72#define EPCTRL_TX_TYPE (0x000C0000)
73#define EPCTRL_RX_TYPE (0x0000000C)
74#define EPCTRL_DATA_TOGGLE_INHIBIT (0x00000020)
75#define EPCTRL_TX_EP_TYPE_SHIFT (18)
76#define EPCTRL_RX_EP_TYPE_SHIFT (2)
77
78#define EPCOMPLETE_MAX_ENDPOINTS (16)
79
80/* endpoint list address bit masks */
81#define USB_EP_LIST_ADDRESS_MASK 0xfffff800
82
83#define PORTSCX_W1C_BITS 0x2a
84#define PORTSCX_PORT_RESET 0x00000100
85#define PORTSCX_PORT_POWER 0x00001000
86#define PORTSCX_FORCE_FULL_SPEED_CONNECT 0x01000000
87#define PORTSCX_PAR_XCVR_SELECT 0xC0000000
88#define PORTSCX_PORT_FORCE_RESUME 0x00000040
89#define PORTSCX_PORT_SUSPEND 0x00000080
90#define PORTSCX_PORT_SPEED_FULL 0x00000000
91#define PORTSCX_PORT_SPEED_LOW 0x04000000
92#define PORTSCX_PORT_SPEED_HIGH 0x08000000
93#define PORTSCX_PORT_SPEED_MASK 0x0C000000
94
95/* USB MODE Register Bit Masks */
96#define USBMODE_CTRL_MODE_IDLE 0x00000000
97#define USBMODE_CTRL_MODE_DEVICE 0x00000002
98#define USBMODE_CTRL_MODE_HOST 0x00000003
99#define USBMODE_CTRL_MODE_RSV 0x00000001
100#define USBMODE_SETUP_LOCK_OFF 0x00000008
101#define USBMODE_STREAM_DISABLE 0x00000010
102
103/* USB STS Register Bit Masks */
104#define USBSTS_INT 0x00000001
105#define USBSTS_ERR 0x00000002
106#define USBSTS_PORT_CHANGE 0x00000004
107#define USBSTS_FRM_LST_ROLL 0x00000008
108#define USBSTS_SYS_ERR 0x00000010
109#define USBSTS_IAA 0x00000020
110#define USBSTS_RESET 0x00000040
111#define USBSTS_SOF 0x00000080
112#define USBSTS_SUSPEND 0x00000100
113#define USBSTS_HC_HALTED 0x00001000
114#define USBSTS_RCL 0x00002000
115#define USBSTS_PERIODIC_SCHEDULE 0x00004000
116#define USBSTS_ASYNC_SCHEDULE 0x00008000
117
118
119/* Interrupt Enable Register Bit Masks */
120#define USBINTR_INT_EN (0x00000001)
121#define USBINTR_ERR_INT_EN (0x00000002)
122#define USBINTR_PORT_CHANGE_DETECT_EN (0x00000004)
123
124#define USBINTR_ASYNC_ADV_AAE (0x00000020)
125#define USBINTR_ASYNC_ADV_AAE_ENABLE (0x00000020)
126#define USBINTR_ASYNC_ADV_AAE_DISABLE (0xFFFFFFDF)
127
128#define USBINTR_RESET_EN (0x00000040)
129#define USBINTR_SOF_UFRAME_EN (0x00000080)
130#define USBINTR_DEVICE_SUSPEND (0x00000100)
131
132#define USB_DEVICE_ADDRESS_MASK (0xfe000000)
133#define USB_DEVICE_ADDRESS_BIT_SHIFT (25)
134
135struct mv_cap_regs {
136 u32 caplength_hciversion;
137 u32 hcsparams; /* HC structural parameters */
138 u32 hccparams; /* HC Capability Parameters*/
139 u32 reserved[5];
140 u32 dciversion; /* DC version number and reserved 16 bits */
141 u32 dccparams; /* DC Capability Parameters */
142};
143
144struct mv_op_regs {
145 u32 usbcmd; /* Command register */
146 u32 usbsts; /* Status register */
147 u32 usbintr; /* Interrupt enable */
148 u32 frindex; /* Frame index */
149 u32 reserved1[1];
150 u32 deviceaddr; /* Device Address */
151 u32 eplistaddr; /* Endpoint List Address */
152 u32 ttctrl; /* HOST TT status and control */
153 u32 burstsize; /* Programmable Burst Size */
154 u32 txfilltuning; /* Host Transmit Pre-Buffer Packet Tuning */
155 u32 reserved[4];
156 u32 epnak; /* Endpoint NAK */
157 u32 epnaken; /* Endpoint NAK Enable */
158 u32 configflag; /* Configured Flag register */
159 u32 portsc[VUSBHS_MAX_PORTS]; /* Port Status/Control x, x = 1..8 */
160 u32 otgsc;
161 u32 usbmode; /* USB Host/Device mode */
162 u32 epsetupstat; /* Endpoint Setup Status */
163 u32 epprime; /* Endpoint Initialize */
164 u32 epflush; /* Endpoint De-initialize */
165 u32 epstatus; /* Endpoint Status */
166 u32 epcomplete; /* Endpoint Interrupt On Complete */
167 u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */
168 u32 mcr; /* Mux Control */
169 u32 isr; /* Interrupt Status */
170 u32 ier; /* Interrupt Enable */
171};
172
173struct mv_udc {
174 struct usb_gadget gadget;
175 struct usb_gadget_driver *driver;
176 spinlock_t lock;
177 struct completion *done;
178 struct platform_device *dev;
179 int irq;
180
181 struct mv_cap_regs __iomem *cap_regs;
182 struct mv_op_regs __iomem *op_regs;
183 void __iomem *phy_regs;
184 unsigned int max_eps;
185 struct mv_dqh *ep_dqh;
186 size_t ep_dqh_size;
187 dma_addr_t ep_dqh_dma;
188
189 struct dma_pool *dtd_pool;
190 struct mv_ep *eps;
191
192 struct mv_dtd *dtd_head;
193 struct mv_dtd *dtd_tail;
194 unsigned int dtd_entries;
195
196 struct mv_req *status_req;
197 struct usb_ctrlrequest local_setup_buff;
198
199 unsigned int resume_state; /* USB state to resume */
200 unsigned int usb_state; /* USB current state */
201 unsigned int ep0_state; /* Endpoint zero state */
202 unsigned int ep0_dir;
203
204 unsigned int dev_addr;
205 unsigned int test_mode;
206
207 int errors;
208 unsigned softconnect:1,
209 vbus_active:1,
210 remote_wakeup:1,
211 softconnected:1,
212 force_fs:1,
213 clock_gating:1,
214 active:1,
215 stopped:1; /* stop bit is setted */
216
217 struct work_struct vbus_work;
218 struct workqueue_struct *qwork;
219
220 struct usb_phy *transceiver;
221
222 struct mv_usb_platform_data *pdata;
223
224 /* some SOC has mutiple clock sources for USB*/
225 unsigned int clknum;
226 struct clk *clk[0];
227};
228
229/* endpoint data structure */
230struct mv_ep {
231 struct usb_ep ep;
232 struct mv_udc *udc;
233 struct list_head queue;
234 struct mv_dqh *dqh;
235 u32 direction;
236 char name[14];
237 unsigned stopped:1,
238 wedge:1,
239 ep_type:2,
240 ep_num:8;
241};
242
243/* request data structure */
244struct mv_req {
245 struct usb_request req;
246 struct mv_dtd *dtd, *head, *tail;
247 struct mv_ep *ep;
248 struct list_head queue;
249 unsigned int test_mode;
250 unsigned dtd_count;
251 unsigned mapped:1;
252};
253
254#define EP_QUEUE_HEAD_MULT_POS 30
255#define EP_QUEUE_HEAD_ZLT_SEL 0x20000000
256#define EP_QUEUE_HEAD_MAX_PKT_LEN_POS 16
257#define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff)
258#define EP_QUEUE_HEAD_IOS 0x00008000
259#define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001
260#define EP_QUEUE_HEAD_IOC 0x00008000
261#define EP_QUEUE_HEAD_MULTO 0x00000C00
262#define EP_QUEUE_HEAD_STATUS_HALT 0x00000040
263#define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080
264#define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF
265#define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0
266#define EP_QUEUE_FRINDEX_MASK 0x000007FF
267#define EP_MAX_LENGTH_TRANSFER 0x4000
268
269struct mv_dqh {
270 /* Bits 16..26 Bit 15 is Interrupt On Setup */
271 u32 max_packet_length;
272 u32 curr_dtd_ptr; /* Current dTD Pointer */
273 u32 next_dtd_ptr; /* Next dTD Pointer */
274 /* Total bytes (16..30), IOC (15), INT (8), STS (0-7) */
275 u32 size_ioc_int_sts;
276 u32 buff_ptr0; /* Buffer pointer Page 0 (12-31) */
277 u32 buff_ptr1; /* Buffer pointer Page 1 (12-31) */
278 u32 buff_ptr2; /* Buffer pointer Page 2 (12-31) */
279 u32 buff_ptr3; /* Buffer pointer Page 3 (12-31) */
280 u32 buff_ptr4; /* Buffer pointer Page 4 (12-31) */
281 u32 reserved1;
282 /* 8 bytes of setup data that follows the Setup PID */
283 u8 setup_buffer[8];
284 u32 reserved2[4];
285};
286
287
288#define DTD_NEXT_TERMINATE (0x00000001)
289#define DTD_IOC (0x00008000)
290#define DTD_STATUS_ACTIVE (0x00000080)
291#define DTD_STATUS_HALTED (0x00000040)
292#define DTD_STATUS_DATA_BUFF_ERR (0x00000020)
293#define DTD_STATUS_TRANSACTION_ERR (0x00000008)
294#define DTD_RESERVED_FIELDS (0x00007F00)
295#define DTD_ERROR_MASK (0x68)
296#define DTD_ADDR_MASK (0xFFFFFFE0)
297#define DTD_PACKET_SIZE 0x7FFF0000
298#define DTD_LENGTH_BIT_POS (16)
299
300struct mv_dtd {
301 u32 dtd_next;
302 u32 size_ioc_sts;
303 u32 buff_ptr0; /* Buffer pointer Page 0 */
304 u32 buff_ptr1; /* Buffer pointer Page 1 */
305 u32 buff_ptr2; /* Buffer pointer Page 2 */
306 u32 buff_ptr3; /* Buffer pointer Page 3 */
307 u32 buff_ptr4; /* Buffer pointer Page 4 */
308 u32 scratch_ptr;
309 /* 32 bytes */
310 dma_addr_t td_dma; /* dma address for this td */
311 struct mv_dtd *next_dtd_virt;
312};
313
314#endif