Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * pm8xxx RTC driver
4 *
5 * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
6 * Copyright (c) 2023, Linaro Limited
7 */
8#include <linux/of.h>
9#include <linux/module.h>
10#include <linux/nvmem-consumer.h>
11#include <linux/init.h>
12#include <linux/rtc.h>
13#include <linux/platform_device.h>
14#include <linux/pm.h>
15#include <linux/pm_wakeirq.h>
16#include <linux/regmap.h>
17#include <linux/slab.h>
18#include <linux/spinlock.h>
19
20#include <asm/unaligned.h>
21
22/* RTC_CTRL register bit fields */
23#define PM8xxx_RTC_ENABLE BIT(7)
24#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
25#define PM8xxx_RTC_ALARM_ENABLE BIT(7)
26
27#define NUM_8_BIT_RTC_REGS 0x4
28
29/**
30 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
31 * @ctrl: address of control register
32 * @write: base address of write registers
33 * @read: base address of read registers
34 * @alarm_ctrl: address of alarm control register
35 * @alarm_ctrl2: address of alarm control2 register
36 * @alarm_rw: base address of alarm read-write registers
37 * @alarm_en: alarm enable mask
38 */
39struct pm8xxx_rtc_regs {
40 unsigned int ctrl;
41 unsigned int write;
42 unsigned int read;
43 unsigned int alarm_ctrl;
44 unsigned int alarm_ctrl2;
45 unsigned int alarm_rw;
46 unsigned int alarm_en;
47};
48
49/**
50 * struct pm8xxx_rtc - RTC driver internal structure
51 * @rtc: RTC device
52 * @regmap: regmap used to access registers
53 * @allow_set_time: whether the time can be set
54 * @alarm_irq: alarm irq number
55 * @regs: register description
56 * @dev: device structure
57 * @nvmem_cell: nvmem cell for offset
58 * @offset: offset from epoch in seconds
59 */
60struct pm8xxx_rtc {
61 struct rtc_device *rtc;
62 struct regmap *regmap;
63 bool allow_set_time;
64 int alarm_irq;
65 const struct pm8xxx_rtc_regs *regs;
66 struct device *dev;
67 struct nvmem_cell *nvmem_cell;
68 u32 offset;
69};
70
71static int pm8xxx_rtc_read_nvmem_offset(struct pm8xxx_rtc *rtc_dd)
72{
73 size_t len;
74 void *buf;
75 int rc;
76
77 buf = nvmem_cell_read(rtc_dd->nvmem_cell, &len);
78 if (IS_ERR(buf)) {
79 rc = PTR_ERR(buf);
80 dev_dbg(rtc_dd->dev, "failed to read nvmem offset: %d\n", rc);
81 return rc;
82 }
83
84 if (len != sizeof(u32)) {
85 dev_dbg(rtc_dd->dev, "unexpected nvmem cell size %zu\n", len);
86 kfree(buf);
87 return -EINVAL;
88 }
89
90 rtc_dd->offset = get_unaligned_le32(buf);
91
92 kfree(buf);
93
94 return 0;
95}
96
97static int pm8xxx_rtc_write_nvmem_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)
98{
99 u8 buf[sizeof(u32)];
100 int rc;
101
102 put_unaligned_le32(offset, buf);
103
104 rc = nvmem_cell_write(rtc_dd->nvmem_cell, buf, sizeof(buf));
105 if (rc < 0) {
106 dev_dbg(rtc_dd->dev, "failed to write nvmem offset: %d\n", rc);
107 return rc;
108 }
109
110 return 0;
111}
112
113static int pm8xxx_rtc_read_offset(struct pm8xxx_rtc *rtc_dd)
114{
115 if (!rtc_dd->nvmem_cell)
116 return 0;
117
118 return pm8xxx_rtc_read_nvmem_offset(rtc_dd);
119}
120
121static int pm8xxx_rtc_read_raw(struct pm8xxx_rtc *rtc_dd, u32 *secs)
122{
123 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
124 u8 value[NUM_8_BIT_RTC_REGS];
125 unsigned int reg;
126 int rc;
127
128 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
129 if (rc)
130 return rc;
131
132 /*
133 * Read the LSB again and check if there has been a carry over.
134 * If there has, redo the read operation.
135 */
136 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
137 if (rc < 0)
138 return rc;
139
140 if (reg < value[0]) {
141 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value,
142 sizeof(value));
143 if (rc)
144 return rc;
145 }
146
147 *secs = get_unaligned_le32(value);
148
149 return 0;
150}
151
152static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs)
153{
154 u32 raw_secs;
155 u32 offset;
156 int rc;
157
158 if (!rtc_dd->nvmem_cell)
159 return -ENODEV;
160
161 rc = pm8xxx_rtc_read_raw(rtc_dd, &raw_secs);
162 if (rc)
163 return rc;
164
165 offset = secs - raw_secs;
166
167 if (offset == rtc_dd->offset)
168 return 0;
169
170 rc = pm8xxx_rtc_write_nvmem_offset(rtc_dd, offset);
171 if (rc)
172 return rc;
173
174 rtc_dd->offset = offset;
175
176 return 0;
177}
178
179/*
180 * Steps to write the RTC registers.
181 * 1. Disable alarm if enabled.
182 * 2. Disable rtc if enabled.
183 * 3. Write 0x00 to LSB.
184 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
185 * 5. Enable rtc if disabled in step 2.
186 * 6. Enable alarm if disabled in step 1.
187 */
188static int __pm8xxx_rtc_set_time(struct pm8xxx_rtc *rtc_dd, u32 secs)
189{
190 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
191 u8 value[NUM_8_BIT_RTC_REGS];
192 bool alarm_enabled;
193 int rc;
194
195 put_unaligned_le32(secs, value);
196
197 rc = regmap_update_bits_check(rtc_dd->regmap, regs->alarm_ctrl,
198 regs->alarm_en, 0, &alarm_enabled);
199 if (rc)
200 return rc;
201
202 /* Disable RTC */
203 rc = regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE, 0);
204 if (rc)
205 return rc;
206
207 /* Write 0 to Byte[0] */
208 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
209 if (rc)
210 return rc;
211
212 /* Write Byte[1], Byte[2], Byte[3] */
213 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
214 &value[1], sizeof(value) - 1);
215 if (rc)
216 return rc;
217
218 /* Write Byte[0] */
219 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
220 if (rc)
221 return rc;
222
223 /* Enable RTC */
224 rc = regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE,
225 PM8xxx_RTC_ENABLE);
226 if (rc)
227 return rc;
228
229 if (alarm_enabled) {
230 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
231 regs->alarm_en, regs->alarm_en);
232 if (rc)
233 return rc;
234 }
235
236 return 0;
237}
238
239static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
240{
241 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
242 u32 secs;
243 int rc;
244
245 secs = rtc_tm_to_time64(tm);
246
247 if (rtc_dd->allow_set_time)
248 rc = __pm8xxx_rtc_set_time(rtc_dd, secs);
249 else
250 rc = pm8xxx_rtc_update_offset(rtc_dd, secs);
251
252 if (rc)
253 return rc;
254
255 dev_dbg(dev, "set time: %ptRd %ptRt (%u + %u)\n", tm, tm,
256 secs - rtc_dd->offset, rtc_dd->offset);
257 return 0;
258}
259
260static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
261{
262 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
263 u32 secs;
264 int rc;
265
266 rc = pm8xxx_rtc_read_raw(rtc_dd, &secs);
267 if (rc)
268 return rc;
269
270 secs += rtc_dd->offset;
271 rtc_time64_to_tm(secs, tm);
272
273 dev_dbg(dev, "read time: %ptRd %ptRt (%u + %u)\n", tm, tm,
274 secs - rtc_dd->offset, rtc_dd->offset);
275 return 0;
276}
277
278static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
279{
280 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
281 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
282 u8 value[NUM_8_BIT_RTC_REGS];
283 u32 secs;
284 int rc;
285
286 secs = rtc_tm_to_time64(&alarm->time);
287 secs -= rtc_dd->offset;
288 put_unaligned_le32(secs, value);
289
290 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
291 regs->alarm_en, 0);
292 if (rc)
293 return rc;
294
295 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
296 sizeof(value));
297 if (rc)
298 return rc;
299
300 if (alarm->enabled) {
301 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
302 regs->alarm_en, regs->alarm_en);
303 if (rc)
304 return rc;
305 }
306
307 dev_dbg(dev, "set alarm: %ptRd %ptRt\n", &alarm->time, &alarm->time);
308
309 return 0;
310}
311
312static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
313{
314 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
315 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
316 u8 value[NUM_8_BIT_RTC_REGS];
317 unsigned int ctrl_reg;
318 u32 secs;
319 int rc;
320
321 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
322 sizeof(value));
323 if (rc)
324 return rc;
325
326 secs = get_unaligned_le32(value);
327 secs += rtc_dd->offset;
328 rtc_time64_to_tm(secs, &alarm->time);
329
330 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
331 if (rc)
332 return rc;
333
334 alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);
335
336 dev_dbg(dev, "read alarm: %ptRd %ptRt\n", &alarm->time, &alarm->time);
337
338 return 0;
339}
340
341static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
342{
343 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
344 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
345 u8 value[NUM_8_BIT_RTC_REGS] = {0};
346 unsigned int val;
347 int rc;
348
349 if (enable)
350 val = regs->alarm_en;
351 else
352 val = 0;
353
354 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
355 regs->alarm_en, val);
356 if (rc)
357 return rc;
358
359 /* Clear alarm register */
360 if (!enable) {
361 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
362 sizeof(value));
363 if (rc)
364 return rc;
365 }
366
367 return 0;
368}
369
370static const struct rtc_class_ops pm8xxx_rtc_ops = {
371 .read_time = pm8xxx_rtc_read_time,
372 .set_time = pm8xxx_rtc_set_time,
373 .set_alarm = pm8xxx_rtc_set_alarm,
374 .read_alarm = pm8xxx_rtc_read_alarm,
375 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
376};
377
378static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
379{
380 struct pm8xxx_rtc *rtc_dd = dev_id;
381 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
382 int rc;
383
384 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
385
386 /* Disable alarm */
387 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
388 regs->alarm_en, 0);
389 if (rc)
390 return IRQ_NONE;
391
392 /* Clear alarm status */
393 rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl2,
394 PM8xxx_RTC_ALARM_CLEAR, 0);
395 if (rc)
396 return IRQ_NONE;
397
398 return IRQ_HANDLED;
399}
400
401static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
402{
403 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
404
405 return regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE,
406 PM8xxx_RTC_ENABLE);
407}
408
409static const struct pm8xxx_rtc_regs pm8921_regs = {
410 .ctrl = 0x11d,
411 .write = 0x11f,
412 .read = 0x123,
413 .alarm_rw = 0x127,
414 .alarm_ctrl = 0x11d,
415 .alarm_ctrl2 = 0x11e,
416 .alarm_en = BIT(1),
417};
418
419static const struct pm8xxx_rtc_regs pm8058_regs = {
420 .ctrl = 0x1e8,
421 .write = 0x1ea,
422 .read = 0x1ee,
423 .alarm_rw = 0x1f2,
424 .alarm_ctrl = 0x1e8,
425 .alarm_ctrl2 = 0x1e9,
426 .alarm_en = BIT(1),
427};
428
429static const struct pm8xxx_rtc_regs pm8941_regs = {
430 .ctrl = 0x6046,
431 .write = 0x6040,
432 .read = 0x6048,
433 .alarm_rw = 0x6140,
434 .alarm_ctrl = 0x6146,
435 .alarm_ctrl2 = 0x6148,
436 .alarm_en = BIT(7),
437};
438
439static const struct pm8xxx_rtc_regs pmk8350_regs = {
440 .ctrl = 0x6146,
441 .write = 0x6140,
442 .read = 0x6148,
443 .alarm_rw = 0x6240,
444 .alarm_ctrl = 0x6246,
445 .alarm_ctrl2 = 0x6248,
446 .alarm_en = BIT(7),
447};
448
449static const struct of_device_id pm8xxx_id_table[] = {
450 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
451 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
452 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
453 { .compatible = "qcom,pmk8350-rtc", .data = &pmk8350_regs },
454 { },
455};
456MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
457
458static int pm8xxx_rtc_probe(struct platform_device *pdev)
459{
460 const struct of_device_id *match;
461 struct pm8xxx_rtc *rtc_dd;
462 int rc;
463
464 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
465 if (!match)
466 return -ENXIO;
467
468 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
469 if (rtc_dd == NULL)
470 return -ENOMEM;
471
472 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
473 if (!rtc_dd->regmap)
474 return -ENXIO;
475
476 rtc_dd->alarm_irq = platform_get_irq(pdev, 0);
477 if (rtc_dd->alarm_irq < 0)
478 return -ENXIO;
479
480 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
481 "allow-set-time");
482
483 rtc_dd->nvmem_cell = devm_nvmem_cell_get(&pdev->dev, "offset");
484 if (IS_ERR(rtc_dd->nvmem_cell)) {
485 rc = PTR_ERR(rtc_dd->nvmem_cell);
486 if (rc != -ENOENT)
487 return rc;
488 rtc_dd->nvmem_cell = NULL;
489 }
490
491 rtc_dd->regs = match->data;
492 rtc_dd->dev = &pdev->dev;
493
494 if (!rtc_dd->allow_set_time) {
495 rc = pm8xxx_rtc_read_offset(rtc_dd);
496 if (rc)
497 return rc;
498 }
499
500 rc = pm8xxx_rtc_enable(rtc_dd);
501 if (rc)
502 return rc;
503
504 platform_set_drvdata(pdev, rtc_dd);
505
506 device_init_wakeup(&pdev->dev, 1);
507
508 rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
509 if (IS_ERR(rtc_dd->rtc))
510 return PTR_ERR(rtc_dd->rtc);
511
512 rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
513 rtc_dd->rtc->range_max = U32_MAX;
514
515 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->alarm_irq,
516 pm8xxx_alarm_trigger,
517 IRQF_TRIGGER_RISING,
518 "pm8xxx_rtc_alarm", rtc_dd);
519 if (rc < 0)
520 return rc;
521
522 rc = devm_rtc_register_device(rtc_dd->rtc);
523 if (rc)
524 return rc;
525
526 rc = dev_pm_set_wake_irq(&pdev->dev, rtc_dd->alarm_irq);
527 if (rc)
528 return rc;
529
530 return 0;
531}
532
533static void pm8xxx_remove(struct platform_device *pdev)
534{
535 dev_pm_clear_wake_irq(&pdev->dev);
536}
537
538static struct platform_driver pm8xxx_rtc_driver = {
539 .probe = pm8xxx_rtc_probe,
540 .remove_new = pm8xxx_remove,
541 .driver = {
542 .name = "rtc-pm8xxx",
543 .of_match_table = pm8xxx_id_table,
544 },
545};
546
547module_platform_driver(pm8xxx_rtc_driver);
548
549MODULE_ALIAS("platform:rtc-pm8xxx");
550MODULE_DESCRIPTION("PMIC8xxx RTC driver");
551MODULE_LICENSE("GPL v2");
552MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
553MODULE_AUTHOR("Johan Hovold <johan@kernel.org>");
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/rtc.h>
16#include <linux/pm.h>
17#include <linux/slab.h>
18#include <linux/spinlock.h>
19
20#include <linux/mfd/pm8xxx/core.h>
21#include <linux/mfd/pm8xxx/rtc.h>
22
23
24/* RTC Register offsets from RTC CTRL REG */
25#define PM8XXX_ALARM_CTRL_OFFSET 0x01
26#define PM8XXX_RTC_WRITE_OFFSET 0x02
27#define PM8XXX_RTC_READ_OFFSET 0x06
28#define PM8XXX_ALARM_RW_OFFSET 0x0A
29
30/* RTC_CTRL register bit fields */
31#define PM8xxx_RTC_ENABLE BIT(7)
32#define PM8xxx_RTC_ALARM_ENABLE BIT(1)
33#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
34
35#define NUM_8_BIT_RTC_REGS 0x4
36
37/**
38 * struct pm8xxx_rtc - rtc driver internal structure
39 * @rtc: rtc device for this driver.
40 * @rtc_alarm_irq: rtc alarm irq number.
41 * @rtc_base: address of rtc control register.
42 * @rtc_read_base: base address of read registers.
43 * @rtc_write_base: base address of write registers.
44 * @alarm_rw_base: base address of alarm registers.
45 * @ctrl_reg: rtc control register.
46 * @rtc_dev: device structure.
47 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
48 */
49struct pm8xxx_rtc {
50 struct rtc_device *rtc;
51 int rtc_alarm_irq;
52 int rtc_base;
53 int rtc_read_base;
54 int rtc_write_base;
55 int alarm_rw_base;
56 u8 ctrl_reg;
57 struct device *rtc_dev;
58 spinlock_t ctrl_reg_lock;
59};
60
61/*
62 * The RTC registers need to be read/written one byte at a time. This is a
63 * hardware limitation.
64 */
65static int pm8xxx_read_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val,
66 int base, int count)
67{
68 int i, rc;
69 struct device *parent = rtc_dd->rtc_dev->parent;
70
71 for (i = 0; i < count; i++) {
72 rc = pm8xxx_readb(parent, base + i, &rtc_val[i]);
73 if (rc < 0) {
74 dev_err(rtc_dd->rtc_dev, "PMIC read failed\n");
75 return rc;
76 }
77 }
78
79 return 0;
80}
81
82static int pm8xxx_write_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_val,
83 int base, int count)
84{
85 int i, rc;
86 struct device *parent = rtc_dd->rtc_dev->parent;
87
88 for (i = 0; i < count; i++) {
89 rc = pm8xxx_writeb(parent, base + i, rtc_val[i]);
90 if (rc < 0) {
91 dev_err(rtc_dd->rtc_dev, "PMIC write failed\n");
92 return rc;
93 }
94 }
95
96 return 0;
97}
98
99/*
100 * Steps to write the RTC registers.
101 * 1. Disable alarm if enabled.
102 * 2. Write 0x00 to LSB.
103 * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0].
104 * 4. Enable alarm if disabled in step 1.
105 */
106static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
107{
108 int rc, i;
109 unsigned long secs, irq_flags;
110 u8 value[NUM_8_BIT_RTC_REGS], reg = 0, alarm_enabled = 0, ctrl_reg;
111 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
112
113 rtc_tm_to_time(tm, &secs);
114
115 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
116 value[i] = secs & 0xFF;
117 secs >>= 8;
118 }
119
120 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
121
122 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
123 ctrl_reg = rtc_dd->ctrl_reg;
124
125 if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) {
126 alarm_enabled = 1;
127 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
128 rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base,
129 1);
130 if (rc < 0) {
131 dev_err(dev, "Write to RTC control register "
132 "failed\n");
133 goto rtc_rw_fail;
134 }
135 rtc_dd->ctrl_reg = ctrl_reg;
136 } else
137 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
138
139 /* Write 0 to Byte[0] */
140 reg = 0;
141 rc = pm8xxx_write_wrapper(rtc_dd, ®, rtc_dd->rtc_write_base, 1);
142 if (rc < 0) {
143 dev_err(dev, "Write to RTC write data register failed\n");
144 goto rtc_rw_fail;
145 }
146
147 /* Write Byte[1], Byte[2], Byte[3] */
148 rc = pm8xxx_write_wrapper(rtc_dd, value + 1,
149 rtc_dd->rtc_write_base + 1, 3);
150 if (rc < 0) {
151 dev_err(dev, "Write to RTC write data register failed\n");
152 goto rtc_rw_fail;
153 }
154
155 /* Write Byte[0] */
156 rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->rtc_write_base, 1);
157 if (rc < 0) {
158 dev_err(dev, "Write to RTC write data register failed\n");
159 goto rtc_rw_fail;
160 }
161
162 if (alarm_enabled) {
163 ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
164 rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base,
165 1);
166 if (rc < 0) {
167 dev_err(dev, "Write to RTC control register "
168 "failed\n");
169 goto rtc_rw_fail;
170 }
171 rtc_dd->ctrl_reg = ctrl_reg;
172 }
173
174rtc_rw_fail:
175 if (alarm_enabled)
176 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
177
178 return rc;
179}
180
181static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
182{
183 int rc;
184 u8 value[NUM_8_BIT_RTC_REGS], reg;
185 unsigned long secs;
186 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
187
188 rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->rtc_read_base,
189 NUM_8_BIT_RTC_REGS);
190 if (rc < 0) {
191 dev_err(dev, "RTC read data register failed\n");
192 return rc;
193 }
194
195 /*
196 * Read the LSB again and check if there has been a carry over.
197 * If there is, redo the read operation.
198 */
199 rc = pm8xxx_read_wrapper(rtc_dd, ®, rtc_dd->rtc_read_base, 1);
200 if (rc < 0) {
201 dev_err(dev, "RTC read data register failed\n");
202 return rc;
203 }
204
205 if (unlikely(reg < value[0])) {
206 rc = pm8xxx_read_wrapper(rtc_dd, value,
207 rtc_dd->rtc_read_base, NUM_8_BIT_RTC_REGS);
208 if (rc < 0) {
209 dev_err(dev, "RTC read data register failed\n");
210 return rc;
211 }
212 }
213
214 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
215
216 rtc_time_to_tm(secs, tm);
217
218 rc = rtc_valid_tm(tm);
219 if (rc < 0) {
220 dev_err(dev, "Invalid time read from RTC\n");
221 return rc;
222 }
223
224 dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n",
225 secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
226 tm->tm_mday, tm->tm_mon, tm->tm_year);
227
228 return 0;
229}
230
231static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
232{
233 int rc, i;
234 u8 value[NUM_8_BIT_RTC_REGS], ctrl_reg;
235 unsigned long secs, irq_flags;
236 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
237
238 rtc_tm_to_time(&alarm->time, &secs);
239
240 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
241 value[i] = secs & 0xFF;
242 secs >>= 8;
243 }
244
245 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
246
247 rc = pm8xxx_write_wrapper(rtc_dd, value, rtc_dd->alarm_rw_base,
248 NUM_8_BIT_RTC_REGS);
249 if (rc < 0) {
250 dev_err(dev, "Write to RTC ALARM register failed\n");
251 goto rtc_rw_fail;
252 }
253
254 ctrl_reg = rtc_dd->ctrl_reg;
255 ctrl_reg = alarm->enabled ? (ctrl_reg | PM8xxx_RTC_ALARM_ENABLE) :
256 (ctrl_reg & ~PM8xxx_RTC_ALARM_ENABLE);
257
258 rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
259 if (rc < 0) {
260 dev_err(dev, "Write to RTC control register failed\n");
261 goto rtc_rw_fail;
262 }
263
264 rtc_dd->ctrl_reg = ctrl_reg;
265
266 dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
267 alarm->time.tm_hour, alarm->time.tm_min,
268 alarm->time.tm_sec, alarm->time.tm_mday,
269 alarm->time.tm_mon, alarm->time.tm_year);
270rtc_rw_fail:
271 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
272 return rc;
273}
274
275static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
276{
277 int rc;
278 u8 value[NUM_8_BIT_RTC_REGS];
279 unsigned long secs;
280 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
281
282 rc = pm8xxx_read_wrapper(rtc_dd, value, rtc_dd->alarm_rw_base,
283 NUM_8_BIT_RTC_REGS);
284 if (rc < 0) {
285 dev_err(dev, "RTC alarm time read failed\n");
286 return rc;
287 }
288
289 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
290
291 rtc_time_to_tm(secs, &alarm->time);
292
293 rc = rtc_valid_tm(&alarm->time);
294 if (rc < 0) {
295 dev_err(dev, "Invalid alarm time read from RTC\n");
296 return rc;
297 }
298
299 dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
300 alarm->time.tm_hour, alarm->time.tm_min,
301 alarm->time.tm_sec, alarm->time.tm_mday,
302 alarm->time.tm_mon, alarm->time.tm_year);
303
304 return 0;
305}
306
307static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
308{
309 int rc;
310 unsigned long irq_flags;
311 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
312 u8 ctrl_reg;
313
314 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
315 ctrl_reg = rtc_dd->ctrl_reg;
316 ctrl_reg = (enable) ? (ctrl_reg | PM8xxx_RTC_ALARM_ENABLE) :
317 (ctrl_reg & ~PM8xxx_RTC_ALARM_ENABLE);
318
319 rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
320 if (rc < 0) {
321 dev_err(dev, "Write to RTC control register failed\n");
322 goto rtc_rw_fail;
323 }
324
325 rtc_dd->ctrl_reg = ctrl_reg;
326
327rtc_rw_fail:
328 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
329 return rc;
330}
331
332static struct rtc_class_ops pm8xxx_rtc_ops = {
333 .read_time = pm8xxx_rtc_read_time,
334 .set_alarm = pm8xxx_rtc_set_alarm,
335 .read_alarm = pm8xxx_rtc_read_alarm,
336 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
337};
338
339static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
340{
341 struct pm8xxx_rtc *rtc_dd = dev_id;
342 u8 ctrl_reg;
343 int rc;
344 unsigned long irq_flags;
345
346 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
347
348 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
349
350 /* Clear the alarm enable bit */
351 ctrl_reg = rtc_dd->ctrl_reg;
352 ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
353
354 rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
355 if (rc < 0) {
356 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
357 dev_err(rtc_dd->rtc_dev, "Write to RTC control register "
358 "failed\n");
359 goto rtc_alarm_handled;
360 }
361
362 rtc_dd->ctrl_reg = ctrl_reg;
363 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
364
365 /* Clear RTC alarm register */
366 rc = pm8xxx_read_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base +
367 PM8XXX_ALARM_CTRL_OFFSET, 1);
368 if (rc < 0) {
369 dev_err(rtc_dd->rtc_dev, "RTC Alarm control register read "
370 "failed\n");
371 goto rtc_alarm_handled;
372 }
373
374 ctrl_reg &= ~PM8xxx_RTC_ALARM_CLEAR;
375 rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base +
376 PM8XXX_ALARM_CTRL_OFFSET, 1);
377 if (rc < 0)
378 dev_err(rtc_dd->rtc_dev, "Write to RTC Alarm control register"
379 " failed\n");
380
381rtc_alarm_handled:
382 return IRQ_HANDLED;
383}
384
385static int __devinit pm8xxx_rtc_probe(struct platform_device *pdev)
386{
387 int rc;
388 u8 ctrl_reg;
389 bool rtc_write_enable = false;
390 struct pm8xxx_rtc *rtc_dd;
391 struct resource *rtc_resource;
392 const struct pm8xxx_rtc_platform_data *pdata =
393 dev_get_platdata(&pdev->dev);
394
395 if (pdata != NULL)
396 rtc_write_enable = pdata->rtc_write_enable;
397
398 rtc_dd = kzalloc(sizeof(*rtc_dd), GFP_KERNEL);
399 if (rtc_dd == NULL) {
400 dev_err(&pdev->dev, "Unable to allocate memory!\n");
401 return -ENOMEM;
402 }
403
404 /* Initialise spinlock to protect RTC control register */
405 spin_lock_init(&rtc_dd->ctrl_reg_lock);
406
407 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
408 if (rtc_dd->rtc_alarm_irq < 0) {
409 dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
410 rc = -ENXIO;
411 goto fail_rtc_enable;
412 }
413
414 rtc_resource = platform_get_resource_byname(pdev, IORESOURCE_IO,
415 "pmic_rtc_base");
416 if (!(rtc_resource && rtc_resource->start)) {
417 dev_err(&pdev->dev, "RTC IO resource absent!\n");
418 rc = -ENXIO;
419 goto fail_rtc_enable;
420 }
421
422 rtc_dd->rtc_base = rtc_resource->start;
423
424 /* Setup RTC register addresses */
425 rtc_dd->rtc_write_base = rtc_dd->rtc_base + PM8XXX_RTC_WRITE_OFFSET;
426 rtc_dd->rtc_read_base = rtc_dd->rtc_base + PM8XXX_RTC_READ_OFFSET;
427 rtc_dd->alarm_rw_base = rtc_dd->rtc_base + PM8XXX_ALARM_RW_OFFSET;
428
429 rtc_dd->rtc_dev = &pdev->dev;
430
431 /* Check if the RTC is on, else turn it on */
432 rc = pm8xxx_read_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base, 1);
433 if (rc < 0) {
434 dev_err(&pdev->dev, "RTC control register read failed!\n");
435 goto fail_rtc_enable;
436 }
437
438 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
439 ctrl_reg |= PM8xxx_RTC_ENABLE;
440 rc = pm8xxx_write_wrapper(rtc_dd, &ctrl_reg, rtc_dd->rtc_base,
441 1);
442 if (rc < 0) {
443 dev_err(&pdev->dev, "Write to RTC control register "
444 "failed\n");
445 goto fail_rtc_enable;
446 }
447 }
448
449 rtc_dd->ctrl_reg = ctrl_reg;
450 if (rtc_write_enable == true)
451 pm8xxx_rtc_ops.set_time = pm8xxx_rtc_set_time;
452
453 platform_set_drvdata(pdev, rtc_dd);
454
455 /* Register the RTC device */
456 rtc_dd->rtc = rtc_device_register("pm8xxx_rtc", &pdev->dev,
457 &pm8xxx_rtc_ops, THIS_MODULE);
458 if (IS_ERR(rtc_dd->rtc)) {
459 dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
460 __func__, PTR_ERR(rtc_dd->rtc));
461 rc = PTR_ERR(rtc_dd->rtc);
462 goto fail_rtc_enable;
463 }
464
465 /* Request the alarm IRQ */
466 rc = request_any_context_irq(rtc_dd->rtc_alarm_irq,
467 pm8xxx_alarm_trigger, IRQF_TRIGGER_RISING,
468 "pm8xxx_rtc_alarm", rtc_dd);
469 if (rc < 0) {
470 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
471 goto fail_req_irq;
472 }
473
474 device_init_wakeup(&pdev->dev, 1);
475
476 dev_dbg(&pdev->dev, "Probe success !!\n");
477
478 return 0;
479
480fail_req_irq:
481 rtc_device_unregister(rtc_dd->rtc);
482fail_rtc_enable:
483 platform_set_drvdata(pdev, NULL);
484 kfree(rtc_dd);
485 return rc;
486}
487
488static int __devexit pm8xxx_rtc_remove(struct platform_device *pdev)
489{
490 struct pm8xxx_rtc *rtc_dd = platform_get_drvdata(pdev);
491
492 device_init_wakeup(&pdev->dev, 0);
493 free_irq(rtc_dd->rtc_alarm_irq, rtc_dd);
494 rtc_device_unregister(rtc_dd->rtc);
495 platform_set_drvdata(pdev, NULL);
496 kfree(rtc_dd);
497
498 return 0;
499}
500
501#ifdef CONFIG_PM_SLEEP
502static int pm8xxx_rtc_resume(struct device *dev)
503{
504 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
505
506 if (device_may_wakeup(dev))
507 disable_irq_wake(rtc_dd->rtc_alarm_irq);
508
509 return 0;
510}
511
512static int pm8xxx_rtc_suspend(struct device *dev)
513{
514 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
515
516 if (device_may_wakeup(dev))
517 enable_irq_wake(rtc_dd->rtc_alarm_irq);
518
519 return 0;
520}
521#endif
522
523static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops, pm8xxx_rtc_suspend, pm8xxx_rtc_resume);
524
525static struct platform_driver pm8xxx_rtc_driver = {
526 .probe = pm8xxx_rtc_probe,
527 .remove = __devexit_p(pm8xxx_rtc_remove),
528 .driver = {
529 .name = PM8XXX_RTC_DEV_NAME,
530 .owner = THIS_MODULE,
531 .pm = &pm8xxx_rtc_pm_ops,
532 },
533};
534
535module_platform_driver(pm8xxx_rtc_driver);
536
537MODULE_ALIAS("platform:rtc-pm8xxx");
538MODULE_DESCRIPTION("PMIC8xxx RTC driver");
539MODULE_LICENSE("GPL v2");
540MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");