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1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29#ifndef __REALTEK_92S_REG_H__
30#define __REALTEK_92S_REG_H__
31
32/* 1. System Configuration Registers */
33#define REG_SYS_ISO_CTRL 0x0000
34#define REG_SYS_FUNC_EN 0x0002
35#define PMC_FSM 0x0004
36#define SYS_CLKR 0x0008
37#define EPROM_CMD 0x000A
38#define EE_VPD 0x000C
39#define AFE_MISC 0x0010
40#define SPS0_CTRL 0x0011
41#define SPS1_CTRL 0x0018
42#define RF_CTRL 0x001F
43#define LDOA15_CTRL 0x0020
44#define LDOV12D_CTRL 0x0021
45#define LDOHCI12_CTRL 0x0022
46#define LDO_USB_SDIO 0x0023
47#define LPLDO_CTRL 0x0024
48#define AFE_XTAL_CTRL 0x0026
49#define AFE_PLL_CTRL 0x0028
50#define REG_EFUSE_CTRL 0x0030
51#define REG_EFUSE_TEST 0x0034
52#define PWR_DATA 0x0038
53#define DBG_PORT 0x003A
54#define DPS_TIMER 0x003C
55#define RCLK_MON 0x003E
56
57/* 2. Command Control Registers */
58#define CMDR 0x0040
59#define TXPAUSE 0x0042
60#define LBKMD_SEL 0x0043
61#define TCR 0x0044
62#define RCR 0x0048
63#define MSR 0x004C
64#define SYSF_CFG 0x004D
65#define RX_PKY_LIMIT 0x004E
66#define MBIDCTRL 0x004F
67
68/* 3. MACID Setting Registers */
69#define MACIDR 0x0050
70#define MACIDR0 0x0050
71#define MACIDR4 0x0054
72#define BSSIDR 0x0058
73#define HWVID 0x005E
74#define MAR 0x0060
75#define MBIDCAMCONTENT 0x0068
76#define MBIDCAMCFG 0x0070
77#define BUILDTIME 0x0074
78#define BUILDUSER 0x0078
79
80#define IDR0 MACIDR0
81#define IDR4 MACIDR4
82
83/* 4. Timing Control Registers */
84#define TSFR 0x0080
85#define SLOT_TIME 0x0089
86#define USTIME 0x008A
87#define SIFS_CCK 0x008C
88#define SIFS_OFDM 0x008E
89#define PIFS_TIME 0x0090
90#define ACK_TIMEOUT 0x0091
91#define EIFSTR 0x0092
92#define BCN_INTERVAL 0x0094
93#define ATIMWND 0x0096
94#define BCN_DRV_EARLY_INT 0x0098
95#define BCN_DMATIME 0x009A
96#define BCN_ERR_THRESH 0x009C
97#define MLT 0x009D
98#define RSVD_MAC_TUNE_US 0x009E
99
100/* 5. FIFO Control Registers */
101#define RQPN 0x00A0
102#define RQPN1 0x00A0
103#define RQPN2 0x00A1
104#define RQPN3 0x00A2
105#define RQPN4 0x00A3
106#define RQPN5 0x00A4
107#define RQPN6 0x00A5
108#define RQPN7 0x00A6
109#define RQPN8 0x00A7
110#define RQPN9 0x00A8
111#define RQPN10 0x00A9
112#define LD_RQPN 0x00AB
113#define RXFF_BNDY 0x00AC
114#define RXRPT_BNDY 0x00B0
115#define TXPKTBUF_PGBNDY 0x00B4
116#define PBP 0x00B5
117#define RXDRVINFO_SZ 0x00B6
118#define TXFF_STATUS 0x00B7
119#define RXFF_STATUS 0x00B8
120#define TXFF_EMPTY_TH 0x00B9
121#define SDIO_RX_BLKSZ 0x00BC
122#define RXDMA 0x00BD
123#define RXPKT_NUM 0x00BE
124#define C2HCMD_UDT_SIZE 0x00C0
125#define C2HCMD_UDT_ADDR 0x00C2
126#define FIFOPAGE1 0x00C4
127#define FIFOPAGE2 0x00C8
128#define FIFOPAGE3 0x00CC
129#define FIFOPAGE4 0x00D0
130#define FIFOPAGE5 0x00D4
131#define FW_RSVD_PG_CRTL 0x00D8
132#define RXDMA_AGG_PG_TH 0x00D9
133#define TXDESC_MSK 0x00DC
134#define TXRPTFF_RDPTR 0x00E0
135#define TXRPTFF_WTPTR 0x00E4
136#define C2HFF_RDPTR 0x00E8
137#define C2HFF_WTPTR 0x00EC
138#define RXFF0_RDPTR 0x00F0
139#define RXFF0_WTPTR 0x00F4
140#define RXFF1_RDPTR 0x00F8
141#define RXFF1_WTPTR 0x00FC
142#define RXRPT0_RDPTR 0x0100
143#define RXRPT0_WTPTR 0x0104
144#define RXRPT1_RDPTR 0x0108
145#define RXRPT1_WTPTR 0x010C
146#define RX0_UDT_SIZE 0x0110
147#define RX1PKTNUM 0x0114
148#define RXFILTERMAP 0x0116
149#define RXFILTERMAP_GP1 0x0118
150#define RXFILTERMAP_GP2 0x011A
151#define RXFILTERMAP_GP3 0x011C
152#define BCNQ_CTRL 0x0120
153#define MGTQ_CTRL 0x0124
154#define HIQ_CTRL 0x0128
155#define VOTID7_CTRL 0x012c
156#define VOTID6_CTRL 0x0130
157#define VITID5_CTRL 0x0134
158#define VITID4_CTRL 0x0138
159#define BETID3_CTRL 0x013c
160#define BETID0_CTRL 0x0140
161#define BKTID2_CTRL 0x0144
162#define BKTID1_CTRL 0x0148
163#define CMDQ_CTRL 0x014c
164#define TXPKT_NUM_CTRL 0x0150
165#define TXQ_PGADD 0x0152
166#define TXFF_PG_NUM 0x0154
167#define TRXDMA_STATUS 0x0156
168
169/* 6. Adaptive Control Registers */
170#define INIMCS_SEL 0x0160
171#define TX_RATE_REG INIMCS_SEL
172#define INIRTSMCS_SEL 0x0180
173#define RRSR 0x0181
174#define ARFR0 0x0184
175#define ARFR1 0x0188
176#define ARFR2 0x018C
177#define ARFR3 0x0190
178#define ARFR4 0x0194
179#define ARFR5 0x0198
180#define ARFR6 0x019C
181#define ARFR7 0x01A0
182#define AGGLEN_LMT_H 0x01A7
183#define AGGLEN_LMT_L 0x01A8
184#define DARFRC 0x01B0
185#define RARFRC 0x01B8
186#define MCS_TXAGC 0x01C0
187#define CCK_TXAGC 0x01C8
188
189/* 7. EDCA Setting Registers */
190#define EDCAPARA_VO 0x01D0
191#define EDCAPARA_VI 0x01D4
192#define EDCAPARA_BE 0x01D8
193#define EDCAPARA_BK 0x01DC
194#define BCNTCFG 0x01E0
195#define CWRR 0x01E2
196#define ACMAVG 0x01E4
197#define AcmHwCtrl 0x01E7
198#define VO_ADMTM 0x01E8
199#define VI_ADMTM 0x01EC
200#define BE_ADMTM 0x01F0
201#define RETRY_LIMIT 0x01F4
202#define SG_RATE 0x01F6
203
204/* 8. WMAC, BA and CCX related Register. */
205#define NAV_CTRL 0x0200
206#define BW_OPMODE 0x0203
207#define BACAMCMD 0x0204
208#define BACAMCONTENT 0x0208
209
210/* the 0x2xx register WMAC definition */
211#define LBDLY 0x0210
212#define FWDLY 0x0211
213#define HWPC_RX_CTRL 0x0218
214#define MQIR 0x0220
215#define MAIR 0x0222
216#define MSIR 0x0224
217#define CLM_RESULT 0x0227
218#define NHM_RPI_CNT 0x0228
219#define RXERR_RPT 0x0230
220#define NAV_PROT_LEN 0x0234
221#define CFEND_TH 0x0236
222#define AMPDU_MIN_SPACE 0x0237
223#define TXOP_STALL_CTRL 0x0238
224
225/* 9. Security Control Registers */
226#define REG_RWCAM 0x0240
227#define REG_WCAMI 0x0244
228#define REG_RCAMO 0x0248
229#define REG_CAMDBG 0x024C
230#define REG_SECR 0x0250
231
232/* 10. Power Save Control Registers */
233#define WOW_CTRL 0x0260
234#define PSSTATUS 0x0261
235#define PSSWITCH 0x0262
236#define MIMOPS_WAIT_PERIOD 0x0263
237#define LPNAV_CTRL 0x0264
238#define WFM0 0x0270
239#define WFM1 0x0280
240#define WFM2 0x0290
241#define WFM3 0x02A0
242#define WFM4 0x02B0
243#define WFM5 0x02C0
244#define WFCRC 0x02D0
245#define FW_RPT_REG 0x02c4
246
247/* 11. General Purpose Registers */
248#define PSTIME 0x02E0
249#define TIMER0 0x02E4
250#define TIMER1 0x02E8
251#define GPIO_IN_SE 0x02EC
252#define GPIO_IO_SEL 0x02EE
253#define MAC_PINMUX_CFG 0x02F1
254#define LEDCFG 0x02F2
255#define PHY_REG 0x02F3
256#define PHY_REG_DATA 0x02F4
257#define REG_EFUSE_CLK 0x02F8
258
259/* 12. Host Interrupt Status Registers */
260#define INTA_MASK 0x0300
261#define ISR 0x0308
262
263/* 13. Test Mode and Debug Control Registers */
264#define DBG_PORT_SWITCH 0x003A
265#define BIST 0x0310
266#define DBS 0x0314
267#define CPUINST 0x0318
268#define CPUCAUSE 0x031C
269#define LBUS_ERR_ADDR 0x0320
270#define LBUS_ERR_CMD 0x0324
271#define LBUS_ERR_DATA_L 0x0328
272#define LBUS_ERR_DATA_H 0x032C
273#define LX_EXCEPTION_ADDR 0x0330
274#define WDG_CTRL 0x0334
275#define INTMTU 0x0338
276#define INTM 0x033A
277#define FDLOCKTURN0 0x033C
278#define FDLOCKTURN1 0x033D
279#define TRXPKTBUF_DBG_DATA 0x0340
280#define TRXPKTBUF_DBG_CTRL 0x0348
281#define DPLL 0x034A
282#define CBUS_ERR_ADDR 0x0350
283#define CBUS_ERR_CMD 0x0354
284#define CBUS_ERR_DATA_L 0x0358
285#define CBUS_ERR_DATA_H 0x035C
286#define USB_SIE_INTF_ADDR 0x0360
287#define USB_SIE_INTF_WD 0x0361
288#define USB_SIE_INTF_RD 0x0362
289#define USB_SIE_INTF_CTRL 0x0363
290#define LBUS_MON_ADDR 0x0364
291#define LBUS_ADDR_MASK 0x0368
292
293/* Boundary is 0x37F */
294
295/* 14. PCIE config register */
296#define TP_POLL 0x0500
297#define PM_CTRL 0x0502
298#define PCIF 0x0503
299
300#define THPDA 0x0514
301#define TMDA 0x0518
302#define TCDA 0x051C
303#define HDA 0x0520
304#define TVODA 0x0524
305#define TVIDA 0x0528
306#define TBEDA 0x052C
307#define TBKDA 0x0530
308#define TBDA 0x0534
309#define RCDA 0x0538
310#define RDQDA 0x053C
311#define DBI_WDATA 0x0540
312#define DBI_RDATA 0x0544
313#define DBI_CTRL 0x0548
314#define MDIO_DATA 0x0550
315#define MDIO_CTRL 0x0554
316#define PCI_RPWM 0x0561
317#define PCI_CPWM 0x0563
318
319/* Config register (Offset 0x800-) */
320#define PHY_CCA 0x803
321
322/* Min Spacing related settings. */
323#define MAX_MSS_DENSITY_2T 0x13
324#define MAX_MSS_DENSITY_1T 0x0A
325
326/* Rx DMA Control related settings */
327#define RXDMA_AGG_EN BIT(7)
328
329#define RPWM PCI_RPWM
330
331/* Regsiter Bit and Content definition */
332
333#define ISO_MD2PP BIT(0)
334#define ISO_PA2PCIE BIT(3)
335#define ISO_PLL2MD BIT(4)
336#define ISO_PWC_DV2RP BIT(11)
337#define ISO_PWC_RV2RP BIT(12)
338
339
340#define FEN_MREGEN BIT(15)
341#define FEN_DCORE BIT(11)
342#define FEN_CPUEN BIT(10)
343
344#define PAD_HWPD_IDN BIT(22)
345
346#define SYS_CLKSEL_80M BIT(0)
347#define SYS_PS_CLKSEL BIT(1)
348#define SYS_CPU_CLKSEL BIT(2)
349#define SYS_MAC_CLK_EN BIT(11)
350#define SYS_SWHW_SEL BIT(14)
351#define SYS_FWHW_SEL BIT(15)
352
353#define CmdEEPROM_En BIT(5)
354#define CmdEERPOMSEL BIT(4)
355#define Cmd9346CR_9356SEL BIT(4)
356
357#define AFE_MBEN BIT(1)
358#define AFE_BGEN BIT(0)
359
360#define SPS1_SWEN BIT(1)
361#define SPS1_LDEN BIT(0)
362
363#define RF_EN BIT(0)
364#define RF_RSTB BIT(1)
365#define RF_SDMRSTB BIT(2)
366
367#define LDA15_EN BIT(0)
368
369#define LDV12_EN BIT(0)
370#define LDV12_SDBY BIT(1)
371
372#define XTAL_GATE_AFE BIT(10)
373
374#define APLL_EN BIT(0)
375
376#define AFR_CardBEn BIT(0)
377#define AFR_CLKRUN_SEL BIT(1)
378#define AFR_FuncRegEn BIT(2)
379
380#define APSDOFF_STATUS BIT(15)
381#define APSDOFF BIT(14)
382#define BBRSTN BIT(13)
383#define BB_GLB_RSTN BIT(12)
384#define SCHEDULE_EN BIT(10)
385#define MACRXEN BIT(9)
386#define MACTXEN BIT(8)
387#define DDMA_EN BIT(7)
388#define FW2HW_EN BIT(6)
389#define RXDMA_EN BIT(5)
390#define TXDMA_EN BIT(4)
391#define HCI_RXDMA_EN BIT(3)
392#define HCI_TXDMA_EN BIT(2)
393
394#define StopHCCA BIT(6)
395#define StopHigh BIT(5)
396#define StopMgt BIT(4)
397#define StopVO BIT(3)
398#define StopVI BIT(2)
399#define StopBE BIT(1)
400#define StopBK BIT(0)
401
402#define LBK_NORMAL 0x00
403#define LBK_MAC_LB (BIT(0) | BIT(1) | BIT(3))
404#define LBK_MAC_DLB (BIT(0) | BIT(1))
405#define LBK_DMA_LB (BIT(0) | BIT(1) | BIT(2))
406
407#define TCP_OFDL_EN BIT(25)
408#define HWPC_TX_EN BIT(24)
409#define TXDMAPRE2FULL BIT(23)
410#define DISCW BIT(20)
411#define TCRICV BIT(19)
412#define CfendForm BIT(17)
413#define TCRCRC BIT(16)
414#define FAKE_IMEM_EN BIT(15)
415#define TSFRST BIT(9)
416#define TSFEN BIT(8)
417#define FWALLRDY (BIT(0) | BIT(1) | BIT(2) | \
418 BIT(3) | BIT(4) | BIT(5) | \
419 BIT(6) | BIT(7))
420#define FWRDY BIT(7)
421#define BASECHG BIT(6)
422#define IMEM BIT(5)
423#define DMEM_CODE_DONE BIT(4)
424#define EXT_IMEM_CHK_RPT BIT(3)
425#define EXT_IMEM_CODE_DONE BIT(2)
426#define IMEM_CHK_RPT BIT(1)
427#define IMEM_CODE_DONE BIT(0)
428#define IMEM_CODE_DONE BIT(0)
429#define IMEM_CHK_RPT BIT(1)
430#define EMEM_CODE_DONE BIT(2)
431#define EMEM_CHK_RPT BIT(3)
432#define DMEM_CODE_DONE BIT(4)
433#define IMEM_RDY BIT(5)
434#define BASECHG BIT(6)
435#define FWRDY BIT(7)
436#define LOAD_FW_READY (IMEM_CODE_DONE | \
437 IMEM_CHK_RPT | \
438 EMEM_CODE_DONE | \
439 EMEM_CHK_RPT | \
440 DMEM_CODE_DONE | \
441 IMEM_RDY | \
442 BASECHG | \
443 FWRDY)
444#define TCR_TSFEN BIT(8)
445#define TCR_TSFRST BIT(9)
446#define TCR_FAKE_IMEM_EN BIT(15)
447#define TCR_CRC BIT(16)
448#define TCR_ICV BIT(19)
449#define TCR_DISCW BIT(20)
450#define TCR_HWPC_TX_EN BIT(24)
451#define TCR_TCP_OFDL_EN BIT(25)
452#define TXDMA_INIT_VALUE (IMEM_CHK_RPT | \
453 EXT_IMEM_CHK_RPT)
454
455#define RCR_APPFCS BIT(31)
456#define RCR_DIS_ENC_2BYTE BIT(30)
457#define RCR_DIS_AES_2BYTE BIT(29)
458#define RCR_HTC_LOC_CTRL BIT(28)
459#define RCR_ENMBID BIT(27)
460#define RCR_RX_TCPOFDL_EN BIT(26)
461#define RCR_APP_PHYST_RXFF BIT(25)
462#define RCR_APP_PHYST_STAFF BIT(24)
463#define RCR_CBSSID BIT(23)
464#define RCR_APWRMGT BIT(22)
465#define RCR_ADD3 BIT(21)
466#define RCR_AMF BIT(20)
467#define RCR_ACF BIT(19)
468#define RCR_ADF BIT(18)
469#define RCR_APP_MIC BIT(17)
470#define RCR_APP_ICV BIT(16)
471#define RCR_RXFTH BIT(13)
472#define RCR_AICV BIT(12)
473#define RCR_RXDESC_LK_EN BIT(11)
474#define RCR_APP_BA_SSN BIT(6)
475#define RCR_ACRC32 BIT(5)
476#define RCR_RXSHFT_EN BIT(4)
477#define RCR_AB BIT(3)
478#define RCR_AM BIT(2)
479#define RCR_APM BIT(1)
480#define RCR_AAP BIT(0)
481#define RCR_MXDMA_OFFSET 8
482#define RCR_FIFO_OFFSET 13
483
484
485#define MSR_LINK_MASK ((1 << 0) | (1 << 1))
486#define MSR_LINK_MANAGED 2
487#define MSR_LINK_NONE 0
488#define MSR_LINK_SHIFT 0
489#define MSR_LINK_ADHOC 1
490#define MSR_LINK_MASTER 3
491#define MSR_NOLINK 0x00
492#define MSR_ADHOC 0x01
493#define MSR_INFRA 0x02
494#define MSR_AP 0x03
495
496#define ENUART BIT(7)
497#define ENJTAG BIT(3)
498#define BTMODE (BIT(2) | BIT(1))
499#define ENBT BIT(0)
500
501#define ENMBID BIT(7)
502#define BCNUM (BIT(6) | BIT(5) | BIT(4))
503
504#define USTIME_EDCA 0xFF00
505#define USTIME_TSF 0x00FF
506
507#define SIFS_TRX 0xFF00
508#define SIFS_CTX 0x00FF
509
510#define ENSWBCN BIT(15)
511#define DRVERLY_TU 0x0FF0
512#define DRVERLY_US 0x000F
513#define BCN_TCFG_CW_SHIFT 8
514#define BCN_TCFG_IFS 0
515
516#define RRSR_RSC_OFFSET 21
517#define RRSR_SHORT_OFFSET 23
518#define RRSR_RSC_BW_40M 0x600000
519#define RRSR_RSC_UPSUBCHNL 0x400000
520#define RRSR_RSC_LOWSUBCHNL 0x200000
521#define RRSR_SHORT 0x800000
522#define RRSR_1M BIT(0)
523#define RRSR_2M BIT(1)
524#define RRSR_5_5M BIT(2)
525#define RRSR_11M BIT(3)
526#define RRSR_6M BIT(4)
527#define RRSR_9M BIT(5)
528#define RRSR_12M BIT(6)
529#define RRSR_18M BIT(7)
530#define RRSR_24M BIT(8)
531#define RRSR_36M BIT(9)
532#define RRSR_48M BIT(10)
533#define RRSR_54M BIT(11)
534#define RRSR_MCS0 BIT(12)
535#define RRSR_MCS1 BIT(13)
536#define RRSR_MCS2 BIT(14)
537#define RRSR_MCS3 BIT(15)
538#define RRSR_MCS4 BIT(16)
539#define RRSR_MCS5 BIT(17)
540#define RRSR_MCS6 BIT(18)
541#define RRSR_MCS7 BIT(19)
542#define BRSR_AckShortPmb BIT(23)
543
544#define RATR_1M 0x00000001
545#define RATR_2M 0x00000002
546#define RATR_55M 0x00000004
547#define RATR_11M 0x00000008
548#define RATR_6M 0x00000010
549#define RATR_9M 0x00000020
550#define RATR_12M 0x00000040
551#define RATR_18M 0x00000080
552#define RATR_24M 0x00000100
553#define RATR_36M 0x00000200
554#define RATR_48M 0x00000400
555#define RATR_54M 0x00000800
556#define RATR_MCS0 0x00001000
557#define RATR_MCS1 0x00002000
558#define RATR_MCS2 0x00004000
559#define RATR_MCS3 0x00008000
560#define RATR_MCS4 0x00010000
561#define RATR_MCS5 0x00020000
562#define RATR_MCS6 0x00040000
563#define RATR_MCS7 0x00080000
564#define RATR_MCS8 0x00100000
565#define RATR_MCS9 0x00200000
566#define RATR_MCS10 0x00400000
567#define RATR_MCS11 0x00800000
568#define RATR_MCS12 0x01000000
569#define RATR_MCS13 0x02000000
570#define RATR_MCS14 0x04000000
571#define RATR_MCS15 0x08000000
572
573#define RATE_ALL_CCK (RATR_1M | RATR_2M | \
574 RATR_55M | RATR_11M)
575#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | \
576 RATR_12M | RATR_18M | \
577 RATR_24M | RATR_36M | \
578 RATR_48M | RATR_54M)
579#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | \
580 RATR_MCS2 | RATR_MCS3 | \
581 RATR_MCS4 | RATR_MCS5 | \
582 RATR_MCS6 | RATR_MCS7)
583#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | \
584 RATR_MCS10 | RATR_MCS11 | \
585 RATR_MCS12 | RATR_MCS13 | \
586 RATR_MCS14 | RATR_MCS15)
587
588#define AC_PARAM_TXOP_LIMIT_OFFSET 16
589#define AC_PARAM_ECW_MAX_OFFSET 12
590#define AC_PARAM_ECW_MIN_OFFSET 8
591#define AC_PARAM_AIFS_OFFSET 0
592
593#define AcmHw_HwEn BIT(0)
594#define AcmHw_BeqEn BIT(1)
595#define AcmHw_ViqEn BIT(2)
596#define AcmHw_VoqEn BIT(3)
597#define AcmHw_BeqStatus BIT(4)
598#define AcmHw_ViqStatus BIT(5)
599#define AcmHw_VoqStatus BIT(6)
600
601#define RETRY_LIMIT_SHORT_SHIFT 8
602#define RETRY_LIMIT_LONG_SHIFT 0
603
604#define NAV_UPPER_EN BIT(16)
605#define NAV_UPPER 0xFF00
606#define NAV_RTSRST 0xFF
607
608#define BW_OPMODE_20MHZ BIT(2)
609#define BW_OPMODE_5G BIT(1)
610#define BW_OPMODE_11J BIT(0)
611
612#define RXERR_RPT_RST BIT(27)
613#define RXERR_OFDM_PPDU 0
614#define RXERR_OFDM_FALSE_ALARM 1
615#define RXERR_OFDM_MPDU_OK 2
616#define RXERR_OFDM_MPDU_FAIL 3
617#define RXERR_CCK_PPDU 4
618#define RXERR_CCK_FALSE_ALARM 5
619#define RXERR_CCK_MPDU_OK 6
620#define RXERR_CCK_MPDU_FAIL 7
621#define RXERR_HT_PPDU 8
622#define RXERR_HT_FALSE_ALARM 9
623#define RXERR_HT_MPDU_TOTAL 10
624#define RXERR_HT_MPDU_OK 11
625#define RXERR_HT_MPDU_FAIL 12
626#define RXERR_RX_FULL_DROP 15
627
628#define SCR_TXUSEDK BIT(0)
629#define SCR_RXUSEDK BIT(1)
630#define SCR_TXENCENABLE BIT(2)
631#define SCR_RXENCENABLE BIT(3)
632#define SCR_SKBYA2 BIT(4)
633#define SCR_NOSKMC BIT(5)
634
635#define CAM_VALID BIT(15)
636#define CAM_NOTVALID 0x0000
637#define CAM_USEDK BIT(5)
638
639#define CAM_NONE 0x0
640#define CAM_WEP40 0x01
641#define CAM_TKIP 0x02
642#define CAM_AES 0x04
643#define CAM_WEP104 0x05
644
645#define TOTAL_CAM_ENTRY 32
646#define HALF_CAM_ENTRY 16
647
648#define CAM_WRITE BIT(16)
649#define CAM_READ 0x00000000
650#define CAM_POLLINIG BIT(31)
651
652#define WOW_PMEN BIT(0)
653#define WOW_WOMEN BIT(1)
654#define WOW_MAGIC BIT(2)
655#define WOW_UWF BIT(3)
656
657#define GPIOMUX_EN BIT(3)
658#define GPIOSEL_GPIO 0
659#define GPIOSEL_PHYDBG 1
660#define GPIOSEL_BT 2
661#define GPIOSEL_WLANDBG 3
662#define GPIOSEL_GPIO_MASK (~(BIT(0)|BIT(1)))
663
664#define HST_RDBUSY BIT(0)
665#define CPU_WTBUSY BIT(1)
666
667#define IMR8190_DISABLED 0x0
668#define IMR_CPUERR BIT(5)
669#define IMR_ATIMEND BIT(4)
670#define IMR_TBDOK BIT(3)
671#define IMR_TBDER BIT(2)
672#define IMR_BCNDMAINT8 BIT(1)
673#define IMR_BCNDMAINT7 BIT(0)
674#define IMR_BCNDMAINT6 BIT(31)
675#define IMR_BCNDMAINT5 BIT(30)
676#define IMR_BCNDMAINT4 BIT(29)
677#define IMR_BCNDMAINT3 BIT(28)
678#define IMR_BCNDMAINT2 BIT(27)
679#define IMR_BCNDMAINT1 BIT(26)
680#define IMR_BCNDOK8 BIT(25)
681#define IMR_BCNDOK7 BIT(24)
682#define IMR_BCNDOK6 BIT(23)
683#define IMR_BCNDOK5 BIT(22)
684#define IMR_BCNDOK4 BIT(21)
685#define IMR_BCNDOK3 BIT(20)
686#define IMR_BCNDOK2 BIT(19)
687#define IMR_BCNDOK1 BIT(18)
688#define IMR_TIMEOUT2 BIT(17)
689#define IMR_TIMEOUT1 BIT(16)
690#define IMR_TXFOVW BIT(15)
691#define IMR_PSTIMEOUT BIT(14)
692#define IMR_BCNINT BIT(13)
693#define IMR_RXFOVW BIT(12)
694#define IMR_RDU BIT(11)
695#define IMR_RXCMDOK BIT(10)
696#define IMR_BDOK BIT(9)
697#define IMR_HIGHDOK BIT(8)
698#define IMR_COMDOK BIT(7)
699#define IMR_MGNTDOK BIT(6)
700#define IMR_HCCADOK BIT(5)
701#define IMR_BKDOK BIT(4)
702#define IMR_BEDOK BIT(3)
703#define IMR_VIDOK BIT(2)
704#define IMR_VODOK BIT(1)
705#define IMR_ROK BIT(0)
706
707#define TPPOLL_BKQ BIT(0)
708#define TPPOLL_BEQ BIT(1)
709#define TPPOLL_VIQ BIT(2)
710#define TPPOLL_VOQ BIT(3)
711#define TPPOLL_BQ BIT(4)
712#define TPPOLL_CQ BIT(5)
713#define TPPOLL_MQ BIT(6)
714#define TPPOLL_HQ BIT(7)
715#define TPPOLL_HCCAQ BIT(8)
716#define TPPOLL_STOPBK BIT(9)
717#define TPPOLL_STOPBE BIT(10)
718#define TPPOLL_STOPVI BIT(11)
719#define TPPOLL_STOPVO BIT(12)
720#define TPPOLL_STOPMGT BIT(13)
721#define TPPOLL_STOPHIGH BIT(14)
722#define TPPOLL_STOPHCCA BIT(15)
723#define TPPOLL_SHIFT 8
724
725#define CCX_CMD_CLM_ENABLE BIT(0)
726#define CCX_CMD_NHM_ENABLE BIT(1)
727#define CCX_CMD_FUNCTION_ENABLE BIT(8)
728#define CCX_CMD_IGNORE_CCA BIT(9)
729#define CCX_CMD_IGNORE_TXON BIT(10)
730#define CCX_CLM_RESULT_READY BIT(16)
731#define CCX_NHM_RESULT_READY BIT(16)
732#define CCX_CMD_RESET 0x0
733
734
735#define HWSET_MAX_SIZE_92S 128
736#define EFUSE_MAX_SECTION 16
737#define EFUSE_REAL_CONTENT_LEN 512
738#define EFUSE_OOB_PROTECT_BYTES 15
739
740#define RTL8190_EEPROM_ID 0x8129
741#define EEPROM_HPON 0x02
742#define EEPROM_CLK 0x06
743#define EEPROM_TESTR 0x08
744
745#define EEPROM_VID 0x0A
746#define EEPROM_DID 0x0C
747#define EEPROM_SVID 0x0E
748#define EEPROM_SMID 0x10
749
750#define EEPROM_MAC_ADDR 0x12
751#define EEPROM_NODE_ADDRESS_BYTE_0 0x12
752
753#define EEPROM_PWDIFF 0x54
754
755#define EEPROM_TXPOWERBASE 0x50
756#define EEPROM_TX_PWR_INDEX_RANGE 28
757
758#define EEPROM_TX_PWR_HT20_DIFF 0x62
759#define DEFAULT_HT20_TXPWR_DIFF 2
760#define EEPROM_TX_PWR_OFDM_DIFF 0x65
761
762#define EEPROM_TXPWRGROUP 0x67
763#define EEPROM_REGULATORY 0x6D
764
765#define TX_PWR_SAFETY_CHK 0x6D
766#define EEPROM_TXPWINDEX_CCK_24G 0x5D
767#define EEPROM_TXPWINDEX_OFDM_24G 0x6B
768#define EEPROM_HT2T_CH1_A 0x6c
769#define EEPROM_HT2T_CH7_A 0x6d
770#define EEPROM_HT2T_CH13_A 0x6e
771#define EEPROM_HT2T_CH1_B 0x6f
772#define EEPROM_HT2T_CH7_B 0x70
773#define EEPROM_HT2T_CH13_B 0x71
774
775#define EEPROM_TSSI_A 0x74
776#define EEPROM_TSSI_B 0x75
777
778#define EEPROM_RFIND_POWERDIFF 0x76
779#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
780
781#define EEPROM_THERMALMETER 0x77
782#define EEPROM_BLUETOOTH_COEXIST 0x78
783#define EEPROM_BLUETOOTH_TYPE 0x4f
784
785#define EEPROM_OPTIONAL 0x78
786#define EEPROM_WOWLAN 0x78
787
788#define EEPROM_CRYSTALCAP 0x79
789#define EEPROM_CHANNELPLAN 0x7B
790#define EEPROM_VERSION 0x7C
791#define EEPROM_CUSTOMID 0x7A
792#define EEPROM_BOARDTYPE 0x7E
793
794#define EEPROM_CHANNEL_PLAN_FCC 0x0
795#define EEPROM_CHANNEL_PLAN_IC 0x1
796#define EEPROM_CHANNEL_PLAN_ETSI 0x2
797#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
798#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
799#define EEPROM_CHANNEL_PLAN_MKK 0x5
800#define EEPROM_CHANNEL_PLAN_MKK1 0x6
801#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
802#define EEPROM_CHANNEL_PLAN_TELEC 0x8
803#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
804#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
805#define EEPROM_CHANNEL_PLAN_NCC 0xB
806#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
807
808#define FW_DIG_DISABLE 0xfd00cc00
809#define FW_DIG_ENABLE 0xfd000000
810#define FW_DIG_HALT 0xfd000001
811#define FW_DIG_RESUME 0xfd000002
812#define FW_HIGH_PWR_DISABLE 0xfd000008
813#define FW_HIGH_PWR_ENABLE 0xfd000009
814#define FW_ADD_A2_ENTRY 0xfd000016
815#define FW_TXPWR_TRACK_ENABLE 0xfd000017
816#define FW_TXPWR_TRACK_DISABLE 0xfd000018
817#define FW_TXPWR_TRACK_THERMAL 0xfd000019
818#define FW_TXANT_SWITCH_ENABLE 0xfd000023
819#define FW_TXANT_SWITCH_DISABLE 0xfd000024
820#define FW_RA_INIT 0xfd000026
821#define FW_CTRL_DM_BY_DRIVER 0Xfd00002a
822#define FW_RA_IOT_BG_COMB 0xfd000030
823#define FW_RA_IOT_N_COMB 0xfd000031
824#define FW_RA_REFRESH 0xfd0000a0
825#define FW_RA_UPDATE_MASK 0xfd0000a2
826#define FW_RA_DISABLE 0xfd0000a4
827#define FW_RA_ACTIVE 0xfd0000a6
828#define FW_RA_DISABLE_RSSI_MASK 0xfd0000ac
829#define FW_RA_ENABLE_RSSI_MASK 0xfd0000ad
830#define FW_RA_RESET 0xfd0000af
831#define FW_DM_DISABLE 0xfd00aa00
832#define FW_IQK_ENABLE 0xf0000020
833#define FW_IQK_SUCCESS 0x0000dddd
834#define FW_IQK_FAIL 0x0000ffff
835#define FW_OP_FAILURE 0xffffffff
836#define FW_TX_FEEDBACK_NONE 0xfb000000
837#define FW_TX_FEEDBACK_DTM_ENABLE (FW_TX_FEEDBACK_NONE | 0x1)
838#define FW_TX_FEEDBACK_CCX_ENABL (FW_TX_FEEDBACK_NONE | 0x2)
839#define FW_BB_RESET_ENABLE 0xff00000d
840#define FW_BB_RESET_DISABLE 0xff00000e
841#define FW_CCA_CHK_ENABLE 0xff000011
842#define FW_CCK_RESET_CNT 0xff000013
843#define FW_LPS_ENTER 0xfe000010
844#define FW_LPS_LEAVE 0xfe000011
845#define FW_INDIRECT_READ 0xf2000000
846#define FW_INDIRECT_WRITE 0xf2000001
847#define FW_CHAN_SET 0xf3000001
848
849#define RFPC 0x5F
850#define RCR_9356SEL BIT(6)
851#define TCR_LRL_OFFSET 0
852#define TCR_SRL_OFFSET 8
853#define TCR_MXDMA_OFFSET 21
854#define TCR_SAT BIT(24)
855#define RCR_MXDMA_OFFSET 8
856#define RCR_FIFO_OFFSET 13
857#define RCR_OnlyErlPkt BIT(31)
858#define CWR 0xDC
859#define RETRYCTR 0xDE
860
861#define CPU_GEN_SYSTEM_RESET 0x00000001
862
863#define CCX_COMMAND_REG 0x890
864#define CLM_PERIOD_REG 0x894
865#define NHM_PERIOD_REG 0x896
866
867#define NHM_THRESHOLD0 0x898
868#define NHM_THRESHOLD1 0x899
869#define NHM_THRESHOLD2 0x89A
870#define NHM_THRESHOLD3 0x89B
871#define NHM_THRESHOLD4 0x89C
872#define NHM_THRESHOLD5 0x89D
873#define NHM_THRESHOLD6 0x89E
874#define CLM_RESULT_REG 0x8D0
875#define NHM_RESULT_REG 0x8D4
876#define NHM_RPI_COUNTER0 0x8D8
877#define NHM_RPI_COUNTER1 0x8D9
878#define NHM_RPI_COUNTER2 0x8DA
879#define NHM_RPI_COUNTER3 0x8DB
880#define NHM_RPI_COUNTER4 0x8DC
881#define NHM_RPI_COUNTER5 0x8DD
882#define NHM_RPI_COUNTER6 0x8DE
883#define NHM_RPI_COUNTER7 0x8DF
884
885#define HAL_8192S_HW_GPIO_OFF_BIT BIT(3)
886#define HAL_8192S_HW_GPIO_OFF_MASK 0xF7
887#define HAL_8192S_HW_GPIO_WPS_BIT BIT(4)
888
889#define RPMAC_RESET 0x100
890#define RPMAC_TXSTART 0x104
891#define RPMAC_TXLEGACYSIG 0x108
892#define RPMAC_TXHTSIG1 0x10c
893#define RPMAC_TXHTSIG2 0x110
894#define RPMAC_PHYDEBUG 0x114
895#define RPMAC_TXPACKETNNM 0x118
896#define RPMAC_TXIDLE 0x11c
897#define RPMAC_TXMACHEADER0 0x120
898#define RPMAC_TXMACHEADER1 0x124
899#define RPMAC_TXMACHEADER2 0x128
900#define RPMAC_TXMACHEADER3 0x12c
901#define RPMAC_TXMACHEADER4 0x130
902#define RPMAC_TXMACHEADER5 0x134
903#define RPMAC_TXDATATYPE 0x138
904#define RPMAC_TXRANDOMSEED 0x13c
905#define RPMAC_CCKPLCPPREAMBLE 0x140
906#define RPMAC_CCKPLCPHEADER 0x144
907#define RPMAC_CCKCRC16 0x148
908#define RPMAC_OFDMRXCRC32OK 0x170
909#define RPMAC_OFDMRXCRC32ER 0x174
910#define RPMAC_OFDMRXPARITYER 0x178
911#define RPMAC_OFDMRXCRC8ER 0x17c
912#define RPMAC_CCKCRXRC16ER 0x180
913#define RPMAC_CCKCRXRC32ER 0x184
914#define RPMAC_CCKCRXRC32OK 0x188
915#define RPMAC_TXSTATUS 0x18c
916
917#define RF_BB_CMD_ADDR 0x02c0
918#define RF_BB_CMD_DATA 0x02c4
919
920#define RFPGA0_RFMOD 0x800
921
922#define RFPGA0_TXINFO 0x804
923#define RFPGA0_PSDFUNCTION 0x808
924
925#define RFPGA0_TXGAINSTAGE 0x80c
926
927#define RFPGA0_RFTIMING1 0x810
928#define RFPGA0_RFTIMING2 0x814
929#define RFPGA0_XA_HSSIPARAMETER1 0x820
930#define RFPGA0_XA_HSSIPARAMETER2 0x824
931#define RFPGA0_XB_HSSIPARAMETER1 0x828
932#define RFPGA0_XB_HSSIPARAMETER2 0x82c
933#define RFPGA0_XC_HSSIPARAMETER1 0x830
934#define RFPGA0_XC_HSSIPARAMETER2 0x834
935#define RFPGA0_XD_HSSIPARAMETER1 0x838
936#define RFPGA0_XD_HSSIPARAMETER2 0x83c
937#define RFPGA0_XA_LSSIPARAMETER 0x840
938#define RFPGA0_XB_LSSIPARAMETER 0x844
939#define RFPGA0_XC_LSSIPARAMETER 0x848
940#define RFPGA0_XD_LSSIPARAMETER 0x84c
941
942#define RFPGA0_RFWAKEUP_PARAMETER 0x850
943#define RFPGA0_RFSLEEPUP_PARAMETER 0x854
944
945#define RFPGA0_XAB_SWITCHCONTROL 0x858
946#define RFPGA0_XCD_SWITCHCONTROL 0x85c
947
948#define RFPGA0_XA_RFINTERFACEOE 0x860
949#define RFPGA0_XB_RFINTERFACEOE 0x864
950#define RFPGA0_XC_RFINTERFACEOE 0x868
951#define RFPGA0_XD_RFINTERFACEOE 0x86c
952
953#define RFPGA0_XAB_RFINTERFACESW 0x870
954#define RFPGA0_XCD_RFINTERFACESW 0x874
955
956#define RFPGA0_XAB_RFPARAMETER 0x878
957#define RFPGA0_XCD_RFPARAMETER 0x87c
958
959#define RFPGA0_ANALOGPARAMETER1 0x880
960#define RFPGA0_ANALOGPARAMETER2 0x884
961#define RFPGA0_ANALOGPARAMETER3 0x888
962#define RFPGA0_ANALOGPARAMETER4 0x88c
963
964#define RFPGA0_XA_LSSIREADBACK 0x8a0
965#define RFPGA0_XB_LSSIREADBACK 0x8a4
966#define RFPGA0_XC_LSSIREADBACK 0x8a8
967#define RFPGA0_XD_LSSIREADBACK 0x8ac
968
969#define RFPGA0_PSDREPORT 0x8b4
970#define TRANSCEIVERA_HSPI_READBACK 0x8b8
971#define TRANSCEIVERB_HSPI_READBACK 0x8bc
972#define RFPGA0_XAB_RFINTERFACERB 0x8e0
973#define RFPGA0_XCD_RFINTERFACERB 0x8e4
974#define RFPGA1_RFMOD 0x900
975
976#define RFPGA1_TXBLOCK 0x904
977#define RFPGA1_DEBUGSELECT 0x908
978#define RFPGA1_TXINFO 0x90c
979
980#define RCCK0_SYSTEM 0xa00
981
982#define RCCK0_AFESETTING 0xa04
983#define RCCK0_CCA 0xa08
984
985#define RCCK0_RXAGC1 0xa0c
986#define RCCK0_RXAGC2 0xa10
987
988#define RCCK0_RXHP 0xa14
989
990#define RCCK0_DSPPARAMETER1 0xa18
991#define RCCK0_DSPPARAMETER2 0xa1c
992
993#define RCCK0_TXFILTER1 0xa20
994#define RCCK0_TXFILTER2 0xa24
995#define RCCK0_DEBUGPORT 0xa28
996#define RCCK0_FALSEALARMREPORT 0xa2c
997#define RCCK0_TRSSIREPORT 0xa50
998#define RCCK0_RXREPORT 0xa54
999#define RCCK0_FACOUNTERLOWER 0xa5c
1000#define RCCK0_FACOUNTERUPPER 0xa58
1001
1002#define ROFDM0_LSTF 0xc00
1003
1004#define ROFDM0_TRXPATHENABLE 0xc04
1005#define ROFDM0_TRMUXPAR 0xc08
1006#define ROFDM0_TRSWISOLATION 0xc0c
1007
1008#define ROFDM0_XARXAFE 0xc10
1009#define ROFDM0_XARXIQIMBALANCE 0xc14
1010#define ROFDM0_XBRXAFE 0xc18
1011#define ROFDM0_XBRXIQIMBALANCE 0xc1c
1012#define ROFDM0_XCRXAFE 0xc20
1013#define ROFDM0_XCRXIQIMBALANCE 0xc24
1014#define ROFDM0_XDRXAFE 0xc28
1015#define ROFDM0_XDRXIQIMBALANCE 0xc2c
1016
1017#define ROFDM0_RXDETECTOR1 0xc30
1018#define ROFDM0_RXDETECTOR2 0xc34
1019#define ROFDM0_RXDETECTOR3 0xc38
1020#define ROFDM0_RXDETECTOR4 0xc3c
1021
1022#define ROFDM0_RXDSP 0xc40
1023#define ROFDM0_CFO_AND_DAGC 0xc44
1024#define ROFDM0_CCADROP_THRESHOLD 0xc48
1025#define ROFDM0_ECCA_THRESHOLD 0xc4c
1026
1027#define ROFDM0_XAAGCCORE1 0xc50
1028#define ROFDM0_XAAGCCORE2 0xc54
1029#define ROFDM0_XBAGCCORE1 0xc58
1030#define ROFDM0_XBAGCCORE2 0xc5c
1031#define ROFDM0_XCAGCCORE1 0xc60
1032#define ROFDM0_XCAGCCORE2 0xc64
1033#define ROFDM0_XDAGCCORE1 0xc68
1034#define ROFDM0_XDAGCCORE2 0xc6c
1035
1036#define ROFDM0_AGCPARAMETER1 0xc70
1037#define ROFDM0_AGCPARAMETER2 0xc74
1038#define ROFDM0_AGCRSSITABLE 0xc78
1039#define ROFDM0_HTSTFAGC 0xc7c
1040
1041#define ROFDM0_XATXIQIMBALANCE 0xc80
1042#define ROFDM0_XATXAFE 0xc84
1043#define ROFDM0_XBTXIQIMBALANCE 0xc88
1044#define ROFDM0_XBTXAFE 0xc8c
1045#define ROFDM0_XCTXIQIMBALANCE 0xc90
1046#define ROFDM0_XCTXAFE 0xc94
1047#define ROFDM0_XDTXIQIMBALANCE 0xc98
1048#define ROFDM0_XDTXAFE 0xc9c
1049
1050#define ROFDM0_RXHP_PARAMETER 0xce0
1051#define ROFDM0_TXPSEUDO_NOISE_WGT 0xce4
1052#define ROFDM0_FRAME_SYNC 0xcf0
1053#define ROFDM0_DFSREPORT 0xcf4
1054#define ROFDM0_TXCOEFF1 0xca4
1055#define ROFDM0_TXCOEFF2 0xca8
1056#define ROFDM0_TXCOEFF3 0xcac
1057#define ROFDM0_TXCOEFF4 0xcb0
1058#define ROFDM0_TXCOEFF5 0xcb4
1059#define ROFDM0_TXCOEFF6 0xcb8
1060
1061
1062#define ROFDM1_LSTF 0xd00
1063#define ROFDM1_TRXPATHENABLE 0xd04
1064
1065#define ROFDM1_CFO 0xd08
1066#define ROFDM1_CSI1 0xd10
1067#define ROFDM1_SBD 0xd14
1068#define ROFDM1_CSI2 0xd18
1069#define ROFDM1_CFOTRACKING 0xd2c
1070#define ROFDM1_TRXMESAURE1 0xd34
1071#define ROFDM1_INTF_DET 0xd3c
1072#define ROFDM1_PSEUDO_NOISESTATEAB 0xd50
1073#define ROFDM1_PSEUDO_NOISESTATECD 0xd54
1074#define ROFDM1_RX_PSEUDO_NOISE_WGT 0xd58
1075
1076#define ROFDM_PHYCOUNTER1 0xda0
1077#define ROFDM_PHYCOUNTER2 0xda4
1078#define ROFDM_PHYCOUNTER3 0xda8
1079
1080#define ROFDM_SHORT_CFOAB 0xdac
1081#define ROFDM_SHORT_CFOCD 0xdb0
1082#define ROFDM_LONG_CFOAB 0xdb4
1083#define ROFDM_LONG_CFOCD 0xdb8
1084#define ROFDM_TAIL_CFOAB 0xdbc
1085#define ROFDM_TAIL_CFOCD 0xdc0
1086#define ROFDM_PW_MEASURE1 0xdc4
1087#define ROFDM_PW_MEASURE2 0xdc8
1088#define ROFDM_BW_REPORT 0xdcc
1089#define ROFDM_AGC_REPORT 0xdd0
1090#define ROFDM_RXSNR 0xdd4
1091#define ROFDM_RXEVMCSI 0xdd8
1092#define ROFDM_SIG_REPORT 0xddc
1093
1094
1095#define RTXAGC_RATE18_06 0xe00
1096#define RTXAGC_RATE54_24 0xe04
1097#define RTXAGC_CCK_MCS32 0xe08
1098#define RTXAGC_MCS03_MCS00 0xe10
1099#define RTXAGC_MCS07_MCS04 0xe14
1100#define RTXAGC_MCS11_MCS08 0xe18
1101#define RTXAGC_MCS15_MCS12 0xe1c
1102
1103
1104#define RF_AC 0x00
1105#define RF_IQADJ_G1 0x01
1106#define RF_IQADJ_G2 0x02
1107#define RF_POW_TRSW 0x05
1108#define RF_GAIN_RX 0x06
1109#define RF_GAIN_TX 0x07
1110#define RF_TXM_IDAC 0x08
1111#define RF_BS_IQGEN 0x0F
1112
1113#define RF_MODE1 0x10
1114#define RF_MODE2 0x11
1115#define RF_RX_AGC_HP 0x12
1116#define RF_TX_AGC 0x13
1117#define RF_BIAS 0x14
1118#define RF_IPA 0x15
1119#define RF_POW_ABILITY 0x17
1120#define RF_MODE_AG 0x18
1121#define RF_CHANNEL 0x18
1122#define RF_CHNLBW 0x18
1123#define RF_TOP 0x19
1124#define RF_RX_G1 0x1A
1125#define RF_RX_G2 0x1B
1126#define RF_RX_BB2 0x1C
1127#define RF_RX_BB1 0x1D
1128#define RF_RCK1 0x1E
1129#define RF_RCK2 0x1F
1130
1131#define RF_TX_G1 0x20
1132#define RF_TX_G2 0x21
1133#define RF_TX_G3 0x22
1134#define RF_TX_BB1 0x23
1135#define RF_T_METER 0x24
1136#define RF_SYN_G1 0x25
1137#define RF_SYN_G2 0x26
1138#define RF_SYN_G3 0x27
1139#define RF_SYN_G4 0x28
1140#define RF_SYN_G5 0x29
1141#define RF_SYN_G6 0x2A
1142#define RF_SYN_G7 0x2B
1143#define RF_SYN_G8 0x2C
1144
1145#define RF_RCK_OS 0x30
1146#define RF_TXPA_G1 0x31
1147#define RF_TXPA_G2 0x32
1148#define RF_TXPA_G3 0x33
1149
1150#define BRFMOD 0x1
1151#define BCCKEN 0x1000000
1152#define BOFDMEN 0x2000000
1153
1154#define BXBTXAGC 0xf00
1155#define BXCTXAGC 0xf000
1156#define BXDTXAGC 0xf0000
1157
1158#define B3WIRE_DATALENGTH 0x800
1159#define B3WIRE_ADDRESSLENGTH 0x400
1160
1161#define BRFSI_RFENV 0x10
1162
1163#define BLSSI_READADDRESS 0x7f800000
1164#define BLSSI_READEDGE 0x80000000
1165#define BLSSI_READBACK_DATA 0xfffff
1166
1167#define BADCLKPHASE 0x4000000
1168
1169#define BCCK_SIDEBAND 0x10
1170
1171#define BTX_AGCRATECCK 0x7f00
1172
1173#define MASKBYTE0 0xff
1174#define MASKBYTE1 0xff00
1175#define MASKBYTE2 0xff0000
1176#define MASKBYTE3 0xff000000
1177#define MASKHWORD 0xffff0000
1178#define MASKLWORD 0x0000ffff
1179#define MASKDWORD 0xffffffff
1180
1181#define MAKS12BITS 0xfffff
1182#define MASK20BITS 0xfffff
1183#define RFREG_OFFSET_MASK 0xfffff
1184
1185#endif