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1/*
2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
11 <http://rt2x00.serialmonkey.com>
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the
25 Free Software Foundation, Inc.,
26 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 */
28
29/*
30 Module: rt2800
31 Abstract: Data structures and registers for the rt2800 modules.
32 Supported chipsets: RT2800E, RT2800ED & RT2800U.
33 */
34
35#ifndef RT2800_H
36#define RT2800_H
37
38/*
39 * RF chip defines.
40 *
41 * RF2820 2.4G 2T3R
42 * RF2850 2.4G/5G 2T3R
43 * RF2720 2.4G 1T2R
44 * RF2750 2.4G/5G 1T2R
45 * RF3020 2.4G 1T1R
46 * RF2020 2.4G B/G
47 * RF3021 2.4G 1T2R
48 * RF3022 2.4G 2T2R
49 * RF3052 2.4G/5G 2T2R
50 * RF2853 2.4G/5G 3T3R
51 * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
52 * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
53 * RF3053 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
54 * RF5370 2.4G 1T1R
55 * RF5390 2.4G 1T1R
56 */
57#define RF2820 0x0001
58#define RF2850 0x0002
59#define RF2720 0x0003
60#define RF2750 0x0004
61#define RF3020 0x0005
62#define RF2020 0x0006
63#define RF3021 0x0007
64#define RF3022 0x0008
65#define RF3052 0x0009
66#define RF2853 0x000a
67#define RF3320 0x000b
68#define RF3322 0x000c
69#define RF3053 0x000d
70#define RF5370 0x5370
71#define RF5372 0x5372
72#define RF5390 0x5390
73
74/*
75 * Chipset revisions.
76 */
77#define REV_RT2860C 0x0100
78#define REV_RT2860D 0x0101
79#define REV_RT2872E 0x0200
80#define REV_RT3070E 0x0200
81#define REV_RT3070F 0x0201
82#define REV_RT3071E 0x0211
83#define REV_RT3090E 0x0211
84#define REV_RT3390E 0x0211
85#define REV_RT5390F 0x0502
86#define REV_RT5390R 0x1502
87
88/*
89 * Signal information.
90 * Default offset is required for RSSI <-> dBm conversion.
91 */
92#define DEFAULT_RSSI_OFFSET 120
93
94/*
95 * Register layout information.
96 */
97#define CSR_REG_BASE 0x1000
98#define CSR_REG_SIZE 0x0800
99#define EEPROM_BASE 0x0000
100#define EEPROM_SIZE 0x0110
101#define BBP_BASE 0x0000
102#define BBP_SIZE 0x00ff
103#define RF_BASE 0x0004
104#define RF_SIZE 0x0010
105#define RFCSR_BASE 0x0000
106#define RFCSR_SIZE 0x0040
107
108/*
109 * Number of TX queues.
110 */
111#define NUM_TX_QUEUES 4
112
113/*
114 * Registers.
115 */
116
117/*
118 * E2PROM_CSR: PCI EEPROM control register.
119 * RELOAD: Write 1 to reload eeprom content.
120 * TYPE: 0: 93c46, 1:93c66.
121 * LOAD_STATUS: 1:loading, 0:done.
122 */
123#define E2PROM_CSR 0x0004
124#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
125#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
126#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
127#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
128#define E2PROM_CSR_TYPE FIELD32(0x00000030)
129#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
130#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
131
132/*
133 * AUX_CTRL: Aux/PCI-E related configuration
134 */
135#define AUX_CTRL 0x10c
136#define AUX_CTRL_WAKE_PCIE_EN FIELD32(0x00000002)
137#define AUX_CTRL_FORCE_PCIE_CLK FIELD32(0x00000400)
138
139/*
140 * OPT_14: Unknown register used by rt3xxx devices.
141 */
142#define OPT_14_CSR 0x0114
143#define OPT_14_CSR_BIT0 FIELD32(0x00000001)
144
145/*
146 * INT_SOURCE_CSR: Interrupt source register.
147 * Write one to clear corresponding bit.
148 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
149 */
150#define INT_SOURCE_CSR 0x0200
151#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
152#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
153#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
154#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
155#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
156#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
157#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
158#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
159#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
160#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
161#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
162#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
163#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
164#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
165#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
166#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
167#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
168#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
169
170/*
171 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
172 */
173#define INT_MASK_CSR 0x0204
174#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
175#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
176#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
177#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
178#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
179#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
180#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
181#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
182#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
183#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
184#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
185#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
186#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
187#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
188#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
189#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
190#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
191#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
192
193/*
194 * WPDMA_GLO_CFG
195 */
196#define WPDMA_GLO_CFG 0x0208
197#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
198#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
199#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
200#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
201#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
202#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
203#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
204#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
205#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
206
207/*
208 * WPDMA_RST_IDX
209 */
210#define WPDMA_RST_IDX 0x020c
211#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
212#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
213#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
214#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
215#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
216#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
217#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
218
219/*
220 * DELAY_INT_CFG
221 */
222#define DELAY_INT_CFG 0x0210
223#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
224#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
225#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
226#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
227#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
228#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
229
230/*
231 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
232 * AIFSN0: AC_VO
233 * AIFSN1: AC_VI
234 * AIFSN2: AC_BE
235 * AIFSN3: AC_BK
236 */
237#define WMM_AIFSN_CFG 0x0214
238#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
239#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
240#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
241#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
242
243/*
244 * WMM_CWMIN_CSR: CWmin for each EDCA AC
245 * CWMIN0: AC_VO
246 * CWMIN1: AC_VI
247 * CWMIN2: AC_BE
248 * CWMIN3: AC_BK
249 */
250#define WMM_CWMIN_CFG 0x0218
251#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
252#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
253#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
254#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
255
256/*
257 * WMM_CWMAX_CSR: CWmax for each EDCA AC
258 * CWMAX0: AC_VO
259 * CWMAX1: AC_VI
260 * CWMAX2: AC_BE
261 * CWMAX3: AC_BK
262 */
263#define WMM_CWMAX_CFG 0x021c
264#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
265#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
266#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
267#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
268
269/*
270 * AC_TXOP0: AC_VO/AC_VI TXOP register
271 * AC0TXOP: AC_VO in unit of 32us
272 * AC1TXOP: AC_VI in unit of 32us
273 */
274#define WMM_TXOP0_CFG 0x0220
275#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
276#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
277
278/*
279 * AC_TXOP1: AC_BE/AC_BK TXOP register
280 * AC2TXOP: AC_BE in unit of 32us
281 * AC3TXOP: AC_BK in unit of 32us
282 */
283#define WMM_TXOP1_CFG 0x0224
284#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
285#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
286
287/*
288 * GPIO_CTRL_CFG:
289 * GPIOD: GPIO direction, 0: Output, 1: Input
290 */
291#define GPIO_CTRL_CFG 0x0228
292#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
293#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
294#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
295#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
296#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
297#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
298#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
299#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
300#define GPIO_CTRL_CFG_GPIOD_BIT0 FIELD32(0x00000100)
301#define GPIO_CTRL_CFG_GPIOD_BIT1 FIELD32(0x00000200)
302#define GPIO_CTRL_CFG_GPIOD_BIT2 FIELD32(0x00000400)
303#define GPIO_CTRL_CFG_GPIOD_BIT3 FIELD32(0x00000800)
304#define GPIO_CTRL_CFG_GPIOD_BIT4 FIELD32(0x00001000)
305#define GPIO_CTRL_CFG_GPIOD_BIT5 FIELD32(0x00002000)
306#define GPIO_CTRL_CFG_GPIOD_BIT6 FIELD32(0x00004000)
307#define GPIO_CTRL_CFG_GPIOD_BIT7 FIELD32(0x00008000)
308
309/*
310 * MCU_CMD_CFG
311 */
312#define MCU_CMD_CFG 0x022c
313
314/*
315 * AC_VO register offsets
316 */
317#define TX_BASE_PTR0 0x0230
318#define TX_MAX_CNT0 0x0234
319#define TX_CTX_IDX0 0x0238
320#define TX_DTX_IDX0 0x023c
321
322/*
323 * AC_VI register offsets
324 */
325#define TX_BASE_PTR1 0x0240
326#define TX_MAX_CNT1 0x0244
327#define TX_CTX_IDX1 0x0248
328#define TX_DTX_IDX1 0x024c
329
330/*
331 * AC_BE register offsets
332 */
333#define TX_BASE_PTR2 0x0250
334#define TX_MAX_CNT2 0x0254
335#define TX_CTX_IDX2 0x0258
336#define TX_DTX_IDX2 0x025c
337
338/*
339 * AC_BK register offsets
340 */
341#define TX_BASE_PTR3 0x0260
342#define TX_MAX_CNT3 0x0264
343#define TX_CTX_IDX3 0x0268
344#define TX_DTX_IDX3 0x026c
345
346/*
347 * HCCA register offsets
348 */
349#define TX_BASE_PTR4 0x0270
350#define TX_MAX_CNT4 0x0274
351#define TX_CTX_IDX4 0x0278
352#define TX_DTX_IDX4 0x027c
353
354/*
355 * MGMT register offsets
356 */
357#define TX_BASE_PTR5 0x0280
358#define TX_MAX_CNT5 0x0284
359#define TX_CTX_IDX5 0x0288
360#define TX_DTX_IDX5 0x028c
361
362/*
363 * RX register offsets
364 */
365#define RX_BASE_PTR 0x0290
366#define RX_MAX_CNT 0x0294
367#define RX_CRX_IDX 0x0298
368#define RX_DRX_IDX 0x029c
369
370/*
371 * USB_DMA_CFG
372 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
373 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
374 * PHY_CLEAR: phy watch dog enable.
375 * TX_CLEAR: Clear USB DMA TX path.
376 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
377 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
378 * RX_BULK_EN: Enable USB DMA Rx.
379 * TX_BULK_EN: Enable USB DMA Tx.
380 * EP_OUT_VALID: OUT endpoint data valid.
381 * RX_BUSY: USB DMA RX FSM busy.
382 * TX_BUSY: USB DMA TX FSM busy.
383 */
384#define USB_DMA_CFG 0x02a0
385#define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
386#define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
387#define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
388#define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
389#define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
390#define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
391#define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
392#define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
393#define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
394#define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
395#define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
396
397/*
398 * US_CYC_CNT
399 * BT_MODE_EN: Bluetooth mode enable
400 * CLOCK CYCLE: Clock cycle count in 1us.
401 * PCI:0x21, PCIE:0x7d, USB:0x1e
402 */
403#define US_CYC_CNT 0x02a4
404#define US_CYC_CNT_BT_MODE_EN FIELD32(0x00000100)
405#define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
406
407/*
408 * PBF_SYS_CTRL
409 * HOST_RAM_WRITE: enable Host program ram write selection
410 */
411#define PBF_SYS_CTRL 0x0400
412#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
413#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
414
415/*
416 * HOST-MCU shared memory
417 */
418#define HOST_CMD_CSR 0x0404
419#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
420
421/*
422 * PBF registers
423 * Most are for debug. Driver doesn't touch PBF register.
424 */
425#define PBF_CFG 0x0408
426#define PBF_MAX_PCNT 0x040c
427#define PBF_CTRL 0x0410
428#define PBF_INT_STA 0x0414
429#define PBF_INT_ENA 0x0418
430
431/*
432 * BCN_OFFSET0:
433 */
434#define BCN_OFFSET0 0x042c
435#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
436#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
437#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
438#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
439
440/*
441 * BCN_OFFSET1:
442 */
443#define BCN_OFFSET1 0x0430
444#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
445#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
446#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
447#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
448
449/*
450 * TXRXQ_PCNT: PBF register
451 * PCNT_TX0Q: Page count for TX hardware queue 0
452 * PCNT_TX1Q: Page count for TX hardware queue 1
453 * PCNT_TX2Q: Page count for TX hardware queue 2
454 * PCNT_RX0Q: Page count for RX hardware queue
455 */
456#define TXRXQ_PCNT 0x0438
457#define TXRXQ_PCNT_TX0Q FIELD32(0x000000ff)
458#define TXRXQ_PCNT_TX1Q FIELD32(0x0000ff00)
459#define TXRXQ_PCNT_TX2Q FIELD32(0x00ff0000)
460#define TXRXQ_PCNT_RX0Q FIELD32(0xff000000)
461
462/*
463 * PBF register
464 * Debug. Driver doesn't touch PBF register.
465 */
466#define PBF_DBG 0x043c
467
468/*
469 * RF registers
470 */
471#define RF_CSR_CFG 0x0500
472#define RF_CSR_CFG_DATA FIELD32(0x000000ff)
473#define RF_CSR_CFG_REGNUM FIELD32(0x00003f00)
474#define RF_CSR_CFG_WRITE FIELD32(0x00010000)
475#define RF_CSR_CFG_BUSY FIELD32(0x00020000)
476
477/*
478 * EFUSE_CSR: RT30x0 EEPROM
479 */
480#define EFUSE_CTRL 0x0580
481#define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
482#define EFUSE_CTRL_MODE FIELD32(0x000000c0)
483#define EFUSE_CTRL_KICK FIELD32(0x40000000)
484#define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
485
486/*
487 * EFUSE_DATA0
488 */
489#define EFUSE_DATA0 0x0590
490
491/*
492 * EFUSE_DATA1
493 */
494#define EFUSE_DATA1 0x0594
495
496/*
497 * EFUSE_DATA2
498 */
499#define EFUSE_DATA2 0x0598
500
501/*
502 * EFUSE_DATA3
503 */
504#define EFUSE_DATA3 0x059c
505
506/*
507 * LDO_CFG0
508 */
509#define LDO_CFG0 0x05d4
510#define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
511#define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
512#define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
513#define LDO_CFG0_BGSEL FIELD32(0x03000000)
514#define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
515#define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
516#define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
517
518/*
519 * GPIO_SWITCH
520 */
521#define GPIO_SWITCH 0x05dc
522#define GPIO_SWITCH_0 FIELD32(0x00000001)
523#define GPIO_SWITCH_1 FIELD32(0x00000002)
524#define GPIO_SWITCH_2 FIELD32(0x00000004)
525#define GPIO_SWITCH_3 FIELD32(0x00000008)
526#define GPIO_SWITCH_4 FIELD32(0x00000010)
527#define GPIO_SWITCH_5 FIELD32(0x00000020)
528#define GPIO_SWITCH_6 FIELD32(0x00000040)
529#define GPIO_SWITCH_7 FIELD32(0x00000080)
530
531/*
532 * MAC Control/Status Registers(CSR).
533 * Some values are set in TU, whereas 1 TU == 1024 us.
534 */
535
536/*
537 * MAC_CSR0: ASIC revision number.
538 * ASIC_REV: 0
539 * ASIC_VER: 2860 or 2870
540 */
541#define MAC_CSR0 0x1000
542#define MAC_CSR0_REVISION FIELD32(0x0000ffff)
543#define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
544
545/*
546 * MAC_SYS_CTRL:
547 */
548#define MAC_SYS_CTRL 0x1004
549#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
550#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
551#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
552#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
553#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
554#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
555#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
556#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
557
558/*
559 * MAC_ADDR_DW0: STA MAC register 0
560 */
561#define MAC_ADDR_DW0 0x1008
562#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
563#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
564#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
565#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
566
567/*
568 * MAC_ADDR_DW1: STA MAC register 1
569 * UNICAST_TO_ME_MASK:
570 * Used to mask off bits from byte 5 of the MAC address
571 * to determine the UNICAST_TO_ME bit for RX frames.
572 * The full mask is complemented by BSS_ID_MASK:
573 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
574 */
575#define MAC_ADDR_DW1 0x100c
576#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
577#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
578#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
579
580/*
581 * MAC_BSSID_DW0: BSSID register 0
582 */
583#define MAC_BSSID_DW0 0x1010
584#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
585#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
586#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
587#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
588
589/*
590 * MAC_BSSID_DW1: BSSID register 1
591 * BSS_ID_MASK:
592 * 0: 1-BSSID mode (BSS index = 0)
593 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
594 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
595 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
596 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
597 * BSSID. This will make sure that those bits will be ignored
598 * when determining the MY_BSS of RX frames.
599 */
600#define MAC_BSSID_DW1 0x1014
601#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
602#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
603#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
604#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
605
606/*
607 * MAX_LEN_CFG: Maximum frame length register.
608 * MAX_MPDU: rt2860b max 16k bytes
609 * MAX_PSDU: Maximum PSDU length
610 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
611 */
612#define MAX_LEN_CFG 0x1018
613#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
614#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
615#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
616#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
617
618/*
619 * BBP_CSR_CFG: BBP serial control register
620 * VALUE: Register value to program into BBP
621 * REG_NUM: Selected BBP register
622 * READ_CONTROL: 0 write BBP, 1 read BBP
623 * BUSY: ASIC is busy executing BBP commands
624 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
625 * BBP_RW_MODE: 0 serial, 1 parallel
626 */
627#define BBP_CSR_CFG 0x101c
628#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
629#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
630#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
631#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
632#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
633#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
634
635/*
636 * RF_CSR_CFG0: RF control register
637 * REGID_AND_VALUE: Register value to program into RF
638 * BITWIDTH: Selected RF register
639 * STANDBYMODE: 0 high when standby, 1 low when standby
640 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
641 * BUSY: ASIC is busy executing RF commands
642 */
643#define RF_CSR_CFG0 0x1020
644#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
645#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
646#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
647#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
648#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
649#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
650
651/*
652 * RF_CSR_CFG1: RF control register
653 * REGID_AND_VALUE: Register value to program into RF
654 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
655 * 0: 3 system clock cycle (37.5usec)
656 * 1: 5 system clock cycle (62.5usec)
657 */
658#define RF_CSR_CFG1 0x1024
659#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
660#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
661
662/*
663 * RF_CSR_CFG2: RF control register
664 * VALUE: Register value to program into RF
665 */
666#define RF_CSR_CFG2 0x1028
667#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
668
669/*
670 * LED_CFG: LED control
671 * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1)
672 * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1)
673 * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2)
674 * color LED's:
675 * 0: off
676 * 1: blinking upon TX2
677 * 2: periodic slow blinking
678 * 3: always on
679 * LED polarity:
680 * 0: active low
681 * 1: active high
682 */
683#define LED_CFG 0x102c
684#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
685#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
686#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
687#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
688#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
689#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
690#define LED_CFG_LED_POLAR FIELD32(0x40000000)
691
692/*
693 * AMPDU_BA_WINSIZE: Force BlockAck window size
694 * FORCE_WINSIZE_ENABLE:
695 * 0: Disable forcing of BlockAck window size
696 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
697 * window size values in the TXWI
698 * FORCE_WINSIZE: BlockAck window size
699 */
700#define AMPDU_BA_WINSIZE 0x1040
701#define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
702#define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
703
704/*
705 * XIFS_TIME_CFG: MAC timing
706 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
707 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
708 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
709 * when MAC doesn't reference BBP signal BBRXEND
710 * EIFS: unit 1us
711 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
712 *
713 */
714#define XIFS_TIME_CFG 0x1100
715#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
716#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
717#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
718#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
719#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
720
721/*
722 * BKOFF_SLOT_CFG:
723 */
724#define BKOFF_SLOT_CFG 0x1104
725#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
726#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
727
728/*
729 * NAV_TIME_CFG:
730 */
731#define NAV_TIME_CFG 0x1108
732#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
733#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
734#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
735#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
736
737/*
738 * CH_TIME_CFG: count as channel busy
739 * EIFS_BUSY: Count EIFS as channel busy
740 * NAV_BUSY: Count NAS as channel busy
741 * RX_BUSY: Count RX as channel busy
742 * TX_BUSY: Count TX as channel busy
743 * TMR_EN: Enable channel statistics timer
744 */
745#define CH_TIME_CFG 0x110c
746#define CH_TIME_CFG_EIFS_BUSY FIELD32(0x00000010)
747#define CH_TIME_CFG_NAV_BUSY FIELD32(0x00000008)
748#define CH_TIME_CFG_RX_BUSY FIELD32(0x00000004)
749#define CH_TIME_CFG_TX_BUSY FIELD32(0x00000002)
750#define CH_TIME_CFG_TMR_EN FIELD32(0x00000001)
751
752/*
753 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
754 */
755#define PBF_LIFE_TIMER 0x1110
756
757/*
758 * BCN_TIME_CFG:
759 * BEACON_INTERVAL: in unit of 1/16 TU
760 * TSF_TICKING: Enable TSF auto counting
761 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
762 * BEACON_GEN: Enable beacon generator
763 */
764#define BCN_TIME_CFG 0x1114
765#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
766#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
767#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
768#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
769#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
770#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
771
772/*
773 * TBTT_SYNC_CFG:
774 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
775 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
776 */
777#define TBTT_SYNC_CFG 0x1118
778#define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
779#define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
780#define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
781#define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
782
783/*
784 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
785 */
786#define TSF_TIMER_DW0 0x111c
787#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
788
789/*
790 * TSF_TIMER_DW1: Local msb TSF timer, read-only
791 */
792#define TSF_TIMER_DW1 0x1120
793#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
794
795/*
796 * TBTT_TIMER: TImer remains till next TBTT, read-only
797 */
798#define TBTT_TIMER 0x1124
799
800/*
801 * INT_TIMER_CFG: timer configuration
802 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
803 * GP_TIMER: period of general purpose timer in units of 1/16 TU
804 */
805#define INT_TIMER_CFG 0x1128
806#define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
807#define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
808
809/*
810 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
811 */
812#define INT_TIMER_EN 0x112c
813#define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
814#define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
815
816/*
817 * CH_IDLE_STA: channel idle time (in us)
818 */
819#define CH_IDLE_STA 0x1130
820
821/*
822 * CH_BUSY_STA: channel busy time on primary channel (in us)
823 */
824#define CH_BUSY_STA 0x1134
825
826/*
827 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
828 */
829#define CH_BUSY_STA_SEC 0x1138
830
831/*
832 * MAC_STATUS_CFG:
833 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
834 * if 1 or higher one of the 2 registers is busy.
835 */
836#define MAC_STATUS_CFG 0x1200
837#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
838
839/*
840 * PWR_PIN_CFG:
841 */
842#define PWR_PIN_CFG 0x1204
843
844/*
845 * AUTOWAKEUP_CFG: Manual power control / status register
846 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
847 * AUTOWAKE: 0:sleep, 1:awake
848 */
849#define AUTOWAKEUP_CFG 0x1208
850#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
851#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
852#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
853
854/*
855 * EDCA_AC0_CFG:
856 */
857#define EDCA_AC0_CFG 0x1300
858#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
859#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
860#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
861#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
862
863/*
864 * EDCA_AC1_CFG:
865 */
866#define EDCA_AC1_CFG 0x1304
867#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
868#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
869#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
870#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
871
872/*
873 * EDCA_AC2_CFG:
874 */
875#define EDCA_AC2_CFG 0x1308
876#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
877#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
878#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
879#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
880
881/*
882 * EDCA_AC3_CFG:
883 */
884#define EDCA_AC3_CFG 0x130c
885#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
886#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
887#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
888#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
889
890/*
891 * EDCA_TID_AC_MAP:
892 */
893#define EDCA_TID_AC_MAP 0x1310
894
895/*
896 * TX_PWR_CFG:
897 */
898#define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
899#define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
900#define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
901#define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
902#define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
903#define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
904#define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
905#define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
906
907/*
908 * TX_PWR_CFG_0:
909 */
910#define TX_PWR_CFG_0 0x1314
911#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
912#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
913#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
914#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
915#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
916#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
917#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
918#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
919
920/*
921 * TX_PWR_CFG_1:
922 */
923#define TX_PWR_CFG_1 0x1318
924#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
925#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
926#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
927#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
928#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
929#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
930#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
931#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
932
933/*
934 * TX_PWR_CFG_2:
935 */
936#define TX_PWR_CFG_2 0x131c
937#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
938#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
939#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
940#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
941#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
942#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
943#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
944#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
945
946/*
947 * TX_PWR_CFG_3:
948 */
949#define TX_PWR_CFG_3 0x1320
950#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
951#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
952#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
953#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
954#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
955#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
956#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
957#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
958
959/*
960 * TX_PWR_CFG_4:
961 */
962#define TX_PWR_CFG_4 0x1324
963#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
964#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
965#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
966#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
967
968/*
969 * TX_PIN_CFG:
970 */
971#define TX_PIN_CFG 0x1328
972#define TX_PIN_CFG_PA_PE_DISABLE 0xfcfffff0
973#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
974#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
975#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
976#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
977#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
978#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
979#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
980#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
981#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
982#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
983#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
984#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
985#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
986#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
987#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
988#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
989#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
990#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
991#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
992#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
993#define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
994#define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
995#define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
996#define TX_PIN_CFG_PA_PE_G2_POL FIELD32(0x08000000)
997#define TX_PIN_CFG_LNA_PE_A2_EN FIELD32(0x10000000)
998#define TX_PIN_CFG_LNA_PE_G2_EN FIELD32(0x20000000)
999#define TX_PIN_CFG_LNA_PE_A2_POL FIELD32(0x40000000)
1000#define TX_PIN_CFG_LNA_PE_G2_POL FIELD32(0x80000000)
1001
1002/*
1003 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
1004 */
1005#define TX_BAND_CFG 0x132c
1006#define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
1007#define TX_BAND_CFG_A FIELD32(0x00000002)
1008#define TX_BAND_CFG_BG FIELD32(0x00000004)
1009
1010/*
1011 * TX_SW_CFG0:
1012 */
1013#define TX_SW_CFG0 0x1330
1014
1015/*
1016 * TX_SW_CFG1:
1017 */
1018#define TX_SW_CFG1 0x1334
1019
1020/*
1021 * TX_SW_CFG2:
1022 */
1023#define TX_SW_CFG2 0x1338
1024
1025/*
1026 * TXOP_THRES_CFG:
1027 */
1028#define TXOP_THRES_CFG 0x133c
1029
1030/*
1031 * TXOP_CTRL_CFG:
1032 * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
1033 * AC_TRUN_EN: Enable/Disable truncation for AC change
1034 * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
1035 * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
1036 * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
1037 * RESERVED_TRUN_EN: Reserved
1038 * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
1039 * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
1040 * transmissions if extension CCA is clear).
1041 * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
1042 * EXT_CWMIN: CwMin for extension channel backoff
1043 * 0: Disabled
1044 *
1045 */
1046#define TXOP_CTRL_CFG 0x1340
1047#define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN FIELD32(0x00000001)
1048#define TXOP_CTRL_CFG_AC_TRUN_EN FIELD32(0x00000002)
1049#define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
1050#define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
1051#define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN FIELD32(0x00000010)
1052#define TXOP_CTRL_CFG_RESERVED_TRUN_EN FIELD32(0x00000020)
1053#define TXOP_CTRL_CFG_LSIG_TXOP_EN FIELD32(0x00000040)
1054#define TXOP_CTRL_CFG_EXT_CCA_EN FIELD32(0x00000080)
1055#define TXOP_CTRL_CFG_EXT_CCA_DLY FIELD32(0x0000ff00)
1056#define TXOP_CTRL_CFG_EXT_CWMIN FIELD32(0x000f0000)
1057
1058/*
1059 * TX_RTS_CFG:
1060 * RTS_THRES: unit:byte
1061 * RTS_FBK_EN: enable rts rate fallback
1062 */
1063#define TX_RTS_CFG 0x1344
1064#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
1065#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
1066#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
1067
1068/*
1069 * TX_TIMEOUT_CFG:
1070 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
1071 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
1072 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
1073 * it is recommended that:
1074 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
1075 */
1076#define TX_TIMEOUT_CFG 0x1348
1077#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
1078#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
1079#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
1080
1081/*
1082 * TX_RTY_CFG:
1083 * SHORT_RTY_LIMIT: short retry limit
1084 * LONG_RTY_LIMIT: long retry limit
1085 * LONG_RTY_THRE: Long retry threshoold
1086 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
1087 * 0:expired by retry limit, 1: expired by mpdu life timer
1088 * AGG_RTY_MODE: Aggregate MPDU retry mode
1089 * 0:expired by retry limit, 1: expired by mpdu life timer
1090 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1091 */
1092#define TX_RTY_CFG 0x134c
1093#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1094#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1095#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1096#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1097#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1098#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1099
1100/*
1101 * TX_LINK_CFG:
1102 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1103 * MFB_ENABLE: TX apply remote MFB 1:enable
1104 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
1105 * 0: not apply remote remote unsolicit (MFS=7)
1106 * TX_MRQ_EN: MCS request TX enable
1107 * TX_RDG_EN: RDG TX enable
1108 * TX_CF_ACK_EN: Piggyback CF-ACK enable
1109 * REMOTE_MFB: remote MCS feedback
1110 * REMOTE_MFS: remote MCS feedback sequence number
1111 */
1112#define TX_LINK_CFG 0x1350
1113#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1114#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1115#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1116#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1117#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1118#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1119#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1120#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1121
1122/*
1123 * HT_FBK_CFG0:
1124 */
1125#define HT_FBK_CFG0 0x1354
1126#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1127#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1128#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1129#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1130#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1131#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1132#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1133#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1134
1135/*
1136 * HT_FBK_CFG1:
1137 */
1138#define HT_FBK_CFG1 0x1358
1139#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1140#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1141#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1142#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1143#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1144#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1145#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1146#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1147
1148/*
1149 * LG_FBK_CFG0:
1150 */
1151#define LG_FBK_CFG0 0x135c
1152#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1153#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1154#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1155#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1156#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1157#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1158#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1159#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1160
1161/*
1162 * LG_FBK_CFG1:
1163 */
1164#define LG_FBK_CFG1 0x1360
1165#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1166#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1167#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1168#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1169
1170/*
1171 * CCK_PROT_CFG: CCK Protection
1172 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1173 * PROTECT_CTRL: Protection control frame type for CCK TX
1174 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1175 * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV
1176 * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV
1177 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1178 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1179 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1180 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1181 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1182 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1183 * RTS_TH_EN: RTS threshold enable on CCK TX
1184 */
1185#define CCK_PROT_CFG 0x1364
1186#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1187#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1188#define CCK_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1189#define CCK_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1190#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1191#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1192#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1193#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1194#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1195#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1196#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1197
1198/*
1199 * OFDM_PROT_CFG: OFDM Protection
1200 */
1201#define OFDM_PROT_CFG 0x1368
1202#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1203#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1204#define OFDM_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1205#define OFDM_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1206#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1207#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1208#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1209#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1210#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1211#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1212#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1213
1214/*
1215 * MM20_PROT_CFG: MM20 Protection
1216 */
1217#define MM20_PROT_CFG 0x136c
1218#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1219#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1220#define MM20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1221#define MM20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1222#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1223#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1224#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1225#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1226#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1227#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1228#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1229
1230/*
1231 * MM40_PROT_CFG: MM40 Protection
1232 */
1233#define MM40_PROT_CFG 0x1370
1234#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1235#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1236#define MM40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1237#define MM40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1238#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1239#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1240#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1241#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1242#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1243#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1244#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1245
1246/*
1247 * GF20_PROT_CFG: GF20 Protection
1248 */
1249#define GF20_PROT_CFG 0x1374
1250#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1251#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1252#define GF20_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1253#define GF20_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1254#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1255#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1256#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1257#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1258#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1259#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1260#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1261
1262/*
1263 * GF40_PROT_CFG: GF40 Protection
1264 */
1265#define GF40_PROT_CFG 0x1378
1266#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1267#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1268#define GF40_PROT_CFG_PROTECT_NAV_SHORT FIELD32(0x00040000)
1269#define GF40_PROT_CFG_PROTECT_NAV_LONG FIELD32(0x00080000)
1270#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1271#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1272#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1273#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1274#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1275#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1276#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1277
1278/*
1279 * EXP_CTS_TIME:
1280 */
1281#define EXP_CTS_TIME 0x137c
1282
1283/*
1284 * EXP_ACK_TIME:
1285 */
1286#define EXP_ACK_TIME 0x1380
1287
1288/*
1289 * RX_FILTER_CFG: RX configuration register.
1290 */
1291#define RX_FILTER_CFG 0x1400
1292#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1293#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1294#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1295#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1296#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1297#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1298#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1299#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1300#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1301#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1302#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1303#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1304#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1305#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1306#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1307#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1308#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1309
1310/*
1311 * AUTO_RSP_CFG:
1312 * AUTORESPONDER: 0: disable, 1: enable
1313 * BAC_ACK_POLICY: 0:long, 1:short preamble
1314 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1315 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1316 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1317 * DUAL_CTS_EN: Power bit value in control frame
1318 * ACK_CTS_PSM_BIT:Power bit value in control frame
1319 */
1320#define AUTO_RSP_CFG 0x1404
1321#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1322#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1323#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1324#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1325#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1326#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1327#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1328
1329/*
1330 * LEGACY_BASIC_RATE:
1331 */
1332#define LEGACY_BASIC_RATE 0x1408
1333
1334/*
1335 * HT_BASIC_RATE:
1336 */
1337#define HT_BASIC_RATE 0x140c
1338
1339/*
1340 * HT_CTRL_CFG:
1341 */
1342#define HT_CTRL_CFG 0x1410
1343
1344/*
1345 * SIFS_COST_CFG:
1346 */
1347#define SIFS_COST_CFG 0x1414
1348
1349/*
1350 * RX_PARSER_CFG:
1351 * Set NAV for all received frames
1352 */
1353#define RX_PARSER_CFG 0x1418
1354
1355/*
1356 * TX_SEC_CNT0:
1357 */
1358#define TX_SEC_CNT0 0x1500
1359
1360/*
1361 * RX_SEC_CNT0:
1362 */
1363#define RX_SEC_CNT0 0x1504
1364
1365/*
1366 * CCMP_FC_MUTE:
1367 */
1368#define CCMP_FC_MUTE 0x1508
1369
1370/*
1371 * TXOP_HLDR_ADDR0:
1372 */
1373#define TXOP_HLDR_ADDR0 0x1600
1374
1375/*
1376 * TXOP_HLDR_ADDR1:
1377 */
1378#define TXOP_HLDR_ADDR1 0x1604
1379
1380/*
1381 * TXOP_HLDR_ET:
1382 */
1383#define TXOP_HLDR_ET 0x1608
1384
1385/*
1386 * QOS_CFPOLL_RA_DW0:
1387 */
1388#define QOS_CFPOLL_RA_DW0 0x160c
1389
1390/*
1391 * QOS_CFPOLL_RA_DW1:
1392 */
1393#define QOS_CFPOLL_RA_DW1 0x1610
1394
1395/*
1396 * QOS_CFPOLL_QC:
1397 */
1398#define QOS_CFPOLL_QC 0x1614
1399
1400/*
1401 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1402 */
1403#define RX_STA_CNT0 0x1700
1404#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1405#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1406
1407/*
1408 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1409 */
1410#define RX_STA_CNT1 0x1704
1411#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1412#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1413
1414/*
1415 * RX_STA_CNT2:
1416 */
1417#define RX_STA_CNT2 0x1708
1418#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1419#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1420
1421/*
1422 * TX_STA_CNT0: TX Beacon count
1423 */
1424#define TX_STA_CNT0 0x170c
1425#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1426#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1427
1428/*
1429 * TX_STA_CNT1: TX tx count
1430 */
1431#define TX_STA_CNT1 0x1710
1432#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1433#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1434
1435/*
1436 * TX_STA_CNT2: TX tx count
1437 */
1438#define TX_STA_CNT2 0x1714
1439#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1440#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1441
1442/*
1443 * TX_STA_FIFO: TX Result for specific PID status fifo register.
1444 *
1445 * This register is implemented as FIFO with 16 entries in the HW. Each
1446 * register read fetches the next tx result. If the FIFO is full because
1447 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1448 * triggered, the hw seems to simply drop further tx results.
1449 *
1450 * VALID: 1: this tx result is valid
1451 * 0: no valid tx result -> driver should stop reading
1452 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1453 * to match a frame with its tx result (even though the PID is
1454 * only 4 bits wide).
1455 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1456 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1457 * This identification number is calculated by ((idx % 3) + 1).
1458 * TX_SUCCESS: Indicates tx success (1) or failure (0)
1459 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1460 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1461 * WCID: The wireless client ID.
1462 * MCS: The tx rate used during the last transmission of this frame, be it
1463 * successful or not.
1464 * PHYMODE: The phymode used for the transmission.
1465 */
1466#define TX_STA_FIFO 0x1718
1467#define TX_STA_FIFO_VALID FIELD32(0x00000001)
1468#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1469#define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1470#define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1471#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1472#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1473#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1474#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1475#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1476#define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1477#define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1478
1479/*
1480 * TX_AGG_CNT: Debug counter
1481 */
1482#define TX_AGG_CNT 0x171c
1483#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1484#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1485
1486/*
1487 * TX_AGG_CNT0:
1488 */
1489#define TX_AGG_CNT0 0x1720
1490#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1491#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1492
1493/*
1494 * TX_AGG_CNT1:
1495 */
1496#define TX_AGG_CNT1 0x1724
1497#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1498#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1499
1500/*
1501 * TX_AGG_CNT2:
1502 */
1503#define TX_AGG_CNT2 0x1728
1504#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1505#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1506
1507/*
1508 * TX_AGG_CNT3:
1509 */
1510#define TX_AGG_CNT3 0x172c
1511#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1512#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1513
1514/*
1515 * TX_AGG_CNT4:
1516 */
1517#define TX_AGG_CNT4 0x1730
1518#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1519#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1520
1521/*
1522 * TX_AGG_CNT5:
1523 */
1524#define TX_AGG_CNT5 0x1734
1525#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1526#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1527
1528/*
1529 * TX_AGG_CNT6:
1530 */
1531#define TX_AGG_CNT6 0x1738
1532#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1533#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1534
1535/*
1536 * TX_AGG_CNT7:
1537 */
1538#define TX_AGG_CNT7 0x173c
1539#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1540#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1541
1542/*
1543 * MPDU_DENSITY_CNT:
1544 * TX_ZERO_DEL: TX zero length delimiter count
1545 * RX_ZERO_DEL: RX zero length delimiter count
1546 */
1547#define MPDU_DENSITY_CNT 0x1740
1548#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1549#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1550
1551/*
1552 * Security key table memory.
1553 *
1554 * The pairwise key table shares some memory with the beacon frame
1555 * buffers 6 and 7. That basically means that when beacon 6 & 7
1556 * are used we should only use the reduced pairwise key table which
1557 * has a maximum of 222 entries.
1558 *
1559 * ---------------------------------------------
1560 * |0x4000 | Pairwise Key | Reduced Pairwise |
1561 * | | Table | Key Table |
1562 * | | Size: 256 * 32 | Size: 222 * 32 |
1563 * |0x5BC0 | |-------------------
1564 * | | | Beacon 6 |
1565 * |0x5DC0 | |-------------------
1566 * | | | Beacon 7 |
1567 * |0x5FC0 | |-------------------
1568 * |0x5FFF | |
1569 * --------------------------
1570 *
1571 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1572 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1573 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1574 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1575 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1576 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1577 */
1578#define MAC_WCID_BASE 0x1800
1579#define PAIRWISE_KEY_TABLE_BASE 0x4000
1580#define MAC_IVEIV_TABLE_BASE 0x6000
1581#define MAC_WCID_ATTRIBUTE_BASE 0x6800
1582#define SHARED_KEY_TABLE_BASE 0x6c00
1583#define SHARED_KEY_MODE_BASE 0x7000
1584
1585#define MAC_WCID_ENTRY(__idx) \
1586 (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
1587#define PAIRWISE_KEY_ENTRY(__idx) \
1588 (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1589#define MAC_IVEIV_ENTRY(__idx) \
1590 (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
1591#define MAC_WCID_ATTR_ENTRY(__idx) \
1592 (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
1593#define SHARED_KEY_ENTRY(__idx) \
1594 (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
1595#define SHARED_KEY_MODE_ENTRY(__idx) \
1596 (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
1597
1598struct mac_wcid_entry {
1599 u8 mac[6];
1600 u8 reserved[2];
1601} __packed;
1602
1603struct hw_key_entry {
1604 u8 key[16];
1605 u8 tx_mic[8];
1606 u8 rx_mic[8];
1607} __packed;
1608
1609struct mac_iveiv_entry {
1610 u8 iv[8];
1611} __packed;
1612
1613/*
1614 * MAC_WCID_ATTRIBUTE:
1615 */
1616#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1617#define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1618#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1619#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1620#define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1621#define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1622#define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1623#define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1624
1625/*
1626 * SHARED_KEY_MODE:
1627 */
1628#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1629#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1630#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1631#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1632#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1633#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1634#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1635#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1636
1637/*
1638 * HOST-MCU communication
1639 */
1640
1641/*
1642 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1643 * CMD_TOKEN: Command id, 0xff disable status reporting.
1644 */
1645#define H2M_MAILBOX_CSR 0x7010
1646#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1647#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1648#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1649#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1650
1651/*
1652 * H2M_MAILBOX_CID:
1653 * Free slots contain 0xff. MCU will store command's token to lowest free slot.
1654 * If all slots are occupied status will be dropped.
1655 */
1656#define H2M_MAILBOX_CID 0x7014
1657#define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1658#define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1659#define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1660#define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1661
1662/*
1663 * H2M_MAILBOX_STATUS:
1664 * Command status will be saved to same slot as command id.
1665 */
1666#define H2M_MAILBOX_STATUS 0x701c
1667
1668/*
1669 * H2M_INT_SRC:
1670 */
1671#define H2M_INT_SRC 0x7024
1672
1673/*
1674 * H2M_BBP_AGENT:
1675 */
1676#define H2M_BBP_AGENT 0x7028
1677
1678/*
1679 * MCU_LEDCS: LED control for MCU Mailbox.
1680 */
1681#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1682#define MCU_LEDCS_POLARITY FIELD8(0x01)
1683
1684/*
1685 * HW_CS_CTS_BASE:
1686 * Carrier-sense CTS frame base address.
1687 * It's where mac stores carrier-sense frame for carrier-sense function.
1688 */
1689#define HW_CS_CTS_BASE 0x7700
1690
1691/*
1692 * HW_DFS_CTS_BASE:
1693 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1694 */
1695#define HW_DFS_CTS_BASE 0x7780
1696
1697/*
1698 * TXRX control registers - base address 0x3000
1699 */
1700
1701/*
1702 * TXRX_CSR1:
1703 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1704 */
1705#define TXRX_CSR1 0x77d0
1706
1707/*
1708 * HW_DEBUG_SETTING_BASE:
1709 * since NULL frame won't be that long (256 byte)
1710 * We steal 16 tail bytes to save debugging settings
1711 */
1712#define HW_DEBUG_SETTING_BASE 0x77f0
1713#define HW_DEBUG_SETTING_BASE2 0x7770
1714
1715/*
1716 * HW_BEACON_BASE
1717 * In order to support maximum 8 MBSS and its maximum length
1718 * is 512 bytes for each beacon
1719 * Three section discontinue memory segments will be used.
1720 * 1. The original region for BCN 0~3
1721 * 2. Extract memory from FCE table for BCN 4~5
1722 * 3. Extract memory from Pair-wise key table for BCN 6~7
1723 * It occupied those memory of wcid 238~253 for BCN 6
1724 * and wcid 222~237 for BCN 7 (see Security key table memory
1725 * for more info).
1726 *
1727 * IMPORTANT NOTE: Not sure why legacy driver does this,
1728 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1729 */
1730#define HW_BEACON_BASE0 0x7800
1731#define HW_BEACON_BASE1 0x7a00
1732#define HW_BEACON_BASE2 0x7c00
1733#define HW_BEACON_BASE3 0x7e00
1734#define HW_BEACON_BASE4 0x7200
1735#define HW_BEACON_BASE5 0x7400
1736#define HW_BEACON_BASE6 0x5dc0
1737#define HW_BEACON_BASE7 0x5bc0
1738
1739#define HW_BEACON_OFFSET(__index) \
1740 (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
1741 (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
1742 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
1743
1744/*
1745 * BBP registers.
1746 * The wordsize of the BBP is 8 bits.
1747 */
1748
1749/*
1750 * BBP 1: TX Antenna & Power Control
1751 * POWER_CTRL:
1752 * 0 - normal,
1753 * 1 - drop tx power by 6dBm,
1754 * 2 - drop tx power by 12dBm,
1755 * 3 - increase tx power by 6dBm
1756 */
1757#define BBP1_TX_POWER_CTRL FIELD8(0x07)
1758#define BBP1_TX_ANTENNA FIELD8(0x18)
1759
1760/*
1761 * BBP 3: RX Antenna
1762 */
1763#define BBP3_RX_ADC FIELD8(0x03)
1764#define BBP3_RX_ANTENNA FIELD8(0x18)
1765#define BBP3_HT40_MINUS FIELD8(0x20)
1766
1767/*
1768 * BBP 4: Bandwidth
1769 */
1770#define BBP4_TX_BF FIELD8(0x01)
1771#define BBP4_BANDWIDTH FIELD8(0x18)
1772#define BBP4_MAC_IF_CTRL FIELD8(0x40)
1773
1774/*
1775 * BBP 109
1776 */
1777#define BBP109_TX0_POWER FIELD8(0x0f)
1778#define BBP109_TX1_POWER FIELD8(0xf0)
1779
1780/*
1781 * BBP 138: Unknown
1782 */
1783#define BBP138_RX_ADC1 FIELD8(0x02)
1784#define BBP138_RX_ADC2 FIELD8(0x04)
1785#define BBP138_TX_DAC1 FIELD8(0x20)
1786#define BBP138_TX_DAC2 FIELD8(0x40)
1787
1788/*
1789 * BBP 152: Rx Ant
1790 */
1791#define BBP152_RX_DEFAULT_ANT FIELD8(0x80)
1792
1793/*
1794 * RFCSR registers
1795 * The wordsize of the RFCSR is 8 bits.
1796 */
1797
1798/*
1799 * RFCSR 1:
1800 */
1801#define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1802#define RFCSR1_PLL_PD FIELD8(0x02)
1803#define RFCSR1_RX0_PD FIELD8(0x04)
1804#define RFCSR1_TX0_PD FIELD8(0x08)
1805#define RFCSR1_RX1_PD FIELD8(0x10)
1806#define RFCSR1_TX1_PD FIELD8(0x20)
1807#define RFCSR1_RX2_PD FIELD8(0x40)
1808#define RFCSR1_TX2_PD FIELD8(0x80)
1809
1810/*
1811 * RFCSR 2:
1812 */
1813#define RFCSR2_RESCAL_EN FIELD8(0x80)
1814
1815/*
1816 * RFCSR 3:
1817 */
1818#define RFCSR3_K FIELD8(0x0f)
1819/* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */
1820#define RFCSR3_PA1_BIAS_CCK FIELD8(0x70);
1821#define RFCSR3_PA2_CASCODE_BIAS_CCKK FIELD8(0x80);
1822
1823/*
1824 * FRCSR 5:
1825 */
1826#define RFCSR5_R1 FIELD8(0x0c)
1827
1828/*
1829 * RFCSR 6:
1830 */
1831#define RFCSR6_R1 FIELD8(0x03)
1832#define RFCSR6_R2 FIELD8(0x40)
1833#define RFCSR6_TXDIV FIELD8(0x0c)
1834
1835/*
1836 * RFCSR 7:
1837 */
1838#define RFCSR7_RF_TUNING FIELD8(0x01)
1839#define RFCSR7_BIT1 FIELD8(0x02)
1840#define RFCSR7_BIT2 FIELD8(0x04)
1841#define RFCSR7_BIT3 FIELD8(0x08)
1842#define RFCSR7_BIT4 FIELD8(0x10)
1843#define RFCSR7_BIT5 FIELD8(0x20)
1844#define RFCSR7_BITS67 FIELD8(0xc0)
1845
1846/*
1847 * RFCSR 11:
1848 */
1849#define RFCSR11_R FIELD8(0x03)
1850
1851/*
1852 * RFCSR 12:
1853 */
1854#define RFCSR12_TX_POWER FIELD8(0x1f)
1855#define RFCSR12_DR0 FIELD8(0xe0)
1856
1857/*
1858 * RFCSR 13:
1859 */
1860#define RFCSR13_TX_POWER FIELD8(0x1f)
1861#define RFCSR13_DR0 FIELD8(0xe0)
1862
1863/*
1864 * RFCSR 15:
1865 */
1866#define RFCSR15_TX_LO2_EN FIELD8(0x08)
1867
1868/*
1869 * RFCSR 16:
1870 */
1871#define RFCSR16_TXMIXER_GAIN FIELD8(0x07)
1872
1873/*
1874 * RFCSR 17:
1875 */
1876#define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1877#define RFCSR17_TX_LO1_EN FIELD8(0x08)
1878#define RFCSR17_R FIELD8(0x20)
1879#define RFCSR17_CODE FIELD8(0x7f)
1880
1881/*
1882 * RFCSR 20:
1883 */
1884#define RFCSR20_RX_LO1_EN FIELD8(0x08)
1885
1886/*
1887 * RFCSR 21:
1888 */
1889#define RFCSR21_RX_LO2_EN FIELD8(0x08)
1890
1891/*
1892 * RFCSR 22:
1893 */
1894#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1895
1896/*
1897 * RFCSR 23:
1898 */
1899#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1900
1901/*
1902 * RFCSR 24:
1903 */
1904#define RFCSR24_TX_AGC_FC FIELD8(0x1f)
1905#define RFCSR24_TX_H20M FIELD8(0x20)
1906#define RFCSR24_TX_CALIB FIELD8(0x7f)
1907
1908/*
1909 * RFCSR 27:
1910 */
1911#define RFCSR27_R1 FIELD8(0x03)
1912#define RFCSR27_R2 FIELD8(0x04)
1913#define RFCSR27_R3 FIELD8(0x30)
1914#define RFCSR27_R4 FIELD8(0x40)
1915
1916/*
1917 * RFCSR 30:
1918 */
1919#define RFCSR30_TX_H20M FIELD8(0x02)
1920#define RFCSR30_RX_H20M FIELD8(0x04)
1921#define RFCSR30_RX_VCM FIELD8(0x18)
1922#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1923
1924/*
1925 * RFCSR 31:
1926 */
1927#define RFCSR31_RX_AGC_FC FIELD8(0x1f)
1928#define RFCSR31_RX_H20M FIELD8(0x20)
1929#define RFCSR31_RX_CALIB FIELD8(0x7f)
1930
1931/*
1932 * RFCSR 38:
1933 */
1934#define RFCSR38_RX_LO1_EN FIELD8(0x20)
1935
1936/*
1937 * RFCSR 39:
1938 */
1939#define RFCSR39_RX_LO2_EN FIELD8(0x80)
1940
1941/*
1942 * RFCSR 49:
1943 */
1944#define RFCSR49_TX FIELD8(0x3f)
1945
1946/*
1947 * RF registers
1948 */
1949
1950/*
1951 * RF 2
1952 */
1953#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1954#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1955#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1956
1957/*
1958 * RF 3
1959 */
1960#define RF3_TXPOWER_G FIELD32(0x00003e00)
1961#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1962#define RF3_TXPOWER_A FIELD32(0x00003c00)
1963
1964/*
1965 * RF 4
1966 */
1967#define RF4_TXPOWER_G FIELD32(0x000007c0)
1968#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1969#define RF4_TXPOWER_A FIELD32(0x00000780)
1970#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1971#define RF4_HT40 FIELD32(0x00200000)
1972
1973/*
1974 * EEPROM content.
1975 * The wordsize of the EEPROM is 16 bits.
1976 */
1977
1978/*
1979 * Chip ID
1980 */
1981#define EEPROM_CHIP_ID 0x0000
1982
1983/*
1984 * EEPROM Version
1985 */
1986#define EEPROM_VERSION 0x0001
1987#define EEPROM_VERSION_FAE FIELD16(0x00ff)
1988#define EEPROM_VERSION_VERSION FIELD16(0xff00)
1989
1990/*
1991 * HW MAC address.
1992 */
1993#define EEPROM_MAC_ADDR_0 0x0002
1994#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1995#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1996#define EEPROM_MAC_ADDR_1 0x0003
1997#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1998#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1999#define EEPROM_MAC_ADDR_2 0x0004
2000#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
2001#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
2002
2003/*
2004 * EEPROM NIC Configuration 0
2005 * RXPATH: 1: 1R, 2: 2R, 3: 3R
2006 * TXPATH: 1: 1T, 2: 2T, 3: 3T
2007 * RF_TYPE: RFIC type
2008 */
2009#define EEPROM_NIC_CONF0 0x001a
2010#define EEPROM_NIC_CONF0_RXPATH FIELD16(0x000f)
2011#define EEPROM_NIC_CONF0_TXPATH FIELD16(0x00f0)
2012#define EEPROM_NIC_CONF0_RF_TYPE FIELD16(0x0f00)
2013
2014/*
2015 * EEPROM NIC Configuration 1
2016 * HW_RADIO: 0: disable, 1: enable
2017 * EXTERNAL_TX_ALC: 0: disable, 1: enable
2018 * EXTERNAL_LNA_2G: 0: disable, 1: enable
2019 * EXTERNAL_LNA_5G: 0: disable, 1: enable
2020 * CARDBUS_ACCEL: 0: enable, 1: disable
2021 * BW40M_SB_2G: 0: disable, 1: enable
2022 * BW40M_SB_5G: 0: disable, 1: enable
2023 * WPS_PBC: 0: disable, 1: enable
2024 * BW40M_2G: 0: enable, 1: disable
2025 * BW40M_5G: 0: enable, 1: disable
2026 * BROADBAND_EXT_LNA: 0: disable, 1: enable
2027 * ANT_DIVERSITY: 00: Disable, 01: Diversity,
2028 * 10: Main antenna, 11: Aux antenna
2029 * INTERNAL_TX_ALC: 0: disable, 1: enable
2030 * BT_COEXIST: 0: disable, 1: enable
2031 * DAC_TEST: 0: disable, 1: enable
2032 */
2033#define EEPROM_NIC_CONF1 0x001b
2034#define EEPROM_NIC_CONF1_HW_RADIO FIELD16(0x0001)
2035#define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC FIELD16(0x0002)
2036#define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G FIELD16(0x0004)
2037#define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G FIELD16(0x0008)
2038#define EEPROM_NIC_CONF1_CARDBUS_ACCEL FIELD16(0x0010)
2039#define EEPROM_NIC_CONF1_BW40M_SB_2G FIELD16(0x0020)
2040#define EEPROM_NIC_CONF1_BW40M_SB_5G FIELD16(0x0040)
2041#define EEPROM_NIC_CONF1_WPS_PBC FIELD16(0x0080)
2042#define EEPROM_NIC_CONF1_BW40M_2G FIELD16(0x0100)
2043#define EEPROM_NIC_CONF1_BW40M_5G FIELD16(0x0200)
2044#define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA FIELD16(0x400)
2045#define EEPROM_NIC_CONF1_ANT_DIVERSITY FIELD16(0x1800)
2046#define EEPROM_NIC_CONF1_INTERNAL_TX_ALC FIELD16(0x2000)
2047#define EEPROM_NIC_CONF1_BT_COEXIST FIELD16(0x4000)
2048#define EEPROM_NIC_CONF1_DAC_TEST FIELD16(0x8000)
2049
2050/*
2051 * EEPROM frequency
2052 */
2053#define EEPROM_FREQ 0x001d
2054#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
2055#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
2056#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
2057
2058/*
2059 * EEPROM LED
2060 * POLARITY_RDY_G: Polarity RDY_G setting.
2061 * POLARITY_RDY_A: Polarity RDY_A setting.
2062 * POLARITY_ACT: Polarity ACT setting.
2063 * POLARITY_GPIO_0: Polarity GPIO0 setting.
2064 * POLARITY_GPIO_1: Polarity GPIO1 setting.
2065 * POLARITY_GPIO_2: Polarity GPIO2 setting.
2066 * POLARITY_GPIO_3: Polarity GPIO3 setting.
2067 * POLARITY_GPIO_4: Polarity GPIO4 setting.
2068 * LED_MODE: Led mode.
2069 */
2070#define EEPROM_LED_AG_CONF 0x001e
2071#define EEPROM_LED_ACT_CONF 0x001f
2072#define EEPROM_LED_POLARITY 0x0020
2073#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
2074#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
2075#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
2076#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
2077#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
2078#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
2079#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
2080#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
2081#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
2082
2083/*
2084 * EEPROM NIC Configuration 2
2085 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2086 * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
2087 * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
2088 */
2089#define EEPROM_NIC_CONF2 0x0021
2090#define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
2091#define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
2092#define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
2093
2094/*
2095 * EEPROM LNA
2096 */
2097#define EEPROM_LNA 0x0022
2098#define EEPROM_LNA_BG FIELD16(0x00ff)
2099#define EEPROM_LNA_A0 FIELD16(0xff00)
2100
2101/*
2102 * EEPROM RSSI BG offset
2103 */
2104#define EEPROM_RSSI_BG 0x0023
2105#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
2106#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
2107
2108/*
2109 * EEPROM RSSI BG2 offset
2110 */
2111#define EEPROM_RSSI_BG2 0x0024
2112#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
2113#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
2114
2115/*
2116 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
2117 */
2118#define EEPROM_TXMIXER_GAIN_BG 0x0024
2119#define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
2120
2121/*
2122 * EEPROM RSSI A offset
2123 */
2124#define EEPROM_RSSI_A 0x0025
2125#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
2126#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
2127
2128/*
2129 * EEPROM RSSI A2 offset
2130 */
2131#define EEPROM_RSSI_A2 0x0026
2132#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
2133#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
2134
2135/*
2136 * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2).
2137 */
2138#define EEPROM_TXMIXER_GAIN_A 0x0026
2139#define EEPROM_TXMIXER_GAIN_A_VAL FIELD16(0x0007)
2140
2141/*
2142 * EEPROM EIRP Maximum TX power values(unit: dbm)
2143 */
2144#define EEPROM_EIRP_MAX_TX_POWER 0x0027
2145#define EEPROM_EIRP_MAX_TX_POWER_2GHZ FIELD16(0x00ff)
2146#define EEPROM_EIRP_MAX_TX_POWER_5GHZ FIELD16(0xff00)
2147
2148/*
2149 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
2150 * This is delta in 40MHZ.
2151 * VALUE: Tx Power dalta value, MAX=4(unit: dbm)
2152 * TYPE: 1: Plus the delta value, 0: minus the delta value
2153 * ENABLE: enable tx power compensation for 40BW
2154 */
2155#define EEPROM_TXPOWER_DELTA 0x0028
2156#define EEPROM_TXPOWER_DELTA_VALUE_2G FIELD16(0x003f)
2157#define EEPROM_TXPOWER_DELTA_TYPE_2G FIELD16(0x0040)
2158#define EEPROM_TXPOWER_DELTA_ENABLE_2G FIELD16(0x0080)
2159#define EEPROM_TXPOWER_DELTA_VALUE_5G FIELD16(0x3f00)
2160#define EEPROM_TXPOWER_DELTA_TYPE_5G FIELD16(0x4000)
2161#define EEPROM_TXPOWER_DELTA_ENABLE_5G FIELD16(0x8000)
2162
2163/*
2164 * EEPROM TXPOWER 802.11BG
2165 */
2166#define EEPROM_TXPOWER_BG1 0x0029
2167#define EEPROM_TXPOWER_BG2 0x0030
2168#define EEPROM_TXPOWER_BG_SIZE 7
2169#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
2170#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
2171
2172/*
2173 * EEPROM temperature compensation boundaries 802.11BG
2174 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2175 * reduced by (agc_step * -4)
2176 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2177 * reduced by (agc_step * -3)
2178 */
2179#define EEPROM_TSSI_BOUND_BG1 0x0037
2180#define EEPROM_TSSI_BOUND_BG1_MINUS4 FIELD16(0x00ff)
2181#define EEPROM_TSSI_BOUND_BG1_MINUS3 FIELD16(0xff00)
2182
2183/*
2184 * EEPROM temperature compensation boundaries 802.11BG
2185 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2186 * reduced by (agc_step * -2)
2187 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2188 * reduced by (agc_step * -1)
2189 */
2190#define EEPROM_TSSI_BOUND_BG2 0x0038
2191#define EEPROM_TSSI_BOUND_BG2_MINUS2 FIELD16(0x00ff)
2192#define EEPROM_TSSI_BOUND_BG2_MINUS1 FIELD16(0xff00)
2193
2194/*
2195 * EEPROM temperature compensation boundaries 802.11BG
2196 * REF: Reference TSSI value, no tx power changes needed
2197 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2198 * increased by (agc_step * 1)
2199 */
2200#define EEPROM_TSSI_BOUND_BG3 0x0039
2201#define EEPROM_TSSI_BOUND_BG3_REF FIELD16(0x00ff)
2202#define EEPROM_TSSI_BOUND_BG3_PLUS1 FIELD16(0xff00)
2203
2204/*
2205 * EEPROM temperature compensation boundaries 802.11BG
2206 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2207 * increased by (agc_step * 2)
2208 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2209 * increased by (agc_step * 3)
2210 */
2211#define EEPROM_TSSI_BOUND_BG4 0x003a
2212#define EEPROM_TSSI_BOUND_BG4_PLUS2 FIELD16(0x00ff)
2213#define EEPROM_TSSI_BOUND_BG4_PLUS3 FIELD16(0xff00)
2214
2215/*
2216 * EEPROM temperature compensation boundaries 802.11BG
2217 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2218 * increased by (agc_step * 4)
2219 * AGC_STEP: Temperature compensation step.
2220 */
2221#define EEPROM_TSSI_BOUND_BG5 0x003b
2222#define EEPROM_TSSI_BOUND_BG5_PLUS4 FIELD16(0x00ff)
2223#define EEPROM_TSSI_BOUND_BG5_AGC_STEP FIELD16(0xff00)
2224
2225/*
2226 * EEPROM TXPOWER 802.11A
2227 */
2228#define EEPROM_TXPOWER_A1 0x003c
2229#define EEPROM_TXPOWER_A2 0x0053
2230#define EEPROM_TXPOWER_A_SIZE 6
2231#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
2232#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
2233
2234/*
2235 * EEPROM temperature compensation boundaries 802.11A
2236 * MINUS4: If the actual TSSI is below this boundary, tx power needs to be
2237 * reduced by (agc_step * -4)
2238 * MINUS3: If the actual TSSI is below this boundary, tx power needs to be
2239 * reduced by (agc_step * -3)
2240 */
2241#define EEPROM_TSSI_BOUND_A1 0x006a
2242#define EEPROM_TSSI_BOUND_A1_MINUS4 FIELD16(0x00ff)
2243#define EEPROM_TSSI_BOUND_A1_MINUS3 FIELD16(0xff00)
2244
2245/*
2246 * EEPROM temperature compensation boundaries 802.11A
2247 * MINUS2: If the actual TSSI is below this boundary, tx power needs to be
2248 * reduced by (agc_step * -2)
2249 * MINUS1: If the actual TSSI is below this boundary, tx power needs to be
2250 * reduced by (agc_step * -1)
2251 */
2252#define EEPROM_TSSI_BOUND_A2 0x006b
2253#define EEPROM_TSSI_BOUND_A2_MINUS2 FIELD16(0x00ff)
2254#define EEPROM_TSSI_BOUND_A2_MINUS1 FIELD16(0xff00)
2255
2256/*
2257 * EEPROM temperature compensation boundaries 802.11A
2258 * REF: Reference TSSI value, no tx power changes needed
2259 * PLUS1: If the actual TSSI is above this boundary, tx power needs to be
2260 * increased by (agc_step * 1)
2261 */
2262#define EEPROM_TSSI_BOUND_A3 0x006c
2263#define EEPROM_TSSI_BOUND_A3_REF FIELD16(0x00ff)
2264#define EEPROM_TSSI_BOUND_A3_PLUS1 FIELD16(0xff00)
2265
2266/*
2267 * EEPROM temperature compensation boundaries 802.11A
2268 * PLUS2: If the actual TSSI is above this boundary, tx power needs to be
2269 * increased by (agc_step * 2)
2270 * PLUS3: If the actual TSSI is above this boundary, tx power needs to be
2271 * increased by (agc_step * 3)
2272 */
2273#define EEPROM_TSSI_BOUND_A4 0x006d
2274#define EEPROM_TSSI_BOUND_A4_PLUS2 FIELD16(0x00ff)
2275#define EEPROM_TSSI_BOUND_A4_PLUS3 FIELD16(0xff00)
2276
2277/*
2278 * EEPROM temperature compensation boundaries 802.11A
2279 * PLUS4: If the actual TSSI is above this boundary, tx power needs to be
2280 * increased by (agc_step * 4)
2281 * AGC_STEP: Temperature compensation step.
2282 */
2283#define EEPROM_TSSI_BOUND_A5 0x006e
2284#define EEPROM_TSSI_BOUND_A5_PLUS4 FIELD16(0x00ff)
2285#define EEPROM_TSSI_BOUND_A5_AGC_STEP FIELD16(0xff00)
2286
2287/*
2288 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
2289 */
2290#define EEPROM_TXPOWER_BYRATE 0x006f
2291#define EEPROM_TXPOWER_BYRATE_SIZE 9
2292
2293#define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
2294#define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
2295#define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
2296#define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
2297
2298/*
2299 * EEPROM BBP.
2300 */
2301#define EEPROM_BBP_START 0x0078
2302#define EEPROM_BBP_SIZE 16
2303#define EEPROM_BBP_VALUE FIELD16(0x00ff)
2304#define EEPROM_BBP_REG_ID FIELD16(0xff00)
2305
2306/*
2307 * MCU mailbox commands.
2308 * MCU_SLEEP - go to power-save mode.
2309 * arg1: 1: save as much power as possible, 0: save less power.
2310 * status: 1: success, 2: already asleep,
2311 * 3: maybe MAC is busy so can't finish this task.
2312 * MCU_RADIO_OFF
2313 * arg0: 0: do power-saving, NOT turn off radio.
2314 */
2315#define MCU_SLEEP 0x30
2316#define MCU_WAKEUP 0x31
2317#define MCU_RADIO_OFF 0x35
2318#define MCU_CURRENT 0x36
2319#define MCU_LED 0x50
2320#define MCU_LED_STRENGTH 0x51
2321#define MCU_LED_AG_CONF 0x52
2322#define MCU_LED_ACT_CONF 0x53
2323#define MCU_LED_LED_POLARITY 0x54
2324#define MCU_RADAR 0x60
2325#define MCU_BOOT_SIGNAL 0x72
2326#define MCU_ANT_SELECT 0X73
2327#define MCU_BBP_SIGNAL 0x80
2328#define MCU_POWER_SAVE 0x83
2329#define MCU_BAND_SELECT 0x91
2330
2331/*
2332 * MCU mailbox tokens
2333 */
2334#define TOKEN_SLEEP 1
2335#define TOKEN_RADIO_OFF 2
2336#define TOKEN_WAKEUP 3
2337
2338
2339/*
2340 * DMA descriptor defines.
2341 */
2342#define TXWI_DESC_SIZE (4 * sizeof(__le32))
2343#define RXWI_DESC_SIZE (4 * sizeof(__le32))
2344
2345/*
2346 * TX WI structure
2347 */
2348
2349/*
2350 * Word0
2351 * FRAG: 1 To inform TKIP engine this is a fragment.
2352 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2353 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2354 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2355 * duplicate the frame to both channels).
2356 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2357 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2358 * aggregate consecutive frames with the same RA and QoS TID. If
2359 * a frame A with the same RA and QoS TID but AMPDU=0 is queued
2360 * directly after a frame B with AMPDU=1, frame A might still
2361 * get aggregated into the AMPDU started by frame B. So, setting
2362 * AMPDU to 0 does _not_ necessarily mean the frame is sent as
2363 * MPDU, it can still end up in an AMPDU if the previous frame
2364 * was tagged as AMPDU.
2365 */
2366#define TXWI_W0_FRAG FIELD32(0x00000001)
2367#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2368#define TXWI_W0_CF_ACK FIELD32(0x00000004)
2369#define TXWI_W0_TS FIELD32(0x00000008)
2370#define TXWI_W0_AMPDU FIELD32(0x00000010)
2371#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2372#define TXWI_W0_TX_OP FIELD32(0x00000300)
2373#define TXWI_W0_MCS FIELD32(0x007f0000)
2374#define TXWI_W0_BW FIELD32(0x00800000)
2375#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2376#define TXWI_W0_STBC FIELD32(0x06000000)
2377#define TXWI_W0_IFS FIELD32(0x08000000)
2378#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2379
2380/*
2381 * Word1
2382 * ACK: 0: No Ack needed, 1: Ack needed
2383 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2384 * BW_WIN_SIZE: BA windows size of the recipient
2385 * WIRELESS_CLI_ID: Client ID for WCID table access
2386 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2387 * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2388 * frame was processed. If multiple frames are aggregated together
2389 * (AMPDU==1) the reported tx status will always contain the packet
2390 * id of the first frame. 0: Don't report tx status for this frame.
2391 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2392 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2393 * This identification number is calculated by ((idx % 3) + 1).
2394 * The (+1) is required to prevent PACKETID to become 0.
2395 */
2396#define TXWI_W1_ACK FIELD32(0x00000001)
2397#define TXWI_W1_NSEQ FIELD32(0x00000002)
2398#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2399#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2400#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2401#define TXWI_W1_PACKETID FIELD32(0xf0000000)
2402#define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2403#define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2404
2405/*
2406 * Word2
2407 */
2408#define TXWI_W2_IV FIELD32(0xffffffff)
2409
2410/*
2411 * Word3
2412 */
2413#define TXWI_W3_EIV FIELD32(0xffffffff)
2414
2415/*
2416 * RX WI structure
2417 */
2418
2419/*
2420 * Word0
2421 */
2422#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2423#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2424#define RXWI_W0_BSSID FIELD32(0x00001c00)
2425#define RXWI_W0_UDF FIELD32(0x0000e000)
2426#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2427#define RXWI_W0_TID FIELD32(0xf0000000)
2428
2429/*
2430 * Word1
2431 */
2432#define RXWI_W1_FRAG FIELD32(0x0000000f)
2433#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2434#define RXWI_W1_MCS FIELD32(0x007f0000)
2435#define RXWI_W1_BW FIELD32(0x00800000)
2436#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2437#define RXWI_W1_STBC FIELD32(0x06000000)
2438#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2439
2440/*
2441 * Word2
2442 */
2443#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2444#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2445#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2446
2447/*
2448 * Word3
2449 */
2450#define RXWI_W3_SNR0 FIELD32(0x000000ff)
2451#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
2452
2453/*
2454 * Macros for converting txpower from EEPROM to mac80211 value
2455 * and from mac80211 value to register value.
2456 */
2457#define MIN_G_TXPOWER 0
2458#define MIN_A_TXPOWER -7
2459#define MAX_G_TXPOWER 31
2460#define MAX_A_TXPOWER 15
2461#define DEFAULT_TXPOWER 5
2462
2463#define TXPOWER_G_FROM_DEV(__txpower) \
2464 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2465
2466#define TXPOWER_G_TO_DEV(__txpower) \
2467 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
2468
2469#define TXPOWER_A_FROM_DEV(__txpower) \
2470 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2471
2472#define TXPOWER_A_TO_DEV(__txpower) \
2473 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2474
2475/*
2476 * Board's maximun TX power limitation
2477 */
2478#define EIRP_MAX_TX_POWER_LIMIT 0x50
2479
2480/*
2481 * Number of TBTT intervals after which we have to adjust
2482 * the hw beacon timer.
2483 */
2484#define BCN_TBTT_OFFSET 64
2485
2486/*
2487 * RT2800 driver data structure
2488 */
2489struct rt2800_drv_data {
2490 u8 calibration_bw20;
2491 u8 calibration_bw40;
2492 u8 bbp25;
2493 u8 bbp26;
2494 u8 txmixer_gain_24g;
2495 u8 txmixer_gain_5g;
2496 unsigned int tbtt_tick;
2497};
2498
2499#endif /* RT2800_H */