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1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
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21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
22 * USA
23 *
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
26 *
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *
31 * BSD LICENSE
32 *
33 * Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
34 * All rights reserved.
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44 * the documentation and/or other materials provided with the
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49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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62 *****************************************************************************/
63#ifndef __iwl_fh_h__
64#define __iwl_fh_h__
65
66#include <linux/types.h>
67
68/****************************/
69/* Flow Handler Definitions */
70/****************************/
71
72/**
73 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
74 * Addresses are offsets from device's PCI hardware base address.
75 */
76#define FH_MEM_LOWER_BOUND (0x1000)
77#define FH_MEM_UPPER_BOUND (0x2000)
78
79/**
80 * Keep-Warm (KW) buffer base address.
81 *
82 * Driver must allocate a 4KByte buffer that is for keeping the
83 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
84 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
85 * from going into a power-savings mode that would cause higher DRAM latency,
86 * and possible data over/under-runs, before all Tx/Rx is complete.
87 *
88 * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
89 * of the buffer, which must be 4K aligned. Once this is set up, the device
90 * automatically invokes keep-warm accesses when normal accesses might not
91 * be sufficient to maintain fast DRAM response.
92 *
93 * Bit fields:
94 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
95 */
96#define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
97
98
99/**
100 * TFD Circular Buffers Base (CBBC) addresses
101 *
102 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
103 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
104 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04
105 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
106 * aligned (address bits 0-7 must be 0).
107 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
108 * for them are in different places.
109 *
110 * Bit fields in each pointer register:
111 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
112 */
113#define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
114#define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
115#define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0)
116#define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
117#define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20)
118#define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80)
119
120/* Find TFD CB base pointer for given queue */
121static inline unsigned int FH_MEM_CBBC_QUEUE(unsigned int chnl)
122{
123 if (chnl < 16)
124 return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
125 if (chnl < 20)
126 return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
127 WARN_ON_ONCE(chnl >= 32);
128 return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
129}
130
131
132/**
133 * Rx SRAM Control and Status Registers (RSCSR)
134 *
135 * These registers provide handshake between driver and device for the Rx queue
136 * (this queue handles *all* command responses, notifications, Rx data, etc.
137 * sent from uCode to host driver). Unlike Tx, there is only one Rx
138 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
139 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
140 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
141 * mapping between RBDs and RBs.
142 *
143 * Driver must allocate host DRAM memory for the following, and set the
144 * physical address of each into device registers:
145 *
146 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
147 * entries (although any power of 2, up to 4096, is selectable by driver).
148 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
149 * (typically 4K, although 8K or 16K are also selectable by driver).
150 * Driver sets up RB size and number of RBDs in the CB via Rx config
151 * register FH_MEM_RCSR_CHNL0_CONFIG_REG.
152 *
153 * Bit fields within one RBD:
154 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
155 *
156 * Driver sets physical address [35:8] of base of RBD circular buffer
157 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
158 *
159 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
160 * (RBs) have been filled, via a "write pointer", actually the index of
161 * the RB's corresponding RBD within the circular buffer. Driver sets
162 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
163 *
164 * Bit fields in lower dword of Rx status buffer (upper dword not used
165 * by driver:
166 * 31-12: Not used by driver
167 * 11- 0: Index of last filled Rx buffer descriptor
168 * (device writes, driver reads this value)
169 *
170 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
171 * enter pointers to these RBs into contiguous RBD circular buffer entries,
172 * and update the device's "write" index register,
173 * FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
174 *
175 * This "write" index corresponds to the *next* RBD that the driver will make
176 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
177 * the circular buffer. This value should initially be 0 (before preparing any
178 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
179 * wrap back to 0 at the end of the circular buffer (but don't wrap before
180 * "read" index has advanced past 1! See below).
181 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
182 *
183 * As the device fills RBs (referenced from contiguous RBDs within the circular
184 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
185 * to tell the driver the index of the latest filled RBD. The driver must
186 * read this "read" index from DRAM after receiving an Rx interrupt from device
187 *
188 * The driver must also internally keep track of a third index, which is the
189 * next RBD to process. When receiving an Rx interrupt, driver should process
190 * all filled but unprocessed RBs up to, but not including, the RB
191 * corresponding to the "read" index. For example, if "read" index becomes "1",
192 * driver may process the RB pointed to by RBD 0. Depending on volume of
193 * traffic, there may be many RBs to process.
194 *
195 * If read index == write index, device thinks there is no room to put new data.
196 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
197 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
198 * and "read" indexes; that is, make sure that there are no more than 254
199 * buffers waiting to be filled.
200 */
201#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
202#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
203#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
204
205/**
206 * Physical base address of 8-byte Rx Status buffer.
207 * Bit fields:
208 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
209 */
210#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
211
212/**
213 * Physical base address of Rx Buffer Descriptor Circular Buffer.
214 * Bit fields:
215 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
216 */
217#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
218
219/**
220 * Rx write pointer (index, really!).
221 * Bit fields:
222 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
223 * NOTE: For 256-entry circular buffer, use only bits [7:0].
224 */
225#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
226#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
227
228
229/**
230 * Rx Config/Status Registers (RCSR)
231 * Rx Config Reg for channel 0 (only channel used)
232 *
233 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
234 * normal operation (see bit fields).
235 *
236 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
237 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for
238 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
239 *
240 * Bit fields:
241 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
242 * '10' operate normally
243 * 29-24: reserved
244 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
245 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
246 * 19-18: reserved
247 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
248 * '10' 12K, '11' 16K.
249 * 15-14: reserved
250 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
251 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
252 * typical value 0x10 (about 1/2 msec)
253 * 3- 0: reserved
254 */
255#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
256#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
257#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
258
259#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
260
261#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
262#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
263#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
264#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
265#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
266#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
267
268#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
269#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
270#define RX_RB_TIMEOUT (0x10)
271
272#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
273#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
274#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
275
276#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
277#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
278#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
279#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
280
281#define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
282#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
283#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
284
285/**
286 * Rx Shared Status Registers (RSSR)
287 *
288 * After stopping Rx DMA channel (writing 0 to
289 * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
290 * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
291 *
292 * Bit fields:
293 * 24: 1 = Channel 0 is idle
294 *
295 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
296 * contain default values that should not be altered by the driver.
297 */
298#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
299#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
300
301#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
302#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
303#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
304 (FH_MEM_RSSR_LOWER_BOUND + 0x008)
305
306#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
307
308#define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
309
310/* TFDB Area - TFDs buffer table */
311#define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
312#define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900)
313#define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958)
314#define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
315#define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
316
317/**
318 * Transmit DMA Channel Control/Status Registers (TCSR)
319 *
320 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
321 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
322 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
323 *
324 * To use a Tx DMA channel, driver must initialize its
325 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
326 *
327 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
328 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
329 *
330 * All other bits should be 0.
331 *
332 * Bit fields:
333 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
334 * '10' operate normally
335 * 29- 4: Reserved, set to "0"
336 * 3: Enable internal DMA requests (1, normal operation), disable (0)
337 * 2- 0: Reserved, set to "0"
338 */
339#define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
340#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60)
341
342/* Find Control/Status reg for given Tx DMA/FIFO channel */
343#define FH_TCSR_CHNL_NUM (8)
344
345/* TCSR: tx_config register values */
346#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
347 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
348#define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
349 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
350#define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
351 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
352
353#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
354#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
355
356#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
357#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
358
359#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
360#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
361#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
362
363#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
364#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
365#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
366
367#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
368#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
369#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
370
371#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
372#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
373#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
374
375#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
376#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
377
378/**
379 * Tx Shared Status Registers (TSSR)
380 *
381 * After stopping Tx DMA channel (writing 0 to
382 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
383 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
384 * (channel's buffers empty | no pending requests).
385 *
386 * Bit fields:
387 * 31-24: 1 = Channel buffers empty (channel 7:0)
388 * 23-16: 1 = No pending requests (channel 7:0)
389 */
390#define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0)
391#define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0)
392
393#define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010)
394
395/**
396 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
397 * 31: Indicates an address error when accessed to internal memory
398 * uCode/driver must write "1" in order to clear this flag
399 * 30: Indicates that Host did not send the expected number of dwords to FH
400 * uCode/driver must write "1" in order to clear this flag
401 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
402 * command was received from the scheduler while the TRB was already full
403 * with previous command
404 * uCode/driver must write "1" in order to clear this flag
405 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
406 * bit is set, it indicates that the FH has received a full indication
407 * from the RTC TxFIFO and the current value of the TxCredit counter was
408 * not equal to zero. This mean that the credit mechanism was not
409 * synchronized to the TxFIFO status
410 * uCode/driver must write "1" in order to clear this flag
411 */
412#define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018)
413
414#define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
415
416/* Tx service channels */
417#define FH_SRVC_CHNL (9)
418#define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8)
419#define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
420#define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
421 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
422
423#define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98)
424/* Instruct FH to increment the retry count of a packet when
425 * it is brought from the memory to TX-FIFO
426 */
427#define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
428
429#define RX_QUEUE_SIZE 256
430#define RX_QUEUE_MASK 255
431#define RX_QUEUE_SIZE_LOG 8
432
433/*
434 * RX related structures and functions
435 */
436#define RX_FREE_BUFFERS 64
437#define RX_LOW_WATERMARK 8
438
439/**
440 * struct iwl_rb_status - reseve buffer status
441 * host memory mapped FH registers
442 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
443 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
444 * @finished_rb_num [0:11] - Indicates the index of the current RB
445 * in which the last frame was written to
446 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
447 * which was transferred
448 */
449struct iwl_rb_status {
450 __le16 closed_rb_num;
451 __le16 closed_fr_num;
452 __le16 finished_rb_num;
453 __le16 finished_fr_nam;
454 __le32 __unused;
455} __packed;
456
457
458#define TFD_QUEUE_SIZE_MAX (256)
459#define TFD_QUEUE_SIZE_BC_DUP (64)
460#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
461#define IWL_TX_DMA_MASK DMA_BIT_MASK(36)
462#define IWL_NUM_OF_TBS 20
463
464static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr)
465{
466 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
467}
468/**
469 * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor
470 *
471 * This structure contains dma address and length of transmission address
472 *
473 * @lo: low [31:0] portion of the dma address of TX buffer
474 * every even is unaligned on 16 bit boundary
475 * @hi_n_len 0-3 [35:32] portion of dma
476 * 4-15 length of the tx buffer
477 */
478struct iwl_tfd_tb {
479 __le32 lo;
480 __le16 hi_n_len;
481} __packed;
482
483/**
484 * struct iwl_tfd
485 *
486 * Transmit Frame Descriptor (TFD)
487 *
488 * @ __reserved1[3] reserved
489 * @ num_tbs 0-4 number of active tbs
490 * 5 reserved
491 * 6-7 padding (not used)
492 * @ tbs[20] transmit frame buffer descriptors
493 * @ __pad padding
494 *
495 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
496 * Both driver and device share these circular buffers, each of which must be
497 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
498 *
499 * Driver must indicate the physical address of the base of each
500 * circular buffer via the FH_MEM_CBBC_QUEUE registers.
501 *
502 * Each TFD contains pointer/size information for up to 20 data buffers
503 * in host DRAM. These buffers collectively contain the (one) frame described
504 * by the TFD. Each buffer must be a single contiguous block of memory within
505 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
506 * of (4K - 4). The concatenates all of a TFD's buffers into a single
507 * Tx frame, up to 8 KBytes in size.
508 *
509 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
510 */
511struct iwl_tfd {
512 u8 __reserved1[3];
513 u8 num_tbs;
514 struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS];
515 __le32 __pad;
516} __packed;
517
518/* Keep Warm Size */
519#define IWL_KW_SIZE 0x1000 /* 4k */
520
521/* Fixed (non-configurable) rx data from phy */
522
523/**
524 * struct iwlagn_schedq_bc_tbl scheduler byte count table
525 * base physical address provided by SCD_DRAM_BASE_ADDR
526 * @tfd_offset 0-12 - tx command byte count
527 * 12-16 - station index
528 */
529struct iwlagn_scd_bc_tbl {
530 __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
531} __packed;
532
533#endif /* !__iwl_fh_h__ */