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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Broadcom UniMAC MDIO bus controller driver
4 *
5 * Copyright (C) 2014-2017 Broadcom
6 */
7
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/io.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_mdio.h>
15#include <linux/of_platform.h>
16#include <linux/phy.h>
17#include <linux/platform_data/mdio-bcm-unimac.h>
18#include <linux/platform_device.h>
19#include <linux/sched.h>
20
21#define MDIO_CMD 0x00
22#define MDIO_START_BUSY (1 << 29)
23#define MDIO_READ_FAIL (1 << 28)
24#define MDIO_RD (2 << 26)
25#define MDIO_WR (1 << 26)
26#define MDIO_PMD_SHIFT 21
27#define MDIO_PMD_MASK 0x1F
28#define MDIO_REG_SHIFT 16
29#define MDIO_REG_MASK 0x1F
30
31#define MDIO_CFG 0x04
32#define MDIO_C22 (1 << 0)
33#define MDIO_C45 0
34#define MDIO_CLK_DIV_SHIFT 4
35#define MDIO_CLK_DIV_MASK 0x3F
36#define MDIO_SUPP_PREAMBLE (1 << 12)
37
38struct unimac_mdio_priv {
39 struct mii_bus *mii_bus;
40 void __iomem *base;
41 int (*wait_func) (void *wait_func_data);
42 void *wait_func_data;
43 struct clk *clk;
44 u32 clk_freq;
45};
46
47static inline u32 unimac_mdio_readl(struct unimac_mdio_priv *priv, u32 offset)
48{
49 /* MIPS chips strapped for BE will automagically configure the
50 * peripheral registers for CPU-native byte order.
51 */
52 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
53 return __raw_readl(priv->base + offset);
54 else
55 return readl_relaxed(priv->base + offset);
56}
57
58static inline void unimac_mdio_writel(struct unimac_mdio_priv *priv, u32 val,
59 u32 offset)
60{
61 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
62 __raw_writel(val, priv->base + offset);
63 else
64 writel_relaxed(val, priv->base + offset);
65}
66
67static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)
68{
69 u32 reg;
70
71 reg = unimac_mdio_readl(priv, MDIO_CMD);
72 reg |= MDIO_START_BUSY;
73 unimac_mdio_writel(priv, reg, MDIO_CMD);
74}
75
76static int unimac_mdio_poll(void *wait_func_data)
77{
78 struct unimac_mdio_priv *priv = wait_func_data;
79 u32 val;
80
81 /*
82 * C22 transactions should take ~25 usec, will need to adjust
83 * if C45 support is added.
84 */
85 udelay(30);
86
87 return read_poll_timeout(unimac_mdio_readl, val, !(val & MDIO_START_BUSY),
88 2000, 100000, false, priv, MDIO_CMD);
89}
90
91static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
92{
93 struct unimac_mdio_priv *priv = bus->priv;
94 int ret;
95 u32 cmd;
96
97 /* Prepare the read operation */
98 cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
99 unimac_mdio_writel(priv, cmd, MDIO_CMD);
100
101 /* Start MDIO transaction */
102 unimac_mdio_start(priv);
103
104 ret = priv->wait_func(priv->wait_func_data);
105 if (ret)
106 return ret;
107
108 cmd = unimac_mdio_readl(priv, MDIO_CMD);
109
110 /* Some broken devices are known not to release the line during
111 * turn-around, e.g: Broadcom BCM53125 external switches, so check for
112 * that condition here and ignore the MDIO controller read failure
113 * indication.
114 */
115 if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL))
116 return -EIO;
117
118 return cmd & 0xffff;
119}
120
121static int unimac_mdio_write(struct mii_bus *bus, int phy_id,
122 int reg, u16 val)
123{
124 struct unimac_mdio_priv *priv = bus->priv;
125 u32 cmd;
126
127 /* Prepare the write operation */
128 cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
129 (reg << MDIO_REG_SHIFT) | (0xffff & val);
130 unimac_mdio_writel(priv, cmd, MDIO_CMD);
131
132 unimac_mdio_start(priv);
133
134 return priv->wait_func(priv->wait_func_data);
135}
136
137/* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
138 * their internal MDIO management controller making them fail to successfully
139 * be read from or written to for the first transaction. We insert a dummy
140 * BMSR read here to make sure that phy_get_device() and get_phy_id() can
141 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
142 * PHY device for this peripheral.
143 *
144 * Once the PHY driver is registered, we can workaround subsequent reads from
145 * there (e.g: during system-wide power management).
146 *
147 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
148 * therefore the right location to stick that workaround. Since we do not want
149 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
150 * Device Tree scan to limit the search area.
151 */
152static int unimac_mdio_reset(struct mii_bus *bus)
153{
154 struct device_node *np = bus->dev.of_node;
155 struct device_node *child;
156 u32 read_mask = 0;
157 int addr;
158
159 if (!np) {
160 read_mask = ~bus->phy_mask;
161 } else {
162 for_each_available_child_of_node(np, child) {
163 addr = of_mdio_parse_addr(&bus->dev, child);
164 if (addr < 0)
165 continue;
166
167 read_mask |= 1 << addr;
168 }
169 }
170
171 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
172 if (read_mask & 1 << addr) {
173 dev_dbg(&bus->dev, "Workaround for PHY @ %d\n", addr);
174 mdiobus_read(bus, addr, MII_BMSR);
175 }
176 }
177
178 return 0;
179}
180
181static void unimac_mdio_clk_set(struct unimac_mdio_priv *priv)
182{
183 unsigned long rate;
184 u32 reg, div;
185
186 /* Keep the hardware default values */
187 if (!priv->clk_freq)
188 return;
189
190 if (!priv->clk)
191 rate = 250000000;
192 else
193 rate = clk_get_rate(priv->clk);
194
195 div = (rate / (2 * priv->clk_freq)) - 1;
196 if (div & ~MDIO_CLK_DIV_MASK) {
197 pr_warn("Incorrect MDIO clock frequency, ignoring\n");
198 return;
199 }
200
201 /* The MDIO clock is the reference clock (typically 250Mhz) divided by
202 * 2 x (MDIO_CLK_DIV + 1)
203 */
204 reg = unimac_mdio_readl(priv, MDIO_CFG);
205 reg &= ~(MDIO_CLK_DIV_MASK << MDIO_CLK_DIV_SHIFT);
206 reg |= div << MDIO_CLK_DIV_SHIFT;
207 unimac_mdio_writel(priv, reg, MDIO_CFG);
208}
209
210static int unimac_mdio_probe(struct platform_device *pdev)
211{
212 struct unimac_mdio_pdata *pdata = pdev->dev.platform_data;
213 struct unimac_mdio_priv *priv;
214 struct device_node *np;
215 struct mii_bus *bus;
216 struct resource *r;
217 int ret;
218
219 np = pdev->dev.of_node;
220
221 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
222 if (!priv)
223 return -ENOMEM;
224
225 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
226 if (!r)
227 return -EINVAL;
228
229 /* Just ioremap, as this MDIO block is usually integrated into an
230 * Ethernet MAC controller register range
231 */
232 priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
233 if (!priv->base) {
234 dev_err(&pdev->dev, "failed to remap register\n");
235 return -ENOMEM;
236 }
237
238 priv->clk = devm_clk_get_optional(&pdev->dev, NULL);
239 if (IS_ERR(priv->clk))
240 return PTR_ERR(priv->clk);
241
242 ret = clk_prepare_enable(priv->clk);
243 if (ret)
244 return ret;
245
246 if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq))
247 priv->clk_freq = 0;
248
249 unimac_mdio_clk_set(priv);
250
251 priv->mii_bus = mdiobus_alloc();
252 if (!priv->mii_bus) {
253 ret = -ENOMEM;
254 goto out_clk_disable;
255 }
256
257 bus = priv->mii_bus;
258 bus->priv = priv;
259 if (pdata) {
260 bus->name = pdata->bus_name;
261 priv->wait_func = pdata->wait_func;
262 priv->wait_func_data = pdata->wait_func_data;
263 bus->phy_mask = ~pdata->phy_mask;
264 } else {
265 bus->name = "unimac MII bus";
266 priv->wait_func_data = priv;
267 priv->wait_func = unimac_mdio_poll;
268 }
269 bus->parent = &pdev->dev;
270 bus->read = unimac_mdio_read;
271 bus->write = unimac_mdio_write;
272 bus->reset = unimac_mdio_reset;
273 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id);
274
275 ret = of_mdiobus_register(bus, np);
276 if (ret) {
277 dev_err(&pdev->dev, "MDIO bus registration failed\n");
278 goto out_mdio_free;
279 }
280
281 platform_set_drvdata(pdev, priv);
282
283 dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus\n");
284
285 return 0;
286
287out_mdio_free:
288 mdiobus_free(bus);
289out_clk_disable:
290 clk_disable_unprepare(priv->clk);
291 return ret;
292}
293
294static void unimac_mdio_remove(struct platform_device *pdev)
295{
296 struct unimac_mdio_priv *priv = platform_get_drvdata(pdev);
297
298 mdiobus_unregister(priv->mii_bus);
299 mdiobus_free(priv->mii_bus);
300 clk_disable_unprepare(priv->clk);
301}
302
303static int __maybe_unused unimac_mdio_suspend(struct device *d)
304{
305 struct unimac_mdio_priv *priv = dev_get_drvdata(d);
306
307 clk_disable_unprepare(priv->clk);
308
309 return 0;
310}
311
312static int __maybe_unused unimac_mdio_resume(struct device *d)
313{
314 struct unimac_mdio_priv *priv = dev_get_drvdata(d);
315 int ret;
316
317 ret = clk_prepare_enable(priv->clk);
318 if (ret)
319 return ret;
320
321 unimac_mdio_clk_set(priv);
322
323 return 0;
324}
325
326static SIMPLE_DEV_PM_OPS(unimac_mdio_pm_ops,
327 unimac_mdio_suspend, unimac_mdio_resume);
328
329static const struct of_device_id unimac_mdio_ids[] = {
330 { .compatible = "brcm,asp-v2.1-mdio", },
331 { .compatible = "brcm,asp-v2.0-mdio", },
332 { .compatible = "brcm,genet-mdio-v5", },
333 { .compatible = "brcm,genet-mdio-v4", },
334 { .compatible = "brcm,genet-mdio-v3", },
335 { .compatible = "brcm,genet-mdio-v2", },
336 { .compatible = "brcm,genet-mdio-v1", },
337 { .compatible = "brcm,unimac-mdio", },
338 { /* sentinel */ },
339};
340MODULE_DEVICE_TABLE(of, unimac_mdio_ids);
341
342static struct platform_driver unimac_mdio_driver = {
343 .driver = {
344 .name = UNIMAC_MDIO_DRV_NAME,
345 .of_match_table = unimac_mdio_ids,
346 .pm = &unimac_mdio_pm_ops,
347 },
348 .probe = unimac_mdio_probe,
349 .remove_new = unimac_mdio_remove,
350};
351module_platform_driver(unimac_mdio_driver);
352
353MODULE_AUTHOR("Broadcom Corporation");
354MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller");
355MODULE_LICENSE("GPL");
356MODULE_ALIAS("platform:" UNIMAC_MDIO_DRV_NAME);