1/* SPDX-License-Identifier: GPL-2.0 */
 2/* Copyright(c) 1999 - 2018 Intel Corporation. */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 3
 4#ifndef _IXGBE_FCOE_H
 5#define _IXGBE_FCOE_H
 6
 7#include <scsi/fc/fc_fs.h>
 8#include <scsi/fc/fc_fcoe.h>
 9
10/* shift bits within STAT fo FCSTAT */
11#define IXGBE_RXDADV_FCSTAT_SHIFT	4
12
13/* ddp user buffer */
14#define IXGBE_BUFFCNT_MAX	256	/* 8 bits bufcnt */
15#define IXGBE_FCPTR_ALIGN	16
16#define IXGBE_FCPTR_MAX	(IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t))
17#define IXGBE_FCBUFF_4KB	0x0
18#define IXGBE_FCBUFF_8KB	0x1
19#define IXGBE_FCBUFF_16KB	0x2
20#define IXGBE_FCBUFF_64KB	0x3
21#define IXGBE_FCBUFF_MAX	65536	/* 64KB max */
22#define IXGBE_FCBUFF_MIN	4096	/* 4KB min */
23#define IXGBE_FCOE_DDP_MAX	512	/* 9 bits xid */
24#define IXGBE_FCOE_DDP_MAX_X550	2048	/* 11 bits xid */
25
26/* Default traffic class to use for FCoE */
27#define IXGBE_FCOE_DEFTC	3
28
29/* fcerr */
30#define IXGBE_FCERR_BADCRC       0x00100000
31
32/* FCoE DDP for target mode */
33#define __IXGBE_FCOE_TARGET	1
34
35struct ixgbe_fcoe_ddp {
36	int len;
37	u32 err;
38	unsigned int sgc;
39	struct scatterlist *sgl;
40	dma_addr_t udp;
41	u64 *udl;
42	struct dma_pool *pool;
43};
44
45/* per cpu variables */
46struct ixgbe_fcoe_ddp_pool {
47	struct dma_pool *pool;
48	u64 noddp;
49	u64 noddp_ext_buff;
50};
51
52struct ixgbe_fcoe {
53	struct ixgbe_fcoe_ddp_pool __percpu *ddp_pool;
54	atomic_t refcnt;
55	spinlock_t lock;
56	struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX_X550];
57	void *extra_ddp_buffer;
58	dma_addr_t extra_ddp_buffer_dma;
59	unsigned long mode;
 
 
 
60	u8 up;
 
61};
62
63#endif /* _IXGBE_FCOE_H */

 1/*******************************************************************************
 2
 3  Intel 10 Gigabit PCI Express Linux driver
 4  Copyright(c) 1999 - 2012 Intel Corporation.
 5
 6  This program is free software; you can redistribute it and/or modify it
 7  under the terms and conditions of the GNU General Public License,
 8  version 2, as published by the Free Software Foundation.
 9
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  more details.
14
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21
22  Contact Information:
23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_FCOE_H
29#define _IXGBE_FCOE_H
30
31#include <scsi/fc/fc_fs.h>
32#include <scsi/fc/fc_fcoe.h>
33
34/* shift bits within STAT fo FCSTAT */
35#define IXGBE_RXDADV_FCSTAT_SHIFT	4
36
37/* ddp user buffer */
38#define IXGBE_BUFFCNT_MAX	256	/* 8 bits bufcnt */
39#define IXGBE_FCPTR_ALIGN	16
40#define IXGBE_FCPTR_MAX	(IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t))
41#define IXGBE_FCBUFF_4KB	0x0
42#define IXGBE_FCBUFF_8KB	0x1
43#define IXGBE_FCBUFF_16KB	0x2
44#define IXGBE_FCBUFF_64KB	0x3
45#define IXGBE_FCBUFF_MAX	65536	/* 64KB max */
46#define IXGBE_FCBUFF_MIN	4096	/* 4KB min */
47#define IXGBE_FCOE_DDP_MAX	512	/* 9 bits xid */
 
48
49/* Default traffic class to use for FCoE */
50#define IXGBE_FCOE_DEFTC	3
51
52/* fcerr */
53#define IXGBE_FCERR_BADCRC       0x00100000
54
55/* FCoE DDP for target mode */
56#define __IXGBE_FCOE_TARGET	1
57
58struct ixgbe_fcoe_ddp {
59	int len;
60	u32 err;
61	unsigned int sgc;
62	struct scatterlist *sgl;
63	dma_addr_t udp;
64	u64 *udl;
65	struct pci_pool *pool;
 
 
 
 
 
 
 
66};
67
68struct ixgbe_fcoe {
69	struct pci_pool **pool;
70	atomic_t refcnt;
71	spinlock_t lock;
72	struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX];
73	unsigned char *extra_ddp_buffer;
74	dma_addr_t extra_ddp_buffer_dma;
75	unsigned long mode;
76	u64 __percpu *pcpu_noddp;
77	u64 __percpu *pcpu_noddp_ext_buff;
78#ifdef CONFIG_IXGBE_DCB
79	u8 up;
80#endif
81};
82
83#endif /* _IXGBE_FCOE_H */