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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#ifndef _IXGBE_COMMON_H_
5#define _IXGBE_COMMON_H_
6
7#include "ixgbe_type.h"
8#include "ixgbe.h"
9
10u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
11s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
12s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
13s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);
14s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
15s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
16 u32 pba_num_size);
17s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
18enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status);
19enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status);
20s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
21void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
22s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
23
24s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
25s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
26s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw);
27
28s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
29s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
30s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
31 u16 words, u16 *data);
32s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
33s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
34 u16 words, u16 *data);
35s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
36s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
37 u16 words, u16 *data);
38s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
39 u16 *data);
40s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
41 u16 words, u16 *data);
42s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
43s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
44 u16 *checksum_val);
45s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
46
47s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
48 u32 enable_addr);
49s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
50s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
51s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
52 struct net_device *netdev);
53s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
54s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
55s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw);
56s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw);
57s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
58s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);
59s32 ixgbe_setup_fc_generic(struct ixgbe_hw *);
60bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);
61void ixgbe_fc_autoneg(struct ixgbe_hw *hw);
62
63s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask);
64void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask);
65s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
66s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq);
68s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
69s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
70s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
71 u32 vind, bool vlan_on, bool vlvf_bypass);
72s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
73s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
74 ixgbe_link_speed *speed,
75 bool *link_up, bool link_up_wait_to_complete);
76s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
77 u16 *wwpn_prefix);
78
79s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);
80s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked);
81
82s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
83s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
84void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
85void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
86s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
87s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
88 u8 build, u8 ver, u16 len, const char *str);
89u8 ixgbe_calculate_checksum(u8 *buffer, u32 length);
90s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, void *, u32 length,
91 u32 timeout, bool return_data);
92s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 len, u32 timeout);
93s32 ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
94 u32 (*data)[FW_PHY_ACT_DATA_COUNT]);
95void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
96bool ixgbe_mng_present(struct ixgbe_hw *hw);
97bool ixgbe_mng_enabled(struct ixgbe_hw *hw);
98
99void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,
100 u32 headroom, int strategy);
101
102extern const u32 ixgbe_mvals_8259X[IXGBE_MVALS_IDX_LIMIT];
103
104#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
105#define IXGBE_EMC_INTERNAL_DATA 0x00
106#define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
107#define IXGBE_EMC_DIODE1_DATA 0x01
108#define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
109#define IXGBE_EMC_DIODE2_DATA 0x23
110#define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
111#define IXGBE_EMC_DIODE3_DATA 0x2A
112#define IXGBE_EMC_DIODE3_THERM_LIMIT 0x30
113
114s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);
115s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);
116void ixgbe_get_etk_id(struct ixgbe_hw *hw,
117 struct ixgbe_nvm_version *nvm_ver);
118void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw,
119 struct ixgbe_nvm_version *nvm_ver);
120void ixgbe_get_orom_version(struct ixgbe_hw *hw,
121 struct ixgbe_nvm_version *nvm_ver);
122void ixgbe_disable_rx_generic(struct ixgbe_hw *hw);
123void ixgbe_enable_rx_generic(struct ixgbe_hw *hw);
124s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
125 ixgbe_link_speed speed,
126 bool autoneg_wait_to_complete);
127void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw,
128 ixgbe_link_speed speed);
129
130#define IXGBE_FAILED_READ_RETRIES 5
131#define IXGBE_FAILED_READ_REG 0xffffffffU
132#define IXGBE_FAILED_READ_CFG_DWORD 0xffffffffU
133#define IXGBE_FAILED_READ_CFG_WORD 0xffffU
134
135u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg);
136void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value);
137
138static inline bool ixgbe_removed(void __iomem *addr)
139{
140 return unlikely(!addr);
141}
142
143static inline void ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 value)
144{
145 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
146
147 if (ixgbe_removed(reg_addr))
148 return;
149 writel(value, reg_addr + reg);
150}
151#define IXGBE_WRITE_REG(a, reg, value) ixgbe_write_reg((a), (reg), (value))
152
153#ifndef writeq
154#define writeq writeq
155static inline void writeq(u64 val, void __iomem *addr)
156{
157 writel((u32)val, addr);
158 writel((u32)(val >> 32), addr + 4);
159}
160#endif
161
162static inline void ixgbe_write_reg64(struct ixgbe_hw *hw, u32 reg, u64 value)
163{
164 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
165
166 if (ixgbe_removed(reg_addr))
167 return;
168 writeq(value, reg_addr + reg);
169}
170#define IXGBE_WRITE_REG64(a, reg, value) ixgbe_write_reg64((a), (reg), (value))
171
172u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg);
173#define IXGBE_READ_REG(a, reg) ixgbe_read_reg((a), (reg))
174
175#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) \
176 ixgbe_write_reg((a), (reg) + ((offset) << 2), (value))
177
178#define IXGBE_READ_REG_ARRAY(a, reg, offset) \
179 ixgbe_read_reg((a), (reg) + ((offset) << 2))
180
181#define IXGBE_WRITE_FLUSH(a) ixgbe_read_reg((a), IXGBE_STATUS)
182
183#define ixgbe_hw_to_netdev(hw) (((struct ixgbe_adapter *)(hw)->back)->netdev)
184
185#define hw_dbg(hw, format, arg...) \
186 netdev_dbg(ixgbe_hw_to_netdev(hw), format, ## arg)
187#define hw_err(hw, format, arg...) \
188 netdev_err(ixgbe_hw_to_netdev(hw), format, ## arg)
189#define e_dev_info(format, arg...) \
190 dev_info(&adapter->pdev->dev, format, ## arg)
191#define e_dev_warn(format, arg...) \
192 dev_warn(&adapter->pdev->dev, format, ## arg)
193#define e_dev_err(format, arg...) \
194 dev_err(&adapter->pdev->dev, format, ## arg)
195#define e_dev_notice(format, arg...) \
196 dev_notice(&adapter->pdev->dev, format, ## arg)
197#define e_info(msglvl, format, arg...) \
198 netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
199#define e_err(msglvl, format, arg...) \
200 netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
201#define e_warn(msglvl, format, arg...) \
202 netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
203#define e_crit(msglvl, format, arg...) \
204 netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
205#endif /* IXGBE_COMMON */
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_COMMON_H_
29#define _IXGBE_COMMON_H_
30
31#include "ixgbe_type.h"
32#include "ixgbe.h"
33
34u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
35s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
36s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
37s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
38s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw);
39s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
40s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
41 u32 pba_num_size);
42s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
43s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
44void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
45s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw);
46
47s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);
48s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);
49
50s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);
51s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
52s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
53 u16 words, u16 *data);
54s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
55s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
58s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
61 u16 *data);
62s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
63 u16 words, u16 *data);
64u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
65s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
66 u16 *checksum_val);
67s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
68
69s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
70 u32 enable_addr);
71s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index);
72s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw);
73s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
74 struct net_device *netdev);
75s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw);
76s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw);
77s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw);
78s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw);
79s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval);
80s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw);
81void ixgbe_fc_autoneg(struct ixgbe_hw *hw);
82
83s32 ixgbe_validate_mac_addr(u8 *mac_addr);
84s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);
85void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);
86s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);
87s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
88s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
89s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw);
90s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan,
91 u32 vind, bool vlan_on);
92s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
93s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
94 ixgbe_link_speed *speed,
95 bool *link_up, bool link_up_wait_to_complete);
96s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
97 u16 *wwpn_prefix);
98s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
99s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
100void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);
101void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
102s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps);
103s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
104 u8 build, u8 ver);
105void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
106
107void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb,
108 u32 headroom, int strategy);
109
110#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
111#define IXGBE_EMC_INTERNAL_DATA 0x00
112#define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
113#define IXGBE_EMC_DIODE1_DATA 0x01
114#define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
115#define IXGBE_EMC_DIODE2_DATA 0x23
116#define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
117#define IXGBE_EMC_DIODE3_DATA 0x2A
118#define IXGBE_EMC_DIODE3_THERM_LIMIT 0x30
119
120s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw);
121s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);
122
123#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
124
125#ifndef writeq
126#define writeq(val, addr) writel((u32) (val), addr); \
127 writel((u32) (val >> 32), (addr + 4));
128#endif
129
130#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
131
132#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
133
134#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) (\
135 writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
136
137#define IXGBE_READ_REG_ARRAY(a, reg, offset) (\
138 readl((a)->hw_addr + (reg) + ((offset) << 2)))
139
140#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
141
142#define hw_dbg(hw, format, arg...) \
143 netdev_dbg(((struct ixgbe_adapter *)(hw->back))->netdev, format, ##arg)
144#define e_dev_info(format, arg...) \
145 dev_info(&adapter->pdev->dev, format, ## arg)
146#define e_dev_warn(format, arg...) \
147 dev_warn(&adapter->pdev->dev, format, ## arg)
148#define e_dev_err(format, arg...) \
149 dev_err(&adapter->pdev->dev, format, ## arg)
150#define e_dev_notice(format, arg...) \
151 dev_notice(&adapter->pdev->dev, format, ## arg)
152#define e_info(msglvl, format, arg...) \
153 netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
154#define e_err(msglvl, format, arg...) \
155 netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
156#define e_warn(msglvl, format, arg...) \
157 netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
158#define e_crit(msglvl, format, arg...) \
159 netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
160#endif /* IXGBE_COMMON */