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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2017 Free Electrons
4 * Copyright (C) 2017 NextThing Co
5 *
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
7 */
8
9#include <linux/sizes.h>
10#include <linux/slab.h>
11
12#include "internals.h"
13
14#define NAND_HYNIX_CMD_SET_PARAMS 0x36
15#define NAND_HYNIX_CMD_APPLY_PARAMS 0x16
16
17#define NAND_HYNIX_1XNM_RR_REPEAT 8
18
19/**
20 * struct hynix_read_retry - read-retry data
21 * @nregs: number of register to set when applying a new read-retry mode
22 * @regs: register offsets (NAND chip dependent)
23 * @values: array of values to set in registers. The array size is equal to
24 * (nregs * nmodes)
25 */
26struct hynix_read_retry {
27 int nregs;
28 const u8 *regs;
29 u8 values[];
30};
31
32/**
33 * struct hynix_nand - private Hynix NAND struct
34 * @nand_technology: manufacturing process expressed in picometer
35 * @read_retry: read-retry information
36 */
37struct hynix_nand {
38 const struct hynix_read_retry *read_retry;
39};
40
41/**
42 * struct hynix_read_retry_otp - structure describing how the read-retry OTP
43 * area
44 * @nregs: number of hynix private registers to set before reading the reading
45 * the OTP area
46 * @regs: registers that should be configured
47 * @values: values that should be set in regs
48 * @page: the address to pass to the READ_PAGE command. Depends on the NAND
49 * chip
50 * @size: size of the read-retry OTP section
51 */
52struct hynix_read_retry_otp {
53 int nregs;
54 const u8 *regs;
55 const u8 *values;
56 int page;
57 int size;
58};
59
60static bool hynix_nand_has_valid_jedecid(struct nand_chip *chip)
61{
62 u8 jedecid[5] = { };
63 int ret;
64
65 ret = nand_readid_op(chip, 0x40, jedecid, sizeof(jedecid));
66 if (ret)
67 return false;
68
69 return !strncmp("JEDEC", jedecid, sizeof(jedecid));
70}
71
72static int hynix_nand_cmd_op(struct nand_chip *chip, u8 cmd)
73{
74 if (nand_has_exec_op(chip)) {
75 struct nand_op_instr instrs[] = {
76 NAND_OP_CMD(cmd, 0),
77 };
78 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
79
80 return nand_exec_op(chip, &op);
81 }
82
83 chip->legacy.cmdfunc(chip, cmd, -1, -1);
84
85 return 0;
86}
87
88static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val)
89{
90 u16 column = ((u16)addr << 8) | addr;
91
92 if (nand_has_exec_op(chip)) {
93 struct nand_op_instr instrs[] = {
94 NAND_OP_ADDR(1, &addr, 0),
95 NAND_OP_8BIT_DATA_OUT(1, &val, 0),
96 };
97 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs);
98
99 return nand_exec_op(chip, &op);
100 }
101
102 chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1);
103 chip->legacy.write_byte(chip, val);
104
105 return 0;
106}
107
108static int hynix_nand_setup_read_retry(struct nand_chip *chip, int retry_mode)
109{
110 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
111 const u8 *values;
112 int i, ret;
113
114 values = hynix->read_retry->values +
115 (retry_mode * hynix->read_retry->nregs);
116
117 /* Enter 'Set Hynix Parameters' mode */
118 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
119 if (ret)
120 return ret;
121
122 /*
123 * Configure the NAND in the requested read-retry mode.
124 * This is done by setting pre-defined values in internal NAND
125 * registers.
126 *
127 * The set of registers is NAND specific, and the values are either
128 * predefined or extracted from an OTP area on the NAND (values are
129 * probably tweaked at production in this case).
130 */
131 for (i = 0; i < hynix->read_retry->nregs; i++) {
132 ret = hynix_nand_reg_write_op(chip, hynix->read_retry->regs[i],
133 values[i]);
134 if (ret)
135 return ret;
136 }
137
138 /* Apply the new settings. */
139 return hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
140}
141
142/**
143 * hynix_get_majority - get the value that is occurring the most in a given
144 * set of values
145 * @in: the array of values to test
146 * @repeat: the size of the in array
147 * @out: pointer used to store the output value
148 *
149 * This function implements the 'majority check' logic that is supposed to
150 * overcome the unreliability of MLC NANDs when reading the OTP area storing
151 * the read-retry parameters.
152 *
153 * It's based on a pretty simple assumption: if we repeat the same value
154 * several times and then take the one that is occurring the most, we should
155 * find the correct value.
156 * Let's hope this dummy algorithm prevents us from losing the read-retry
157 * parameters.
158 */
159static int hynix_get_majority(const u8 *in, int repeat, u8 *out)
160{
161 int i, j, half = repeat / 2;
162
163 /*
164 * We only test the first half of the in array because we must ensure
165 * that the value is at least occurring repeat / 2 times.
166 *
167 * This loop is suboptimal since we may count the occurrences of the
168 * same value several time, but we are doing that on small sets, which
169 * makes it acceptable.
170 */
171 for (i = 0; i < half; i++) {
172 int cnt = 0;
173 u8 val = in[i];
174
175 /* Count all values that are matching the one at index i. */
176 for (j = i + 1; j < repeat; j++) {
177 if (in[j] == val)
178 cnt++;
179 }
180
181 /* We found a value occurring more than repeat / 2. */
182 if (cnt > half) {
183 *out = val;
184 return 0;
185 }
186 }
187
188 return -EIO;
189}
190
191static int hynix_read_rr_otp(struct nand_chip *chip,
192 const struct hynix_read_retry_otp *info,
193 void *buf)
194{
195 int i, ret;
196
197 ret = nand_reset_op(chip);
198 if (ret)
199 return ret;
200
201 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
202 if (ret)
203 return ret;
204
205 for (i = 0; i < info->nregs; i++) {
206 ret = hynix_nand_reg_write_op(chip, info->regs[i],
207 info->values[i]);
208 if (ret)
209 return ret;
210 }
211
212 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
213 if (ret)
214 return ret;
215
216 /* Sequence to enter OTP mode? */
217 ret = hynix_nand_cmd_op(chip, 0x17);
218 if (ret)
219 return ret;
220
221 ret = hynix_nand_cmd_op(chip, 0x4);
222 if (ret)
223 return ret;
224
225 ret = hynix_nand_cmd_op(chip, 0x19);
226 if (ret)
227 return ret;
228
229 /* Now read the page */
230 ret = nand_read_page_op(chip, info->page, 0, buf, info->size);
231 if (ret)
232 return ret;
233
234 /* Put everything back to normal */
235 ret = nand_reset_op(chip);
236 if (ret)
237 return ret;
238
239 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS);
240 if (ret)
241 return ret;
242
243 ret = hynix_nand_reg_write_op(chip, 0x38, 0);
244 if (ret)
245 return ret;
246
247 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS);
248 if (ret)
249 return ret;
250
251 return nand_read_page_op(chip, 0, 0, NULL, 0);
252}
253
254#define NAND_HYNIX_1XNM_RR_COUNT_OFFS 0
255#define NAND_HYNIX_1XNM_RR_REG_COUNT_OFFS 8
256#define NAND_HYNIX_1XNM_RR_SET_OFFS(x, setsize, inv) \
257 (16 + ((((x) * 2) + ((inv) ? 1 : 0)) * (setsize)))
258
259static int hynix_mlc_1xnm_rr_value(const u8 *buf, int nmodes, int nregs,
260 int mode, int reg, bool inv, u8 *val)
261{
262 u8 tmp[NAND_HYNIX_1XNM_RR_REPEAT];
263 int val_offs = (mode * nregs) + reg;
264 int set_size = nmodes * nregs;
265 int i, ret;
266
267 for (i = 0; i < NAND_HYNIX_1XNM_RR_REPEAT; i++) {
268 int set_offs = NAND_HYNIX_1XNM_RR_SET_OFFS(i, set_size, inv);
269
270 tmp[i] = buf[val_offs + set_offs];
271 }
272
273 ret = hynix_get_majority(tmp, NAND_HYNIX_1XNM_RR_REPEAT, val);
274 if (ret)
275 return ret;
276
277 if (inv)
278 *val = ~*val;
279
280 return 0;
281}
282
283static u8 hynix_1xnm_mlc_read_retry_regs[] = {
284 0xcc, 0xbf, 0xaa, 0xab, 0xcd, 0xad, 0xae, 0xaf
285};
286
287static int hynix_mlc_1xnm_rr_init(struct nand_chip *chip,
288 const struct hynix_read_retry_otp *info)
289{
290 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
291 struct hynix_read_retry *rr = NULL;
292 int ret, i, j;
293 u8 nregs, nmodes;
294 u8 *buf;
295
296 buf = kmalloc(info->size, GFP_KERNEL);
297 if (!buf)
298 return -ENOMEM;
299
300 ret = hynix_read_rr_otp(chip, info, buf);
301 if (ret)
302 goto out;
303
304 ret = hynix_get_majority(buf, NAND_HYNIX_1XNM_RR_REPEAT,
305 &nmodes);
306 if (ret)
307 goto out;
308
309 ret = hynix_get_majority(buf + NAND_HYNIX_1XNM_RR_REPEAT,
310 NAND_HYNIX_1XNM_RR_REPEAT,
311 &nregs);
312 if (ret)
313 goto out;
314
315 rr = kzalloc(sizeof(*rr) + (nregs * nmodes), GFP_KERNEL);
316 if (!rr) {
317 ret = -ENOMEM;
318 goto out;
319 }
320
321 for (i = 0; i < nmodes; i++) {
322 for (j = 0; j < nregs; j++) {
323 u8 *val = rr->values + (i * nregs);
324
325 ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j,
326 false, val);
327 if (!ret)
328 continue;
329
330 ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j,
331 true, val);
332 if (ret)
333 goto out;
334 }
335 }
336
337 rr->nregs = nregs;
338 rr->regs = hynix_1xnm_mlc_read_retry_regs;
339 hynix->read_retry = rr;
340 chip->ops.setup_read_retry = hynix_nand_setup_read_retry;
341 chip->read_retries = nmodes;
342
343out:
344 kfree(buf);
345
346 if (ret)
347 kfree(rr);
348
349 return ret;
350}
351
352static const u8 hynix_mlc_1xnm_rr_otp_regs[] = { 0x38 };
353static const u8 hynix_mlc_1xnm_rr_otp_values[] = { 0x52 };
354
355static const struct hynix_read_retry_otp hynix_mlc_1xnm_rr_otps[] = {
356 {
357 .nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs),
358 .regs = hynix_mlc_1xnm_rr_otp_regs,
359 .values = hynix_mlc_1xnm_rr_otp_values,
360 .page = 0x21f,
361 .size = 784
362 },
363 {
364 .nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs),
365 .regs = hynix_mlc_1xnm_rr_otp_regs,
366 .values = hynix_mlc_1xnm_rr_otp_values,
367 .page = 0x200,
368 .size = 528,
369 },
370};
371
372static int hynix_nand_rr_init(struct nand_chip *chip)
373{
374 int i, ret = 0;
375 bool valid_jedecid;
376
377 valid_jedecid = hynix_nand_has_valid_jedecid(chip);
378
379 /*
380 * We only support read-retry for 1xnm NANDs, and those NANDs all
381 * expose a valid JEDEC ID.
382 */
383 if (valid_jedecid) {
384 u8 nand_tech = chip->id.data[5] >> 4;
385
386 /* 1xnm technology */
387 if (nand_tech == 4) {
388 for (i = 0; i < ARRAY_SIZE(hynix_mlc_1xnm_rr_otps);
389 i++) {
390 /*
391 * FIXME: Hynix recommend to copy the
392 * read-retry OTP area into a normal page.
393 */
394 ret = hynix_mlc_1xnm_rr_init(chip,
395 hynix_mlc_1xnm_rr_otps);
396 if (!ret)
397 break;
398 }
399 }
400 }
401
402 if (ret)
403 pr_warn("failed to initialize read-retry infrastructure");
404
405 return 0;
406}
407
408static void hynix_nand_extract_oobsize(struct nand_chip *chip,
409 bool valid_jedecid)
410{
411 struct mtd_info *mtd = nand_to_mtd(chip);
412 struct nand_memory_organization *memorg;
413 u8 oobsize;
414
415 memorg = nanddev_get_memorg(&chip->base);
416
417 oobsize = ((chip->id.data[3] >> 2) & 0x3) |
418 ((chip->id.data[3] >> 4) & 0x4);
419
420 if (valid_jedecid) {
421 switch (oobsize) {
422 case 0:
423 memorg->oobsize = 2048;
424 break;
425 case 1:
426 memorg->oobsize = 1664;
427 break;
428 case 2:
429 memorg->oobsize = 1024;
430 break;
431 case 3:
432 memorg->oobsize = 640;
433 break;
434 default:
435 /*
436 * We should never reach this case, but if that
437 * happens, this probably means Hynix decided to use
438 * a different extended ID format, and we should find
439 * a way to support it.
440 */
441 WARN(1, "Invalid OOB size");
442 break;
443 }
444 } else {
445 switch (oobsize) {
446 case 0:
447 memorg->oobsize = 128;
448 break;
449 case 1:
450 memorg->oobsize = 224;
451 break;
452 case 2:
453 memorg->oobsize = 448;
454 break;
455 case 3:
456 memorg->oobsize = 64;
457 break;
458 case 4:
459 memorg->oobsize = 32;
460 break;
461 case 5:
462 memorg->oobsize = 16;
463 break;
464 case 6:
465 memorg->oobsize = 640;
466 break;
467 default:
468 /*
469 * We should never reach this case, but if that
470 * happens, this probably means Hynix decided to use
471 * a different extended ID format, and we should find
472 * a way to support it.
473 */
474 WARN(1, "Invalid OOB size");
475 break;
476 }
477
478 /*
479 * The datasheet of H27UCG8T2BTR mentions that the "Redundant
480 * Area Size" is encoded "per 8KB" (page size). This chip uses
481 * a page size of 16KiB. The datasheet mentions an OOB size of
482 * 1.280 bytes, but the OOB size encoded in the ID bytes (using
483 * the existing logic above) is 640 bytes.
484 * Update the OOB size for this chip by taking the value
485 * determined above and scaling it to the actual page size (so
486 * the actual OOB size for this chip is: 640 * 16k / 8k).
487 */
488 if (chip->id.data[1] == 0xde)
489 memorg->oobsize *= memorg->pagesize / SZ_8K;
490 }
491
492 mtd->oobsize = memorg->oobsize;
493}
494
495static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip,
496 bool valid_jedecid)
497{
498 struct nand_device *base = &chip->base;
499 struct nand_ecc_props requirements = {};
500 u8 ecc_level = (chip->id.data[4] >> 4) & 0x7;
501
502 if (valid_jedecid) {
503 /* Reference: H27UCG8T2E datasheet */
504 requirements.step_size = 1024;
505
506 switch (ecc_level) {
507 case 0:
508 requirements.step_size = 0;
509 requirements.strength = 0;
510 break;
511 case 1:
512 requirements.strength = 4;
513 break;
514 case 2:
515 requirements.strength = 24;
516 break;
517 case 3:
518 requirements.strength = 32;
519 break;
520 case 4:
521 requirements.strength = 40;
522 break;
523 case 5:
524 requirements.strength = 50;
525 break;
526 case 6:
527 requirements.strength = 60;
528 break;
529 default:
530 /*
531 * We should never reach this case, but if that
532 * happens, this probably means Hynix decided to use
533 * a different extended ID format, and we should find
534 * a way to support it.
535 */
536 WARN(1, "Invalid ECC requirements");
537 }
538 } else {
539 /*
540 * The ECC requirements field meaning depends on the
541 * NAND technology.
542 */
543 u8 nand_tech = chip->id.data[5] & 0x7;
544
545 if (nand_tech < 3) {
546 /* > 26nm, reference: H27UBG8T2A datasheet */
547 if (ecc_level < 5) {
548 requirements.step_size = 512;
549 requirements.strength = 1 << ecc_level;
550 } else if (ecc_level < 7) {
551 if (ecc_level == 5)
552 requirements.step_size = 2048;
553 else
554 requirements.step_size = 1024;
555 requirements.strength = 24;
556 } else {
557 /*
558 * We should never reach this case, but if that
559 * happens, this probably means Hynix decided
560 * to use a different extended ID format, and
561 * we should find a way to support it.
562 */
563 WARN(1, "Invalid ECC requirements");
564 }
565 } else {
566 /* <= 26nm, reference: H27UBG8T2B datasheet */
567 if (!ecc_level) {
568 requirements.step_size = 0;
569 requirements.strength = 0;
570 } else if (ecc_level < 5) {
571 requirements.step_size = 512;
572 requirements.strength = 1 << (ecc_level - 1);
573 } else {
574 requirements.step_size = 1024;
575 requirements.strength = 24 +
576 (8 * (ecc_level - 5));
577 }
578 }
579 }
580
581 nanddev_set_ecc_requirements(base, &requirements);
582}
583
584static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,
585 bool valid_jedecid)
586{
587 u8 nand_tech;
588
589 /* We need scrambling on all TLC NANDs*/
590 if (nanddev_bits_per_cell(&chip->base) > 2)
591 chip->options |= NAND_NEED_SCRAMBLING;
592
593 /* And on MLC NANDs with sub-3xnm process */
594 if (valid_jedecid) {
595 nand_tech = chip->id.data[5] >> 4;
596
597 /* < 3xnm */
598 if (nand_tech > 0)
599 chip->options |= NAND_NEED_SCRAMBLING;
600 } else {
601 nand_tech = chip->id.data[5] & 0x7;
602
603 /* < 32nm */
604 if (nand_tech > 2)
605 chip->options |= NAND_NEED_SCRAMBLING;
606 }
607}
608
609static void hynix_nand_decode_id(struct nand_chip *chip)
610{
611 struct mtd_info *mtd = nand_to_mtd(chip);
612 struct nand_memory_organization *memorg;
613 bool valid_jedecid;
614 u8 tmp;
615
616 memorg = nanddev_get_memorg(&chip->base);
617
618 /*
619 * Exclude all SLC NANDs from this advanced detection scheme.
620 * According to the ranges defined in several datasheets, it might
621 * appear that even SLC NANDs could fall in this extended ID scheme.
622 * If that the case rework the test to let SLC NANDs go through the
623 * detection process.
624 */
625 if (chip->id.len < 6 || nand_is_slc(chip)) {
626 nand_decode_ext_id(chip);
627 return;
628 }
629
630 /* Extract pagesize */
631 memorg->pagesize = 2048 << (chip->id.data[3] & 0x03);
632 mtd->writesize = memorg->pagesize;
633
634 tmp = (chip->id.data[3] >> 4) & 0x3;
635 /*
636 * When bit7 is set that means we start counting at 1MiB, otherwise
637 * we start counting at 128KiB and shift this value the content of
638 * ID[3][4:5].
639 * The only exception is when ID[3][4:5] == 3 and ID[3][7] == 0, in
640 * this case the erasesize is set to 768KiB.
641 */
642 if (chip->id.data[3] & 0x80) {
643 memorg->pages_per_eraseblock = (SZ_1M << tmp) /
644 memorg->pagesize;
645 mtd->erasesize = SZ_1M << tmp;
646 } else if (tmp == 3) {
647 memorg->pages_per_eraseblock = (SZ_512K + SZ_256K) /
648 memorg->pagesize;
649 mtd->erasesize = SZ_512K + SZ_256K;
650 } else {
651 memorg->pages_per_eraseblock = (SZ_128K << tmp) /
652 memorg->pagesize;
653 mtd->erasesize = SZ_128K << tmp;
654 }
655
656 /*
657 * Modern Toggle DDR NANDs have a valid JEDECID even though they are
658 * not exposing a valid JEDEC parameter table.
659 * These NANDs use a different NAND ID scheme.
660 */
661 valid_jedecid = hynix_nand_has_valid_jedecid(chip);
662
663 hynix_nand_extract_oobsize(chip, valid_jedecid);
664 hynix_nand_extract_ecc_requirements(chip, valid_jedecid);
665 hynix_nand_extract_scrambling_requirements(chip, valid_jedecid);
666}
667
668static void hynix_nand_cleanup(struct nand_chip *chip)
669{
670 struct hynix_nand *hynix = nand_get_manufacturer_data(chip);
671
672 if (!hynix)
673 return;
674
675 kfree(hynix->read_retry);
676 kfree(hynix);
677 nand_set_manufacturer_data(chip, NULL);
678}
679
680static int
681h27ucg8t2atrbc_choose_interface_config(struct nand_chip *chip,
682 struct nand_interface_config *iface)
683{
684 onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4);
685
686 return nand_choose_best_sdr_timings(chip, iface, NULL);
687}
688
689static int h27ucg8t2etrbc_init(struct nand_chip *chip)
690{
691 struct mtd_info *mtd = nand_to_mtd(chip);
692
693 chip->options |= NAND_NEED_SCRAMBLING;
694 mtd_set_pairing_scheme(mtd, &dist3_pairing_scheme);
695
696 return 0;
697}
698
699static int hynix_nand_init(struct nand_chip *chip)
700{
701 struct hynix_nand *hynix;
702 int ret;
703
704 if (!nand_is_slc(chip))
705 chip->options |= NAND_BBM_LASTPAGE;
706 else
707 chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
708
709 hynix = kzalloc(sizeof(*hynix), GFP_KERNEL);
710 if (!hynix)
711 return -ENOMEM;
712
713 nand_set_manufacturer_data(chip, hynix);
714
715 if (!strncmp("H27UCG8T2ATR-BC", chip->parameters.model,
716 sizeof("H27UCG8T2ATR-BC") - 1))
717 chip->ops.choose_interface_config =
718 h27ucg8t2atrbc_choose_interface_config;
719
720 if (!strncmp("H27UCG8T2ETR-BC", chip->parameters.model,
721 sizeof("H27UCG8T2ETR-BC") - 1))
722 h27ucg8t2etrbc_init(chip);
723
724 ret = hynix_nand_rr_init(chip);
725 if (ret)
726 hynix_nand_cleanup(chip);
727
728 return ret;
729}
730
731static void hynix_fixup_onfi_param_page(struct nand_chip *chip,
732 struct nand_onfi_params *p)
733{
734 /*
735 * Certain chips might report a 0 on sdr_timing_mode field
736 * (bytes 129-130). This has been seen on H27U4G8F2GDA-BI.
737 * According to ONFI specification, bit 0 of this field "shall be 1".
738 * Forcibly set this bit.
739 */
740 p->sdr_timing_modes |= cpu_to_le16(BIT(0));
741}
742
743const struct nand_manufacturer_ops hynix_nand_manuf_ops = {
744 .detect = hynix_nand_decode_id,
745 .init = hynix_nand_init,
746 .cleanup = hynix_nand_cleanup,
747 .fixup_onfi_param_page = hynix_fixup_onfi_param_page,
748};