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1/*
2 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
3 *
4 * Copyright © 2006 Texas Instruments.
5 *
6 * Port to 2.6.23 Copyright © 2008 by:
7 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
8 * Troy Kisky <troy.kisky@boundarydevices.com>
9 * Dirk Behme <Dirk.Behme@gmail.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/err.h>
31#include <linux/clk.h>
32#include <linux/io.h>
33#include <linux/mtd/nand.h>
34#include <linux/mtd/partitions.h>
35#include <linux/slab.h>
36
37#include <mach/nand.h>
38#include <mach/aemif.h>
39
40/*
41 * This is a device driver for the NAND flash controller found on the
42 * various DaVinci family chips. It handles up to four SoC chipselects,
43 * and some flavors of secondary chipselect (e.g. based on A12) as used
44 * with multichip packages.
45 *
46 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
47 * available on chips like the DM355 and OMAP-L137 and needed with the
48 * more error-prone MLC NAND chips.
49 *
50 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
51 * outputs in a "wire-AND" configuration, with no per-chip signals.
52 */
53struct davinci_nand_info {
54 struct mtd_info mtd;
55 struct nand_chip chip;
56 struct nand_ecclayout ecclayout;
57
58 struct device *dev;
59 struct clk *clk;
60
61 bool is_readmode;
62
63 void __iomem *base;
64 void __iomem *vaddr;
65
66 uint32_t ioaddr;
67 uint32_t current_cs;
68
69 uint32_t mask_chipsel;
70 uint32_t mask_ale;
71 uint32_t mask_cle;
72
73 uint32_t core_chipsel;
74
75 struct davinci_aemif_timing *timing;
76};
77
78static DEFINE_SPINLOCK(davinci_nand_lock);
79static bool ecc4_busy;
80
81#define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
82
83
84static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
85 int offset)
86{
87 return __raw_readl(info->base + offset);
88}
89
90static inline void davinci_nand_writel(struct davinci_nand_info *info,
91 int offset, unsigned long value)
92{
93 __raw_writel(value, info->base + offset);
94}
95
96/*----------------------------------------------------------------------*/
97
98/*
99 * Access to hardware control lines: ALE, CLE, secondary chipselect.
100 */
101
102static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
103 unsigned int ctrl)
104{
105 struct davinci_nand_info *info = to_davinci_nand(mtd);
106 uint32_t addr = info->current_cs;
107 struct nand_chip *nand = mtd->priv;
108
109 /* Did the control lines change? */
110 if (ctrl & NAND_CTRL_CHANGE) {
111 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
112 addr |= info->mask_cle;
113 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
114 addr |= info->mask_ale;
115
116 nand->IO_ADDR_W = (void __iomem __force *)addr;
117 }
118
119 if (cmd != NAND_CMD_NONE)
120 iowrite8(cmd, nand->IO_ADDR_W);
121}
122
123static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
124{
125 struct davinci_nand_info *info = to_davinci_nand(mtd);
126 uint32_t addr = info->ioaddr;
127
128 /* maybe kick in a second chipselect */
129 if (chip > 0)
130 addr |= info->mask_chipsel;
131 info->current_cs = addr;
132
133 info->chip.IO_ADDR_W = (void __iomem __force *)addr;
134 info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
135}
136
137/*----------------------------------------------------------------------*/
138
139/*
140 * 1-bit hardware ECC ... context maintained for each core chipselect
141 */
142
143static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
144{
145 struct davinci_nand_info *info = to_davinci_nand(mtd);
146
147 return davinci_nand_readl(info, NANDF1ECC_OFFSET
148 + 4 * info->core_chipsel);
149}
150
151static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
152{
153 struct davinci_nand_info *info;
154 uint32_t nandcfr;
155 unsigned long flags;
156
157 info = to_davinci_nand(mtd);
158
159 /* Reset ECC hardware */
160 nand_davinci_readecc_1bit(mtd);
161
162 spin_lock_irqsave(&davinci_nand_lock, flags);
163
164 /* Restart ECC hardware */
165 nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
166 nandcfr |= BIT(8 + info->core_chipsel);
167 davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
168
169 spin_unlock_irqrestore(&davinci_nand_lock, flags);
170}
171
172/*
173 * Read hardware ECC value and pack into three bytes
174 */
175static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
176 const u_char *dat, u_char *ecc_code)
177{
178 unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
179 unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
180
181 /* invert so that erased block ecc is correct */
182 ecc24 = ~ecc24;
183 ecc_code[0] = (u_char)(ecc24);
184 ecc_code[1] = (u_char)(ecc24 >> 8);
185 ecc_code[2] = (u_char)(ecc24 >> 16);
186
187 return 0;
188}
189
190static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
191 u_char *read_ecc, u_char *calc_ecc)
192{
193 struct nand_chip *chip = mtd->priv;
194 uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
195 (read_ecc[2] << 16);
196 uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
197 (calc_ecc[2] << 16);
198 uint32_t diff = eccCalc ^ eccNand;
199
200 if (diff) {
201 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
202 /* Correctable error */
203 if ((diff >> (12 + 3)) < chip->ecc.size) {
204 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
205 return 1;
206 } else {
207 return -1;
208 }
209 } else if (!(diff & (diff - 1))) {
210 /* Single bit ECC error in the ECC itself,
211 * nothing to fix */
212 return 1;
213 } else {
214 /* Uncorrectable error */
215 return -1;
216 }
217
218 }
219 return 0;
220}
221
222/*----------------------------------------------------------------------*/
223
224/*
225 * 4-bit hardware ECC ... context maintained over entire AEMIF
226 *
227 * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
228 * since that forces use of a problematic "infix OOB" layout.
229 * Among other things, it trashes manufacturer bad block markers.
230 * Also, and specific to this hardware, it ECC-protects the "prepad"
231 * in the OOB ... while having ECC protection for parts of OOB would
232 * seem useful, the current MTD stack sometimes wants to update the
233 * OOB without recomputing ECC.
234 */
235
236static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
237{
238 struct davinci_nand_info *info = to_davinci_nand(mtd);
239 unsigned long flags;
240 u32 val;
241
242 spin_lock_irqsave(&davinci_nand_lock, flags);
243
244 /* Start 4-bit ECC calculation for read/write */
245 val = davinci_nand_readl(info, NANDFCR_OFFSET);
246 val &= ~(0x03 << 4);
247 val |= (info->core_chipsel << 4) | BIT(12);
248 davinci_nand_writel(info, NANDFCR_OFFSET, val);
249
250 info->is_readmode = (mode == NAND_ECC_READ);
251
252 spin_unlock_irqrestore(&davinci_nand_lock, flags);
253}
254
255/* Read raw ECC code after writing to NAND. */
256static void
257nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
258{
259 const u32 mask = 0x03ff03ff;
260
261 code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
262 code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
263 code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
264 code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
265}
266
267/* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
268static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
269 const u_char *dat, u_char *ecc_code)
270{
271 struct davinci_nand_info *info = to_davinci_nand(mtd);
272 u32 raw_ecc[4], *p;
273 unsigned i;
274
275 /* After a read, terminate ECC calculation by a dummy read
276 * of some 4-bit ECC register. ECC covers everything that
277 * was read; correct() just uses the hardware state, so
278 * ecc_code is not needed.
279 */
280 if (info->is_readmode) {
281 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
282 return 0;
283 }
284
285 /* Pack eight raw 10-bit ecc values into ten bytes, making
286 * two passes which each convert four values (in upper and
287 * lower halves of two 32-bit words) into five bytes. The
288 * ROM boot loader uses this same packing scheme.
289 */
290 nand_davinci_readecc_4bit(info, raw_ecc);
291 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
292 *ecc_code++ = p[0] & 0xff;
293 *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
294 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
295 *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
296 *ecc_code++ = (p[1] >> 18) & 0xff;
297 }
298
299 return 0;
300}
301
302/* Correct up to 4 bits in data we just read, using state left in the
303 * hardware plus the ecc_code computed when it was first written.
304 */
305static int nand_davinci_correct_4bit(struct mtd_info *mtd,
306 u_char *data, u_char *ecc_code, u_char *null)
307{
308 int i;
309 struct davinci_nand_info *info = to_davinci_nand(mtd);
310 unsigned short ecc10[8];
311 unsigned short *ecc16;
312 u32 syndrome[4];
313 u32 ecc_state;
314 unsigned num_errors, corrected;
315 unsigned long timeo;
316
317 /* All bytes 0xff? It's an erased page; ignore its ECC. */
318 for (i = 0; i < 10; i++) {
319 if (ecc_code[i] != 0xff)
320 goto compare;
321 }
322 return 0;
323
324compare:
325 /* Unpack ten bytes into eight 10 bit values. We know we're
326 * little-endian, and use type punning for less shifting/masking.
327 */
328 if (WARN_ON(0x01 & (unsigned) ecc_code))
329 return -EINVAL;
330 ecc16 = (unsigned short *)ecc_code;
331
332 ecc10[0] = (ecc16[0] >> 0) & 0x3ff;
333 ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
334 ecc10[2] = (ecc16[1] >> 4) & 0x3ff;
335 ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc);
336 ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300);
337 ecc10[5] = (ecc16[3] >> 2) & 0x3ff;
338 ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0);
339 ecc10[7] = (ecc16[4] >> 6) & 0x3ff;
340
341 /* Tell ECC controller about the expected ECC codes. */
342 for (i = 7; i >= 0; i--)
343 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
344
345 /* Allow time for syndrome calculation ... then read it.
346 * A syndrome of all zeroes 0 means no detected errors.
347 */
348 davinci_nand_readl(info, NANDFSR_OFFSET);
349 nand_davinci_readecc_4bit(info, syndrome);
350 if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
351 return 0;
352
353 /*
354 * Clear any previous address calculation by doing a dummy read of an
355 * error address register.
356 */
357 davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
358
359 /* Start address calculation, and wait for it to complete.
360 * We _could_ start reading more data while this is working,
361 * to speed up the overall page read.
362 */
363 davinci_nand_writel(info, NANDFCR_OFFSET,
364 davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
365
366 /*
367 * ECC_STATE field reads 0x3 (Error correction complete) immediately
368 * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
369 * begin trying to poll for the state, you may fall right out of your
370 * loop without any of the correction calculations having taken place.
371 * The recommendation from the hardware team is to initially delay as
372 * long as ECC_STATE reads less than 4. After that, ECC HW has entered
373 * correction state.
374 */
375 timeo = jiffies + usecs_to_jiffies(100);
376 do {
377 ecc_state = (davinci_nand_readl(info,
378 NANDFSR_OFFSET) >> 8) & 0x0f;
379 cpu_relax();
380 } while ((ecc_state < 4) && time_before(jiffies, timeo));
381
382 for (;;) {
383 u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
384
385 switch ((fsr >> 8) & 0x0f) {
386 case 0: /* no error, should not happen */
387 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
388 return 0;
389 case 1: /* five or more errors detected */
390 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
391 return -EIO;
392 case 2: /* error addresses computed */
393 case 3:
394 num_errors = 1 + ((fsr >> 16) & 0x03);
395 goto correct;
396 default: /* still working on it */
397 cpu_relax();
398 continue;
399 }
400 }
401
402correct:
403 /* correct each error */
404 for (i = 0, corrected = 0; i < num_errors; i++) {
405 int error_address, error_value;
406
407 if (i > 1) {
408 error_address = davinci_nand_readl(info,
409 NAND_ERR_ADD2_OFFSET);
410 error_value = davinci_nand_readl(info,
411 NAND_ERR_ERRVAL2_OFFSET);
412 } else {
413 error_address = davinci_nand_readl(info,
414 NAND_ERR_ADD1_OFFSET);
415 error_value = davinci_nand_readl(info,
416 NAND_ERR_ERRVAL1_OFFSET);
417 }
418
419 if (i & 1) {
420 error_address >>= 16;
421 error_value >>= 16;
422 }
423 error_address &= 0x3ff;
424 error_address = (512 + 7) - error_address;
425
426 if (error_address < 512) {
427 data[error_address] ^= error_value;
428 corrected++;
429 }
430 }
431
432 return corrected;
433}
434
435/*----------------------------------------------------------------------*/
436
437/*
438 * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
439 * how these chips are normally wired. This translates to both 8 and 16
440 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
441 *
442 * For now we assume that configuration, or any other one which ignores
443 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
444 * and have that transparently morphed into multiple NAND operations.
445 */
446static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
447{
448 struct nand_chip *chip = mtd->priv;
449
450 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
451 ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
452 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
453 ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
454 else
455 ioread8_rep(chip->IO_ADDR_R, buf, len);
456}
457
458static void nand_davinci_write_buf(struct mtd_info *mtd,
459 const uint8_t *buf, int len)
460{
461 struct nand_chip *chip = mtd->priv;
462
463 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
464 iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
465 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
466 iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
467 else
468 iowrite8_rep(chip->IO_ADDR_R, buf, len);
469}
470
471/*
472 * Check hardware register for wait status. Returns 1 if device is ready,
473 * 0 if it is still busy.
474 */
475static int nand_davinci_dev_ready(struct mtd_info *mtd)
476{
477 struct davinci_nand_info *info = to_davinci_nand(mtd);
478
479 return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
480}
481
482/*----------------------------------------------------------------------*/
483
484/* An ECC layout for using 4-bit ECC with small-page flash, storing
485 * ten ECC bytes plus the manufacturer's bad block marker byte, and
486 * and not overlapping the default BBT markers.
487 */
488static struct nand_ecclayout hwecc4_small __initconst = {
489 .eccbytes = 10,
490 .eccpos = { 0, 1, 2, 3, 4,
491 /* offset 5 holds the badblock marker */
492 6, 7,
493 13, 14, 15, },
494 .oobfree = {
495 {.offset = 8, .length = 5, },
496 {.offset = 16, },
497 },
498};
499
500/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
501 * storing ten ECC bytes plus the manufacturer's bad block marker byte,
502 * and not overlapping the default BBT markers.
503 */
504static struct nand_ecclayout hwecc4_2048 __initconst = {
505 .eccbytes = 40,
506 .eccpos = {
507 /* at the end of spare sector */
508 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
509 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
510 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
511 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
512 },
513 .oobfree = {
514 /* 2 bytes at offset 0 hold manufacturer badblock markers */
515 {.offset = 2, .length = 22, },
516 /* 5 bytes at offset 8 hold BBT markers */
517 /* 8 bytes at offset 16 hold JFFS2 clean markers */
518 },
519};
520
521static int __init nand_davinci_probe(struct platform_device *pdev)
522{
523 struct davinci_nand_pdata *pdata = pdev->dev.platform_data;
524 struct davinci_nand_info *info;
525 struct resource *res1;
526 struct resource *res2;
527 void __iomem *vaddr;
528 void __iomem *base;
529 int ret;
530 uint32_t val;
531 nand_ecc_modes_t ecc_mode;
532
533 /* insist on board-specific configuration */
534 if (!pdata)
535 return -ENODEV;
536
537 /* which external chipselect will we be managing? */
538 if (pdev->id < 0 || pdev->id > 3)
539 return -ENODEV;
540
541 info = kzalloc(sizeof(*info), GFP_KERNEL);
542 if (!info) {
543 dev_err(&pdev->dev, "unable to allocate memory\n");
544 ret = -ENOMEM;
545 goto err_nomem;
546 }
547
548 platform_set_drvdata(pdev, info);
549
550 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
551 res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
552 if (!res1 || !res2) {
553 dev_err(&pdev->dev, "resource missing\n");
554 ret = -EINVAL;
555 goto err_nomem;
556 }
557
558 vaddr = ioremap(res1->start, resource_size(res1));
559 base = ioremap(res2->start, resource_size(res2));
560 if (!vaddr || !base) {
561 dev_err(&pdev->dev, "ioremap failed\n");
562 ret = -EINVAL;
563 goto err_ioremap;
564 }
565
566 info->dev = &pdev->dev;
567 info->base = base;
568 info->vaddr = vaddr;
569
570 info->mtd.priv = &info->chip;
571 info->mtd.name = dev_name(&pdev->dev);
572 info->mtd.owner = THIS_MODULE;
573
574 info->mtd.dev.parent = &pdev->dev;
575
576 info->chip.IO_ADDR_R = vaddr;
577 info->chip.IO_ADDR_W = vaddr;
578 info->chip.chip_delay = 0;
579 info->chip.select_chip = nand_davinci_select_chip;
580
581 /* options such as NAND_BBT_USE_FLASH */
582 info->chip.bbt_options = pdata->bbt_options;
583 /* options such as 16-bit widths */
584 info->chip.options = pdata->options;
585 info->chip.bbt_td = pdata->bbt_td;
586 info->chip.bbt_md = pdata->bbt_md;
587 info->timing = pdata->timing;
588
589 info->ioaddr = (uint32_t __force) vaddr;
590
591 info->current_cs = info->ioaddr;
592 info->core_chipsel = pdev->id;
593 info->mask_chipsel = pdata->mask_chipsel;
594
595 /* use nandboot-capable ALE/CLE masks by default */
596 info->mask_ale = pdata->mask_ale ? : MASK_ALE;
597 info->mask_cle = pdata->mask_cle ? : MASK_CLE;
598
599 /* Set address of hardware control function */
600 info->chip.cmd_ctrl = nand_davinci_hwcontrol;
601 info->chip.dev_ready = nand_davinci_dev_ready;
602
603 /* Speed up buffer I/O */
604 info->chip.read_buf = nand_davinci_read_buf;
605 info->chip.write_buf = nand_davinci_write_buf;
606
607 /* Use board-specific ECC config */
608 ecc_mode = pdata->ecc_mode;
609
610 ret = -EINVAL;
611 switch (ecc_mode) {
612 case NAND_ECC_NONE:
613 case NAND_ECC_SOFT:
614 pdata->ecc_bits = 0;
615 break;
616 case NAND_ECC_HW:
617 if (pdata->ecc_bits == 4) {
618 /* No sanity checks: CPUs must support this,
619 * and the chips may not use NAND_BUSWIDTH_16.
620 */
621
622 /* No sharing 4-bit hardware between chipselects yet */
623 spin_lock_irq(&davinci_nand_lock);
624 if (ecc4_busy)
625 ret = -EBUSY;
626 else
627 ecc4_busy = true;
628 spin_unlock_irq(&davinci_nand_lock);
629
630 if (ret == -EBUSY)
631 goto err_ecc;
632
633 info->chip.ecc.calculate = nand_davinci_calculate_4bit;
634 info->chip.ecc.correct = nand_davinci_correct_4bit;
635 info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
636 info->chip.ecc.bytes = 10;
637 } else {
638 info->chip.ecc.calculate = nand_davinci_calculate_1bit;
639 info->chip.ecc.correct = nand_davinci_correct_1bit;
640 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
641 info->chip.ecc.bytes = 3;
642 }
643 info->chip.ecc.size = 512;
644 info->chip.ecc.strength = pdata->ecc_bits;
645 break;
646 default:
647 ret = -EINVAL;
648 goto err_ecc;
649 }
650 info->chip.ecc.mode = ecc_mode;
651
652 info->clk = clk_get(&pdev->dev, "aemif");
653 if (IS_ERR(info->clk)) {
654 ret = PTR_ERR(info->clk);
655 dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
656 goto err_clk;
657 }
658
659 ret = clk_enable(info->clk);
660 if (ret < 0) {
661 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
662 ret);
663 goto err_clk_enable;
664 }
665
666 /*
667 * Setup Async configuration register in case we did not boot from
668 * NAND and so bootloader did not bother to set it up.
669 */
670 val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4);
671
672 /* Extended Wait is not valid and Select Strobe mode is not used */
673 val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
674 if (info->chip.options & NAND_BUSWIDTH_16)
675 val |= 0x1;
676
677 davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val);
678
679 ret = 0;
680 if (info->timing)
681 ret = davinci_aemif_setup_timing(info->timing, info->base,
682 info->core_chipsel);
683 if (ret < 0) {
684 dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
685 goto err_timing;
686 }
687
688 spin_lock_irq(&davinci_nand_lock);
689
690 /* put CSxNAND into NAND mode */
691 val = davinci_nand_readl(info, NANDFCR_OFFSET);
692 val |= BIT(info->core_chipsel);
693 davinci_nand_writel(info, NANDFCR_OFFSET, val);
694
695 spin_unlock_irq(&davinci_nand_lock);
696
697 /* Scan to find existence of the device(s) */
698 ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL);
699 if (ret < 0) {
700 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
701 goto err_scan;
702 }
703
704 /* Update ECC layout if needed ... for 1-bit HW ECC, the default
705 * is OK, but it allocates 6 bytes when only 3 are needed (for
706 * each 512 bytes). For the 4-bit HW ECC, that default is not
707 * usable: 10 bytes are needed, not 6.
708 */
709 if (pdata->ecc_bits == 4) {
710 int chunks = info->mtd.writesize / 512;
711
712 if (!chunks || info->mtd.oobsize < 16) {
713 dev_dbg(&pdev->dev, "too small\n");
714 ret = -EINVAL;
715 goto err_scan;
716 }
717
718 /* For small page chips, preserve the manufacturer's
719 * badblock marking data ... and make sure a flash BBT
720 * table marker fits in the free bytes.
721 */
722 if (chunks == 1) {
723 info->ecclayout = hwecc4_small;
724 info->ecclayout.oobfree[1].length =
725 info->mtd.oobsize - 16;
726 goto syndrome_done;
727 }
728 if (chunks == 4) {
729 info->ecclayout = hwecc4_2048;
730 info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
731 goto syndrome_done;
732 }
733
734 /* 4KiB page chips are not yet supported. The eccpos from
735 * nand_ecclayout cannot hold 80 bytes and change to eccpos[]
736 * breaks userspace ioctl interface with mtd-utils. Once we
737 * resolve this issue, NAND_ECC_HW_OOB_FIRST mode can be used
738 * for the 4KiB page chips.
739 *
740 * TODO: Note that nand_ecclayout has now been expanded and can
741 * hold plenty of OOB entries.
742 */
743 dev_warn(&pdev->dev, "no 4-bit ECC support yet "
744 "for 4KiB-page NAND\n");
745 ret = -EIO;
746 goto err_scan;
747
748syndrome_done:
749 info->chip.ecc.layout = &info->ecclayout;
750 }
751
752 ret = nand_scan_tail(&info->mtd);
753 if (ret < 0)
754 goto err_scan;
755
756 ret = mtd_device_parse_register(&info->mtd, NULL, NULL, pdata->parts,
757 pdata->nr_parts);
758
759 if (ret < 0)
760 goto err_scan;
761
762 val = davinci_nand_readl(info, NRCSR_OFFSET);
763 dev_info(&pdev->dev, "controller rev. %d.%d\n",
764 (val >> 8) & 0xff, val & 0xff);
765
766 return 0;
767
768err_scan:
769err_timing:
770 clk_disable(info->clk);
771
772err_clk_enable:
773 clk_put(info->clk);
774
775 spin_lock_irq(&davinci_nand_lock);
776 if (ecc_mode == NAND_ECC_HW_SYNDROME)
777 ecc4_busy = false;
778 spin_unlock_irq(&davinci_nand_lock);
779
780err_ecc:
781err_clk:
782err_ioremap:
783 if (base)
784 iounmap(base);
785 if (vaddr)
786 iounmap(vaddr);
787
788err_nomem:
789 kfree(info);
790 return ret;
791}
792
793static int __exit nand_davinci_remove(struct platform_device *pdev)
794{
795 struct davinci_nand_info *info = platform_get_drvdata(pdev);
796
797 spin_lock_irq(&davinci_nand_lock);
798 if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
799 ecc4_busy = false;
800 spin_unlock_irq(&davinci_nand_lock);
801
802 iounmap(info->base);
803 iounmap(info->vaddr);
804
805 nand_release(&info->mtd);
806
807 clk_disable(info->clk);
808 clk_put(info->clk);
809
810 kfree(info);
811
812 return 0;
813}
814
815static struct platform_driver nand_davinci_driver = {
816 .remove = __exit_p(nand_davinci_remove),
817 .driver = {
818 .name = "davinci_nand",
819 },
820};
821MODULE_ALIAS("platform:davinci_nand");
822
823static int __init nand_davinci_init(void)
824{
825 return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe);
826}
827module_init(nand_davinci_init);
828
829static void __exit nand_davinci_exit(void)
830{
831 platform_driver_unregister(&nand_davinci_driver);
832}
833module_exit(nand_davinci_exit);
834
835MODULE_LICENSE("GPL");
836MODULE_AUTHOR("Texas Instruments");
837MODULE_DESCRIPTION("Davinci NAND flash driver");
838