1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Interconnect framework driver for i.MX8MM SoC
  4 *
  5 * Copyright (c) 2019, BayLibre
  6 * Copyright (c) 2019-2020, NXP
  7 * Author: Alexandre Bailon <abailon@baylibre.com>
  8 * Author: Leonard Crestez <leonard.crestez@nxp.com>
  9 */
 10
 11#include <linux/module.h>
 12#include <linux/platform_device.h>
 13#include <dt-bindings/interconnect/imx8mm.h>
 14
 15#include "imx.h"
 16
 17static const struct imx_icc_node_adj_desc imx8mm_dram_adj = {
 18	.bw_mul = 1,
 19	.bw_div = 16,
 20	.phandle_name = "fsl,ddrc",
 21};
 22
 23static const struct imx_icc_node_adj_desc imx8mm_noc_adj = {
 24	.bw_mul = 1,
 25	.bw_div = 16,
 26	.main_noc = true,
 27};
 28
 29/*
 30 * Describe bus masters, slaves and connections between them
 31 *
 32 * This is a simplified subset of the bus diagram, there are several other
 33 * PL301 nics which are skipped/merged into PL301_MAIN
 34 */
 35static struct imx_icc_node_desc nodes[] = {
 36	DEFINE_BUS_INTERCONNECT("NOC", IMX8MM_ICN_NOC, &imx8mm_noc_adj,
 37			IMX8MM_ICS_DRAM, IMX8MM_ICN_MAIN),
 38
 39	DEFINE_BUS_SLAVE("DRAM", IMX8MM_ICS_DRAM, &imx8mm_dram_adj),
 40	DEFINE_BUS_SLAVE("OCRAM", IMX8MM_ICS_OCRAM, NULL),
 41	DEFINE_BUS_MASTER("A53", IMX8MM_ICM_A53, IMX8MM_ICN_NOC),
 42
 43	/* VPUMIX */
 44	DEFINE_BUS_MASTER("VPU H1", IMX8MM_ICM_VPU_H1, IMX8MM_ICN_VIDEO),
 45	DEFINE_BUS_MASTER("VPU G1", IMX8MM_ICM_VPU_G1, IMX8MM_ICN_VIDEO),
 46	DEFINE_BUS_MASTER("VPU G2", IMX8MM_ICM_VPU_G2, IMX8MM_ICN_VIDEO),
 47	DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MM_ICN_VIDEO, NULL, IMX8MM_ICN_NOC),
 48
 49	/* GPUMIX */
 50	DEFINE_BUS_MASTER("GPU 2D", IMX8MM_ICM_GPU2D, IMX8MM_ICN_GPU),
 51	DEFINE_BUS_MASTER("GPU 3D", IMX8MM_ICM_GPU3D, IMX8MM_ICN_GPU),
 52	DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MM_ICN_GPU, NULL, IMX8MM_ICN_NOC),
 53
 54	/* DISPLAYMIX */
 55	DEFINE_BUS_MASTER("CSI", IMX8MM_ICM_CSI, IMX8MM_ICN_MIPI),
 56	DEFINE_BUS_MASTER("LCDIF", IMX8MM_ICM_LCDIF, IMX8MM_ICN_MIPI),
 57	DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MM_ICN_MIPI, NULL, IMX8MM_ICN_NOC),
 58
 59	/* HSIO */
 60	DEFINE_BUS_MASTER("USB1", IMX8MM_ICM_USB1, IMX8MM_ICN_HSIO),
 61	DEFINE_BUS_MASTER("USB2", IMX8MM_ICM_USB2, IMX8MM_ICN_HSIO),
 62	DEFINE_BUS_MASTER("PCIE", IMX8MM_ICM_PCIE, IMX8MM_ICN_HSIO),
 63	DEFINE_BUS_INTERCONNECT("PL301_HSIO", IMX8MM_ICN_HSIO, NULL, IMX8MM_ICN_NOC),
 64
 65	/* Audio */
 66	DEFINE_BUS_MASTER("SDMA2", IMX8MM_ICM_SDMA2, IMX8MM_ICN_AUDIO),
 67	DEFINE_BUS_MASTER("SDMA3", IMX8MM_ICM_SDMA3, IMX8MM_ICN_AUDIO),
 68	DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MM_ICN_AUDIO, NULL, IMX8MM_ICN_MAIN),
 69
 70	/* Ethernet */
 71	DEFINE_BUS_MASTER("ENET", IMX8MM_ICM_ENET, IMX8MM_ICN_ENET),
 72	DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MM_ICN_ENET, NULL, IMX8MM_ICN_MAIN),
 73
 74	/* Other */
 75	DEFINE_BUS_MASTER("SDMA1", IMX8MM_ICM_SDMA1, IMX8MM_ICN_MAIN),
 76	DEFINE_BUS_MASTER("NAND", IMX8MM_ICM_NAND, IMX8MM_ICN_MAIN),
 77	DEFINE_BUS_MASTER("USDHC1", IMX8MM_ICM_USDHC1, IMX8MM_ICN_MAIN),
 78	DEFINE_BUS_MASTER("USDHC2", IMX8MM_ICM_USDHC2, IMX8MM_ICN_MAIN),
 79	DEFINE_BUS_MASTER("USDHC3", IMX8MM_ICM_USDHC3, IMX8MM_ICN_MAIN),
 80	DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MM_ICN_MAIN, NULL,
 81			IMX8MM_ICN_NOC, IMX8MM_ICS_OCRAM),
 82};
 83
 84static int imx8mm_icc_probe(struct platform_device *pdev)
 85{
 86	return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL);
 87}
 88
 89static struct platform_driver imx8mm_icc_driver = {
 90	.probe = imx8mm_icc_probe,
 91	.remove_new = imx_icc_unregister,
 92	.driver = {
 93		.name = "imx8mm-interconnect",
 94	},
 95};
 96
 97module_platform_driver(imx8mm_icc_driver);
 98MODULE_AUTHOR("Alexandre Bailon <abailon@baylibre.com>");
 99MODULE_LICENSE("GPL v2");
100MODULE_ALIAS("platform:imx8mm-interconnect");