Loading...
Note: File does not exist in v6.8.
1/*
2 * Support for IDE interfaces on PowerMacs.
3 *
4 * These IDE interfaces are memory-mapped and have a DBDMA channel
5 * for doing DMA.
6 *
7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
8 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
25#include <linux/types.h>
26#include <linux/kernel.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/notifier.h>
31#include <linux/module.h>
32#include <linux/reboot.h>
33#include <linux/pci.h>
34#include <linux/adb.h>
35#include <linux/pmu.h>
36#include <linux/scatterlist.h>
37#include <linux/slab.h>
38
39#include <asm/prom.h>
40#include <asm/io.h>
41#include <asm/dbdma.h>
42#include <asm/ide.h>
43#include <asm/pci-bridge.h>
44#include <asm/machdep.h>
45#include <asm/pmac_feature.h>
46#include <asm/sections.h>
47#include <asm/irq.h>
48#include <asm/mediabay.h>
49
50#define DRV_NAME "ide-pmac"
51
52#undef IDE_PMAC_DEBUG
53
54#define DMA_WAIT_TIMEOUT 50
55
56typedef struct pmac_ide_hwif {
57 unsigned long regbase;
58 int irq;
59 int kind;
60 int aapl_bus_id;
61 unsigned broken_dma : 1;
62 unsigned broken_dma_warn : 1;
63 struct device_node* node;
64 struct macio_dev *mdev;
65 u32 timings[4];
66 volatile u32 __iomem * *kauai_fcr;
67 ide_hwif_t *hwif;
68
69 /* Those fields are duplicating what is in hwif. We currently
70 * can't use the hwif ones because of some assumptions that are
71 * beeing done by the generic code about the kind of dma controller
72 * and format of the dma table. This will have to be fixed though.
73 */
74 volatile struct dbdma_regs __iomem * dma_regs;
75 struct dbdma_cmd* dma_table_cpu;
76} pmac_ide_hwif_t;
77
78enum {
79 controller_ohare, /* OHare based */
80 controller_heathrow, /* Heathrow/Paddington */
81 controller_kl_ata3, /* KeyLargo ATA-3 */
82 controller_kl_ata4, /* KeyLargo ATA-4 */
83 controller_un_ata6, /* UniNorth2 ATA-6 */
84 controller_k2_ata6, /* K2 ATA-6 */
85 controller_sh_ata6, /* Shasta ATA-6 */
86};
87
88static const char* model_name[] = {
89 "OHare ATA", /* OHare based */
90 "Heathrow ATA", /* Heathrow/Paddington */
91 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
92 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
93 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
94 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
95 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
96};
97
98/*
99 * Extra registers, both 32-bit little-endian
100 */
101#define IDE_TIMING_CONFIG 0x200
102#define IDE_INTERRUPT 0x300
103
104/* Kauai (U2) ATA has different register setup */
105#define IDE_KAUAI_PIO_CONFIG 0x200
106#define IDE_KAUAI_ULTRA_CONFIG 0x210
107#define IDE_KAUAI_POLL_CONFIG 0x220
108
109/*
110 * Timing configuration register definitions
111 */
112
113/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
114#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
115#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
116#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
117#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
118
119/* 133Mhz cell, found in shasta.
120 * See comments about 100 Mhz Uninorth 2...
121 * Note that PIO_MASK and MDMA_MASK seem to overlap
122 */
123#define TR_133_PIOREG_PIO_MASK 0xff000fff
124#define TR_133_PIOREG_MDMA_MASK 0x00fff800
125#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
126#define TR_133_UDMAREG_UDMA_EN 0x00000001
127
128/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
129 * this one yet, it appears as a pci device (106b/0033) on uninorth
130 * internal PCI bus and it's clock is controlled like gem or fw. It
131 * appears to be an evolution of keylargo ATA4 with a timing register
132 * extended to 2 32bits registers and a similar DBDMA channel. Other
133 * registers seem to exist but I can't tell much about them.
134 *
135 * So far, I'm using pre-calculated tables for this extracted from
136 * the values used by the MacOS X driver.
137 *
138 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
139 * register controls the UDMA timings. At least, it seems bit 0
140 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
141 * cycle time in units of 10ns. Bits 8..15 are used by I don't
142 * know their meaning yet
143 */
144#define TR_100_PIOREG_PIO_MASK 0xff000fff
145#define TR_100_PIOREG_MDMA_MASK 0x00fff000
146#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
147#define TR_100_UDMAREG_UDMA_EN 0x00000001
148
149
150/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
151 * 40 connector cable and to 4 on 80 connector one.
152 * Clock unit is 15ns (66Mhz)
153 *
154 * 3 Values can be programmed:
155 * - Write data setup, which appears to match the cycle time. They
156 * also call it DIOW setup.
157 * - Ready to pause time (from spec)
158 * - Address setup. That one is weird. I don't see where exactly
159 * it fits in UDMA cycles, I got it's name from an obscure piece
160 * of commented out code in Darwin. They leave it to 0, we do as
161 * well, despite a comment that would lead to think it has a
162 * min value of 45ns.
163 * Apple also add 60ns to the write data setup (or cycle time ?) on
164 * reads.
165 */
166#define TR_66_UDMA_MASK 0xfff00000
167#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
168#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
169#define TR_66_UDMA_ADDRSETUP_SHIFT 29
170#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
171#define TR_66_UDMA_RDY2PAUS_SHIFT 25
172#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
173#define TR_66_UDMA_WRDATASETUP_SHIFT 21
174#define TR_66_MDMA_MASK 0x000ffc00
175#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
176#define TR_66_MDMA_RECOVERY_SHIFT 15
177#define TR_66_MDMA_ACCESS_MASK 0x00007c00
178#define TR_66_MDMA_ACCESS_SHIFT 10
179#define TR_66_PIO_MASK 0x000003ff
180#define TR_66_PIO_RECOVERY_MASK 0x000003e0
181#define TR_66_PIO_RECOVERY_SHIFT 5
182#define TR_66_PIO_ACCESS_MASK 0x0000001f
183#define TR_66_PIO_ACCESS_SHIFT 0
184
185/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
186 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
187 *
188 * The access time and recovery time can be programmed. Some older
189 * Darwin code base limit OHare to 150ns cycle time. I decided to do
190 * the same here fore safety against broken old hardware ;)
191 * The HalfTick bit, when set, adds half a clock (15ns) to the access
192 * time and removes one from recovery. It's not supported on KeyLargo
193 * implementation afaik. The E bit appears to be set for PIO mode 0 and
194 * is used to reach long timings used in this mode.
195 */
196#define TR_33_MDMA_MASK 0x003ff800
197#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
198#define TR_33_MDMA_RECOVERY_SHIFT 16
199#define TR_33_MDMA_ACCESS_MASK 0x0000f800
200#define TR_33_MDMA_ACCESS_SHIFT 11
201#define TR_33_MDMA_HALFTICK 0x00200000
202#define TR_33_PIO_MASK 0x000007ff
203#define TR_33_PIO_E 0x00000400
204#define TR_33_PIO_RECOVERY_MASK 0x000003e0
205#define TR_33_PIO_RECOVERY_SHIFT 5
206#define TR_33_PIO_ACCESS_MASK 0x0000001f
207#define TR_33_PIO_ACCESS_SHIFT 0
208
209/*
210 * Interrupt register definitions
211 */
212#define IDE_INTR_DMA 0x80000000
213#define IDE_INTR_DEVICE 0x40000000
214
215/*
216 * FCR Register on Kauai. Not sure what bit 0x4 is ...
217 */
218#define KAUAI_FCR_UATA_MAGIC 0x00000004
219#define KAUAI_FCR_UATA_RESET_N 0x00000002
220#define KAUAI_FCR_UATA_ENABLE 0x00000001
221
222/* Rounded Multiword DMA timings
223 *
224 * I gave up finding a generic formula for all controller
225 * types and instead, built tables based on timing values
226 * used by Apple in Darwin's implementation.
227 */
228struct mdma_timings_t {
229 int accessTime;
230 int recoveryTime;
231 int cycleTime;
232};
233
234struct mdma_timings_t mdma_timings_33[] =
235{
236 { 240, 240, 480 },
237 { 180, 180, 360 },
238 { 135, 135, 270 },
239 { 120, 120, 240 },
240 { 105, 105, 210 },
241 { 90, 90, 180 },
242 { 75, 75, 150 },
243 { 75, 45, 120 },
244 { 0, 0, 0 }
245};
246
247struct mdma_timings_t mdma_timings_33k[] =
248{
249 { 240, 240, 480 },
250 { 180, 180, 360 },
251 { 150, 150, 300 },
252 { 120, 120, 240 },
253 { 90, 120, 210 },
254 { 90, 90, 180 },
255 { 90, 60, 150 },
256 { 90, 30, 120 },
257 { 0, 0, 0 }
258};
259
260struct mdma_timings_t mdma_timings_66[] =
261{
262 { 240, 240, 480 },
263 { 180, 180, 360 },
264 { 135, 135, 270 },
265 { 120, 120, 240 },
266 { 105, 105, 210 },
267 { 90, 90, 180 },
268 { 90, 75, 165 },
269 { 75, 45, 120 },
270 { 0, 0, 0 }
271};
272
273/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
274struct {
275 int addrSetup; /* ??? */
276 int rdy2pause;
277 int wrDataSetup;
278} kl66_udma_timings[] =
279{
280 { 0, 180, 120 }, /* Mode 0 */
281 { 0, 150, 90 }, /* 1 */
282 { 0, 120, 60 }, /* 2 */
283 { 0, 90, 45 }, /* 3 */
284 { 0, 90, 30 } /* 4 */
285};
286
287/* UniNorth 2 ATA/100 timings */
288struct kauai_timing {
289 int cycle_time;
290 u32 timing_reg;
291};
292
293static struct kauai_timing kauai_pio_timings[] =
294{
295 { 930 , 0x08000fff },
296 { 600 , 0x08000a92 },
297 { 383 , 0x0800060f },
298 { 360 , 0x08000492 },
299 { 330 , 0x0800048f },
300 { 300 , 0x080003cf },
301 { 270 , 0x080003cc },
302 { 240 , 0x0800038b },
303 { 239 , 0x0800030c },
304 { 180 , 0x05000249 },
305 { 120 , 0x04000148 },
306 { 0 , 0 },
307};
308
309static struct kauai_timing kauai_mdma_timings[] =
310{
311 { 1260 , 0x00fff000 },
312 { 480 , 0x00618000 },
313 { 360 , 0x00492000 },
314 { 270 , 0x0038e000 },
315 { 240 , 0x0030c000 },
316 { 210 , 0x002cb000 },
317 { 180 , 0x00249000 },
318 { 150 , 0x00209000 },
319 { 120 , 0x00148000 },
320 { 0 , 0 },
321};
322
323static struct kauai_timing kauai_udma_timings[] =
324{
325 { 120 , 0x000070c0 },
326 { 90 , 0x00005d80 },
327 { 60 , 0x00004a60 },
328 { 45 , 0x00003a50 },
329 { 30 , 0x00002a30 },
330 { 20 , 0x00002921 },
331 { 0 , 0 },
332};
333
334static struct kauai_timing shasta_pio_timings[] =
335{
336 { 930 , 0x08000fff },
337 { 600 , 0x0A000c97 },
338 { 383 , 0x07000712 },
339 { 360 , 0x040003cd },
340 { 330 , 0x040003cd },
341 { 300 , 0x040003cd },
342 { 270 , 0x040003cd },
343 { 240 , 0x040003cd },
344 { 239 , 0x040003cd },
345 { 180 , 0x0400028b },
346 { 120 , 0x0400010a },
347 { 0 , 0 },
348};
349
350static struct kauai_timing shasta_mdma_timings[] =
351{
352 { 1260 , 0x00fff000 },
353 { 480 , 0x00820800 },
354 { 360 , 0x00820800 },
355 { 270 , 0x00820800 },
356 { 240 , 0x00820800 },
357 { 210 , 0x00820800 },
358 { 180 , 0x00820800 },
359 { 150 , 0x0028b000 },
360 { 120 , 0x001ca000 },
361 { 0 , 0 },
362};
363
364static struct kauai_timing shasta_udma133_timings[] =
365{
366 { 120 , 0x00035901, },
367 { 90 , 0x000348b1, },
368 { 60 , 0x00033881, },
369 { 45 , 0x00033861, },
370 { 30 , 0x00033841, },
371 { 20 , 0x00033031, },
372 { 15 , 0x00033021, },
373 { 0 , 0 },
374};
375
376
377static inline u32
378kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
379{
380 int i;
381
382 for (i=0; table[i].cycle_time; i++)
383 if (cycle_time > table[i+1].cycle_time)
384 return table[i].timing_reg;
385 BUG();
386 return 0;
387}
388
389/* allow up to 256 DBDMA commands per xfer */
390#define MAX_DCMDS 256
391
392/*
393 * Wait 1s for disk to answer on IDE bus after a hard reset
394 * of the device (via GPIO/FCR).
395 *
396 * Some devices seem to "pollute" the bus even after dropping
397 * the BSY bit (typically some combo drives slave on the UDMA
398 * bus) after a hard reset. Since we hard reset all drives on
399 * KeyLargo ATA66, we have to keep that delay around. I may end
400 * up not hard resetting anymore on these and keep the delay only
401 * for older interfaces instead (we have to reset when coming
402 * from MacOS...) --BenH.
403 */
404#define IDE_WAKEUP_DELAY (1*HZ)
405
406static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *);
407
408#define PMAC_IDE_REG(x) \
409 ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
410
411/*
412 * Apply the timings of the proper unit (master/slave) to the shared
413 * timing register when selecting that unit. This version is for
414 * ASICs with a single timing register
415 */
416static void pmac_ide_apply_timings(ide_drive_t *drive)
417{
418 ide_hwif_t *hwif = drive->hwif;
419 pmac_ide_hwif_t *pmif =
420 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
421
422 if (drive->dn & 1)
423 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
424 else
425 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
426 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
427}
428
429/*
430 * Apply the timings of the proper unit (master/slave) to the shared
431 * timing register when selecting that unit. This version is for
432 * ASICs with a dual timing register (Kauai)
433 */
434static void pmac_ide_kauai_apply_timings(ide_drive_t *drive)
435{
436 ide_hwif_t *hwif = drive->hwif;
437 pmac_ide_hwif_t *pmif =
438 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
439
440 if (drive->dn & 1) {
441 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
442 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
443 } else {
444 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
445 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
446 }
447 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
448}
449
450/*
451 * Force an update of controller timing values for a given drive
452 */
453static void
454pmac_ide_do_update_timings(ide_drive_t *drive)
455{
456 ide_hwif_t *hwif = drive->hwif;
457 pmac_ide_hwif_t *pmif =
458 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
459
460 if (pmif->kind == controller_sh_ata6 ||
461 pmif->kind == controller_un_ata6 ||
462 pmif->kind == controller_k2_ata6)
463 pmac_ide_kauai_apply_timings(drive);
464 else
465 pmac_ide_apply_timings(drive);
466}
467
468static void pmac_dev_select(ide_drive_t *drive)
469{
470 pmac_ide_apply_timings(drive);
471
472 writeb(drive->select | ATA_DEVICE_OBS,
473 (void __iomem *)drive->hwif->io_ports.device_addr);
474}
475
476static void pmac_kauai_dev_select(ide_drive_t *drive)
477{
478 pmac_ide_kauai_apply_timings(drive);
479
480 writeb(drive->select | ATA_DEVICE_OBS,
481 (void __iomem *)drive->hwif->io_ports.device_addr);
482}
483
484static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd)
485{
486 writeb(cmd, (void __iomem *)hwif->io_ports.command_addr);
487 (void)readl((void __iomem *)(hwif->io_ports.data_addr
488 + IDE_TIMING_CONFIG));
489}
490
491static void pmac_write_devctl(ide_hwif_t *hwif, u8 ctl)
492{
493 writeb(ctl, (void __iomem *)hwif->io_ports.ctl_addr);
494 (void)readl((void __iomem *)(hwif->io_ports.data_addr
495 + IDE_TIMING_CONFIG));
496}
497
498/*
499 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
500 */
501static void pmac_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
502{
503 pmac_ide_hwif_t *pmif =
504 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
505 const u8 pio = drive->pio_mode - XFER_PIO_0;
506 struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
507 u32 *timings, t;
508 unsigned accessTicks, recTicks;
509 unsigned accessTime, recTime;
510 unsigned int cycle_time;
511
512 /* which drive is it ? */
513 timings = &pmif->timings[drive->dn & 1];
514 t = *timings;
515
516 cycle_time = ide_pio_cycle_time(drive, pio);
517
518 switch (pmif->kind) {
519 case controller_sh_ata6: {
520 /* 133Mhz cell */
521 u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
522 t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
523 break;
524 }
525 case controller_un_ata6:
526 case controller_k2_ata6: {
527 /* 100Mhz cell */
528 u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
529 t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
530 break;
531 }
532 case controller_kl_ata4:
533 /* 66Mhz cell */
534 recTime = cycle_time - tim->active - tim->setup;
535 recTime = max(recTime, 150U);
536 accessTime = tim->active;
537 accessTime = max(accessTime, 150U);
538 accessTicks = SYSCLK_TICKS_66(accessTime);
539 accessTicks = min(accessTicks, 0x1fU);
540 recTicks = SYSCLK_TICKS_66(recTime);
541 recTicks = min(recTicks, 0x1fU);
542 t = (t & ~TR_66_PIO_MASK) |
543 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
544 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
545 break;
546 default: {
547 /* 33Mhz cell */
548 int ebit = 0;
549 recTime = cycle_time - tim->active - tim->setup;
550 recTime = max(recTime, 150U);
551 accessTime = tim->active;
552 accessTime = max(accessTime, 150U);
553 accessTicks = SYSCLK_TICKS(accessTime);
554 accessTicks = min(accessTicks, 0x1fU);
555 accessTicks = max(accessTicks, 4U);
556 recTicks = SYSCLK_TICKS(recTime);
557 recTicks = min(recTicks, 0x1fU);
558 recTicks = max(recTicks, 5U) - 4;
559 if (recTicks > 9) {
560 recTicks--; /* guess, but it's only for PIO0, so... */
561 ebit = 1;
562 }
563 t = (t & ~TR_33_PIO_MASK) |
564 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
565 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
566 if (ebit)
567 t |= TR_33_PIO_E;
568 break;
569 }
570 }
571
572#ifdef IDE_PMAC_DEBUG
573 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
574 drive->name, pio, *timings);
575#endif
576
577 *timings = t;
578 pmac_ide_do_update_timings(drive);
579}
580
581/*
582 * Calculate KeyLargo ATA/66 UDMA timings
583 */
584static int
585set_timings_udma_ata4(u32 *timings, u8 speed)
586{
587 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
588
589 if (speed > XFER_UDMA_4)
590 return 1;
591
592 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
593 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
594 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
595
596 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
597 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
598 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
599 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
600 TR_66_UDMA_EN;
601#ifdef IDE_PMAC_DEBUG
602 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
603 speed & 0xf, *timings);
604#endif
605
606 return 0;
607}
608
609/*
610 * Calculate Kauai ATA/100 UDMA timings
611 */
612static int
613set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
614{
615 struct ide_timing *t = ide_timing_find_mode(speed);
616 u32 tr;
617
618 if (speed > XFER_UDMA_5 || t == NULL)
619 return 1;
620 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
621 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
622 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
623
624 return 0;
625}
626
627/*
628 * Calculate Shasta ATA/133 UDMA timings
629 */
630static int
631set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
632{
633 struct ide_timing *t = ide_timing_find_mode(speed);
634 u32 tr;
635
636 if (speed > XFER_UDMA_6 || t == NULL)
637 return 1;
638 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
639 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
640 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
641
642 return 0;
643}
644
645/*
646 * Calculate MDMA timings for all cells
647 */
648static void
649set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
650 u8 speed)
651{
652 u16 *id = drive->id;
653 int cycleTime, accessTime = 0, recTime = 0;
654 unsigned accessTicks, recTicks;
655 struct mdma_timings_t* tm = NULL;
656 int i;
657
658 /* Get default cycle time for mode */
659 switch(speed & 0xf) {
660 case 0: cycleTime = 480; break;
661 case 1: cycleTime = 150; break;
662 case 2: cycleTime = 120; break;
663 default:
664 BUG();
665 break;
666 }
667
668 /* Check if drive provides explicit DMA cycle time */
669 if ((id[ATA_ID_FIELD_VALID] & 2) && id[ATA_ID_EIDE_DMA_TIME])
670 cycleTime = max_t(int, id[ATA_ID_EIDE_DMA_TIME], cycleTime);
671
672 /* OHare limits according to some old Apple sources */
673 if ((intf_type == controller_ohare) && (cycleTime < 150))
674 cycleTime = 150;
675 /* Get the proper timing array for this controller */
676 switch(intf_type) {
677 case controller_sh_ata6:
678 case controller_un_ata6:
679 case controller_k2_ata6:
680 break;
681 case controller_kl_ata4:
682 tm = mdma_timings_66;
683 break;
684 case controller_kl_ata3:
685 tm = mdma_timings_33k;
686 break;
687 default:
688 tm = mdma_timings_33;
689 break;
690 }
691 if (tm != NULL) {
692 /* Lookup matching access & recovery times */
693 i = -1;
694 for (;;) {
695 if (tm[i+1].cycleTime < cycleTime)
696 break;
697 i++;
698 }
699 cycleTime = tm[i].cycleTime;
700 accessTime = tm[i].accessTime;
701 recTime = tm[i].recoveryTime;
702
703#ifdef IDE_PMAC_DEBUG
704 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
705 drive->name, cycleTime, accessTime, recTime);
706#endif
707 }
708 switch(intf_type) {
709 case controller_sh_ata6: {
710 /* 133Mhz cell */
711 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
712 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
713 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
714 }
715 case controller_un_ata6:
716 case controller_k2_ata6: {
717 /* 100Mhz cell */
718 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
719 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
720 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
721 }
722 break;
723 case controller_kl_ata4:
724 /* 66Mhz cell */
725 accessTicks = SYSCLK_TICKS_66(accessTime);
726 accessTicks = min(accessTicks, 0x1fU);
727 accessTicks = max(accessTicks, 0x1U);
728 recTicks = SYSCLK_TICKS_66(recTime);
729 recTicks = min(recTicks, 0x1fU);
730 recTicks = max(recTicks, 0x3U);
731 /* Clear out mdma bits and disable udma */
732 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
733 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
734 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
735 break;
736 case controller_kl_ata3:
737 /* 33Mhz cell on KeyLargo */
738 accessTicks = SYSCLK_TICKS(accessTime);
739 accessTicks = max(accessTicks, 1U);
740 accessTicks = min(accessTicks, 0x1fU);
741 accessTime = accessTicks * IDE_SYSCLK_NS;
742 recTicks = SYSCLK_TICKS(recTime);
743 recTicks = max(recTicks, 1U);
744 recTicks = min(recTicks, 0x1fU);
745 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
746 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
747 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
748 break;
749 default: {
750 /* 33Mhz cell on others */
751 int halfTick = 0;
752 int origAccessTime = accessTime;
753 int origRecTime = recTime;
754
755 accessTicks = SYSCLK_TICKS(accessTime);
756 accessTicks = max(accessTicks, 1U);
757 accessTicks = min(accessTicks, 0x1fU);
758 accessTime = accessTicks * IDE_SYSCLK_NS;
759 recTicks = SYSCLK_TICKS(recTime);
760 recTicks = max(recTicks, 2U) - 1;
761 recTicks = min(recTicks, 0x1fU);
762 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
763 if ((accessTicks > 1) &&
764 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
765 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
766 halfTick = 1;
767 accessTicks--;
768 }
769 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
770 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
771 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
772 if (halfTick)
773 *timings |= TR_33_MDMA_HALFTICK;
774 }
775 }
776#ifdef IDE_PMAC_DEBUG
777 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
778 drive->name, speed & 0xf, *timings);
779#endif
780}
781
782static void pmac_ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
783{
784 pmac_ide_hwif_t *pmif =
785 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
786 int ret = 0;
787 u32 *timings, *timings2, tl[2];
788 u8 unit = drive->dn & 1;
789 const u8 speed = drive->dma_mode;
790
791 timings = &pmif->timings[unit];
792 timings2 = &pmif->timings[unit+2];
793
794 /* Copy timings to local image */
795 tl[0] = *timings;
796 tl[1] = *timings2;
797
798 if (speed >= XFER_UDMA_0) {
799 if (pmif->kind == controller_kl_ata4)
800 ret = set_timings_udma_ata4(&tl[0], speed);
801 else if (pmif->kind == controller_un_ata6
802 || pmif->kind == controller_k2_ata6)
803 ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
804 else if (pmif->kind == controller_sh_ata6)
805 ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
806 else
807 ret = -1;
808 } else
809 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
810
811 if (ret)
812 return;
813
814 /* Apply timings to controller */
815 *timings = tl[0];
816 *timings2 = tl[1];
817
818 pmac_ide_do_update_timings(drive);
819}
820
821/*
822 * Blast some well known "safe" values to the timing registers at init or
823 * wakeup from sleep time, before we do real calculation
824 */
825static void
826sanitize_timings(pmac_ide_hwif_t *pmif)
827{
828 unsigned int value, value2 = 0;
829
830 switch(pmif->kind) {
831 case controller_sh_ata6:
832 value = 0x0a820c97;
833 value2 = 0x00033031;
834 break;
835 case controller_un_ata6:
836 case controller_k2_ata6:
837 value = 0x08618a92;
838 value2 = 0x00002921;
839 break;
840 case controller_kl_ata4:
841 value = 0x0008438c;
842 break;
843 case controller_kl_ata3:
844 value = 0x00084526;
845 break;
846 case controller_heathrow:
847 case controller_ohare:
848 default:
849 value = 0x00074526;
850 break;
851 }
852 pmif->timings[0] = pmif->timings[1] = value;
853 pmif->timings[2] = pmif->timings[3] = value2;
854}
855
856static int on_media_bay(pmac_ide_hwif_t *pmif)
857{
858 return pmif->mdev && pmif->mdev->media_bay != NULL;
859}
860
861/* Suspend call back, should be called after the child devices
862 * have actually been suspended
863 */
864static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif)
865{
866 /* We clear the timings */
867 pmif->timings[0] = 0;
868 pmif->timings[1] = 0;
869
870 disable_irq(pmif->irq);
871
872 /* The media bay will handle itself just fine */
873 if (on_media_bay(pmif))
874 return 0;
875
876 /* Kauai has bus control FCRs directly here */
877 if (pmif->kauai_fcr) {
878 u32 fcr = readl(pmif->kauai_fcr);
879 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
880 writel(fcr, pmif->kauai_fcr);
881 }
882
883 /* Disable the bus on older machines and the cell on kauai */
884 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
885 0);
886
887 return 0;
888}
889
890/* Resume call back, should be called before the child devices
891 * are resumed
892 */
893static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
894{
895 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
896 if (!on_media_bay(pmif)) {
897 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
898 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
899 msleep(10);
900 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
901
902 /* Kauai has it different */
903 if (pmif->kauai_fcr) {
904 u32 fcr = readl(pmif->kauai_fcr);
905 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
906 writel(fcr, pmif->kauai_fcr);
907 }
908
909 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
910 }
911
912 /* Sanitize drive timings */
913 sanitize_timings(pmif);
914
915 enable_irq(pmif->irq);
916
917 return 0;
918}
919
920static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
921{
922 pmac_ide_hwif_t *pmif =
923 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
924 struct device_node *np = pmif->node;
925 const char *cable = of_get_property(np, "cable-type", NULL);
926 struct device_node *root = of_find_node_by_path("/");
927 const char *model = of_get_property(root, "model", NULL);
928
929 /* Get cable type from device-tree. */
930 if (cable && !strncmp(cable, "80-", 3)) {
931 /* Some drives fail to detect 80c cable in PowerBook */
932 /* These machine use proprietary short IDE cable anyway */
933 if (!strncmp(model, "PowerBook", 9))
934 return ATA_CBL_PATA40_SHORT;
935 else
936 return ATA_CBL_PATA80;
937 }
938
939 /*
940 * G5's seem to have incorrect cable type in device-tree.
941 * Let's assume they have a 80 conductor cable, this seem
942 * to be always the case unless the user mucked around.
943 */
944 if (of_device_is_compatible(np, "K2-UATA") ||
945 of_device_is_compatible(np, "shasta-ata"))
946 return ATA_CBL_PATA80;
947
948 return ATA_CBL_PATA40;
949}
950
951static void pmac_ide_init_dev(ide_drive_t *drive)
952{
953 ide_hwif_t *hwif = drive->hwif;
954 pmac_ide_hwif_t *pmif =
955 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
956
957 if (on_media_bay(pmif)) {
958 if (check_media_bay(pmif->mdev->media_bay) == MB_CD) {
959 drive->dev_flags &= ~IDE_DFLAG_NOPROBE;
960 return;
961 }
962 drive->dev_flags |= IDE_DFLAG_NOPROBE;
963 }
964}
965
966static const struct ide_tp_ops pmac_tp_ops = {
967 .exec_command = pmac_exec_command,
968 .read_status = ide_read_status,
969 .read_altstatus = ide_read_altstatus,
970 .write_devctl = pmac_write_devctl,
971
972 .dev_select = pmac_dev_select,
973 .tf_load = ide_tf_load,
974 .tf_read = ide_tf_read,
975
976 .input_data = ide_input_data,
977 .output_data = ide_output_data,
978};
979
980static const struct ide_tp_ops pmac_ata6_tp_ops = {
981 .exec_command = pmac_exec_command,
982 .read_status = ide_read_status,
983 .read_altstatus = ide_read_altstatus,
984 .write_devctl = pmac_write_devctl,
985
986 .dev_select = pmac_kauai_dev_select,
987 .tf_load = ide_tf_load,
988 .tf_read = ide_tf_read,
989
990 .input_data = ide_input_data,
991 .output_data = ide_output_data,
992};
993
994static const struct ide_port_ops pmac_ide_ata4_port_ops = {
995 .init_dev = pmac_ide_init_dev,
996 .set_pio_mode = pmac_ide_set_pio_mode,
997 .set_dma_mode = pmac_ide_set_dma_mode,
998 .cable_detect = pmac_ide_cable_detect,
999};
1000
1001static const struct ide_port_ops pmac_ide_port_ops = {
1002 .init_dev = pmac_ide_init_dev,
1003 .set_pio_mode = pmac_ide_set_pio_mode,
1004 .set_dma_mode = pmac_ide_set_dma_mode,
1005};
1006
1007static const struct ide_dma_ops pmac_dma_ops;
1008
1009static const struct ide_port_info pmac_port_info = {
1010 .name = DRV_NAME,
1011 .init_dma = pmac_ide_init_dma,
1012 .chipset = ide_pmac,
1013 .tp_ops = &pmac_tp_ops,
1014 .port_ops = &pmac_ide_port_ops,
1015 .dma_ops = &pmac_dma_ops,
1016 .host_flags = IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
1017 IDE_HFLAG_POST_SET_MODE |
1018 IDE_HFLAG_MMIO |
1019 IDE_HFLAG_UNMASK_IRQS,
1020 .pio_mask = ATA_PIO4,
1021 .mwdma_mask = ATA_MWDMA2,
1022};
1023
1024/*
1025 * Setup, register & probe an IDE channel driven by this driver, this is
1026 * called by one of the 2 probe functions (macio or PCI).
1027 */
1028static int __devinit pmac_ide_setup_device(pmac_ide_hwif_t *pmif,
1029 struct ide_hw *hw)
1030{
1031 struct device_node *np = pmif->node;
1032 const int *bidp;
1033 struct ide_host *host;
1034 ide_hwif_t *hwif;
1035 struct ide_hw *hws[] = { hw };
1036 struct ide_port_info d = pmac_port_info;
1037 int rc;
1038
1039 pmif->broken_dma = pmif->broken_dma_warn = 0;
1040 if (of_device_is_compatible(np, "shasta-ata")) {
1041 pmif->kind = controller_sh_ata6;
1042 d.tp_ops = &pmac_ata6_tp_ops;
1043 d.port_ops = &pmac_ide_ata4_port_ops;
1044 d.udma_mask = ATA_UDMA6;
1045 } else if (of_device_is_compatible(np, "kauai-ata")) {
1046 pmif->kind = controller_un_ata6;
1047 d.tp_ops = &pmac_ata6_tp_ops;
1048 d.port_ops = &pmac_ide_ata4_port_ops;
1049 d.udma_mask = ATA_UDMA5;
1050 } else if (of_device_is_compatible(np, "K2-UATA")) {
1051 pmif->kind = controller_k2_ata6;
1052 d.tp_ops = &pmac_ata6_tp_ops;
1053 d.port_ops = &pmac_ide_ata4_port_ops;
1054 d.udma_mask = ATA_UDMA5;
1055 } else if (of_device_is_compatible(np, "keylargo-ata")) {
1056 if (strcmp(np->name, "ata-4") == 0) {
1057 pmif->kind = controller_kl_ata4;
1058 d.port_ops = &pmac_ide_ata4_port_ops;
1059 d.udma_mask = ATA_UDMA4;
1060 } else
1061 pmif->kind = controller_kl_ata3;
1062 } else if (of_device_is_compatible(np, "heathrow-ata")) {
1063 pmif->kind = controller_heathrow;
1064 } else {
1065 pmif->kind = controller_ohare;
1066 pmif->broken_dma = 1;
1067 }
1068
1069 bidp = of_get_property(np, "AAPL,bus-id", NULL);
1070 pmif->aapl_bus_id = bidp ? *bidp : 0;
1071
1072 /* On Kauai-type controllers, we make sure the FCR is correct */
1073 if (pmif->kauai_fcr)
1074 writel(KAUAI_FCR_UATA_MAGIC |
1075 KAUAI_FCR_UATA_RESET_N |
1076 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1077
1078 /* Make sure we have sane timings */
1079 sanitize_timings(pmif);
1080
1081 /* If we are on a media bay, wait for it to settle and lock it */
1082 if (pmif->mdev)
1083 lock_media_bay(pmif->mdev->media_bay);
1084
1085 host = ide_host_alloc(&d, hws, 1);
1086 if (host == NULL) {
1087 rc = -ENOMEM;
1088 goto bail;
1089 }
1090 hwif = pmif->hwif = host->ports[0];
1091
1092 if (on_media_bay(pmif)) {
1093 /* Fixup bus ID for media bay */
1094 if (!bidp)
1095 pmif->aapl_bus_id = 1;
1096 } else if (pmif->kind == controller_ohare) {
1097 /* The code below is having trouble on some ohare machines
1098 * (timing related ?). Until I can put my hand on one of these
1099 * units, I keep the old way
1100 */
1101 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1102 } else {
1103 /* This is necessary to enable IDE when net-booting */
1104 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1105 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1106 msleep(10);
1107 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1108 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1109 }
1110
1111 printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
1112 "bus ID %d%s, irq %d\n", model_name[pmif->kind],
1113 pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
1114 on_media_bay(pmif) ? " (mediabay)" : "", hw->irq);
1115
1116 rc = ide_host_register(host, &d, hws);
1117 if (rc)
1118 pmif->hwif = NULL;
1119
1120 if (pmif->mdev)
1121 unlock_media_bay(pmif->mdev->media_bay);
1122
1123 bail:
1124 if (rc && host)
1125 ide_host_free(host);
1126 return rc;
1127}
1128
1129static void __devinit pmac_ide_init_ports(struct ide_hw *hw, unsigned long base)
1130{
1131 int i;
1132
1133 for (i = 0; i < 8; ++i)
1134 hw->io_ports_array[i] = base + i * 0x10;
1135
1136 hw->io_ports.ctl_addr = base + 0x160;
1137}
1138
1139/*
1140 * Attach to a macio probed interface
1141 */
1142static int __devinit
1143pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1144{
1145 void __iomem *base;
1146 unsigned long regbase;
1147 pmac_ide_hwif_t *pmif;
1148 int irq, rc;
1149 struct ide_hw hw;
1150
1151 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1152 if (pmif == NULL)
1153 return -ENOMEM;
1154
1155 if (macio_resource_count(mdev) == 0) {
1156 printk(KERN_WARNING "ide-pmac: no address for %s\n",
1157 mdev->ofdev.dev.of_node->full_name);
1158 rc = -ENXIO;
1159 goto out_free_pmif;
1160 }
1161
1162 /* Request memory resource for IO ports */
1163 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1164 printk(KERN_ERR "ide-pmac: can't request MMIO resource for "
1165 "%s!\n", mdev->ofdev.dev.of_node->full_name);
1166 rc = -EBUSY;
1167 goto out_free_pmif;
1168 }
1169
1170 /* XXX This is bogus. Should be fixed in the registry by checking
1171 * the kind of host interrupt controller, a bit like gatwick
1172 * fixes in irq.c. That works well enough for the single case
1173 * where that happens though...
1174 */
1175 if (macio_irq_count(mdev) == 0) {
1176 printk(KERN_WARNING "ide-pmac: no intrs for device %s, using "
1177 "13\n", mdev->ofdev.dev.of_node->full_name);
1178 irq = irq_create_mapping(NULL, 13);
1179 } else
1180 irq = macio_irq(mdev, 0);
1181
1182 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1183 regbase = (unsigned long) base;
1184
1185 pmif->mdev = mdev;
1186 pmif->node = mdev->ofdev.dev.of_node;
1187 pmif->regbase = regbase;
1188 pmif->irq = irq;
1189 pmif->kauai_fcr = NULL;
1190
1191 if (macio_resource_count(mdev) >= 2) {
1192 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1193 printk(KERN_WARNING "ide-pmac: can't request DMA "
1194 "resource for %s!\n",
1195 mdev->ofdev.dev.of_node->full_name);
1196 else
1197 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1198 } else
1199 pmif->dma_regs = NULL;
1200
1201 dev_set_drvdata(&mdev->ofdev.dev, pmif);
1202
1203 memset(&hw, 0, sizeof(hw));
1204 pmac_ide_init_ports(&hw, pmif->regbase);
1205 hw.irq = irq;
1206 hw.dev = &mdev->bus->pdev->dev;
1207 hw.parent = &mdev->ofdev.dev;
1208
1209 rc = pmac_ide_setup_device(pmif, &hw);
1210 if (rc != 0) {
1211 /* The inteface is released to the common IDE layer */
1212 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1213 iounmap(base);
1214 if (pmif->dma_regs) {
1215 iounmap(pmif->dma_regs);
1216 macio_release_resource(mdev, 1);
1217 }
1218 macio_release_resource(mdev, 0);
1219 kfree(pmif);
1220 }
1221
1222 return rc;
1223
1224out_free_pmif:
1225 kfree(pmif);
1226 return rc;
1227}
1228
1229static int
1230pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1231{
1232 pmac_ide_hwif_t *pmif =
1233 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1234 int rc = 0;
1235
1236 if (mesg.event != mdev->ofdev.dev.power.power_state.event
1237 && (mesg.event & PM_EVENT_SLEEP)) {
1238 rc = pmac_ide_do_suspend(pmif);
1239 if (rc == 0)
1240 mdev->ofdev.dev.power.power_state = mesg;
1241 }
1242
1243 return rc;
1244}
1245
1246static int
1247pmac_ide_macio_resume(struct macio_dev *mdev)
1248{
1249 pmac_ide_hwif_t *pmif =
1250 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1251 int rc = 0;
1252
1253 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1254 rc = pmac_ide_do_resume(pmif);
1255 if (rc == 0)
1256 mdev->ofdev.dev.power.power_state = PMSG_ON;
1257 }
1258
1259 return rc;
1260}
1261
1262/*
1263 * Attach to a PCI probed interface
1264 */
1265static int __devinit
1266pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1267{
1268 struct device_node *np;
1269 pmac_ide_hwif_t *pmif;
1270 void __iomem *base;
1271 unsigned long rbase, rlen;
1272 int rc;
1273 struct ide_hw hw;
1274
1275 np = pci_device_to_OF_node(pdev);
1276 if (np == NULL) {
1277 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1278 return -ENODEV;
1279 }
1280
1281 pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1282 if (pmif == NULL)
1283 return -ENOMEM;
1284
1285 if (pci_enable_device(pdev)) {
1286 printk(KERN_WARNING "ide-pmac: Can't enable PCI device for "
1287 "%s\n", np->full_name);
1288 rc = -ENXIO;
1289 goto out_free_pmif;
1290 }
1291 pci_set_master(pdev);
1292
1293 if (pci_request_regions(pdev, "Kauai ATA")) {
1294 printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for "
1295 "%s\n", np->full_name);
1296 rc = -ENXIO;
1297 goto out_free_pmif;
1298 }
1299
1300 pmif->mdev = NULL;
1301 pmif->node = np;
1302
1303 rbase = pci_resource_start(pdev, 0);
1304 rlen = pci_resource_len(pdev, 0);
1305
1306 base = ioremap(rbase, rlen);
1307 pmif->regbase = (unsigned long) base + 0x2000;
1308 pmif->dma_regs = base + 0x1000;
1309 pmif->kauai_fcr = base;
1310 pmif->irq = pdev->irq;
1311
1312 pci_set_drvdata(pdev, pmif);
1313
1314 memset(&hw, 0, sizeof(hw));
1315 pmac_ide_init_ports(&hw, pmif->regbase);
1316 hw.irq = pdev->irq;
1317 hw.dev = &pdev->dev;
1318
1319 rc = pmac_ide_setup_device(pmif, &hw);
1320 if (rc != 0) {
1321 /* The inteface is released to the common IDE layer */
1322 pci_set_drvdata(pdev, NULL);
1323 iounmap(base);
1324 pci_release_regions(pdev);
1325 kfree(pmif);
1326 }
1327
1328 return rc;
1329
1330out_free_pmif:
1331 kfree(pmif);
1332 return rc;
1333}
1334
1335static int
1336pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1337{
1338 pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
1339 int rc = 0;
1340
1341 if (mesg.event != pdev->dev.power.power_state.event
1342 && (mesg.event & PM_EVENT_SLEEP)) {
1343 rc = pmac_ide_do_suspend(pmif);
1344 if (rc == 0)
1345 pdev->dev.power.power_state = mesg;
1346 }
1347
1348 return rc;
1349}
1350
1351static int
1352pmac_ide_pci_resume(struct pci_dev *pdev)
1353{
1354 pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
1355 int rc = 0;
1356
1357 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1358 rc = pmac_ide_do_resume(pmif);
1359 if (rc == 0)
1360 pdev->dev.power.power_state = PMSG_ON;
1361 }
1362
1363 return rc;
1364}
1365
1366#ifdef CONFIG_PMAC_MEDIABAY
1367static void pmac_ide_macio_mb_event(struct macio_dev* mdev, int mb_state)
1368{
1369 pmac_ide_hwif_t *pmif =
1370 (pmac_ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1371
1372 switch(mb_state) {
1373 case MB_CD:
1374 if (!pmif->hwif->present)
1375 ide_port_scan(pmif->hwif);
1376 break;
1377 default:
1378 if (pmif->hwif->present)
1379 ide_port_unregister_devices(pmif->hwif);
1380 }
1381}
1382#endif /* CONFIG_PMAC_MEDIABAY */
1383
1384
1385static struct of_device_id pmac_ide_macio_match[] =
1386{
1387 {
1388 .name = "IDE",
1389 },
1390 {
1391 .name = "ATA",
1392 },
1393 {
1394 .type = "ide",
1395 },
1396 {
1397 .type = "ata",
1398 },
1399 {},
1400};
1401
1402static struct macio_driver pmac_ide_macio_driver =
1403{
1404 .driver = {
1405 .name = "ide-pmac",
1406 .owner = THIS_MODULE,
1407 .of_match_table = pmac_ide_macio_match,
1408 },
1409 .probe = pmac_ide_macio_attach,
1410 .suspend = pmac_ide_macio_suspend,
1411 .resume = pmac_ide_macio_resume,
1412#ifdef CONFIG_PMAC_MEDIABAY
1413 .mediabay_event = pmac_ide_macio_mb_event,
1414#endif
1415};
1416
1417static const struct pci_device_id pmac_ide_pci_match[] = {
1418 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA), 0 },
1419 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100), 0 },
1420 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100), 0 },
1421 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA), 0 },
1422 { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA), 0 },
1423 {},
1424};
1425
1426static struct pci_driver pmac_ide_pci_driver = {
1427 .name = "ide-pmac",
1428 .id_table = pmac_ide_pci_match,
1429 .probe = pmac_ide_pci_attach,
1430 .suspend = pmac_ide_pci_suspend,
1431 .resume = pmac_ide_pci_resume,
1432};
1433MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1434
1435int __init pmac_ide_probe(void)
1436{
1437 int error;
1438
1439 if (!machine_is(powermac))
1440 return -ENODEV;
1441
1442#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1443 error = pci_register_driver(&pmac_ide_pci_driver);
1444 if (error)
1445 goto out;
1446 error = macio_register_driver(&pmac_ide_macio_driver);
1447 if (error) {
1448 pci_unregister_driver(&pmac_ide_pci_driver);
1449 goto out;
1450 }
1451#else
1452 error = macio_register_driver(&pmac_ide_macio_driver);
1453 if (error)
1454 goto out;
1455 error = pci_register_driver(&pmac_ide_pci_driver);
1456 if (error) {
1457 macio_unregister_driver(&pmac_ide_macio_driver);
1458 goto out;
1459 }
1460#endif
1461out:
1462 return error;
1463}
1464
1465/*
1466 * pmac_ide_build_dmatable builds the DBDMA command list
1467 * for a transfer and sets the DBDMA channel to point to it.
1468 */
1469static int pmac_ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
1470{
1471 ide_hwif_t *hwif = drive->hwif;
1472 pmac_ide_hwif_t *pmif =
1473 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1474 struct dbdma_cmd *table;
1475 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1476 struct scatterlist *sg;
1477 int wr = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
1478 int i = cmd->sg_nents, count = 0;
1479
1480 /* DMA table is already aligned */
1481 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1482
1483 /* Make sure DMA controller is stopped (necessary ?) */
1484 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1485 while (readl(&dma->status) & RUN)
1486 udelay(1);
1487
1488 /* Build DBDMA commands list */
1489 sg = hwif->sg_table;
1490 while (i && sg_dma_len(sg)) {
1491 u32 cur_addr;
1492 u32 cur_len;
1493
1494 cur_addr = sg_dma_address(sg);
1495 cur_len = sg_dma_len(sg);
1496
1497 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1498 if (pmif->broken_dma_warn == 0) {
1499 printk(KERN_WARNING "%s: DMA on non aligned address, "
1500 "switching to PIO on Ohare chipset\n", drive->name);
1501 pmif->broken_dma_warn = 1;
1502 }
1503 return 0;
1504 }
1505 while (cur_len) {
1506 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1507
1508 if (count++ >= MAX_DCMDS) {
1509 printk(KERN_WARNING "%s: DMA table too small\n",
1510 drive->name);
1511 return 0;
1512 }
1513 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1514 st_le16(&table->req_count, tc);
1515 st_le32(&table->phy_addr, cur_addr);
1516 table->cmd_dep = 0;
1517 table->xfer_status = 0;
1518 table->res_count = 0;
1519 cur_addr += tc;
1520 cur_len -= tc;
1521 ++table;
1522 }
1523 sg = sg_next(sg);
1524 i--;
1525 }
1526
1527 /* convert the last command to an input/output last command */
1528 if (count) {
1529 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1530 /* add the stop command to the end of the list */
1531 memset(table, 0, sizeof(struct dbdma_cmd));
1532 st_le16(&table->command, DBDMA_STOP);
1533 mb();
1534 writel(hwif->dmatable_dma, &dma->cmdptr);
1535 return 1;
1536 }
1537
1538 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1539
1540 return 0; /* revert to PIO for this request */
1541}
1542
1543/*
1544 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1545 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1546 */
1547static int pmac_ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
1548{
1549 ide_hwif_t *hwif = drive->hwif;
1550 pmac_ide_hwif_t *pmif =
1551 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1552 u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4);
1553 u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
1554
1555 if (pmac_ide_build_dmatable(drive, cmd) == 0)
1556 return 1;
1557
1558 /* Apple adds 60ns to wrDataSetup on reads */
1559 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1560 writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL),
1561 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1562 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1563 }
1564
1565 return 0;
1566}
1567
1568/*
1569 * Kick the DMA controller into life after the DMA command has been issued
1570 * to the drive.
1571 */
1572static void
1573pmac_ide_dma_start(ide_drive_t *drive)
1574{
1575 ide_hwif_t *hwif = drive->hwif;
1576 pmac_ide_hwif_t *pmif =
1577 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1578 volatile struct dbdma_regs __iomem *dma;
1579
1580 dma = pmif->dma_regs;
1581
1582 writel((RUN << 16) | RUN, &dma->control);
1583 /* Make sure it gets to the controller right now */
1584 (void)readl(&dma->control);
1585}
1586
1587/*
1588 * After a DMA transfer, make sure the controller is stopped
1589 */
1590static int
1591pmac_ide_dma_end (ide_drive_t *drive)
1592{
1593 ide_hwif_t *hwif = drive->hwif;
1594 pmac_ide_hwif_t *pmif =
1595 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1596 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1597 u32 dstat;
1598
1599 dstat = readl(&dma->status);
1600 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1601
1602 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1603 * in theory, but with ATAPI decices doing buffer underruns, that would
1604 * cause us to disable DMA, which isn't what we want
1605 */
1606 return (dstat & (RUN|DEAD)) != RUN;
1607}
1608
1609/*
1610 * Check out that the interrupt we got was for us. We can't always know this
1611 * for sure with those Apple interfaces (well, we could on the recent ones but
1612 * that's not implemented yet), on the other hand, we don't have shared interrupts
1613 * so it's not really a problem
1614 */
1615static int
1616pmac_ide_dma_test_irq (ide_drive_t *drive)
1617{
1618 ide_hwif_t *hwif = drive->hwif;
1619 pmac_ide_hwif_t *pmif =
1620 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1621 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1622 unsigned long status, timeout;
1623
1624 /* We have to things to deal with here:
1625 *
1626 * - The dbdma won't stop if the command was started
1627 * but completed with an error without transferring all
1628 * datas. This happens when bad blocks are met during
1629 * a multi-block transfer.
1630 *
1631 * - The dbdma fifo hasn't yet finished flushing to
1632 * to system memory when the disk interrupt occurs.
1633 *
1634 */
1635
1636 /* If ACTIVE is cleared, the STOP command have passed and
1637 * transfer is complete.
1638 */
1639 status = readl(&dma->status);
1640 if (!(status & ACTIVE))
1641 return 1;
1642
1643 /* If dbdma didn't execute the STOP command yet, the
1644 * active bit is still set. We consider that we aren't
1645 * sharing interrupts (which is hopefully the case with
1646 * those controllers) and so we just try to flush the
1647 * channel for pending data in the fifo
1648 */
1649 udelay(1);
1650 writel((FLUSH << 16) | FLUSH, &dma->control);
1651 timeout = 0;
1652 for (;;) {
1653 udelay(1);
1654 status = readl(&dma->status);
1655 if ((status & FLUSH) == 0)
1656 break;
1657 if (++timeout > 100) {
1658 printk(KERN_WARNING "ide%d, ide_dma_test_irq timeout flushing channel\n",
1659 hwif->index);
1660 break;
1661 }
1662 }
1663 return 1;
1664}
1665
1666static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
1667{
1668}
1669
1670static void
1671pmac_ide_dma_lost_irq (ide_drive_t *drive)
1672{
1673 ide_hwif_t *hwif = drive->hwif;
1674 pmac_ide_hwif_t *pmif =
1675 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1676 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1677 unsigned long status = readl(&dma->status);
1678
1679 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1680}
1681
1682static const struct ide_dma_ops pmac_dma_ops = {
1683 .dma_host_set = pmac_ide_dma_host_set,
1684 .dma_setup = pmac_ide_dma_setup,
1685 .dma_start = pmac_ide_dma_start,
1686 .dma_end = pmac_ide_dma_end,
1687 .dma_test_irq = pmac_ide_dma_test_irq,
1688 .dma_lost_irq = pmac_ide_dma_lost_irq,
1689};
1690
1691/*
1692 * Allocate the data structures needed for using DMA with an interface
1693 * and fill the proper list of functions pointers
1694 */
1695static int __devinit pmac_ide_init_dma(ide_hwif_t *hwif,
1696 const struct ide_port_info *d)
1697{
1698 pmac_ide_hwif_t *pmif =
1699 (pmac_ide_hwif_t *)dev_get_drvdata(hwif->gendev.parent);
1700 struct pci_dev *dev = to_pci_dev(hwif->dev);
1701
1702 /* We won't need pci_dev if we switch to generic consistent
1703 * DMA routines ...
1704 */
1705 if (dev == NULL || pmif->dma_regs == 0)
1706 return -ENODEV;
1707 /*
1708 * Allocate space for the DBDMA commands.
1709 * The +2 is +1 for the stop command and +1 to allow for
1710 * aligning the start address to a multiple of 16 bytes.
1711 */
1712 pmif->dma_table_cpu = pci_alloc_consistent(
1713 dev,
1714 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1715 &hwif->dmatable_dma);
1716 if (pmif->dma_table_cpu == NULL) {
1717 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1718 hwif->name);
1719 return -ENOMEM;
1720 }
1721
1722 hwif->sg_max_nents = MAX_DCMDS;
1723
1724 return 0;
1725}
1726
1727module_init(pmac_ide_probe);
1728
1729MODULE_LICENSE("GPL");