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1/*
2 * arch/powerpc/sysdev/qe_lib/ucc.c
3 *
4 * QE UCC API Set - UCC specific routines implementations.
5 *
6 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
7 *
8 * Authors: Shlomi Gridish <gridish@freescale.com>
9 * Li Yang <leoli@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/errno.h>
19#include <linux/stddef.h>
20#include <linux/spinlock.h>
21#include <linux/export.h>
22
23#include <asm/irq.h>
24#include <asm/io.h>
25#include <asm/immap_qe.h>
26#include <asm/qe.h>
27#include <asm/ucc.h>
28
29int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
30{
31 unsigned long flags;
32
33 if (ucc_num > UCC_MAX_NUM - 1)
34 return -EINVAL;
35
36 spin_lock_irqsave(&cmxgcr_lock, flags);
37 clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
38 ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
39 spin_unlock_irqrestore(&cmxgcr_lock, flags);
40
41 return 0;
42}
43EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng);
44
45/* Configure the UCC to either Slow or Fast.
46 *
47 * A given UCC can be figured to support either "slow" devices (e.g. UART)
48 * or "fast" devices (e.g. Ethernet).
49 *
50 * 'ucc_num' is the UCC number, from 0 - 7.
51 *
52 * This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit
53 * must always be set to 1.
54 */
55int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
56{
57 u8 __iomem *guemr;
58
59 /* The GUEMR register is at the same location for both slow and fast
60 devices, so we just use uccX.slow.guemr. */
61 switch (ucc_num) {
62 case 0: guemr = &qe_immr->ucc1.slow.guemr;
63 break;
64 case 1: guemr = &qe_immr->ucc2.slow.guemr;
65 break;
66 case 2: guemr = &qe_immr->ucc3.slow.guemr;
67 break;
68 case 3: guemr = &qe_immr->ucc4.slow.guemr;
69 break;
70 case 4: guemr = &qe_immr->ucc5.slow.guemr;
71 break;
72 case 5: guemr = &qe_immr->ucc6.slow.guemr;
73 break;
74 case 6: guemr = &qe_immr->ucc7.slow.guemr;
75 break;
76 case 7: guemr = &qe_immr->ucc8.slow.guemr;
77 break;
78 default:
79 return -EINVAL;
80 }
81
82 clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
83 UCC_GUEMR_SET_RESERVED3 | speed);
84
85 return 0;
86}
87
88static void get_cmxucr_reg(unsigned int ucc_num, __be32 __iomem **cmxucr,
89 unsigned int *reg_num, unsigned int *shift)
90{
91 unsigned int cmx = ((ucc_num & 1) << 1) + (ucc_num > 3);
92
93 *reg_num = cmx + 1;
94 *cmxucr = &qe_immr->qmx.cmxucr[cmx];
95 *shift = 16 - 8 * (ucc_num & 2);
96}
97
98int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
99{
100 __be32 __iomem *cmxucr;
101 unsigned int reg_num;
102 unsigned int shift;
103
104 /* check if the UCC number is in range. */
105 if (ucc_num > UCC_MAX_NUM - 1)
106 return -EINVAL;
107
108 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
109
110 if (set)
111 setbits32(cmxucr, mask << shift);
112 else
113 clrbits32(cmxucr, mask << shift);
114
115 return 0;
116}
117
118int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
119 enum comm_dir mode)
120{
121 __be32 __iomem *cmxucr;
122 unsigned int reg_num;
123 unsigned int shift;
124 u32 clock_bits = 0;
125
126 /* check if the UCC number is in range. */
127 if (ucc_num > UCC_MAX_NUM - 1)
128 return -EINVAL;
129
130 /* The communications direction must be RX or TX */
131 if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))
132 return -EINVAL;
133
134 get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
135
136 switch (reg_num) {
137 case 1:
138 switch (clock) {
139 case QE_BRG1: clock_bits = 1; break;
140 case QE_BRG2: clock_bits = 2; break;
141 case QE_BRG7: clock_bits = 3; break;
142 case QE_BRG8: clock_bits = 4; break;
143 case QE_CLK9: clock_bits = 5; break;
144 case QE_CLK10: clock_bits = 6; break;
145 case QE_CLK11: clock_bits = 7; break;
146 case QE_CLK12: clock_bits = 8; break;
147 case QE_CLK15: clock_bits = 9; break;
148 case QE_CLK16: clock_bits = 10; break;
149 default: break;
150 }
151 break;
152 case 2:
153 switch (clock) {
154 case QE_BRG5: clock_bits = 1; break;
155 case QE_BRG6: clock_bits = 2; break;
156 case QE_BRG7: clock_bits = 3; break;
157 case QE_BRG8: clock_bits = 4; break;
158 case QE_CLK13: clock_bits = 5; break;
159 case QE_CLK14: clock_bits = 6; break;
160 case QE_CLK19: clock_bits = 7; break;
161 case QE_CLK20: clock_bits = 8; break;
162 case QE_CLK15: clock_bits = 9; break;
163 case QE_CLK16: clock_bits = 10; break;
164 default: break;
165 }
166 break;
167 case 3:
168 switch (clock) {
169 case QE_BRG9: clock_bits = 1; break;
170 case QE_BRG10: clock_bits = 2; break;
171 case QE_BRG15: clock_bits = 3; break;
172 case QE_BRG16: clock_bits = 4; break;
173 case QE_CLK3: clock_bits = 5; break;
174 case QE_CLK4: clock_bits = 6; break;
175 case QE_CLK17: clock_bits = 7; break;
176 case QE_CLK18: clock_bits = 8; break;
177 case QE_CLK7: clock_bits = 9; break;
178 case QE_CLK8: clock_bits = 10; break;
179 case QE_CLK16: clock_bits = 11; break;
180 default: break;
181 }
182 break;
183 case 4:
184 switch (clock) {
185 case QE_BRG13: clock_bits = 1; break;
186 case QE_BRG14: clock_bits = 2; break;
187 case QE_BRG15: clock_bits = 3; break;
188 case QE_BRG16: clock_bits = 4; break;
189 case QE_CLK5: clock_bits = 5; break;
190 case QE_CLK6: clock_bits = 6; break;
191 case QE_CLK21: clock_bits = 7; break;
192 case QE_CLK22: clock_bits = 8; break;
193 case QE_CLK7: clock_bits = 9; break;
194 case QE_CLK8: clock_bits = 10; break;
195 case QE_CLK16: clock_bits = 11; break;
196 default: break;
197 }
198 break;
199 default: break;
200 }
201
202 /* Check for invalid combination of clock and UCC number */
203 if (!clock_bits)
204 return -ENOENT;
205
206 if (mode == COMM_DIR_RX)
207 shift += 4;
208
209 clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
210 clock_bits << shift);
211
212 return 0;
213}