Loading...
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * MPC85xx/86xx PCI Express structure define
4 *
5 * Copyright 2007,2011 Freescale Semiconductor, Inc
6 */
7
8#ifdef __KERNEL__
9#ifndef __POWERPC_FSL_PCI_H
10#define __POWERPC_FSL_PCI_H
11
12struct platform_device;
13
14
15/* FSL PCI controller BRR1 register */
16#define PCI_FSL_BRR1 0xbf8
17#define PCI_FSL_BRR1_VER 0xffff
18
19#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
20#define PCIE_LTSSM_L0 0x16 /* L0 state */
21#define PCIE_FSL_CSR_CLASSCODE 0x474 /* FSL GPEX CSR */
22#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
23#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
24#define PIWAR_EN 0x80000000 /* Enable */
25#define PIWAR_PF 0x20000000 /* prefetch */
26#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
27#define PIWAR_READ_SNOOP 0x00050000
28#define PIWAR_WRITE_SNOOP 0x00005000
29#define PIWAR_SZ_MASK 0x0000003f
30
31#define PEX_PMCR_PTOMR 0x1
32#define PEX_PMCR_EXL2S 0x2
33
34#define PME_DISR_EN_PTOD 0x00008000
35#define PME_DISR_EN_ENL23D 0x00002000
36#define PME_DISR_EN_EXL23D 0x00001000
37
38/* PCI/PCI Express outbound window reg */
39struct pci_outbound_window_regs {
40 __be32 potar; /* 0x.0 - Outbound translation address register */
41 __be32 potear; /* 0x.4 - Outbound translation extended address register */
42 __be32 powbar; /* 0x.8 - Outbound window base address register */
43 u8 res1[4];
44 __be32 powar; /* 0x.10 - Outbound window attributes register */
45 u8 res2[12];
46};
47
48/* PCI/PCI Express inbound window reg */
49struct pci_inbound_window_regs {
50 __be32 pitar; /* 0x.0 - Inbound translation address register */
51 u8 res1[4];
52 __be32 piwbar; /* 0x.8 - Inbound window base address register */
53 __be32 piwbear; /* 0x.c - Inbound window base extended address register */
54 __be32 piwar; /* 0x.10 - Inbound window attributes register */
55 u8 res2[12];
56};
57
58/* PCI/PCI Express IO block registers for 85xx/86xx */
59struct ccsr_pci {
60 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
61 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
62 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
63 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
64 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
65 __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
66 __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
67 u8 res2[4];
68 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
69 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
70 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
71 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
72 u8 res3[3016];
73 __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
74 __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
75
76/* PCI/PCI Express outbound window 0-4
77 * Window 0 is the default window and is the only window enabled upon reset.
78 * The default outbound register set is used when a transaction misses
79 * in all of the other outbound windows.
80 */
81 struct pci_outbound_window_regs pow[5];
82 u8 res14[96];
83 struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
84 u8 res6[96];
85/* PCI/PCI Express inbound window 3-0
86 * inbound window 1 supports only a 32-bit base address and does not
87 * define an inbound window base extended address register.
88 */
89 struct pci_inbound_window_regs piw[4];
90
91 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
92 u8 res21[4];
93 __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
94 u8 res22[4];
95 __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
96 u8 res23[12];
97 __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
98 u8 res24[4];
99 __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
100 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
101 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
102 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
103 u8 res_e38[200];
104 __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
105 u8 res_f04[16];
106 __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
107#define PEX_CSR0_LTSSM_MASK 0xFC
108#define PEX_CSR0_LTSSM_SHIFT 2
109#define PEX_CSR0_LTSSM_L0 0x11
110 __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
111 u8 res_f1c[228];
112
113};
114
115extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
116extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
117extern int mpc83xx_add_bridge(struct device_node *dev);
118u64 fsl_pci_immrbar_base(struct pci_controller *hose);
119
120extern struct device_node *fsl_pci_primary;
121
122#ifdef CONFIG_PCI
123void __init fsl_pci_assign_primary(void);
124#else
125static inline void fsl_pci_assign_primary(void) {}
126#endif
127
128#ifdef CONFIG_FSL_PCI
129extern int fsl_pci_mcheck_exception(struct pt_regs *);
130#else
131static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
132#endif
133
134#endif /* __POWERPC_FSL_PCI_H */
135#endif /* __KERNEL__ */
1/*
2 * MPC85xx/86xx PCI Express structure define
3 *
4 * Copyright 2007,2011 Freescale Semiconductor, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifdef __KERNEL__
14#ifndef __POWERPC_FSL_PCI_H
15#define __POWERPC_FSL_PCI_H
16
17#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
18#define PCIE_LTSSM_L0 0x16 /* L0 state */
19#define PIWAR_EN 0x80000000 /* Enable */
20#define PIWAR_PF 0x20000000 /* prefetch */
21#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
22#define PIWAR_READ_SNOOP 0x00050000
23#define PIWAR_WRITE_SNOOP 0x00005000
24#define PIWAR_SZ_MASK 0x0000003f
25
26/* PCI/PCI Express outbound window reg */
27struct pci_outbound_window_regs {
28 __be32 potar; /* 0x.0 - Outbound translation address register */
29 __be32 potear; /* 0x.4 - Outbound translation extended address register */
30 __be32 powbar; /* 0x.8 - Outbound window base address register */
31 u8 res1[4];
32 __be32 powar; /* 0x.10 - Outbound window attributes register */
33 u8 res2[12];
34};
35
36/* PCI/PCI Express inbound window reg */
37struct pci_inbound_window_regs {
38 __be32 pitar; /* 0x.0 - Inbound translation address register */
39 u8 res1[4];
40 __be32 piwbar; /* 0x.8 - Inbound window base address register */
41 __be32 piwbear; /* 0x.c - Inbound window base extended address register */
42 __be32 piwar; /* 0x.10 - Inbound window attributes register */
43 u8 res2[12];
44};
45
46/* PCI/PCI Express IO block registers for 85xx/86xx */
47struct ccsr_pci {
48 __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
49 __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
50 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
51 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
52 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
53 __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
54 __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
55 u8 res2[4];
56 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
57 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
58 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
59 __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
60 u8 res3[3024];
61
62/* PCI/PCI Express outbound window 0-4
63 * Window 0 is the default window and is the only window enabled upon reset.
64 * The default outbound register set is used when a transaction misses
65 * in all of the other outbound windows.
66 */
67 struct pci_outbound_window_regs pow[5];
68 u8 res14[96];
69 struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
70 u8 res6[96];
71/* PCI/PCI Express inbound window 3-0
72 * inbound window 1 supports only a 32-bit base address and does not
73 * define an inbound window base extended address register.
74 */
75 struct pci_inbound_window_regs piw[4];
76
77 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
78 u8 res21[4];
79 __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
80 u8 res22[4];
81 __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
82 u8 res23[12];
83 __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
84 u8 res24[4];
85 __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
86 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
87 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
88 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
89};
90
91extern int fsl_add_bridge(struct device_node *dev, int is_primary);
92extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
93extern int mpc83xx_add_bridge(struct device_node *dev);
94u64 fsl_pci_immrbar_base(struct pci_controller *hose);
95
96#endif /* __POWERPC_FSL_PCI_H */
97#endif /* __KERNEL__ */