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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale LBC and UPM routines.
4 *
5 * Copyright © 2007-2008 MontaVista Software, Inc.
6 * Copyright © 2010 Freescale Semiconductor
7 *
8 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
9 * Author: Jack Lan <Jack.Lan@freescale.com>
10 * Author: Roy Zang <tie-fei.zang@freescale.com>
11 */
12
13#include <linux/init.h>
14#include <linux/export.h>
15#include <linux/kernel.h>
16#include <linux/compiler.h>
17#include <linux/spinlock.h>
18#include <linux/types.h>
19#include <linux/io.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
23#include <linux/slab.h>
24#include <linux/sched.h>
25#include <linux/platform_device.h>
26#include <linux/interrupt.h>
27#include <linux/mod_devicetable.h>
28#include <linux/syscore_ops.h>
29#include <asm/fsl_lbc.h>
30
31static DEFINE_SPINLOCK(fsl_lbc_lock);
32struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
33EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
34
35/**
36 * fsl_lbc_addr - convert the base address
37 * @addr_base: base address of the memory bank
38 *
39 * This function converts a base address of lbc into the right format for the
40 * BR register. If the SOC has eLBC then it returns 32bit physical address
41 * else it converts a 34bit local bus physical address to correct format of
42 * 32bit address for BR register (Example: MPC8641).
43 */
44u32 fsl_lbc_addr(phys_addr_t addr_base)
45{
46 struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
47 u32 addr = addr_base & 0xffff8000;
48
49 if (of_device_is_compatible(np, "fsl,elbc"))
50 return addr;
51
52 return addr | ((addr_base & 0x300000000ull) >> 19);
53}
54EXPORT_SYMBOL(fsl_lbc_addr);
55
56/**
57 * fsl_lbc_find - find Localbus bank
58 * @addr_base: base address of the memory bank
59 *
60 * This function walks LBC banks comparing "Base address" field of the BR
61 * registers with the supplied addr_base argument. When bases match this
62 * function returns bank number (starting with 0), otherwise it returns
63 * appropriate errno value.
64 */
65int fsl_lbc_find(phys_addr_t addr_base)
66{
67 int i;
68 struct fsl_lbc_regs __iomem *lbc;
69
70 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
71 return -ENODEV;
72
73 lbc = fsl_lbc_ctrl_dev->regs;
74 for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
75 u32 br = in_be32(&lbc->bank[i].br);
76 u32 or = in_be32(&lbc->bank[i].or);
77
78 if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
79 return i;
80 }
81
82 return -ENOENT;
83}
84EXPORT_SYMBOL(fsl_lbc_find);
85
86/**
87 * fsl_upm_find - find pre-programmed UPM via base address
88 * @addr_base: base address of the memory bank controlled by the UPM
89 * @upm: pointer to the allocated fsl_upm structure
90 *
91 * This function fills fsl_upm structure so you can use it with the rest of
92 * UPM API. On success this function returns 0, otherwise it returns
93 * appropriate errno value.
94 */
95int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
96{
97 int bank;
98 u32 br;
99 struct fsl_lbc_regs __iomem *lbc;
100
101 bank = fsl_lbc_find(addr_base);
102 if (bank < 0)
103 return bank;
104
105 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
106 return -ENODEV;
107
108 lbc = fsl_lbc_ctrl_dev->regs;
109 br = in_be32(&lbc->bank[bank].br);
110
111 switch (br & BR_MSEL) {
112 case BR_MS_UPMA:
113 upm->mxmr = &lbc->mamr;
114 break;
115 case BR_MS_UPMB:
116 upm->mxmr = &lbc->mbmr;
117 break;
118 case BR_MS_UPMC:
119 upm->mxmr = &lbc->mcmr;
120 break;
121 default:
122 return -EINVAL;
123 }
124
125 switch (br & BR_PS) {
126 case BR_PS_8:
127 upm->width = 8;
128 break;
129 case BR_PS_16:
130 upm->width = 16;
131 break;
132 case BR_PS_32:
133 upm->width = 32;
134 break;
135 default:
136 return -EINVAL;
137 }
138
139 return 0;
140}
141EXPORT_SYMBOL(fsl_upm_find);
142
143/**
144 * fsl_upm_run_pattern - actually run an UPM pattern
145 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
146 * @io_base: remapped pointer to where memory access should happen
147 * @mar: MAR register content during pattern execution
148 *
149 * This function triggers dummy write to the memory specified by the io_base,
150 * thus UPM pattern actually executed. Note that mar usage depends on the
151 * pre-programmed AMX bits in the UPM RAM.
152 */
153int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
154{
155 int ret = 0;
156 unsigned long flags;
157
158 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
159 return -ENODEV;
160
161 spin_lock_irqsave(&fsl_lbc_lock, flags);
162
163 out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
164
165 switch (upm->width) {
166 case 8:
167 out_8(io_base, 0x0);
168 break;
169 case 16:
170 out_be16(io_base, 0x0);
171 break;
172 case 32:
173 out_be32(io_base, 0x0);
174 break;
175 default:
176 ret = -EINVAL;
177 break;
178 }
179
180 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
181
182 return ret;
183}
184EXPORT_SYMBOL(fsl_upm_run_pattern);
185
186static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
187 struct device_node *node)
188{
189 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
190
191 /* clear event registers */
192 setbits32(&lbc->ltesr, LTESR_CLEAR);
193 out_be32(&lbc->lteatr, 0);
194 out_be32(&lbc->ltear, 0);
195 out_be32(&lbc->lteccr, LTECCR_CLEAR);
196 out_be32(&lbc->ltedr, LTEDR_ENABLE);
197
198 /* Set the monitor timeout value to the maximum for erratum A001 */
199 if (of_device_is_compatible(node, "fsl,elbc"))
200 clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
201
202 return 0;
203}
204
205/*
206 * NOTE: This interrupt is used to report localbus events of various kinds,
207 * such as transaction errors on the chipselects.
208 */
209
210static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
211{
212 struct fsl_lbc_ctrl *ctrl = data;
213 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
214 u32 status;
215 unsigned long flags;
216
217 spin_lock_irqsave(&fsl_lbc_lock, flags);
218 status = in_be32(&lbc->ltesr);
219 if (!status) {
220 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
221 return IRQ_NONE;
222 }
223
224 out_be32(&lbc->ltesr, LTESR_CLEAR);
225 out_be32(&lbc->lteatr, 0);
226 out_be32(&lbc->ltear, 0);
227 ctrl->irq_status = status;
228
229 if (status & LTESR_BM)
230 dev_err(ctrl->dev, "Local bus monitor time-out: "
231 "LTESR 0x%08X\n", status);
232 if (status & LTESR_WP)
233 dev_err(ctrl->dev, "Write protect error: "
234 "LTESR 0x%08X\n", status);
235 if (status & LTESR_ATMW)
236 dev_err(ctrl->dev, "Atomic write error: "
237 "LTESR 0x%08X\n", status);
238 if (status & LTESR_ATMR)
239 dev_err(ctrl->dev, "Atomic read error: "
240 "LTESR 0x%08X\n", status);
241 if (status & LTESR_CS)
242 dev_err(ctrl->dev, "Chip select error: "
243 "LTESR 0x%08X\n", status);
244 if (status & LTESR_FCT) {
245 dev_err(ctrl->dev, "FCM command time-out: "
246 "LTESR 0x%08X\n", status);
247 smp_wmb();
248 wake_up(&ctrl->irq_wait);
249 }
250 if (status & LTESR_PAR) {
251 dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
252 "LTESR 0x%08X\n", status);
253 smp_wmb();
254 wake_up(&ctrl->irq_wait);
255 }
256 if (status & LTESR_CC) {
257 smp_wmb();
258 wake_up(&ctrl->irq_wait);
259 }
260 if (status & ~LTESR_MASK)
261 dev_err(ctrl->dev, "Unknown error: "
262 "LTESR 0x%08X\n", status);
263 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
264 return IRQ_HANDLED;
265}
266
267/*
268 * fsl_lbc_ctrl_probe
269 *
270 * called by device layer when it finds a device matching
271 * one our driver can handled. This code allocates all of
272 * the resources needed for the controller only. The
273 * resources for the NAND banks themselves are allocated
274 * in the chip probe function.
275*/
276
277static int fsl_lbc_ctrl_probe(struct platform_device *dev)
278{
279 int ret;
280
281 if (!dev->dev.of_node) {
282 dev_err(&dev->dev, "Device OF-Node is NULL");
283 return -EFAULT;
284 }
285
286 fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
287 if (!fsl_lbc_ctrl_dev)
288 return -ENOMEM;
289
290 dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
291
292 spin_lock_init(&fsl_lbc_ctrl_dev->lock);
293 init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
294
295 fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
296 if (!fsl_lbc_ctrl_dev->regs) {
297 dev_err(&dev->dev, "failed to get memory region\n");
298 ret = -ENODEV;
299 goto err;
300 }
301
302 fsl_lbc_ctrl_dev->irq[0] = irq_of_parse_and_map(dev->dev.of_node, 0);
303 if (!fsl_lbc_ctrl_dev->irq[0]) {
304 dev_err(&dev->dev, "failed to get irq resource\n");
305 ret = -ENODEV;
306 goto err;
307 }
308
309 fsl_lbc_ctrl_dev->dev = &dev->dev;
310
311 ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, dev->dev.of_node);
312 if (ret < 0)
313 goto err;
314
315 ret = request_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_irq, 0,
316 "fsl-lbc", fsl_lbc_ctrl_dev);
317 if (ret != 0) {
318 dev_err(&dev->dev, "failed to install irq (%d)\n",
319 fsl_lbc_ctrl_dev->irq[0]);
320 ret = fsl_lbc_ctrl_dev->irq[0];
321 goto err;
322 }
323
324 fsl_lbc_ctrl_dev->irq[1] = irq_of_parse_and_map(dev->dev.of_node, 1);
325 if (fsl_lbc_ctrl_dev->irq[1]) {
326 ret = request_irq(fsl_lbc_ctrl_dev->irq[1], fsl_lbc_ctrl_irq,
327 IRQF_SHARED, "fsl-lbc-err", fsl_lbc_ctrl_dev);
328 if (ret) {
329 dev_err(&dev->dev, "failed to install irq (%d)\n",
330 fsl_lbc_ctrl_dev->irq[1]);
331 ret = fsl_lbc_ctrl_dev->irq[1];
332 goto err1;
333 }
334 }
335
336 /* Enable interrupts for any detected events */
337 out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
338
339 return 0;
340
341err1:
342 free_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_dev);
343err:
344 iounmap(fsl_lbc_ctrl_dev->regs);
345 kfree(fsl_lbc_ctrl_dev);
346 fsl_lbc_ctrl_dev = NULL;
347 return ret;
348}
349
350#ifdef CONFIG_SUSPEND
351
352/* save lbc registers */
353static int fsl_lbc_syscore_suspend(void)
354{
355 struct fsl_lbc_ctrl *ctrl;
356 struct fsl_lbc_regs __iomem *lbc;
357
358 ctrl = fsl_lbc_ctrl_dev;
359 if (!ctrl)
360 goto out;
361
362 lbc = ctrl->regs;
363 if (!lbc)
364 goto out;
365
366 ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL);
367 if (!ctrl->saved_regs)
368 return -ENOMEM;
369
370 _memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs));
371
372out:
373 return 0;
374}
375
376/* restore lbc registers */
377static void fsl_lbc_syscore_resume(void)
378{
379 struct fsl_lbc_ctrl *ctrl;
380 struct fsl_lbc_regs __iomem *lbc;
381
382 ctrl = fsl_lbc_ctrl_dev;
383 if (!ctrl)
384 goto out;
385
386 lbc = ctrl->regs;
387 if (!lbc)
388 goto out;
389
390 if (ctrl->saved_regs) {
391 _memcpy_toio(lbc, ctrl->saved_regs,
392 sizeof(struct fsl_lbc_regs));
393 kfree(ctrl->saved_regs);
394 ctrl->saved_regs = NULL;
395 }
396
397out:
398 return;
399}
400#endif /* CONFIG_SUSPEND */
401
402static const struct of_device_id fsl_lbc_match[] = {
403 { .compatible = "fsl,elbc", },
404 { .compatible = "fsl,pq3-localbus", },
405 { .compatible = "fsl,pq2-localbus", },
406 { .compatible = "fsl,pq2pro-localbus", },
407 {},
408};
409
410#ifdef CONFIG_SUSPEND
411static struct syscore_ops lbc_syscore_pm_ops = {
412 .suspend = fsl_lbc_syscore_suspend,
413 .resume = fsl_lbc_syscore_resume,
414};
415#endif
416
417static struct platform_driver fsl_lbc_ctrl_driver = {
418 .driver = {
419 .name = "fsl-lbc",
420 .of_match_table = fsl_lbc_match,
421 },
422 .probe = fsl_lbc_ctrl_probe,
423};
424
425static int __init fsl_lbc_init(void)
426{
427#ifdef CONFIG_SUSPEND
428 register_syscore_ops(&lbc_syscore_pm_ops);
429#endif
430 return platform_driver_register(&fsl_lbc_ctrl_driver);
431}
432subsys_initcall(fsl_lbc_init);
1/*
2 * Freescale LBC and UPM routines.
3 *
4 * Copyright © 2007-2008 MontaVista Software, Inc.
5 * Copyright © 2010 Freescale Semiconductor
6 *
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 * Author: Jack Lan <Jack.Lan@freescale.com>
9 * Author: Roy Zang <tie-fei.zang@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#include <linux/init.h>
18#include <linux/export.h>
19#include <linux/kernel.h>
20#include <linux/compiler.h>
21#include <linux/spinlock.h>
22#include <linux/types.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/slab.h>
26#include <linux/sched.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/mod_devicetable.h>
30#include <asm/prom.h>
31#include <asm/fsl_lbc.h>
32
33static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
34struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
35EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
36
37/**
38 * fsl_lbc_addr - convert the base address
39 * @addr_base: base address of the memory bank
40 *
41 * This function converts a base address of lbc into the right format for the
42 * BR register. If the SOC has eLBC then it returns 32bit physical address
43 * else it convers a 34bit local bus physical address to correct format of
44 * 32bit address for BR register (Example: MPC8641).
45 */
46u32 fsl_lbc_addr(phys_addr_t addr_base)
47{
48 struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
49 u32 addr = addr_base & 0xffff8000;
50
51 if (of_device_is_compatible(np, "fsl,elbc"))
52 return addr;
53
54 return addr | ((addr_base & 0x300000000ull) >> 19);
55}
56EXPORT_SYMBOL(fsl_lbc_addr);
57
58/**
59 * fsl_lbc_find - find Localbus bank
60 * @addr_base: base address of the memory bank
61 *
62 * This function walks LBC banks comparing "Base address" field of the BR
63 * registers with the supplied addr_base argument. When bases match this
64 * function returns bank number (starting with 0), otherwise it returns
65 * appropriate errno value.
66 */
67int fsl_lbc_find(phys_addr_t addr_base)
68{
69 int i;
70 struct fsl_lbc_regs __iomem *lbc;
71
72 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
73 return -ENODEV;
74
75 lbc = fsl_lbc_ctrl_dev->regs;
76 for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
77 __be32 br = in_be32(&lbc->bank[i].br);
78 __be32 or = in_be32(&lbc->bank[i].or);
79
80 if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
81 return i;
82 }
83
84 return -ENOENT;
85}
86EXPORT_SYMBOL(fsl_lbc_find);
87
88/**
89 * fsl_upm_find - find pre-programmed UPM via base address
90 * @addr_base: base address of the memory bank controlled by the UPM
91 * @upm: pointer to the allocated fsl_upm structure
92 *
93 * This function fills fsl_upm structure so you can use it with the rest of
94 * UPM API. On success this function returns 0, otherwise it returns
95 * appropriate errno value.
96 */
97int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
98{
99 int bank;
100 __be32 br;
101 struct fsl_lbc_regs __iomem *lbc;
102
103 bank = fsl_lbc_find(addr_base);
104 if (bank < 0)
105 return bank;
106
107 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
108 return -ENODEV;
109
110 lbc = fsl_lbc_ctrl_dev->regs;
111 br = in_be32(&lbc->bank[bank].br);
112
113 switch (br & BR_MSEL) {
114 case BR_MS_UPMA:
115 upm->mxmr = &lbc->mamr;
116 break;
117 case BR_MS_UPMB:
118 upm->mxmr = &lbc->mbmr;
119 break;
120 case BR_MS_UPMC:
121 upm->mxmr = &lbc->mcmr;
122 break;
123 default:
124 return -EINVAL;
125 }
126
127 switch (br & BR_PS) {
128 case BR_PS_8:
129 upm->width = 8;
130 break;
131 case BR_PS_16:
132 upm->width = 16;
133 break;
134 case BR_PS_32:
135 upm->width = 32;
136 break;
137 default:
138 return -EINVAL;
139 }
140
141 return 0;
142}
143EXPORT_SYMBOL(fsl_upm_find);
144
145/**
146 * fsl_upm_run_pattern - actually run an UPM pattern
147 * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
148 * @io_base: remapped pointer to where memory access should happen
149 * @mar: MAR register content during pattern execution
150 *
151 * This function triggers dummy write to the memory specified by the io_base,
152 * thus UPM pattern actually executed. Note that mar usage depends on the
153 * pre-programmed AMX bits in the UPM RAM.
154 */
155int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
156{
157 int ret = 0;
158 unsigned long flags;
159
160 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
161 return -ENODEV;
162
163 spin_lock_irqsave(&fsl_lbc_lock, flags);
164
165 out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
166
167 switch (upm->width) {
168 case 8:
169 out_8(io_base, 0x0);
170 break;
171 case 16:
172 out_be16(io_base, 0x0);
173 break;
174 case 32:
175 out_be32(io_base, 0x0);
176 break;
177 default:
178 ret = -EINVAL;
179 break;
180 }
181
182 spin_unlock_irqrestore(&fsl_lbc_lock, flags);
183
184 return ret;
185}
186EXPORT_SYMBOL(fsl_upm_run_pattern);
187
188static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
189 struct device_node *node)
190{
191 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
192
193 /* clear event registers */
194 setbits32(&lbc->ltesr, LTESR_CLEAR);
195 out_be32(&lbc->lteatr, 0);
196 out_be32(&lbc->ltear, 0);
197 out_be32(&lbc->lteccr, LTECCR_CLEAR);
198 out_be32(&lbc->ltedr, LTEDR_ENABLE);
199
200 /* Set the monitor timeout value to the maximum for erratum A001 */
201 if (of_device_is_compatible(node, "fsl,elbc"))
202 clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
203
204 return 0;
205}
206
207/*
208 * NOTE: This interrupt is used to report localbus events of various kinds,
209 * such as transaction errors on the chipselects.
210 */
211
212static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
213{
214 struct fsl_lbc_ctrl *ctrl = data;
215 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
216 u32 status;
217
218 status = in_be32(&lbc->ltesr);
219 if (!status)
220 return IRQ_NONE;
221
222 out_be32(&lbc->ltesr, LTESR_CLEAR);
223 out_be32(&lbc->lteatr, 0);
224 out_be32(&lbc->ltear, 0);
225 ctrl->irq_status = status;
226
227 if (status & LTESR_BM)
228 dev_err(ctrl->dev, "Local bus monitor time-out: "
229 "LTESR 0x%08X\n", status);
230 if (status & LTESR_WP)
231 dev_err(ctrl->dev, "Write protect error: "
232 "LTESR 0x%08X\n", status);
233 if (status & LTESR_ATMW)
234 dev_err(ctrl->dev, "Atomic write error: "
235 "LTESR 0x%08X\n", status);
236 if (status & LTESR_ATMR)
237 dev_err(ctrl->dev, "Atomic read error: "
238 "LTESR 0x%08X\n", status);
239 if (status & LTESR_CS)
240 dev_err(ctrl->dev, "Chip select error: "
241 "LTESR 0x%08X\n", status);
242 if (status & LTESR_UPM)
243 ;
244 if (status & LTESR_FCT) {
245 dev_err(ctrl->dev, "FCM command time-out: "
246 "LTESR 0x%08X\n", status);
247 smp_wmb();
248 wake_up(&ctrl->irq_wait);
249 }
250 if (status & LTESR_PAR) {
251 dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
252 "LTESR 0x%08X\n", status);
253 smp_wmb();
254 wake_up(&ctrl->irq_wait);
255 }
256 if (status & LTESR_CC) {
257 smp_wmb();
258 wake_up(&ctrl->irq_wait);
259 }
260 if (status & ~LTESR_MASK)
261 dev_err(ctrl->dev, "Unknown error: "
262 "LTESR 0x%08X\n", status);
263 return IRQ_HANDLED;
264}
265
266/*
267 * fsl_lbc_ctrl_probe
268 *
269 * called by device layer when it finds a device matching
270 * one our driver can handled. This code allocates all of
271 * the resources needed for the controller only. The
272 * resources for the NAND banks themselves are allocated
273 * in the chip probe function.
274*/
275
276static int __devinit fsl_lbc_ctrl_probe(struct platform_device *dev)
277{
278 int ret;
279
280 if (!dev->dev.of_node) {
281 dev_err(&dev->dev, "Device OF-Node is NULL");
282 return -EFAULT;
283 }
284
285 fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
286 if (!fsl_lbc_ctrl_dev)
287 return -ENOMEM;
288
289 dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
290
291 spin_lock_init(&fsl_lbc_ctrl_dev->lock);
292 init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
293
294 fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
295 if (!fsl_lbc_ctrl_dev->regs) {
296 dev_err(&dev->dev, "failed to get memory region\n");
297 ret = -ENODEV;
298 goto err;
299 }
300
301 fsl_lbc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
302 if (fsl_lbc_ctrl_dev->irq == NO_IRQ) {
303 dev_err(&dev->dev, "failed to get irq resource\n");
304 ret = -ENODEV;
305 goto err;
306 }
307
308 fsl_lbc_ctrl_dev->dev = &dev->dev;
309
310 ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, dev->dev.of_node);
311 if (ret < 0)
312 goto err;
313
314 ret = request_irq(fsl_lbc_ctrl_dev->irq, fsl_lbc_ctrl_irq, 0,
315 "fsl-lbc", fsl_lbc_ctrl_dev);
316 if (ret != 0) {
317 dev_err(&dev->dev, "failed to install irq (%d)\n",
318 fsl_lbc_ctrl_dev->irq);
319 ret = fsl_lbc_ctrl_dev->irq;
320 goto err;
321 }
322
323 /* Enable interrupts for any detected events */
324 out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
325
326 return 0;
327
328err:
329 iounmap(fsl_lbc_ctrl_dev->regs);
330 kfree(fsl_lbc_ctrl_dev);
331 fsl_lbc_ctrl_dev = NULL;
332 return ret;
333}
334
335#ifdef CONFIG_SUSPEND
336
337/* save lbc registers */
338static int fsl_lbc_suspend(struct platform_device *pdev, pm_message_t state)
339{
340 struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
341 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
342
343 ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL);
344 if (!ctrl->saved_regs)
345 return -ENOMEM;
346
347 _memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs));
348 return 0;
349}
350
351/* restore lbc registers */
352static int fsl_lbc_resume(struct platform_device *pdev)
353{
354 struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
355 struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
356
357 if (ctrl->saved_regs) {
358 _memcpy_toio(lbc, ctrl->saved_regs,
359 sizeof(struct fsl_lbc_regs));
360 kfree(ctrl->saved_regs);
361 ctrl->saved_regs = NULL;
362 }
363 return 0;
364}
365#endif /* CONFIG_SUSPEND */
366
367static const struct of_device_id fsl_lbc_match[] = {
368 { .compatible = "fsl,elbc", },
369 { .compatible = "fsl,pq3-localbus", },
370 { .compatible = "fsl,pq2-localbus", },
371 { .compatible = "fsl,pq2pro-localbus", },
372 {},
373};
374
375static struct platform_driver fsl_lbc_ctrl_driver = {
376 .driver = {
377 .name = "fsl-lbc",
378 .of_match_table = fsl_lbc_match,
379 },
380 .probe = fsl_lbc_ctrl_probe,
381#ifdef CONFIG_SUSPEND
382 .suspend = fsl_lbc_suspend,
383 .resume = fsl_lbc_resume,
384#endif
385};
386
387static int __init fsl_lbc_init(void)
388{
389 return platform_driver_register(&fsl_lbc_ctrl_driver);
390}
391module_init(fsl_lbc_init);