1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Enter and leave sleep state on chips with 6xx-style HID0
 4 * power management bits, which don't leave sleep state via reset.
 5 *
 6 * Author: Scott Wood <scottwood@freescale.com>
 7 *
 8 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
 
 
 
 
 9 */
10
11#include <asm/ppc_asm.h>
12#include <asm/reg.h>
13#include <asm/thread_info.h>
14#include <asm/asm-offsets.h>
15
16_GLOBAL(mpc6xx_enter_standby)
17	mflr	r4
18
19	mfspr	r5, SPRN_HID0
20	rlwinm	r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
21	oris	r5, r5, HID0_SLEEP@h
22	mtspr	SPRN_HID0, r5
23	isync
24
25	lis	r5, ret_from_standby@h
26	ori	r5, r5, ret_from_standby@l
27	mtlr	r5
28
29	lwz	r6, TI_LOCAL_FLAGS(r2)
 
30	ori	r6, r6, _TLF_SLEEPING
31	stw	r6, TI_LOCAL_FLAGS(r2)
32
33	mfmsr	r5
34	ori	r5, r5, MSR_EE
35	oris	r5, r5, MSR_POW@h
36	sync
37	mtmsr	r5
38	isync
39
401:	b	1b
41
42ret_from_standby:
43	mfspr	r5, SPRN_HID0
44	rlwinm	r5, r5, 0, ~HID0_SLEEP
45	mtspr	SPRN_HID0, r5
46
47	mtlr	r4
48	blr

 
 1/*
 2 * Enter and leave sleep state on chips with 6xx-style HID0
 3 * power management bits, which don't leave sleep state via reset.
 4 *
 5 * Author: Scott Wood <scottwood@freescale.com>
 6 *
 7 * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
 8 *
 9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <asm/ppc_asm.h>
15#include <asm/reg.h>
16#include <asm/thread_info.h>
17#include <asm/asm-offsets.h>
18
19_GLOBAL(mpc6xx_enter_standby)
20	mflr	r4
21
22	mfspr	r5, SPRN_HID0
23	rlwinm	r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
24	oris	r5, r5, HID0_SLEEP@h
25	mtspr	SPRN_HID0, r5
26	isync
27
28	lis	r5, ret_from_standby@h
29	ori	r5, r5, ret_from_standby@l
30	mtlr	r5
31
32	rlwinm	r5, r1, 0, 0, 31-THREAD_SHIFT
33	lwz	r6, TI_LOCAL_FLAGS(r5)
34	ori	r6, r6, _TLF_SLEEPING
35	stw	r6, TI_LOCAL_FLAGS(r5)
36
37	mfmsr	r5
38	ori	r5, r5, MSR_EE
39	oris	r5, r5, MSR_POW@h
40	sync
41	mtmsr	r5
42	isync
43
441:	b	1b
45
46ret_from_standby:
47	mfspr	r5, SPRN_HID0
48	rlwinm	r5, r5, 0, ~HID0_SLEEP
49	mtspr	SPRN_HID0, r5
50
51	mtlr	r4
52	blr