1/*
  2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
  3 * Added mmcra[slot] support:
  4 * Copyright (C) 2006-2007 Will Schmidt <willschm@us.ibm.com>, IBM
  5 *
  6 * This program is free software; you can redistribute it and/or
  7 * modify it under the terms of the GNU General Public License
  8 * as published by the Free Software Foundation; either version
  9 * 2 of the License, or (at your option) any later version.
 10 */
 11
 12#include <linux/oprofile.h>
 13#include <linux/init.h>
 14#include <linux/smp.h>
 15#include <asm/firmware.h>
 16#include <asm/ptrace.h>
 17#include <asm/processor.h>
 18#include <asm/cputable.h>
 19#include <asm/rtas.h>
 20#include <asm/oprofile_impl.h>
 21#include <asm/reg.h>
 22
 23#define dbg(args...)
 24
 25static unsigned long reset_value[OP_MAX_COUNTER];
 26
 27static int oprofile_running;
 28static int use_slot_nums;
 29
 30/* mmcr values are set in power4_reg_setup, used in power4_cpu_setup */
 31static u32 mmcr0_val;
 32static u64 mmcr1_val;
 33static u64 mmcra_val;
 34
 35static int power4_reg_setup(struct op_counter_config *ctr,
 36			     struct op_system_config *sys,
 37			     int num_ctrs)
 38{
 39	int i;
 40
 41	/*
 42	 * The performance counter event settings are given in the mmcr0,
 43	 * mmcr1 and mmcra values passed from the user in the
 44	 * op_system_config structure (sys variable).
 45	 */
 46	mmcr0_val = sys->mmcr0;
 47	mmcr1_val = sys->mmcr1;
 48	mmcra_val = sys->mmcra;
 49
 50	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i)
 51		reset_value[i] = 0x80000000UL - ctr[i].count;
 52
 53	/* setup user and kernel profiling */
 54	if (sys->enable_kernel)
 55		mmcr0_val &= ~MMCR0_KERNEL_DISABLE;
 56	else
 57		mmcr0_val |= MMCR0_KERNEL_DISABLE;
 58
 59	if (sys->enable_user)
 60		mmcr0_val &= ~MMCR0_PROBLEM_DISABLE;
 61	else
 62		mmcr0_val |= MMCR0_PROBLEM_DISABLE;
 63
 64	if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
 65	    __is_processor(PV_970) || __is_processor(PV_970FX) ||
 66	    __is_processor(PV_970MP) || __is_processor(PV_970GX) ||
 67	    __is_processor(PV_POWER5) || __is_processor(PV_POWER5p))
 68		use_slot_nums = 1;
 69
 70	return 0;
 71}
 72
 73extern void ppc_enable_pmcs(void);
 74
 75/*
 76 * Older CPUs require the MMCRA sample bit to be always set, but newer 
 77 * CPUs only want it set for some groups. Eventually we will remove all
 78 * knowledge of this bit in the kernel, oprofile userspace should be
 79 * setting it when required.
 80 *
 81 * In order to keep current installations working we force the bit for
 82 * those older CPUs. Once everyone has updated their oprofile userspace we
 83 * can remove this hack.
 84 */
 85static inline int mmcra_must_set_sample(void)
 86{
 87	if (__is_processor(PV_POWER4) || __is_processor(PV_POWER4p) ||
 88	    __is_processor(PV_970) || __is_processor(PV_970FX) ||
 89	    __is_processor(PV_970MP) || __is_processor(PV_970GX))
 90		return 1;
 91
 92	return 0;
 93}
 94
 95static int power4_cpu_setup(struct op_counter_config *ctr)
 96{
 97	unsigned int mmcr0 = mmcr0_val;
 98	unsigned long mmcra = mmcra_val;
 99
100	ppc_enable_pmcs();
101
102	/* set the freeze bit */
103	mmcr0 |= MMCR0_FC;
104	mtspr(SPRN_MMCR0, mmcr0);
105
106	mmcr0 |= MMCR0_FCM1|MMCR0_PMXE|MMCR0_FCECE;
107	mmcr0 |= MMCR0_PMC1CE|MMCR0_PMCjCE;
108	mtspr(SPRN_MMCR0, mmcr0);
109
110	mtspr(SPRN_MMCR1, mmcr1_val);
111
112	if (mmcra_must_set_sample())
113		mmcra |= MMCRA_SAMPLE_ENABLE;
114	mtspr(SPRN_MMCRA, mmcra);
115
116	dbg("setup on cpu %d, mmcr0 %lx\n", smp_processor_id(),
117	    mfspr(SPRN_MMCR0));
118	dbg("setup on cpu %d, mmcr1 %lx\n", smp_processor_id(),
119	    mfspr(SPRN_MMCR1));
120	dbg("setup on cpu %d, mmcra %lx\n", smp_processor_id(),
121	    mfspr(SPRN_MMCRA));
122
123	return 0;
124}
125
126static int power4_start(struct op_counter_config *ctr)
127{
128	int i;
129	unsigned int mmcr0;
130
131	/* set the PMM bit (see comment below) */
132	mtmsrd(mfmsr() | MSR_PMM);
133
134	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
135		if (ctr[i].enabled) {
136			classic_ctr_write(i, reset_value[i]);
137		} else {
138			classic_ctr_write(i, 0);
139		}
140	}
141
142	mmcr0 = mfspr(SPRN_MMCR0);
143
144	/*
145	 * We must clear the PMAO bit on some (GQ) chips. Just do it
146	 * all the time
147	 */
148	mmcr0 &= ~MMCR0_PMAO;
149
150	/*
151	 * now clear the freeze bit, counting will not start until we
152	 * rfid from this excetion, because only at that point will
153	 * the PMM bit be cleared
154	 */
155	mmcr0 &= ~MMCR0_FC;
156	mtspr(SPRN_MMCR0, mmcr0);
157
158	oprofile_running = 1;
159
160	dbg("start on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
161	return 0;
162}
163
164static void power4_stop(void)
165{
166	unsigned int mmcr0;
167
168	/* freeze counters */
169	mmcr0 = mfspr(SPRN_MMCR0);
170	mmcr0 |= MMCR0_FC;
171	mtspr(SPRN_MMCR0, mmcr0);
172
173	oprofile_running = 0;
174
175	dbg("stop on cpu %d, mmcr0 %x\n", smp_processor_id(), mmcr0);
176
177	mb();
178}
179
180/* Fake functions used by canonicalize_pc */
181static void __used hypervisor_bucket(void)
182{
183}
184
185static void __used rtas_bucket(void)
186{
187}
188
189static void __used kernel_unknown_bucket(void)
190{
191}
192
193/*
194 * On GQ and newer the MMCRA stores the HV and PR bits at the time
195 * the SIAR was sampled. We use that to work out if the SIAR was sampled in
196 * the hypervisor, our exception vectors or RTAS.
197 * If the MMCRA_SAMPLE_ENABLE bit is set, we can use the MMCRA[slot] bits
198 * to more accurately identify the address of the sampled instruction. The
199 * mmcra[slot] bits represent the slot number of a sampled instruction
200 * within an instruction group.  The slot will contain a value between 1
201 * and 5 if MMCRA_SAMPLE_ENABLE is set, otherwise 0.
202 */
203static unsigned long get_pc(struct pt_regs *regs)
204{
205	unsigned long pc = mfspr(SPRN_SIAR);
206	unsigned long mmcra;
207	unsigned long slot;
208
209	/* Can't do much about it */
210	if (!cur_cpu_spec->oprofile_mmcra_sihv)
211		return pc;
212
213	mmcra = mfspr(SPRN_MMCRA);
214
215	if (use_slot_nums && (mmcra & MMCRA_SAMPLE_ENABLE)) {
216		slot = ((mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT);
217		if (slot > 1)
218			pc += 4 * (slot - 1);
219	}
220
221	/* Were we in the hypervisor? */
222	if (firmware_has_feature(FW_FEATURE_LPAR) &&
223	    (mmcra & cur_cpu_spec->oprofile_mmcra_sihv))
224		/* function descriptor madness */
225		return *((unsigned long *)hypervisor_bucket);
226
227	/* We were in userspace, nothing to do */
228	if (mmcra & cur_cpu_spec->oprofile_mmcra_sipr)
229		return pc;
230
231#ifdef CONFIG_PPC_RTAS
232	/* Were we in RTAS? */
233	if (pc >= rtas.base && pc < (rtas.base + rtas.size))
234		/* function descriptor madness */
235		return *((unsigned long *)rtas_bucket);
236#endif
237
238	/* Were we in our exception vectors or SLB real mode miss handler? */
239	if (pc < 0x1000000UL)
240		return (unsigned long)__va(pc);
241
242	/* Not sure where we were */
243	if (!is_kernel_addr(pc))
244		/* function descriptor madness */
245		return *((unsigned long *)kernel_unknown_bucket);
246
247	return pc;
248}
249
250static int get_kernel(unsigned long pc, unsigned long mmcra)
251{
252	int is_kernel;
253
254	if (!cur_cpu_spec->oprofile_mmcra_sihv) {
255		is_kernel = is_kernel_addr(pc);
256	} else {
257		is_kernel = ((mmcra & cur_cpu_spec->oprofile_mmcra_sipr) == 0);
258	}
259
260	return is_kernel;
261}
262
263static bool pmc_overflow(unsigned long val)
264{
265	if ((int)val < 0)
266		return true;
267
268	/*
269	 * Events on POWER7 can roll back if a speculative event doesn't
270	 * eventually complete. Unfortunately in some rare cases they will
271	 * raise a performance monitor exception. We need to catch this to
272	 * ensure we reset the PMC. In all cases the PMC will be 256 or less
273	 * cycles from overflow.
274	 *
275	 * We only do this if the first pass fails to find any overflowing
276	 * PMCs because a user might set a period of less than 256 and we
277	 * don't want to mistakenly reset them.
278	 */
279	if (__is_processor(PV_POWER7) && ((0x80000000 - val) <= 256))
280		return true;
281
282	return false;
283}
284
285static void power4_handle_interrupt(struct pt_regs *regs,
286				    struct op_counter_config *ctr)
287{
288	unsigned long pc;
289	int is_kernel;
290	int val;
291	int i;
292	unsigned int mmcr0;
293	unsigned long mmcra;
294
295	mmcra = mfspr(SPRN_MMCRA);
296
297	pc = get_pc(regs);
298	is_kernel = get_kernel(pc, mmcra);
299
300	/* set the PMM bit (see comment below) */
301	mtmsrd(mfmsr() | MSR_PMM);
302
303	for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
304		val = classic_ctr_read(i);
305		if (pmc_overflow(val)) {
306			if (oprofile_running && ctr[i].enabled) {
307				oprofile_add_ext_sample(pc, regs, i, is_kernel);
308				classic_ctr_write(i, reset_value[i]);
309			} else {
310				classic_ctr_write(i, 0);
311			}
312		}
313	}
314
315	mmcr0 = mfspr(SPRN_MMCR0);
316
317	/* reset the perfmon trigger */
318	mmcr0 |= MMCR0_PMXE;
319
320	/*
321	 * We must clear the PMAO bit on some (GQ) chips. Just do it
322	 * all the time
323	 */
324	mmcr0 &= ~MMCR0_PMAO;
325
326	/* Clear the appropriate bits in the MMCRA */
327	mmcra &= ~cur_cpu_spec->oprofile_mmcra_clear;
328	mtspr(SPRN_MMCRA, mmcra);
329
330	/*
331	 * now clear the freeze bit, counting will not start until we
332	 * rfid from this exception, because only at that point will
333	 * the PMM bit be cleared
334	 */
335	mmcr0 &= ~MMCR0_FC;
336	mtspr(SPRN_MMCR0, mmcr0);
337}
338
339struct op_powerpc_model op_model_power4 = {
340	.reg_setup		= power4_reg_setup,
341	.cpu_setup		= power4_cpu_setup,
342	.start			= power4_start,
343	.stop			= power4_stop,
344	.handle_interrupt	= power4_handle_interrupt,
345};