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1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (C) 2003-2018 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_GMXX_DEFS_H__
29#define __CVMX_GMXX_DEFS_H__
30
31static inline uint64_t CVMX_GMXX_HG2_CONTROL(unsigned long block_id)
32{
33 switch (cvmx_get_octeon_family()) {
34 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
35 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x1000000ull;
36 }
37 return CVMX_ADD_IO_SEG(0x0001180008000550ull) + (block_id) * 0x8000000ull;
38}
39
40static inline uint64_t CVMX_GMXX_INF_MODE(unsigned long block_id)
41{
42 switch (cvmx_get_octeon_family()) {
43 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
44 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x1000000ull;
45 }
46 return CVMX_ADD_IO_SEG(0x00011800080007F8ull) + (block_id) * 0x8000000ull;
47}
48
49static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
50{
51 switch (cvmx_get_octeon_family()) {
52 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
53 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x0ull) * 2048;
54 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
55 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
56 }
57 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
58}
59
60static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
61{
62 switch (cvmx_get_octeon_family()) {
63 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
64 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x0ull) * 2048;
65 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
66 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
67 }
68 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
69}
70
71static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
72{
73 switch (cvmx_get_octeon_family()) {
74 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
75 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x0ull) * 2048;
76 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
77 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
78 }
79 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
80}
81
82static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
83{
84 switch (cvmx_get_octeon_family()) {
85 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
86 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x0ull) * 2048;
87 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
88 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
89 }
90 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
91}
92
93static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
94{
95 switch (cvmx_get_octeon_family()) {
96 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
97 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x0ull) * 2048;
98 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
99 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
100 }
101 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
102}
103
104static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
105{
106 switch (cvmx_get_octeon_family()) {
107 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
108 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x0ull) * 2048;
109 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
110 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
111 }
112 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
113}
114
115static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
116{
117 switch (cvmx_get_octeon_family()) {
118 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
119 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x0ull) * 2048;
120 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
121 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
122 }
123 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
124}
125
126static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
127{
128 switch (cvmx_get_octeon_family()) {
129 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
130 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x0ull) * 2048;
131 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
132 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
133 }
134 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
135}
136
137static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
138{
139 switch (cvmx_get_octeon_family()) {
140 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
141 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x0ull) * 2048;
142 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
143 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
144 }
145 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
146}
147
148static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
149{
150 switch (cvmx_get_octeon_family()) {
151 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
152 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x0ull) * 2048;
153 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
154 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
155 }
156 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
157}
158
159#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
160#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
161
162static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
163{
164 switch (cvmx_get_octeon_family()) {
165 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
166 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x0ull) * 2048;
167 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
168 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
169 }
170 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
171}
172
173static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
174{
175 switch (cvmx_get_octeon_family()) {
176 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
177 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x0ull) * 2048;
178 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
179 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
180 }
181 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
182}
183
184static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
185{
186 switch (cvmx_get_octeon_family()) {
187 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
188 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x0ull) * 2048;
189 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
190 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
191 }
192 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
193}
194
195#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
196
197static inline uint64_t CVMX_GMXX_RX_PRTS(unsigned long block_id)
198{
199 switch (cvmx_get_octeon_family()) {
200 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
201 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x1000000ull;
202 }
203 return CVMX_ADD_IO_SEG(0x0001180008000410ull) + (block_id) * 0x8000000ull;
204}
205
206static inline uint64_t CVMX_GMXX_RX_XAUI_CTL(unsigned long block_id)
207{
208 switch (cvmx_get_octeon_family()) {
209 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
210 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x1000000ull;
211 }
212 return CVMX_ADD_IO_SEG(0x0001180008000530ull) + (block_id) * 0x8000000ull;
213}
214
215static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
216{
217 switch (cvmx_get_octeon_family()) {
218 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
219 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x0ull) * 2048;
220 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
221 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
222 }
223 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
224}
225
226static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
227{
228 switch (cvmx_get_octeon_family()) {
229 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
230 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x0ull) * 2048;
231 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
232 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
233 }
234 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
235}
236
237#define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
238static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
239{
240 switch (cvmx_get_octeon_family()) {
241 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
242 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x0ull) * 2048;
243 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
244 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
245 }
246 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
247}
248
249static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
250{
251 switch (cvmx_get_octeon_family()) {
252 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
253 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x0ull) * 2048;
254 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
255 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
256 }
257 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
258}
259
260static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
261{
262 switch (cvmx_get_octeon_family()) {
263 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
264 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x0ull) * 2048;
265 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
266 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
267 }
268 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
269}
270
271static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
272{
273 switch (cvmx_get_octeon_family()) {
274 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
275 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x0ull) * 2048;
276 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
277 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
278 }
279 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
280}
281
282static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
283{
284 switch (cvmx_get_octeon_family()) {
285 case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
286 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x0ull) * 2048;
287 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
288 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x2000ull) * 2048;
289 }
290 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + ((offset) + (block_id) * 0x10000ull) * 2048;
291}
292
293static inline uint64_t CVMX_GMXX_TX_INT_EN(unsigned long block_id)
294{
295 switch (cvmx_get_octeon_family()) {
296 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
297 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x1000000ull;
298 }
299 return CVMX_ADD_IO_SEG(0x0001180008000508ull) + (block_id) * 0x8000000ull;
300}
301
302static inline uint64_t CVMX_GMXX_TX_INT_REG(unsigned long block_id)
303{
304 switch (cvmx_get_octeon_family()) {
305 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
306 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x1000000ull;
307 }
308 return CVMX_ADD_IO_SEG(0x0001180008000500ull) + (block_id) * 0x8000000ull;
309}
310
311static inline uint64_t CVMX_GMXX_TX_OVR_BP(unsigned long block_id)
312{
313 switch (cvmx_get_octeon_family()) {
314 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
315 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x1000000ull;
316 }
317 return CVMX_ADD_IO_SEG(0x00011800080004C8ull) + (block_id) * 0x8000000ull;
318}
319
320static inline uint64_t CVMX_GMXX_TX_PRTS(unsigned long block_id)
321{
322 switch (cvmx_get_octeon_family()) {
323 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
324 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x1000000ull;
325 }
326 return CVMX_ADD_IO_SEG(0x0001180008000480ull) + (block_id) * 0x8000000ull;
327}
328
329#define CVMX_GMXX_TX_SPI_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800080004C0ull) + ((block_id) & 1) * 0x8000000ull)
330#define CVMX_GMXX_TX_SPI_MAX(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B0ull) + ((block_id) & 1) * 0x8000000ull)
331#define CVMX_GMXX_TX_SPI_THRESH(block_id) (CVMX_ADD_IO_SEG(0x00011800080004B8ull) + ((block_id) & 1) * 0x8000000ull)
332static inline uint64_t CVMX_GMXX_TX_XAUI_CTL(unsigned long block_id)
333{
334 switch (cvmx_get_octeon_family()) {
335 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
336 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x1000000ull;
337 }
338 return CVMX_ADD_IO_SEG(0x0001180008000528ull) + (block_id) * 0x8000000ull;
339}
340
341void __cvmx_interrupt_gmxx_enable(int interface);
342
343union cvmx_gmxx_hg2_control {
344 uint64_t u64;
345 struct cvmx_gmxx_hg2_control_s {
346#ifdef __BIG_ENDIAN_BITFIELD
347 uint64_t reserved_19_63:45;
348 uint64_t hg2tx_en:1;
349 uint64_t hg2rx_en:1;
350 uint64_t phys_en:1;
351 uint64_t logl_en:16;
352#else
353 uint64_t logl_en:16;
354 uint64_t phys_en:1;
355 uint64_t hg2rx_en:1;
356 uint64_t hg2tx_en:1;
357 uint64_t reserved_19_63:45;
358#endif
359 } s;
360};
361
362union cvmx_gmxx_inf_mode {
363 uint64_t u64;
364 struct cvmx_gmxx_inf_mode_s {
365#ifdef __BIG_ENDIAN_BITFIELD
366 uint64_t reserved_20_63:44;
367 uint64_t rate:4;
368 uint64_t reserved_12_15:4;
369 uint64_t speed:4;
370 uint64_t reserved_7_7:1;
371 uint64_t mode:3;
372 uint64_t reserved_3_3:1;
373 uint64_t p0mii:1;
374 uint64_t en:1;
375 uint64_t type:1;
376#else
377 uint64_t type:1;
378 uint64_t en:1;
379 uint64_t p0mii:1;
380 uint64_t reserved_3_3:1;
381 uint64_t mode:3;
382 uint64_t reserved_7_7:1;
383 uint64_t speed:4;
384 uint64_t reserved_12_15:4;
385 uint64_t rate:4;
386 uint64_t reserved_20_63:44;
387#endif
388 } s;
389 struct cvmx_gmxx_inf_mode_cn30xx {
390#ifdef __BIG_ENDIAN_BITFIELD
391 uint64_t reserved_3_63:61;
392 uint64_t p0mii:1;
393 uint64_t en:1;
394 uint64_t type:1;
395#else
396 uint64_t type:1;
397 uint64_t en:1;
398 uint64_t p0mii:1;
399 uint64_t reserved_3_63:61;
400#endif
401 } cn30xx;
402 struct cvmx_gmxx_inf_mode_cn31xx {
403#ifdef __BIG_ENDIAN_BITFIELD
404 uint64_t reserved_2_63:62;
405 uint64_t en:1;
406 uint64_t type:1;
407#else
408 uint64_t type:1;
409 uint64_t en:1;
410 uint64_t reserved_2_63:62;
411#endif
412 } cn31xx;
413 struct cvmx_gmxx_inf_mode_cn52xx {
414#ifdef __BIG_ENDIAN_BITFIELD
415 uint64_t reserved_10_63:54;
416 uint64_t speed:2;
417 uint64_t reserved_6_7:2;
418 uint64_t mode:2;
419 uint64_t reserved_2_3:2;
420 uint64_t en:1;
421 uint64_t type:1;
422#else
423 uint64_t type:1;
424 uint64_t en:1;
425 uint64_t reserved_2_3:2;
426 uint64_t mode:2;
427 uint64_t reserved_6_7:2;
428 uint64_t speed:2;
429 uint64_t reserved_10_63:54;
430#endif
431 } cn52xx;
432 struct cvmx_gmxx_inf_mode_cn61xx {
433#ifdef __BIG_ENDIAN_BITFIELD
434 uint64_t reserved_12_63:52;
435 uint64_t speed:4;
436 uint64_t reserved_5_7:3;
437 uint64_t mode:1;
438 uint64_t reserved_2_3:2;
439 uint64_t en:1;
440 uint64_t type:1;
441#else
442 uint64_t type:1;
443 uint64_t en:1;
444 uint64_t reserved_2_3:2;
445 uint64_t mode:1;
446 uint64_t reserved_5_7:3;
447 uint64_t speed:4;
448 uint64_t reserved_12_63:52;
449#endif
450 } cn61xx;
451 struct cvmx_gmxx_inf_mode_cn66xx {
452#ifdef __BIG_ENDIAN_BITFIELD
453 uint64_t reserved_20_63:44;
454 uint64_t rate:4;
455 uint64_t reserved_12_15:4;
456 uint64_t speed:4;
457 uint64_t reserved_5_7:3;
458 uint64_t mode:1;
459 uint64_t reserved_2_3:2;
460 uint64_t en:1;
461 uint64_t type:1;
462#else
463 uint64_t type:1;
464 uint64_t en:1;
465 uint64_t reserved_2_3:2;
466 uint64_t mode:1;
467 uint64_t reserved_5_7:3;
468 uint64_t speed:4;
469 uint64_t reserved_12_15:4;
470 uint64_t rate:4;
471 uint64_t reserved_20_63:44;
472#endif
473 } cn66xx;
474 struct cvmx_gmxx_inf_mode_cn68xx {
475#ifdef __BIG_ENDIAN_BITFIELD
476 uint64_t reserved_12_63:52;
477 uint64_t speed:4;
478 uint64_t reserved_7_7:1;
479 uint64_t mode:3;
480 uint64_t reserved_2_3:2;
481 uint64_t en:1;
482 uint64_t type:1;
483#else
484 uint64_t type:1;
485 uint64_t en:1;
486 uint64_t reserved_2_3:2;
487 uint64_t mode:3;
488 uint64_t reserved_7_7:1;
489 uint64_t speed:4;
490 uint64_t reserved_12_63:52;
491#endif
492 } cn68xx;
493};
494
495union cvmx_gmxx_prtx_cfg {
496 uint64_t u64;
497 struct cvmx_gmxx_prtx_cfg_s {
498#ifdef __BIG_ENDIAN_BITFIELD
499 uint64_t reserved_22_63:42;
500 uint64_t pknd:6;
501 uint64_t reserved_14_15:2;
502 uint64_t tx_idle:1;
503 uint64_t rx_idle:1;
504 uint64_t reserved_9_11:3;
505 uint64_t speed_msb:1;
506 uint64_t reserved_4_7:4;
507 uint64_t slottime:1;
508 uint64_t duplex:1;
509 uint64_t speed:1;
510 uint64_t en:1;
511#else
512 uint64_t en:1;
513 uint64_t speed:1;
514 uint64_t duplex:1;
515 uint64_t slottime:1;
516 uint64_t reserved_4_7:4;
517 uint64_t speed_msb:1;
518 uint64_t reserved_9_11:3;
519 uint64_t rx_idle:1;
520 uint64_t tx_idle:1;
521 uint64_t reserved_14_15:2;
522 uint64_t pknd:6;
523 uint64_t reserved_22_63:42;
524#endif
525 } s;
526 struct cvmx_gmxx_prtx_cfg_cn30xx {
527#ifdef __BIG_ENDIAN_BITFIELD
528 uint64_t reserved_4_63:60;
529 uint64_t slottime:1;
530 uint64_t duplex:1;
531 uint64_t speed:1;
532 uint64_t en:1;
533#else
534 uint64_t en:1;
535 uint64_t speed:1;
536 uint64_t duplex:1;
537 uint64_t slottime:1;
538 uint64_t reserved_4_63:60;
539#endif
540 } cn30xx;
541 struct cvmx_gmxx_prtx_cfg_cn52xx {
542#ifdef __BIG_ENDIAN_BITFIELD
543 uint64_t reserved_14_63:50;
544 uint64_t tx_idle:1;
545 uint64_t rx_idle:1;
546 uint64_t reserved_9_11:3;
547 uint64_t speed_msb:1;
548 uint64_t reserved_4_7:4;
549 uint64_t slottime:1;
550 uint64_t duplex:1;
551 uint64_t speed:1;
552 uint64_t en:1;
553#else
554 uint64_t en:1;
555 uint64_t speed:1;
556 uint64_t duplex:1;
557 uint64_t slottime:1;
558 uint64_t reserved_4_7:4;
559 uint64_t speed_msb:1;
560 uint64_t reserved_9_11:3;
561 uint64_t rx_idle:1;
562 uint64_t tx_idle:1;
563 uint64_t reserved_14_63:50;
564#endif
565 } cn52xx;
566};
567
568union cvmx_gmxx_rxx_adr_ctl {
569 uint64_t u64;
570 struct cvmx_gmxx_rxx_adr_ctl_s {
571#ifdef __BIG_ENDIAN_BITFIELD
572 uint64_t reserved_4_63:60;
573 uint64_t cam_mode:1;
574 uint64_t mcst:2;
575 uint64_t bcst:1;
576#else
577 uint64_t bcst:1;
578 uint64_t mcst:2;
579 uint64_t cam_mode:1;
580 uint64_t reserved_4_63:60;
581#endif
582 } s;
583};
584
585union cvmx_gmxx_rxx_frm_ctl {
586 uint64_t u64;
587 struct cvmx_gmxx_rxx_frm_ctl_s {
588#ifdef __BIG_ENDIAN_BITFIELD
589 uint64_t reserved_13_63:51;
590 uint64_t ptp_mode:1;
591 uint64_t reserved_11_11:1;
592 uint64_t null_dis:1;
593 uint64_t pre_align:1;
594 uint64_t pad_len:1;
595 uint64_t vlan_len:1;
596 uint64_t pre_free:1;
597 uint64_t ctl_smac:1;
598 uint64_t ctl_mcst:1;
599 uint64_t ctl_bck:1;
600 uint64_t ctl_drp:1;
601 uint64_t pre_strp:1;
602 uint64_t pre_chk:1;
603#else
604 uint64_t pre_chk:1;
605 uint64_t pre_strp:1;
606 uint64_t ctl_drp:1;
607 uint64_t ctl_bck:1;
608 uint64_t ctl_mcst:1;
609 uint64_t ctl_smac:1;
610 uint64_t pre_free:1;
611 uint64_t vlan_len:1;
612 uint64_t pad_len:1;
613 uint64_t pre_align:1;
614 uint64_t null_dis:1;
615 uint64_t reserved_11_11:1;
616 uint64_t ptp_mode:1;
617 uint64_t reserved_13_63:51;
618#endif
619 } s;
620 struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
621#ifdef __BIG_ENDIAN_BITFIELD
622 uint64_t reserved_9_63:55;
623 uint64_t pad_len:1;
624 uint64_t vlan_len:1;
625 uint64_t pre_free:1;
626 uint64_t ctl_smac:1;
627 uint64_t ctl_mcst:1;
628 uint64_t ctl_bck:1;
629 uint64_t ctl_drp:1;
630 uint64_t pre_strp:1;
631 uint64_t pre_chk:1;
632#else
633 uint64_t pre_chk:1;
634 uint64_t pre_strp:1;
635 uint64_t ctl_drp:1;
636 uint64_t ctl_bck:1;
637 uint64_t ctl_mcst:1;
638 uint64_t ctl_smac:1;
639 uint64_t pre_free:1;
640 uint64_t vlan_len:1;
641 uint64_t pad_len:1;
642 uint64_t reserved_9_63:55;
643#endif
644 } cn30xx;
645 struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
646#ifdef __BIG_ENDIAN_BITFIELD
647 uint64_t reserved_8_63:56;
648 uint64_t vlan_len:1;
649 uint64_t pre_free:1;
650 uint64_t ctl_smac:1;
651 uint64_t ctl_mcst:1;
652 uint64_t ctl_bck:1;
653 uint64_t ctl_drp:1;
654 uint64_t pre_strp:1;
655 uint64_t pre_chk:1;
656#else
657 uint64_t pre_chk:1;
658 uint64_t pre_strp:1;
659 uint64_t ctl_drp:1;
660 uint64_t ctl_bck:1;
661 uint64_t ctl_mcst:1;
662 uint64_t ctl_smac:1;
663 uint64_t pre_free:1;
664 uint64_t vlan_len:1;
665 uint64_t reserved_8_63:56;
666#endif
667 } cn31xx;
668 struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
669#ifdef __BIG_ENDIAN_BITFIELD
670 uint64_t reserved_11_63:53;
671 uint64_t null_dis:1;
672 uint64_t pre_align:1;
673 uint64_t reserved_7_8:2;
674 uint64_t pre_free:1;
675 uint64_t ctl_smac:1;
676 uint64_t ctl_mcst:1;
677 uint64_t ctl_bck:1;
678 uint64_t ctl_drp:1;
679 uint64_t pre_strp:1;
680 uint64_t pre_chk:1;
681#else
682 uint64_t pre_chk:1;
683 uint64_t pre_strp:1;
684 uint64_t ctl_drp:1;
685 uint64_t ctl_bck:1;
686 uint64_t ctl_mcst:1;
687 uint64_t ctl_smac:1;
688 uint64_t pre_free:1;
689 uint64_t reserved_7_8:2;
690 uint64_t pre_align:1;
691 uint64_t null_dis:1;
692 uint64_t reserved_11_63:53;
693#endif
694 } cn50xx;
695 struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
696#ifdef __BIG_ENDIAN_BITFIELD
697 uint64_t reserved_10_63:54;
698 uint64_t pre_align:1;
699 uint64_t reserved_7_8:2;
700 uint64_t pre_free:1;
701 uint64_t ctl_smac:1;
702 uint64_t ctl_mcst:1;
703 uint64_t ctl_bck:1;
704 uint64_t ctl_drp:1;
705 uint64_t pre_strp:1;
706 uint64_t pre_chk:1;
707#else
708 uint64_t pre_chk:1;
709 uint64_t pre_strp:1;
710 uint64_t ctl_drp:1;
711 uint64_t ctl_bck:1;
712 uint64_t ctl_mcst:1;
713 uint64_t ctl_smac:1;
714 uint64_t pre_free:1;
715 uint64_t reserved_7_8:2;
716 uint64_t pre_align:1;
717 uint64_t reserved_10_63:54;
718#endif
719 } cn56xxp1;
720 struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
721#ifdef __BIG_ENDIAN_BITFIELD
722 uint64_t reserved_11_63:53;
723 uint64_t null_dis:1;
724 uint64_t pre_align:1;
725 uint64_t pad_len:1;
726 uint64_t vlan_len:1;
727 uint64_t pre_free:1;
728 uint64_t ctl_smac:1;
729 uint64_t ctl_mcst:1;
730 uint64_t ctl_bck:1;
731 uint64_t ctl_drp:1;
732 uint64_t pre_strp:1;
733 uint64_t pre_chk:1;
734#else
735 uint64_t pre_chk:1;
736 uint64_t pre_strp:1;
737 uint64_t ctl_drp:1;
738 uint64_t ctl_bck:1;
739 uint64_t ctl_mcst:1;
740 uint64_t ctl_smac:1;
741 uint64_t pre_free:1;
742 uint64_t vlan_len:1;
743 uint64_t pad_len:1;
744 uint64_t pre_align:1;
745 uint64_t null_dis:1;
746 uint64_t reserved_11_63:53;
747#endif
748 } cn58xx;
749 struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
750#ifdef __BIG_ENDIAN_BITFIELD
751 uint64_t reserved_13_63:51;
752 uint64_t ptp_mode:1;
753 uint64_t reserved_11_11:1;
754 uint64_t null_dis:1;
755 uint64_t pre_align:1;
756 uint64_t reserved_7_8:2;
757 uint64_t pre_free:1;
758 uint64_t ctl_smac:1;
759 uint64_t ctl_mcst:1;
760 uint64_t ctl_bck:1;
761 uint64_t ctl_drp:1;
762 uint64_t pre_strp:1;
763 uint64_t pre_chk:1;
764#else
765 uint64_t pre_chk:1;
766 uint64_t pre_strp:1;
767 uint64_t ctl_drp:1;
768 uint64_t ctl_bck:1;
769 uint64_t ctl_mcst:1;
770 uint64_t ctl_smac:1;
771 uint64_t pre_free:1;
772 uint64_t reserved_7_8:2;
773 uint64_t pre_align:1;
774 uint64_t null_dis:1;
775 uint64_t reserved_11_11:1;
776 uint64_t ptp_mode:1;
777 uint64_t reserved_13_63:51;
778#endif
779 } cn61xx;
780};
781
782union cvmx_gmxx_rxx_frm_max {
783 uint64_t u64;
784 struct cvmx_gmxx_rxx_frm_max_s {
785#ifdef __BIG_ENDIAN_BITFIELD
786 uint64_t reserved_16_63:48;
787 uint64_t len:16;
788#else
789 uint64_t len:16;
790 uint64_t reserved_16_63:48;
791#endif
792 } s;
793};
794
795union cvmx_gmxx_rxx_frm_min {
796 uint64_t u64;
797 struct cvmx_gmxx_rxx_frm_min_s {
798#ifdef __BIG_ENDIAN_BITFIELD
799 uint64_t reserved_16_63:48;
800 uint64_t len:16;
801#else
802 uint64_t len:16;
803 uint64_t reserved_16_63:48;
804#endif
805 } s;
806};
807
808union cvmx_gmxx_rxx_int_en {
809 uint64_t u64;
810 struct cvmx_gmxx_rxx_int_en_s {
811#ifdef __BIG_ENDIAN_BITFIELD
812 uint64_t reserved_29_63:35;
813 uint64_t hg2cc:1;
814 uint64_t hg2fld:1;
815 uint64_t undat:1;
816 uint64_t uneop:1;
817 uint64_t unsop:1;
818 uint64_t bad_term:1;
819 uint64_t bad_seq:1;
820 uint64_t rem_fault:1;
821 uint64_t loc_fault:1;
822 uint64_t pause_drp:1;
823 uint64_t phy_dupx:1;
824 uint64_t phy_spd:1;
825 uint64_t phy_link:1;
826 uint64_t ifgerr:1;
827 uint64_t coldet:1;
828 uint64_t falerr:1;
829 uint64_t rsverr:1;
830 uint64_t pcterr:1;
831 uint64_t ovrerr:1;
832 uint64_t niberr:1;
833 uint64_t skperr:1;
834 uint64_t rcverr:1;
835 uint64_t lenerr:1;
836 uint64_t alnerr:1;
837 uint64_t fcserr:1;
838 uint64_t jabber:1;
839 uint64_t maxerr:1;
840 uint64_t carext:1;
841 uint64_t minerr:1;
842#else
843 uint64_t minerr:1;
844 uint64_t carext:1;
845 uint64_t maxerr:1;
846 uint64_t jabber:1;
847 uint64_t fcserr:1;
848 uint64_t alnerr:1;
849 uint64_t lenerr:1;
850 uint64_t rcverr:1;
851 uint64_t skperr:1;
852 uint64_t niberr:1;
853 uint64_t ovrerr:1;
854 uint64_t pcterr:1;
855 uint64_t rsverr:1;
856 uint64_t falerr:1;
857 uint64_t coldet:1;
858 uint64_t ifgerr:1;
859 uint64_t phy_link:1;
860 uint64_t phy_spd:1;
861 uint64_t phy_dupx:1;
862 uint64_t pause_drp:1;
863 uint64_t loc_fault:1;
864 uint64_t rem_fault:1;
865 uint64_t bad_seq:1;
866 uint64_t bad_term:1;
867 uint64_t unsop:1;
868 uint64_t uneop:1;
869 uint64_t undat:1;
870 uint64_t hg2fld:1;
871 uint64_t hg2cc:1;
872 uint64_t reserved_29_63:35;
873#endif
874 } s;
875 struct cvmx_gmxx_rxx_int_en_cn30xx {
876#ifdef __BIG_ENDIAN_BITFIELD
877 uint64_t reserved_19_63:45;
878 uint64_t phy_dupx:1;
879 uint64_t phy_spd:1;
880 uint64_t phy_link:1;
881 uint64_t ifgerr:1;
882 uint64_t coldet:1;
883 uint64_t falerr:1;
884 uint64_t rsverr:1;
885 uint64_t pcterr:1;
886 uint64_t ovrerr:1;
887 uint64_t niberr:1;
888 uint64_t skperr:1;
889 uint64_t rcverr:1;
890 uint64_t lenerr:1;
891 uint64_t alnerr:1;
892 uint64_t fcserr:1;
893 uint64_t jabber:1;
894 uint64_t maxerr:1;
895 uint64_t carext:1;
896 uint64_t minerr:1;
897#else
898 uint64_t minerr:1;
899 uint64_t carext:1;
900 uint64_t maxerr:1;
901 uint64_t jabber:1;
902 uint64_t fcserr:1;
903 uint64_t alnerr:1;
904 uint64_t lenerr:1;
905 uint64_t rcverr:1;
906 uint64_t skperr:1;
907 uint64_t niberr:1;
908 uint64_t ovrerr:1;
909 uint64_t pcterr:1;
910 uint64_t rsverr:1;
911 uint64_t falerr:1;
912 uint64_t coldet:1;
913 uint64_t ifgerr:1;
914 uint64_t phy_link:1;
915 uint64_t phy_spd:1;
916 uint64_t phy_dupx:1;
917 uint64_t reserved_19_63:45;
918#endif
919 } cn30xx;
920 struct cvmx_gmxx_rxx_int_en_cn50xx {
921#ifdef __BIG_ENDIAN_BITFIELD
922 uint64_t reserved_20_63:44;
923 uint64_t pause_drp:1;
924 uint64_t phy_dupx:1;
925 uint64_t phy_spd:1;
926 uint64_t phy_link:1;
927 uint64_t ifgerr:1;
928 uint64_t coldet:1;
929 uint64_t falerr:1;
930 uint64_t rsverr:1;
931 uint64_t pcterr:1;
932 uint64_t ovrerr:1;
933 uint64_t niberr:1;
934 uint64_t skperr:1;
935 uint64_t rcverr:1;
936 uint64_t reserved_6_6:1;
937 uint64_t alnerr:1;
938 uint64_t fcserr:1;
939 uint64_t jabber:1;
940 uint64_t reserved_2_2:1;
941 uint64_t carext:1;
942 uint64_t reserved_0_0:1;
943#else
944 uint64_t reserved_0_0:1;
945 uint64_t carext:1;
946 uint64_t reserved_2_2:1;
947 uint64_t jabber:1;
948 uint64_t fcserr:1;
949 uint64_t alnerr:1;
950 uint64_t reserved_6_6:1;
951 uint64_t rcverr:1;
952 uint64_t skperr:1;
953 uint64_t niberr:1;
954 uint64_t ovrerr:1;
955 uint64_t pcterr:1;
956 uint64_t rsverr:1;
957 uint64_t falerr:1;
958 uint64_t coldet:1;
959 uint64_t ifgerr:1;
960 uint64_t phy_link:1;
961 uint64_t phy_spd:1;
962 uint64_t phy_dupx:1;
963 uint64_t pause_drp:1;
964 uint64_t reserved_20_63:44;
965#endif
966 } cn50xx;
967 struct cvmx_gmxx_rxx_int_en_cn52xx {
968#ifdef __BIG_ENDIAN_BITFIELD
969 uint64_t reserved_29_63:35;
970 uint64_t hg2cc:1;
971 uint64_t hg2fld:1;
972 uint64_t undat:1;
973 uint64_t uneop:1;
974 uint64_t unsop:1;
975 uint64_t bad_term:1;
976 uint64_t bad_seq:1;
977 uint64_t rem_fault:1;
978 uint64_t loc_fault:1;
979 uint64_t pause_drp:1;
980 uint64_t reserved_16_18:3;
981 uint64_t ifgerr:1;
982 uint64_t coldet:1;
983 uint64_t falerr:1;
984 uint64_t rsverr:1;
985 uint64_t pcterr:1;
986 uint64_t ovrerr:1;
987 uint64_t reserved_9_9:1;
988 uint64_t skperr:1;
989 uint64_t rcverr:1;
990 uint64_t reserved_5_6:2;
991 uint64_t fcserr:1;
992 uint64_t jabber:1;
993 uint64_t reserved_2_2:1;
994 uint64_t carext:1;
995 uint64_t reserved_0_0:1;
996#else
997 uint64_t reserved_0_0:1;
998 uint64_t carext:1;
999 uint64_t reserved_2_2:1;
1000 uint64_t jabber:1;
1001 uint64_t fcserr:1;
1002 uint64_t reserved_5_6:2;
1003 uint64_t rcverr:1;
1004 uint64_t skperr:1;
1005 uint64_t reserved_9_9:1;
1006 uint64_t ovrerr:1;
1007 uint64_t pcterr:1;
1008 uint64_t rsverr:1;
1009 uint64_t falerr:1;
1010 uint64_t coldet:1;
1011 uint64_t ifgerr:1;
1012 uint64_t reserved_16_18:3;
1013 uint64_t pause_drp:1;
1014 uint64_t loc_fault:1;
1015 uint64_t rem_fault:1;
1016 uint64_t bad_seq:1;
1017 uint64_t bad_term:1;
1018 uint64_t unsop:1;
1019 uint64_t uneop:1;
1020 uint64_t undat:1;
1021 uint64_t hg2fld:1;
1022 uint64_t hg2cc:1;
1023 uint64_t reserved_29_63:35;
1024#endif
1025 } cn52xx;
1026 struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
1027#ifdef __BIG_ENDIAN_BITFIELD
1028 uint64_t reserved_27_63:37;
1029 uint64_t undat:1;
1030 uint64_t uneop:1;
1031 uint64_t unsop:1;
1032 uint64_t bad_term:1;
1033 uint64_t bad_seq:1;
1034 uint64_t rem_fault:1;
1035 uint64_t loc_fault:1;
1036 uint64_t pause_drp:1;
1037 uint64_t reserved_16_18:3;
1038 uint64_t ifgerr:1;
1039 uint64_t coldet:1;
1040 uint64_t falerr:1;
1041 uint64_t rsverr:1;
1042 uint64_t pcterr:1;
1043 uint64_t ovrerr:1;
1044 uint64_t reserved_9_9:1;
1045 uint64_t skperr:1;
1046 uint64_t rcverr:1;
1047 uint64_t reserved_5_6:2;
1048 uint64_t fcserr:1;
1049 uint64_t jabber:1;
1050 uint64_t reserved_2_2:1;
1051 uint64_t carext:1;
1052 uint64_t reserved_0_0:1;
1053#else
1054 uint64_t reserved_0_0:1;
1055 uint64_t carext:1;
1056 uint64_t reserved_2_2:1;
1057 uint64_t jabber:1;
1058 uint64_t fcserr:1;
1059 uint64_t reserved_5_6:2;
1060 uint64_t rcverr:1;
1061 uint64_t skperr:1;
1062 uint64_t reserved_9_9:1;
1063 uint64_t ovrerr:1;
1064 uint64_t pcterr:1;
1065 uint64_t rsverr:1;
1066 uint64_t falerr:1;
1067 uint64_t coldet:1;
1068 uint64_t ifgerr:1;
1069 uint64_t reserved_16_18:3;
1070 uint64_t pause_drp:1;
1071 uint64_t loc_fault:1;
1072 uint64_t rem_fault:1;
1073 uint64_t bad_seq:1;
1074 uint64_t bad_term:1;
1075 uint64_t unsop:1;
1076 uint64_t uneop:1;
1077 uint64_t undat:1;
1078 uint64_t reserved_27_63:37;
1079#endif
1080 } cn56xxp1;
1081 struct cvmx_gmxx_rxx_int_en_cn58xx {
1082#ifdef __BIG_ENDIAN_BITFIELD
1083 uint64_t reserved_20_63:44;
1084 uint64_t pause_drp:1;
1085 uint64_t phy_dupx:1;
1086 uint64_t phy_spd:1;
1087 uint64_t phy_link:1;
1088 uint64_t ifgerr:1;
1089 uint64_t coldet:1;
1090 uint64_t falerr:1;
1091 uint64_t rsverr:1;
1092 uint64_t pcterr:1;
1093 uint64_t ovrerr:1;
1094 uint64_t niberr:1;
1095 uint64_t skperr:1;
1096 uint64_t rcverr:1;
1097 uint64_t lenerr:1;
1098 uint64_t alnerr:1;
1099 uint64_t fcserr:1;
1100 uint64_t jabber:1;
1101 uint64_t maxerr:1;
1102 uint64_t carext:1;
1103 uint64_t minerr:1;
1104#else
1105 uint64_t minerr:1;
1106 uint64_t carext:1;
1107 uint64_t maxerr:1;
1108 uint64_t jabber:1;
1109 uint64_t fcserr:1;
1110 uint64_t alnerr:1;
1111 uint64_t lenerr:1;
1112 uint64_t rcverr:1;
1113 uint64_t skperr:1;
1114 uint64_t niberr:1;
1115 uint64_t ovrerr:1;
1116 uint64_t pcterr:1;
1117 uint64_t rsverr:1;
1118 uint64_t falerr:1;
1119 uint64_t coldet:1;
1120 uint64_t ifgerr:1;
1121 uint64_t phy_link:1;
1122 uint64_t phy_spd:1;
1123 uint64_t phy_dupx:1;
1124 uint64_t pause_drp:1;
1125 uint64_t reserved_20_63:44;
1126#endif
1127 } cn58xx;
1128 struct cvmx_gmxx_rxx_int_en_cn61xx {
1129#ifdef __BIG_ENDIAN_BITFIELD
1130 uint64_t reserved_29_63:35;
1131 uint64_t hg2cc:1;
1132 uint64_t hg2fld:1;
1133 uint64_t undat:1;
1134 uint64_t uneop:1;
1135 uint64_t unsop:1;
1136 uint64_t bad_term:1;
1137 uint64_t bad_seq:1;
1138 uint64_t rem_fault:1;
1139 uint64_t loc_fault:1;
1140 uint64_t pause_drp:1;
1141 uint64_t reserved_16_18:3;
1142 uint64_t ifgerr:1;
1143 uint64_t coldet:1;
1144 uint64_t falerr:1;
1145 uint64_t rsverr:1;
1146 uint64_t pcterr:1;
1147 uint64_t ovrerr:1;
1148 uint64_t reserved_9_9:1;
1149 uint64_t skperr:1;
1150 uint64_t rcverr:1;
1151 uint64_t reserved_5_6:2;
1152 uint64_t fcserr:1;
1153 uint64_t jabber:1;
1154 uint64_t reserved_2_2:1;
1155 uint64_t carext:1;
1156 uint64_t minerr:1;
1157#else
1158 uint64_t minerr:1;
1159 uint64_t carext:1;
1160 uint64_t reserved_2_2:1;
1161 uint64_t jabber:1;
1162 uint64_t fcserr:1;
1163 uint64_t reserved_5_6:2;
1164 uint64_t rcverr:1;
1165 uint64_t skperr:1;
1166 uint64_t reserved_9_9:1;
1167 uint64_t ovrerr:1;
1168 uint64_t pcterr:1;
1169 uint64_t rsverr:1;
1170 uint64_t falerr:1;
1171 uint64_t coldet:1;
1172 uint64_t ifgerr:1;
1173 uint64_t reserved_16_18:3;
1174 uint64_t pause_drp:1;
1175 uint64_t loc_fault:1;
1176 uint64_t rem_fault:1;
1177 uint64_t bad_seq:1;
1178 uint64_t bad_term:1;
1179 uint64_t unsop:1;
1180 uint64_t uneop:1;
1181 uint64_t undat:1;
1182 uint64_t hg2fld:1;
1183 uint64_t hg2cc:1;
1184 uint64_t reserved_29_63:35;
1185#endif
1186 } cn61xx;
1187};
1188
1189union cvmx_gmxx_rxx_int_reg {
1190 uint64_t u64;
1191 struct cvmx_gmxx_rxx_int_reg_s {
1192#ifdef __BIG_ENDIAN_BITFIELD
1193 uint64_t reserved_29_63:35;
1194 uint64_t hg2cc:1;
1195 uint64_t hg2fld:1;
1196 uint64_t undat:1;
1197 uint64_t uneop:1;
1198 uint64_t unsop:1;
1199 uint64_t bad_term:1;
1200 uint64_t bad_seq:1;
1201 uint64_t rem_fault:1;
1202 uint64_t loc_fault:1;
1203 uint64_t pause_drp:1;
1204 uint64_t phy_dupx:1;
1205 uint64_t phy_spd:1;
1206 uint64_t phy_link:1;
1207 uint64_t ifgerr:1;
1208 uint64_t coldet:1;
1209 uint64_t falerr:1;
1210 uint64_t rsverr:1;
1211 uint64_t pcterr:1;
1212 uint64_t ovrerr:1;
1213 uint64_t niberr:1;
1214 uint64_t skperr:1;
1215 uint64_t rcverr:1;
1216 uint64_t lenerr:1;
1217 uint64_t alnerr:1;
1218 uint64_t fcserr:1;
1219 uint64_t jabber:1;
1220 uint64_t maxerr:1;
1221 uint64_t carext:1;
1222 uint64_t minerr:1;
1223#else
1224 uint64_t minerr:1;
1225 uint64_t carext:1;
1226 uint64_t maxerr:1;
1227 uint64_t jabber:1;
1228 uint64_t fcserr:1;
1229 uint64_t alnerr:1;
1230 uint64_t lenerr:1;
1231 uint64_t rcverr:1;
1232 uint64_t skperr:1;
1233 uint64_t niberr:1;
1234 uint64_t ovrerr:1;
1235 uint64_t pcterr:1;
1236 uint64_t rsverr:1;
1237 uint64_t falerr:1;
1238 uint64_t coldet:1;
1239 uint64_t ifgerr:1;
1240 uint64_t phy_link:1;
1241 uint64_t phy_spd:1;
1242 uint64_t phy_dupx:1;
1243 uint64_t pause_drp:1;
1244 uint64_t loc_fault:1;
1245 uint64_t rem_fault:1;
1246 uint64_t bad_seq:1;
1247 uint64_t bad_term:1;
1248 uint64_t unsop:1;
1249 uint64_t uneop:1;
1250 uint64_t undat:1;
1251 uint64_t hg2fld:1;
1252 uint64_t hg2cc:1;
1253 uint64_t reserved_29_63:35;
1254#endif
1255 } s;
1256 struct cvmx_gmxx_rxx_int_reg_cn30xx {
1257#ifdef __BIG_ENDIAN_BITFIELD
1258 uint64_t reserved_19_63:45;
1259 uint64_t phy_dupx:1;
1260 uint64_t phy_spd:1;
1261 uint64_t phy_link:1;
1262 uint64_t ifgerr:1;
1263 uint64_t coldet:1;
1264 uint64_t falerr:1;
1265 uint64_t rsverr:1;
1266 uint64_t pcterr:1;
1267 uint64_t ovrerr:1;
1268 uint64_t niberr:1;
1269 uint64_t skperr:1;
1270 uint64_t rcverr:1;
1271 uint64_t lenerr:1;
1272 uint64_t alnerr:1;
1273 uint64_t fcserr:1;
1274 uint64_t jabber:1;
1275 uint64_t maxerr:1;
1276 uint64_t carext:1;
1277 uint64_t minerr:1;
1278#else
1279 uint64_t minerr:1;
1280 uint64_t carext:1;
1281 uint64_t maxerr:1;
1282 uint64_t jabber:1;
1283 uint64_t fcserr:1;
1284 uint64_t alnerr:1;
1285 uint64_t lenerr:1;
1286 uint64_t rcverr:1;
1287 uint64_t skperr:1;
1288 uint64_t niberr:1;
1289 uint64_t ovrerr:1;
1290 uint64_t pcterr:1;
1291 uint64_t rsverr:1;
1292 uint64_t falerr:1;
1293 uint64_t coldet:1;
1294 uint64_t ifgerr:1;
1295 uint64_t phy_link:1;
1296 uint64_t phy_spd:1;
1297 uint64_t phy_dupx:1;
1298 uint64_t reserved_19_63:45;
1299#endif
1300 } cn30xx;
1301 struct cvmx_gmxx_rxx_int_reg_cn50xx {
1302#ifdef __BIG_ENDIAN_BITFIELD
1303 uint64_t reserved_20_63:44;
1304 uint64_t pause_drp:1;
1305 uint64_t phy_dupx:1;
1306 uint64_t phy_spd:1;
1307 uint64_t phy_link:1;
1308 uint64_t ifgerr:1;
1309 uint64_t coldet:1;
1310 uint64_t falerr:1;
1311 uint64_t rsverr:1;
1312 uint64_t pcterr:1;
1313 uint64_t ovrerr:1;
1314 uint64_t niberr:1;
1315 uint64_t skperr:1;
1316 uint64_t rcverr:1;
1317 uint64_t reserved_6_6:1;
1318 uint64_t alnerr:1;
1319 uint64_t fcserr:1;
1320 uint64_t jabber:1;
1321 uint64_t reserved_2_2:1;
1322 uint64_t carext:1;
1323 uint64_t reserved_0_0:1;
1324#else
1325 uint64_t reserved_0_0:1;
1326 uint64_t carext:1;
1327 uint64_t reserved_2_2:1;
1328 uint64_t jabber:1;
1329 uint64_t fcserr:1;
1330 uint64_t alnerr:1;
1331 uint64_t reserved_6_6:1;
1332 uint64_t rcverr:1;
1333 uint64_t skperr:1;
1334 uint64_t niberr:1;
1335 uint64_t ovrerr:1;
1336 uint64_t pcterr:1;
1337 uint64_t rsverr:1;
1338 uint64_t falerr:1;
1339 uint64_t coldet:1;
1340 uint64_t ifgerr:1;
1341 uint64_t phy_link:1;
1342 uint64_t phy_spd:1;
1343 uint64_t phy_dupx:1;
1344 uint64_t pause_drp:1;
1345 uint64_t reserved_20_63:44;
1346#endif
1347 } cn50xx;
1348 struct cvmx_gmxx_rxx_int_reg_cn52xx {
1349#ifdef __BIG_ENDIAN_BITFIELD
1350 uint64_t reserved_29_63:35;
1351 uint64_t hg2cc:1;
1352 uint64_t hg2fld:1;
1353 uint64_t undat:1;
1354 uint64_t uneop:1;
1355 uint64_t unsop:1;
1356 uint64_t bad_term:1;
1357 uint64_t bad_seq:1;
1358 uint64_t rem_fault:1;
1359 uint64_t loc_fault:1;
1360 uint64_t pause_drp:1;
1361 uint64_t reserved_16_18:3;
1362 uint64_t ifgerr:1;
1363 uint64_t coldet:1;
1364 uint64_t falerr:1;
1365 uint64_t rsverr:1;
1366 uint64_t pcterr:1;
1367 uint64_t ovrerr:1;
1368 uint64_t reserved_9_9:1;
1369 uint64_t skperr:1;
1370 uint64_t rcverr:1;
1371 uint64_t reserved_5_6:2;
1372 uint64_t fcserr:1;
1373 uint64_t jabber:1;
1374 uint64_t reserved_2_2:1;
1375 uint64_t carext:1;
1376 uint64_t reserved_0_0:1;
1377#else
1378 uint64_t reserved_0_0:1;
1379 uint64_t carext:1;
1380 uint64_t reserved_2_2:1;
1381 uint64_t jabber:1;
1382 uint64_t fcserr:1;
1383 uint64_t reserved_5_6:2;
1384 uint64_t rcverr:1;
1385 uint64_t skperr:1;
1386 uint64_t reserved_9_9:1;
1387 uint64_t ovrerr:1;
1388 uint64_t pcterr:1;
1389 uint64_t rsverr:1;
1390 uint64_t falerr:1;
1391 uint64_t coldet:1;
1392 uint64_t ifgerr:1;
1393 uint64_t reserved_16_18:3;
1394 uint64_t pause_drp:1;
1395 uint64_t loc_fault:1;
1396 uint64_t rem_fault:1;
1397 uint64_t bad_seq:1;
1398 uint64_t bad_term:1;
1399 uint64_t unsop:1;
1400 uint64_t uneop:1;
1401 uint64_t undat:1;
1402 uint64_t hg2fld:1;
1403 uint64_t hg2cc:1;
1404 uint64_t reserved_29_63:35;
1405#endif
1406 } cn52xx;
1407 struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
1408#ifdef __BIG_ENDIAN_BITFIELD
1409 uint64_t reserved_27_63:37;
1410 uint64_t undat:1;
1411 uint64_t uneop:1;
1412 uint64_t unsop:1;
1413 uint64_t bad_term:1;
1414 uint64_t bad_seq:1;
1415 uint64_t rem_fault:1;
1416 uint64_t loc_fault:1;
1417 uint64_t pause_drp:1;
1418 uint64_t reserved_16_18:3;
1419 uint64_t ifgerr:1;
1420 uint64_t coldet:1;
1421 uint64_t falerr:1;
1422 uint64_t rsverr:1;
1423 uint64_t pcterr:1;
1424 uint64_t ovrerr:1;
1425 uint64_t reserved_9_9:1;
1426 uint64_t skperr:1;
1427 uint64_t rcverr:1;
1428 uint64_t reserved_5_6:2;
1429 uint64_t fcserr:1;
1430 uint64_t jabber:1;
1431 uint64_t reserved_2_2:1;
1432 uint64_t carext:1;
1433 uint64_t reserved_0_0:1;
1434#else
1435 uint64_t reserved_0_0:1;
1436 uint64_t carext:1;
1437 uint64_t reserved_2_2:1;
1438 uint64_t jabber:1;
1439 uint64_t fcserr:1;
1440 uint64_t reserved_5_6:2;
1441 uint64_t rcverr:1;
1442 uint64_t skperr:1;
1443 uint64_t reserved_9_9:1;
1444 uint64_t ovrerr:1;
1445 uint64_t pcterr:1;
1446 uint64_t rsverr:1;
1447 uint64_t falerr:1;
1448 uint64_t coldet:1;
1449 uint64_t ifgerr:1;
1450 uint64_t reserved_16_18:3;
1451 uint64_t pause_drp:1;
1452 uint64_t loc_fault:1;
1453 uint64_t rem_fault:1;
1454 uint64_t bad_seq:1;
1455 uint64_t bad_term:1;
1456 uint64_t unsop:1;
1457 uint64_t uneop:1;
1458 uint64_t undat:1;
1459 uint64_t reserved_27_63:37;
1460#endif
1461 } cn56xxp1;
1462 struct cvmx_gmxx_rxx_int_reg_cn58xx {
1463#ifdef __BIG_ENDIAN_BITFIELD
1464 uint64_t reserved_20_63:44;
1465 uint64_t pause_drp:1;
1466 uint64_t phy_dupx:1;
1467 uint64_t phy_spd:1;
1468 uint64_t phy_link:1;
1469 uint64_t ifgerr:1;
1470 uint64_t coldet:1;
1471 uint64_t falerr:1;
1472 uint64_t rsverr:1;
1473 uint64_t pcterr:1;
1474 uint64_t ovrerr:1;
1475 uint64_t niberr:1;
1476 uint64_t skperr:1;
1477 uint64_t rcverr:1;
1478 uint64_t lenerr:1;
1479 uint64_t alnerr:1;
1480 uint64_t fcserr:1;
1481 uint64_t jabber:1;
1482 uint64_t maxerr:1;
1483 uint64_t carext:1;
1484 uint64_t minerr:1;
1485#else
1486 uint64_t minerr:1;
1487 uint64_t carext:1;
1488 uint64_t maxerr:1;
1489 uint64_t jabber:1;
1490 uint64_t fcserr:1;
1491 uint64_t alnerr:1;
1492 uint64_t lenerr:1;
1493 uint64_t rcverr:1;
1494 uint64_t skperr:1;
1495 uint64_t niberr:1;
1496 uint64_t ovrerr:1;
1497 uint64_t pcterr:1;
1498 uint64_t rsverr:1;
1499 uint64_t falerr:1;
1500 uint64_t coldet:1;
1501 uint64_t ifgerr:1;
1502 uint64_t phy_link:1;
1503 uint64_t phy_spd:1;
1504 uint64_t phy_dupx:1;
1505 uint64_t pause_drp:1;
1506 uint64_t reserved_20_63:44;
1507#endif
1508 } cn58xx;
1509 struct cvmx_gmxx_rxx_int_reg_cn61xx {
1510#ifdef __BIG_ENDIAN_BITFIELD
1511 uint64_t reserved_29_63:35;
1512 uint64_t hg2cc:1;
1513 uint64_t hg2fld:1;
1514 uint64_t undat:1;
1515 uint64_t uneop:1;
1516 uint64_t unsop:1;
1517 uint64_t bad_term:1;
1518 uint64_t bad_seq:1;
1519 uint64_t rem_fault:1;
1520 uint64_t loc_fault:1;
1521 uint64_t pause_drp:1;
1522 uint64_t reserved_16_18:3;
1523 uint64_t ifgerr:1;
1524 uint64_t coldet:1;
1525 uint64_t falerr:1;
1526 uint64_t rsverr:1;
1527 uint64_t pcterr:1;
1528 uint64_t ovrerr:1;
1529 uint64_t reserved_9_9:1;
1530 uint64_t skperr:1;
1531 uint64_t rcverr:1;
1532 uint64_t reserved_5_6:2;
1533 uint64_t fcserr:1;
1534 uint64_t jabber:1;
1535 uint64_t reserved_2_2:1;
1536 uint64_t carext:1;
1537 uint64_t minerr:1;
1538#else
1539 uint64_t minerr:1;
1540 uint64_t carext:1;
1541 uint64_t reserved_2_2:1;
1542 uint64_t jabber:1;
1543 uint64_t fcserr:1;
1544 uint64_t reserved_5_6:2;
1545 uint64_t rcverr:1;
1546 uint64_t skperr:1;
1547 uint64_t reserved_9_9:1;
1548 uint64_t ovrerr:1;
1549 uint64_t pcterr:1;
1550 uint64_t rsverr:1;
1551 uint64_t falerr:1;
1552 uint64_t coldet:1;
1553 uint64_t ifgerr:1;
1554 uint64_t reserved_16_18:3;
1555 uint64_t pause_drp:1;
1556 uint64_t loc_fault:1;
1557 uint64_t rem_fault:1;
1558 uint64_t bad_seq:1;
1559 uint64_t bad_term:1;
1560 uint64_t unsop:1;
1561 uint64_t uneop:1;
1562 uint64_t undat:1;
1563 uint64_t hg2fld:1;
1564 uint64_t hg2cc:1;
1565 uint64_t reserved_29_63:35;
1566#endif
1567 } cn61xx;
1568};
1569
1570union cvmx_gmxx_rxx_jabber {
1571 uint64_t u64;
1572 struct cvmx_gmxx_rxx_jabber_s {
1573#ifdef __BIG_ENDIAN_BITFIELD
1574 uint64_t reserved_16_63:48;
1575 uint64_t cnt:16;
1576#else
1577 uint64_t cnt:16;
1578 uint64_t reserved_16_63:48;
1579#endif
1580 } s;
1581};
1582
1583union cvmx_gmxx_rxx_rx_inbnd {
1584 uint64_t u64;
1585 struct cvmx_gmxx_rxx_rx_inbnd_s {
1586#ifdef __BIG_ENDIAN_BITFIELD
1587 uint64_t reserved_4_63:60;
1588 uint64_t duplex:1;
1589 uint64_t speed:2;
1590 uint64_t status:1;
1591#else
1592 uint64_t status:1;
1593 uint64_t speed:2;
1594 uint64_t duplex:1;
1595 uint64_t reserved_4_63:60;
1596#endif
1597 } s;
1598};
1599
1600union cvmx_gmxx_rx_prts {
1601 uint64_t u64;
1602 struct cvmx_gmxx_rx_prts_s {
1603#ifdef __BIG_ENDIAN_BITFIELD
1604 uint64_t reserved_3_63:61;
1605 uint64_t prts:3;
1606#else
1607 uint64_t prts:3;
1608 uint64_t reserved_3_63:61;
1609#endif
1610 } s;
1611};
1612
1613union cvmx_gmxx_rx_xaui_ctl {
1614 uint64_t u64;
1615 struct cvmx_gmxx_rx_xaui_ctl_s {
1616#ifdef __BIG_ENDIAN_BITFIELD
1617 uint64_t reserved_2_63:62;
1618 uint64_t status:2;
1619#else
1620 uint64_t status:2;
1621 uint64_t reserved_2_63:62;
1622#endif
1623 } s;
1624};
1625
1626union cvmx_gmxx_txx_thresh {
1627 uint64_t u64;
1628 struct cvmx_gmxx_txx_thresh_s {
1629#ifdef __BIG_ENDIAN_BITFIELD
1630 uint64_t reserved_10_63:54;
1631 uint64_t cnt:10;
1632#else
1633 uint64_t cnt:10;
1634 uint64_t reserved_10_63:54;
1635#endif
1636 } s;
1637 struct cvmx_gmxx_txx_thresh_cn30xx {
1638#ifdef __BIG_ENDIAN_BITFIELD
1639 uint64_t reserved_7_63:57;
1640 uint64_t cnt:7;
1641#else
1642 uint64_t cnt:7;
1643 uint64_t reserved_7_63:57;
1644#endif
1645 } cn30xx;
1646 struct cvmx_gmxx_txx_thresh_cn38xx {
1647#ifdef __BIG_ENDIAN_BITFIELD
1648 uint64_t reserved_9_63:55;
1649 uint64_t cnt:9;
1650#else
1651 uint64_t cnt:9;
1652 uint64_t reserved_9_63:55;
1653#endif
1654 } cn38xx;
1655};
1656
1657union cvmx_gmxx_tx_int_en {
1658 uint64_t u64;
1659 struct cvmx_gmxx_tx_int_en_s {
1660#ifdef __BIG_ENDIAN_BITFIELD
1661 uint64_t reserved_25_63:39;
1662 uint64_t xchange:1;
1663 uint64_t ptp_lost:4;
1664 uint64_t late_col:4;
1665 uint64_t xsdef:4;
1666 uint64_t xscol:4;
1667 uint64_t reserved_6_7:2;
1668 uint64_t undflw:4;
1669 uint64_t reserved_1_1:1;
1670 uint64_t pko_nxa:1;
1671#else
1672 uint64_t pko_nxa:1;
1673 uint64_t reserved_1_1:1;
1674 uint64_t undflw:4;
1675 uint64_t reserved_6_7:2;
1676 uint64_t xscol:4;
1677 uint64_t xsdef:4;
1678 uint64_t late_col:4;
1679 uint64_t ptp_lost:4;
1680 uint64_t xchange:1;
1681 uint64_t reserved_25_63:39;
1682#endif
1683 } s;
1684 struct cvmx_gmxx_tx_int_en_cn30xx {
1685#ifdef __BIG_ENDIAN_BITFIELD
1686 uint64_t reserved_19_63:45;
1687 uint64_t late_col:3;
1688 uint64_t reserved_15_15:1;
1689 uint64_t xsdef:3;
1690 uint64_t reserved_11_11:1;
1691 uint64_t xscol:3;
1692 uint64_t reserved_5_7:3;
1693 uint64_t undflw:3;
1694 uint64_t reserved_1_1:1;
1695 uint64_t pko_nxa:1;
1696#else
1697 uint64_t pko_nxa:1;
1698 uint64_t reserved_1_1:1;
1699 uint64_t undflw:3;
1700 uint64_t reserved_5_7:3;
1701 uint64_t xscol:3;
1702 uint64_t reserved_11_11:1;
1703 uint64_t xsdef:3;
1704 uint64_t reserved_15_15:1;
1705 uint64_t late_col:3;
1706 uint64_t reserved_19_63:45;
1707#endif
1708 } cn30xx;
1709 struct cvmx_gmxx_tx_int_en_cn31xx {
1710#ifdef __BIG_ENDIAN_BITFIELD
1711 uint64_t reserved_15_63:49;
1712 uint64_t xsdef:3;
1713 uint64_t reserved_11_11:1;
1714 uint64_t xscol:3;
1715 uint64_t reserved_5_7:3;
1716 uint64_t undflw:3;
1717 uint64_t reserved_1_1:1;
1718 uint64_t pko_nxa:1;
1719#else
1720 uint64_t pko_nxa:1;
1721 uint64_t reserved_1_1:1;
1722 uint64_t undflw:3;
1723 uint64_t reserved_5_7:3;
1724 uint64_t xscol:3;
1725 uint64_t reserved_11_11:1;
1726 uint64_t xsdef:3;
1727 uint64_t reserved_15_63:49;
1728#endif
1729 } cn31xx;
1730 struct cvmx_gmxx_tx_int_en_cn38xx {
1731#ifdef __BIG_ENDIAN_BITFIELD
1732 uint64_t reserved_20_63:44;
1733 uint64_t late_col:4;
1734 uint64_t xsdef:4;
1735 uint64_t xscol:4;
1736 uint64_t reserved_6_7:2;
1737 uint64_t undflw:4;
1738 uint64_t ncb_nxa:1;
1739 uint64_t pko_nxa:1;
1740#else
1741 uint64_t pko_nxa:1;
1742 uint64_t ncb_nxa:1;
1743 uint64_t undflw:4;
1744 uint64_t reserved_6_7:2;
1745 uint64_t xscol:4;
1746 uint64_t xsdef:4;
1747 uint64_t late_col:4;
1748 uint64_t reserved_20_63:44;
1749#endif
1750 } cn38xx;
1751 struct cvmx_gmxx_tx_int_en_cn38xxp2 {
1752#ifdef __BIG_ENDIAN_BITFIELD
1753 uint64_t reserved_16_63:48;
1754 uint64_t xsdef:4;
1755 uint64_t xscol:4;
1756 uint64_t reserved_6_7:2;
1757 uint64_t undflw:4;
1758 uint64_t ncb_nxa:1;
1759 uint64_t pko_nxa:1;
1760#else
1761 uint64_t pko_nxa:1;
1762 uint64_t ncb_nxa:1;
1763 uint64_t undflw:4;
1764 uint64_t reserved_6_7:2;
1765 uint64_t xscol:4;
1766 uint64_t xsdef:4;
1767 uint64_t reserved_16_63:48;
1768#endif
1769 } cn38xxp2;
1770 struct cvmx_gmxx_tx_int_en_cn52xx {
1771#ifdef __BIG_ENDIAN_BITFIELD
1772 uint64_t reserved_20_63:44;
1773 uint64_t late_col:4;
1774 uint64_t xsdef:4;
1775 uint64_t xscol:4;
1776 uint64_t reserved_6_7:2;
1777 uint64_t undflw:4;
1778 uint64_t reserved_1_1:1;
1779 uint64_t pko_nxa:1;
1780#else
1781 uint64_t pko_nxa:1;
1782 uint64_t reserved_1_1:1;
1783 uint64_t undflw:4;
1784 uint64_t reserved_6_7:2;
1785 uint64_t xscol:4;
1786 uint64_t xsdef:4;
1787 uint64_t late_col:4;
1788 uint64_t reserved_20_63:44;
1789#endif
1790 } cn52xx;
1791 struct cvmx_gmxx_tx_int_en_cn63xx {
1792#ifdef __BIG_ENDIAN_BITFIELD
1793 uint64_t reserved_24_63:40;
1794 uint64_t ptp_lost:4;
1795 uint64_t late_col:4;
1796 uint64_t xsdef:4;
1797 uint64_t xscol:4;
1798 uint64_t reserved_6_7:2;
1799 uint64_t undflw:4;
1800 uint64_t reserved_1_1:1;
1801 uint64_t pko_nxa:1;
1802#else
1803 uint64_t pko_nxa:1;
1804 uint64_t reserved_1_1:1;
1805 uint64_t undflw:4;
1806 uint64_t reserved_6_7:2;
1807 uint64_t xscol:4;
1808 uint64_t xsdef:4;
1809 uint64_t late_col:4;
1810 uint64_t ptp_lost:4;
1811 uint64_t reserved_24_63:40;
1812#endif
1813 } cn63xx;
1814 struct cvmx_gmxx_tx_int_en_cn68xx {
1815#ifdef __BIG_ENDIAN_BITFIELD
1816 uint64_t reserved_25_63:39;
1817 uint64_t xchange:1;
1818 uint64_t ptp_lost:4;
1819 uint64_t late_col:4;
1820 uint64_t xsdef:4;
1821 uint64_t xscol:4;
1822 uint64_t reserved_6_7:2;
1823 uint64_t undflw:4;
1824 uint64_t pko_nxp:1;
1825 uint64_t pko_nxa:1;
1826#else
1827 uint64_t pko_nxa:1;
1828 uint64_t pko_nxp:1;
1829 uint64_t undflw:4;
1830 uint64_t reserved_6_7:2;
1831 uint64_t xscol:4;
1832 uint64_t xsdef:4;
1833 uint64_t late_col:4;
1834 uint64_t ptp_lost:4;
1835 uint64_t xchange:1;
1836 uint64_t reserved_25_63:39;
1837#endif
1838 } cn68xx;
1839 struct cvmx_gmxx_tx_int_en_cnf71xx {
1840#ifdef __BIG_ENDIAN_BITFIELD
1841 uint64_t reserved_25_63:39;
1842 uint64_t xchange:1;
1843 uint64_t reserved_22_23:2;
1844 uint64_t ptp_lost:2;
1845 uint64_t reserved_18_19:2;
1846 uint64_t late_col:2;
1847 uint64_t reserved_14_15:2;
1848 uint64_t xsdef:2;
1849 uint64_t reserved_10_11:2;
1850 uint64_t xscol:2;
1851 uint64_t reserved_4_7:4;
1852 uint64_t undflw:2;
1853 uint64_t reserved_1_1:1;
1854 uint64_t pko_nxa:1;
1855#else
1856 uint64_t pko_nxa:1;
1857 uint64_t reserved_1_1:1;
1858 uint64_t undflw:2;
1859 uint64_t reserved_4_7:4;
1860 uint64_t xscol:2;
1861 uint64_t reserved_10_11:2;
1862 uint64_t xsdef:2;
1863 uint64_t reserved_14_15:2;
1864 uint64_t late_col:2;
1865 uint64_t reserved_18_19:2;
1866 uint64_t ptp_lost:2;
1867 uint64_t reserved_22_23:2;
1868 uint64_t xchange:1;
1869 uint64_t reserved_25_63:39;
1870#endif
1871 } cnf71xx;
1872};
1873
1874union cvmx_gmxx_tx_int_reg {
1875 uint64_t u64;
1876 struct cvmx_gmxx_tx_int_reg_s {
1877#ifdef __BIG_ENDIAN_BITFIELD
1878 uint64_t reserved_25_63:39;
1879 uint64_t xchange:1;
1880 uint64_t ptp_lost:4;
1881 uint64_t late_col:4;
1882 uint64_t xsdef:4;
1883 uint64_t xscol:4;
1884 uint64_t reserved_6_7:2;
1885 uint64_t undflw:4;
1886 uint64_t reserved_1_1:1;
1887 uint64_t pko_nxa:1;
1888#else
1889 uint64_t pko_nxa:1;
1890 uint64_t reserved_1_1:1;
1891 uint64_t undflw:4;
1892 uint64_t reserved_6_7:2;
1893 uint64_t xscol:4;
1894 uint64_t xsdef:4;
1895 uint64_t late_col:4;
1896 uint64_t ptp_lost:4;
1897 uint64_t xchange:1;
1898 uint64_t reserved_25_63:39;
1899#endif
1900 } s;
1901 struct cvmx_gmxx_tx_int_reg_cn30xx {
1902#ifdef __BIG_ENDIAN_BITFIELD
1903 uint64_t reserved_19_63:45;
1904 uint64_t late_col:3;
1905 uint64_t reserved_15_15:1;
1906 uint64_t xsdef:3;
1907 uint64_t reserved_11_11:1;
1908 uint64_t xscol:3;
1909 uint64_t reserved_5_7:3;
1910 uint64_t undflw:3;
1911 uint64_t reserved_1_1:1;
1912 uint64_t pko_nxa:1;
1913#else
1914 uint64_t pko_nxa:1;
1915 uint64_t reserved_1_1:1;
1916 uint64_t undflw:3;
1917 uint64_t reserved_5_7:3;
1918 uint64_t xscol:3;
1919 uint64_t reserved_11_11:1;
1920 uint64_t xsdef:3;
1921 uint64_t reserved_15_15:1;
1922 uint64_t late_col:3;
1923 uint64_t reserved_19_63:45;
1924#endif
1925 } cn30xx;
1926 struct cvmx_gmxx_tx_int_reg_cn31xx {
1927#ifdef __BIG_ENDIAN_BITFIELD
1928 uint64_t reserved_15_63:49;
1929 uint64_t xsdef:3;
1930 uint64_t reserved_11_11:1;
1931 uint64_t xscol:3;
1932 uint64_t reserved_5_7:3;
1933 uint64_t undflw:3;
1934 uint64_t reserved_1_1:1;
1935 uint64_t pko_nxa:1;
1936#else
1937 uint64_t pko_nxa:1;
1938 uint64_t reserved_1_1:1;
1939 uint64_t undflw:3;
1940 uint64_t reserved_5_7:3;
1941 uint64_t xscol:3;
1942 uint64_t reserved_11_11:1;
1943 uint64_t xsdef:3;
1944 uint64_t reserved_15_63:49;
1945#endif
1946 } cn31xx;
1947 struct cvmx_gmxx_tx_int_reg_cn38xx {
1948#ifdef __BIG_ENDIAN_BITFIELD
1949 uint64_t reserved_20_63:44;
1950 uint64_t late_col:4;
1951 uint64_t xsdef:4;
1952 uint64_t xscol:4;
1953 uint64_t reserved_6_7:2;
1954 uint64_t undflw:4;
1955 uint64_t ncb_nxa:1;
1956 uint64_t pko_nxa:1;
1957#else
1958 uint64_t pko_nxa:1;
1959 uint64_t ncb_nxa:1;
1960 uint64_t undflw:4;
1961 uint64_t reserved_6_7:2;
1962 uint64_t xscol:4;
1963 uint64_t xsdef:4;
1964 uint64_t late_col:4;
1965 uint64_t reserved_20_63:44;
1966#endif
1967 } cn38xx;
1968 struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
1969#ifdef __BIG_ENDIAN_BITFIELD
1970 uint64_t reserved_16_63:48;
1971 uint64_t xsdef:4;
1972 uint64_t xscol:4;
1973 uint64_t reserved_6_7:2;
1974 uint64_t undflw:4;
1975 uint64_t ncb_nxa:1;
1976 uint64_t pko_nxa:1;
1977#else
1978 uint64_t pko_nxa:1;
1979 uint64_t ncb_nxa:1;
1980 uint64_t undflw:4;
1981 uint64_t reserved_6_7:2;
1982 uint64_t xscol:4;
1983 uint64_t xsdef:4;
1984 uint64_t reserved_16_63:48;
1985#endif
1986 } cn38xxp2;
1987 struct cvmx_gmxx_tx_int_reg_cn52xx {
1988#ifdef __BIG_ENDIAN_BITFIELD
1989 uint64_t reserved_20_63:44;
1990 uint64_t late_col:4;
1991 uint64_t xsdef:4;
1992 uint64_t xscol:4;
1993 uint64_t reserved_6_7:2;
1994 uint64_t undflw:4;
1995 uint64_t reserved_1_1:1;
1996 uint64_t pko_nxa:1;
1997#else
1998 uint64_t pko_nxa:1;
1999 uint64_t reserved_1_1:1;
2000 uint64_t undflw:4;
2001 uint64_t reserved_6_7:2;
2002 uint64_t xscol:4;
2003 uint64_t xsdef:4;
2004 uint64_t late_col:4;
2005 uint64_t reserved_20_63:44;
2006#endif
2007 } cn52xx;
2008 struct cvmx_gmxx_tx_int_reg_cn63xx {
2009#ifdef __BIG_ENDIAN_BITFIELD
2010 uint64_t reserved_24_63:40;
2011 uint64_t ptp_lost:4;
2012 uint64_t late_col:4;
2013 uint64_t xsdef:4;
2014 uint64_t xscol:4;
2015 uint64_t reserved_6_7:2;
2016 uint64_t undflw:4;
2017 uint64_t reserved_1_1:1;
2018 uint64_t pko_nxa:1;
2019#else
2020 uint64_t pko_nxa:1;
2021 uint64_t reserved_1_1:1;
2022 uint64_t undflw:4;
2023 uint64_t reserved_6_7:2;
2024 uint64_t xscol:4;
2025 uint64_t xsdef:4;
2026 uint64_t late_col:4;
2027 uint64_t ptp_lost:4;
2028 uint64_t reserved_24_63:40;
2029#endif
2030 } cn63xx;
2031 struct cvmx_gmxx_tx_int_reg_cn68xx {
2032#ifdef __BIG_ENDIAN_BITFIELD
2033 uint64_t reserved_25_63:39;
2034 uint64_t xchange:1;
2035 uint64_t ptp_lost:4;
2036 uint64_t late_col:4;
2037 uint64_t xsdef:4;
2038 uint64_t xscol:4;
2039 uint64_t reserved_6_7:2;
2040 uint64_t undflw:4;
2041 uint64_t pko_nxp:1;
2042 uint64_t pko_nxa:1;
2043#else
2044 uint64_t pko_nxa:1;
2045 uint64_t pko_nxp:1;
2046 uint64_t undflw:4;
2047 uint64_t reserved_6_7:2;
2048 uint64_t xscol:4;
2049 uint64_t xsdef:4;
2050 uint64_t late_col:4;
2051 uint64_t ptp_lost:4;
2052 uint64_t xchange:1;
2053 uint64_t reserved_25_63:39;
2054#endif
2055 } cn68xx;
2056 struct cvmx_gmxx_tx_int_reg_cnf71xx {
2057#ifdef __BIG_ENDIAN_BITFIELD
2058 uint64_t reserved_25_63:39;
2059 uint64_t xchange:1;
2060 uint64_t reserved_22_23:2;
2061 uint64_t ptp_lost:2;
2062 uint64_t reserved_18_19:2;
2063 uint64_t late_col:2;
2064 uint64_t reserved_14_15:2;
2065 uint64_t xsdef:2;
2066 uint64_t reserved_10_11:2;
2067 uint64_t xscol:2;
2068 uint64_t reserved_4_7:4;
2069 uint64_t undflw:2;
2070 uint64_t reserved_1_1:1;
2071 uint64_t pko_nxa:1;
2072#else
2073 uint64_t pko_nxa:1;
2074 uint64_t reserved_1_1:1;
2075 uint64_t undflw:2;
2076 uint64_t reserved_4_7:4;
2077 uint64_t xscol:2;
2078 uint64_t reserved_10_11:2;
2079 uint64_t xsdef:2;
2080 uint64_t reserved_14_15:2;
2081 uint64_t late_col:2;
2082 uint64_t reserved_18_19:2;
2083 uint64_t ptp_lost:2;
2084 uint64_t reserved_22_23:2;
2085 uint64_t xchange:1;
2086 uint64_t reserved_25_63:39;
2087#endif
2088 } cnf71xx;
2089};
2090
2091union cvmx_gmxx_tx_ovr_bp {
2092 uint64_t u64;
2093 struct cvmx_gmxx_tx_ovr_bp_s {
2094#ifdef __BIG_ENDIAN_BITFIELD
2095 uint64_t reserved_48_63:16;
2096 uint64_t tx_prt_bp:16;
2097 uint64_t reserved_12_31:20;
2098 uint64_t en:4;
2099 uint64_t bp:4;
2100 uint64_t ign_full:4;
2101#else
2102 uint64_t ign_full:4;
2103 uint64_t bp:4;
2104 uint64_t en:4;
2105 uint64_t reserved_12_31:20;
2106 uint64_t tx_prt_bp:16;
2107 uint64_t reserved_48_63:16;
2108#endif
2109 } s;
2110 struct cvmx_gmxx_tx_ovr_bp_cn30xx {
2111#ifdef __BIG_ENDIAN_BITFIELD
2112 uint64_t reserved_11_63:53;
2113 uint64_t en:3;
2114 uint64_t reserved_7_7:1;
2115 uint64_t bp:3;
2116 uint64_t reserved_3_3:1;
2117 uint64_t ign_full:3;
2118#else
2119 uint64_t ign_full:3;
2120 uint64_t reserved_3_3:1;
2121 uint64_t bp:3;
2122 uint64_t reserved_7_7:1;
2123 uint64_t en:3;
2124 uint64_t reserved_11_63:53;
2125#endif
2126 } cn30xx;
2127 struct cvmx_gmxx_tx_ovr_bp_cn38xx {
2128#ifdef __BIG_ENDIAN_BITFIELD
2129 uint64_t reserved_12_63:52;
2130 uint64_t en:4;
2131 uint64_t bp:4;
2132 uint64_t ign_full:4;
2133#else
2134 uint64_t ign_full:4;
2135 uint64_t bp:4;
2136 uint64_t en:4;
2137 uint64_t reserved_12_63:52;
2138#endif
2139 } cn38xx;
2140 struct cvmx_gmxx_tx_ovr_bp_cnf71xx {
2141#ifdef __BIG_ENDIAN_BITFIELD
2142 uint64_t reserved_48_63:16;
2143 uint64_t tx_prt_bp:16;
2144 uint64_t reserved_10_31:22;
2145 uint64_t en:2;
2146 uint64_t reserved_6_7:2;
2147 uint64_t bp:2;
2148 uint64_t reserved_2_3:2;
2149 uint64_t ign_full:2;
2150#else
2151 uint64_t ign_full:2;
2152 uint64_t reserved_2_3:2;
2153 uint64_t bp:2;
2154 uint64_t reserved_6_7:2;
2155 uint64_t en:2;
2156 uint64_t reserved_10_31:22;
2157 uint64_t tx_prt_bp:16;
2158 uint64_t reserved_48_63:16;
2159#endif
2160 } cnf71xx;
2161};
2162
2163union cvmx_gmxx_tx_prts {
2164 uint64_t u64;
2165 struct cvmx_gmxx_tx_prts_s {
2166#ifdef __BIG_ENDIAN_BITFIELD
2167 uint64_t reserved_5_63:59;
2168 uint64_t prts:5;
2169#else
2170 uint64_t prts:5;
2171 uint64_t reserved_5_63:59;
2172#endif
2173 } s;
2174};
2175
2176union cvmx_gmxx_tx_spi_ctl {
2177 uint64_t u64;
2178 struct cvmx_gmxx_tx_spi_ctl_s {
2179#ifdef __BIG_ENDIAN_BITFIELD
2180 uint64_t reserved_2_63:62;
2181 uint64_t tpa_clr:1;
2182 uint64_t cont_pkt:1;
2183#else
2184 uint64_t cont_pkt:1;
2185 uint64_t tpa_clr:1;
2186 uint64_t reserved_2_63:62;
2187#endif
2188 } s;
2189};
2190
2191union cvmx_gmxx_tx_spi_max {
2192 uint64_t u64;
2193 struct cvmx_gmxx_tx_spi_max_s {
2194#ifdef __BIG_ENDIAN_BITFIELD
2195 uint64_t reserved_23_63:41;
2196 uint64_t slice:7;
2197 uint64_t max2:8;
2198 uint64_t max1:8;
2199#else
2200 uint64_t max1:8;
2201 uint64_t max2:8;
2202 uint64_t slice:7;
2203 uint64_t reserved_23_63:41;
2204#endif
2205 } s;
2206 struct cvmx_gmxx_tx_spi_max_cn38xx {
2207#ifdef __BIG_ENDIAN_BITFIELD
2208 uint64_t reserved_16_63:48;
2209 uint64_t max2:8;
2210 uint64_t max1:8;
2211#else
2212 uint64_t max1:8;
2213 uint64_t max2:8;
2214 uint64_t reserved_16_63:48;
2215#endif
2216 } cn38xx;
2217};
2218
2219union cvmx_gmxx_tx_spi_thresh {
2220 uint64_t u64;
2221 struct cvmx_gmxx_tx_spi_thresh_s {
2222#ifdef __BIG_ENDIAN_BITFIELD
2223 uint64_t reserved_6_63:58;
2224 uint64_t thresh:6;
2225#else
2226 uint64_t thresh:6;
2227 uint64_t reserved_6_63:58;
2228#endif
2229 } s;
2230};
2231
2232union cvmx_gmxx_tx_xaui_ctl {
2233 uint64_t u64;
2234 struct cvmx_gmxx_tx_xaui_ctl_s {
2235#ifdef __BIG_ENDIAN_BITFIELD
2236 uint64_t reserved_11_63:53;
2237 uint64_t hg_pause_hgi:2;
2238 uint64_t hg_en:1;
2239 uint64_t reserved_7_7:1;
2240 uint64_t ls_byp:1;
2241 uint64_t ls:2;
2242 uint64_t reserved_2_3:2;
2243 uint64_t uni_en:1;
2244 uint64_t dic_en:1;
2245#else
2246 uint64_t dic_en:1;
2247 uint64_t uni_en:1;
2248 uint64_t reserved_2_3:2;
2249 uint64_t ls:2;
2250 uint64_t ls_byp:1;
2251 uint64_t reserved_7_7:1;
2252 uint64_t hg_en:1;
2253 uint64_t hg_pause_hgi:2;
2254 uint64_t reserved_11_63:53;
2255#endif
2256 } s;
2257};
2258
2259#endif
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_GMXX_DEFS_H__
29#define __CVMX_GMXX_DEFS_H__
30
31#define CVMX_GMXX_BAD_REG(block_id) \
32 CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_GMXX_BIST(block_id) \
34 CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_GMXX_CLK_EN(block_id) \
36 CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_GMXX_HG2_CONTROL(block_id) \
38 CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_GMXX_INF_MODE(block_id) \
40 CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_GMXX_NXA_ADR(block_id) \
42 CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \
44 CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_GMXX_PRTX_CFG(offset, block_id) \
46 CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \
48 CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \
50 CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \
52 CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \
54 CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \
56 CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \
58 CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \
60 CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \
62 CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
63#define CVMX_GMXX_RXX_DECISION(offset, block_id) \
64 CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
65#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \
66 CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
67#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \
68 CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
69#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \
70 CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
71#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \
72 CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
73#define CVMX_GMXX_RXX_IFG(offset, block_id) \
74 CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
75#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \
76 CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
77#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \
78 CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
79#define CVMX_GMXX_RXX_JABBER(offset, block_id) \
80 CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
81#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \
82 CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
83#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \
84 CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
85#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \
86 CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
87#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \
88 CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
89#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \
90 CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
91#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \
92 CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
93#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \
94 CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
95#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \
96 CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
97#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \
98 CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
99#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \
100 CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
101#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \
102 CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
103#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \
104 CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
105#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \
106 CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
107#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \
108 CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
109#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \
110 CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
111#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \
112 CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull))
113#define CVMX_GMXX_RX_HG2_STATUS(block_id) \
114 CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull))
115#define CVMX_GMXX_RX_PASS_EN(block_id) \
116 CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull))
117#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \
118 CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull))
119#define CVMX_GMXX_RX_PRTS(block_id) \
120 CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull))
121#define CVMX_GMXX_RX_PRT_INFO(block_id) \
122 CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull))
123#define CVMX_GMXX_RX_TX_STATUS(block_id) \
124 CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull))
125#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \
126 CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull))
127#define CVMX_GMXX_RX_XAUI_CTL(block_id) \
128 CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull))
129#define CVMX_GMXX_SMACX(offset, block_id) \
130 CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
131#define CVMX_GMXX_STAT_BP(block_id) \
132 CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull))
133#define CVMX_GMXX_TXX_APPEND(offset, block_id) \
134 CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
135#define CVMX_GMXX_TXX_BURST(offset, block_id) \
136 CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
137#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \
138 CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
139#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \
140 CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull))
141#define CVMX_GMXX_TXX_CLK(offset, block_id) \
142 CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
143#define CVMX_GMXX_TXX_CTL(offset, block_id) \
144 CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
145#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \
146 CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
147#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \
148 CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
149#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \
150 CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
151#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \
152 CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
153#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \
154 CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
155#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \
156 CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
157#define CVMX_GMXX_TXX_SLOT(offset, block_id) \
158 CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
159#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \
160 CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
161#define CVMX_GMXX_TXX_STAT0(offset, block_id) \
162 CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
163#define CVMX_GMXX_TXX_STAT1(offset, block_id) \
164 CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
165#define CVMX_GMXX_TXX_STAT2(offset, block_id) \
166 CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
167#define CVMX_GMXX_TXX_STAT3(offset, block_id) \
168 CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
169#define CVMX_GMXX_TXX_STAT4(offset, block_id) \
170 CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
171#define CVMX_GMXX_TXX_STAT5(offset, block_id) \
172 CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
173#define CVMX_GMXX_TXX_STAT6(offset, block_id) \
174 CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
175#define CVMX_GMXX_TXX_STAT7(offset, block_id) \
176 CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
177#define CVMX_GMXX_TXX_STAT8(offset, block_id) \
178 CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
179#define CVMX_GMXX_TXX_STAT9(offset, block_id) \
180 CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
181#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \
182 CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
183#define CVMX_GMXX_TXX_THRESH(offset, block_id) \
184 CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull))
185#define CVMX_GMXX_TX_BP(block_id) \
186 CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull))
187#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \
188 CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull))
189#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \
190 CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull))
191#define CVMX_GMXX_TX_CORRUPT(block_id) \
192 CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull))
193#define CVMX_GMXX_TX_HG2_REG1(block_id) \
194 CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull))
195#define CVMX_GMXX_TX_HG2_REG2(block_id) \
196 CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull))
197#define CVMX_GMXX_TX_IFG(block_id) \
198 CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull))
199#define CVMX_GMXX_TX_INT_EN(block_id) \
200 CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull))
201#define CVMX_GMXX_TX_INT_REG(block_id) \
202 CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull))
203#define CVMX_GMXX_TX_JAM(block_id) \
204 CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull))
205#define CVMX_GMXX_TX_LFSR(block_id) \
206 CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull))
207#define CVMX_GMXX_TX_OVR_BP(block_id) \
208 CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull))
209#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \
210 CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull))
211#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \
212 CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull))
213#define CVMX_GMXX_TX_PRTS(block_id) \
214 CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull))
215#define CVMX_GMXX_TX_SPI_CTL(block_id) \
216 CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull))
217#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \
218 CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull))
219#define CVMX_GMXX_TX_SPI_MAX(block_id) \
220 CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull))
221#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \
222 CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull))
223#define CVMX_GMXX_TX_SPI_THRESH(block_id) \
224 CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull))
225#define CVMX_GMXX_TX_XAUI_CTL(block_id) \
226 CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull))
227#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \
228 CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull))
229
230union cvmx_gmxx_bad_reg {
231 uint64_t u64;
232 struct cvmx_gmxx_bad_reg_s {
233 uint64_t reserved_31_63:33;
234 uint64_t inb_nxa:4;
235 uint64_t statovr:1;
236 uint64_t loststat:4;
237 uint64_t reserved_18_21:4;
238 uint64_t out_ovr:16;
239 uint64_t ncb_ovr:1;
240 uint64_t out_col:1;
241 } s;
242 struct cvmx_gmxx_bad_reg_cn30xx {
243 uint64_t reserved_31_63:33;
244 uint64_t inb_nxa:4;
245 uint64_t statovr:1;
246 uint64_t reserved_25_25:1;
247 uint64_t loststat:3;
248 uint64_t reserved_5_21:17;
249 uint64_t out_ovr:3;
250 uint64_t reserved_0_1:2;
251 } cn30xx;
252 struct cvmx_gmxx_bad_reg_cn30xx cn31xx;
253 struct cvmx_gmxx_bad_reg_s cn38xx;
254 struct cvmx_gmxx_bad_reg_s cn38xxp2;
255 struct cvmx_gmxx_bad_reg_cn30xx cn50xx;
256 struct cvmx_gmxx_bad_reg_cn52xx {
257 uint64_t reserved_31_63:33;
258 uint64_t inb_nxa:4;
259 uint64_t statovr:1;
260 uint64_t loststat:4;
261 uint64_t reserved_6_21:16;
262 uint64_t out_ovr:4;
263 uint64_t reserved_0_1:2;
264 } cn52xx;
265 struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1;
266 struct cvmx_gmxx_bad_reg_cn52xx cn56xx;
267 struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1;
268 struct cvmx_gmxx_bad_reg_s cn58xx;
269 struct cvmx_gmxx_bad_reg_s cn58xxp1;
270};
271
272union cvmx_gmxx_bist {
273 uint64_t u64;
274 struct cvmx_gmxx_bist_s {
275 uint64_t reserved_17_63:47;
276 uint64_t status:17;
277 } s;
278 struct cvmx_gmxx_bist_cn30xx {
279 uint64_t reserved_10_63:54;
280 uint64_t status:10;
281 } cn30xx;
282 struct cvmx_gmxx_bist_cn30xx cn31xx;
283 struct cvmx_gmxx_bist_cn30xx cn38xx;
284 struct cvmx_gmxx_bist_cn30xx cn38xxp2;
285 struct cvmx_gmxx_bist_cn50xx {
286 uint64_t reserved_12_63:52;
287 uint64_t status:12;
288 } cn50xx;
289 struct cvmx_gmxx_bist_cn52xx {
290 uint64_t reserved_16_63:48;
291 uint64_t status:16;
292 } cn52xx;
293 struct cvmx_gmxx_bist_cn52xx cn52xxp1;
294 struct cvmx_gmxx_bist_cn52xx cn56xx;
295 struct cvmx_gmxx_bist_cn52xx cn56xxp1;
296 struct cvmx_gmxx_bist_s cn58xx;
297 struct cvmx_gmxx_bist_s cn58xxp1;
298};
299
300union cvmx_gmxx_clk_en {
301 uint64_t u64;
302 struct cvmx_gmxx_clk_en_s {
303 uint64_t reserved_1_63:63;
304 uint64_t clk_en:1;
305 } s;
306 struct cvmx_gmxx_clk_en_s cn52xx;
307 struct cvmx_gmxx_clk_en_s cn52xxp1;
308 struct cvmx_gmxx_clk_en_s cn56xx;
309 struct cvmx_gmxx_clk_en_s cn56xxp1;
310};
311
312union cvmx_gmxx_hg2_control {
313 uint64_t u64;
314 struct cvmx_gmxx_hg2_control_s {
315 uint64_t reserved_19_63:45;
316 uint64_t hg2tx_en:1;
317 uint64_t hg2rx_en:1;
318 uint64_t phys_en:1;
319 uint64_t logl_en:16;
320 } s;
321 struct cvmx_gmxx_hg2_control_s cn52xx;
322 struct cvmx_gmxx_hg2_control_s cn52xxp1;
323 struct cvmx_gmxx_hg2_control_s cn56xx;
324};
325
326union cvmx_gmxx_inf_mode {
327 uint64_t u64;
328 struct cvmx_gmxx_inf_mode_s {
329 uint64_t reserved_10_63:54;
330 uint64_t speed:2;
331 uint64_t reserved_6_7:2;
332 uint64_t mode:2;
333 uint64_t reserved_3_3:1;
334 uint64_t p0mii:1;
335 uint64_t en:1;
336 uint64_t type:1;
337 } s;
338 struct cvmx_gmxx_inf_mode_cn30xx {
339 uint64_t reserved_3_63:61;
340 uint64_t p0mii:1;
341 uint64_t en:1;
342 uint64_t type:1;
343 } cn30xx;
344 struct cvmx_gmxx_inf_mode_cn31xx {
345 uint64_t reserved_2_63:62;
346 uint64_t en:1;
347 uint64_t type:1;
348 } cn31xx;
349 struct cvmx_gmxx_inf_mode_cn31xx cn38xx;
350 struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2;
351 struct cvmx_gmxx_inf_mode_cn30xx cn50xx;
352 struct cvmx_gmxx_inf_mode_cn52xx {
353 uint64_t reserved_10_63:54;
354 uint64_t speed:2;
355 uint64_t reserved_6_7:2;
356 uint64_t mode:2;
357 uint64_t reserved_2_3:2;
358 uint64_t en:1;
359 uint64_t type:1;
360 } cn52xx;
361 struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1;
362 struct cvmx_gmxx_inf_mode_cn52xx cn56xx;
363 struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1;
364 struct cvmx_gmxx_inf_mode_cn31xx cn58xx;
365 struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1;
366};
367
368union cvmx_gmxx_nxa_adr {
369 uint64_t u64;
370 struct cvmx_gmxx_nxa_adr_s {
371 uint64_t reserved_6_63:58;
372 uint64_t prt:6;
373 } s;
374 struct cvmx_gmxx_nxa_adr_s cn30xx;
375 struct cvmx_gmxx_nxa_adr_s cn31xx;
376 struct cvmx_gmxx_nxa_adr_s cn38xx;
377 struct cvmx_gmxx_nxa_adr_s cn38xxp2;
378 struct cvmx_gmxx_nxa_adr_s cn50xx;
379 struct cvmx_gmxx_nxa_adr_s cn52xx;
380 struct cvmx_gmxx_nxa_adr_s cn52xxp1;
381 struct cvmx_gmxx_nxa_adr_s cn56xx;
382 struct cvmx_gmxx_nxa_adr_s cn56xxp1;
383 struct cvmx_gmxx_nxa_adr_s cn58xx;
384 struct cvmx_gmxx_nxa_adr_s cn58xxp1;
385};
386
387union cvmx_gmxx_prtx_cbfc_ctl {
388 uint64_t u64;
389 struct cvmx_gmxx_prtx_cbfc_ctl_s {
390 uint64_t phys_en:16;
391 uint64_t logl_en:16;
392 uint64_t phys_bp:16;
393 uint64_t reserved_4_15:12;
394 uint64_t bck_en:1;
395 uint64_t drp_en:1;
396 uint64_t tx_en:1;
397 uint64_t rx_en:1;
398 } s;
399 struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx;
400 struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx;
401};
402
403union cvmx_gmxx_prtx_cfg {
404 uint64_t u64;
405 struct cvmx_gmxx_prtx_cfg_s {
406 uint64_t reserved_14_63:50;
407 uint64_t tx_idle:1;
408 uint64_t rx_idle:1;
409 uint64_t reserved_9_11:3;
410 uint64_t speed_msb:1;
411 uint64_t reserved_4_7:4;
412 uint64_t slottime:1;
413 uint64_t duplex:1;
414 uint64_t speed:1;
415 uint64_t en:1;
416 } s;
417 struct cvmx_gmxx_prtx_cfg_cn30xx {
418 uint64_t reserved_4_63:60;
419 uint64_t slottime:1;
420 uint64_t duplex:1;
421 uint64_t speed:1;
422 uint64_t en:1;
423 } cn30xx;
424 struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx;
425 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx;
426 struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2;
427 struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx;
428 struct cvmx_gmxx_prtx_cfg_s cn52xx;
429 struct cvmx_gmxx_prtx_cfg_s cn52xxp1;
430 struct cvmx_gmxx_prtx_cfg_s cn56xx;
431 struct cvmx_gmxx_prtx_cfg_s cn56xxp1;
432 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx;
433 struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1;
434};
435
436union cvmx_gmxx_rxx_adr_cam0 {
437 uint64_t u64;
438 struct cvmx_gmxx_rxx_adr_cam0_s {
439 uint64_t adr:64;
440 } s;
441 struct cvmx_gmxx_rxx_adr_cam0_s cn30xx;
442 struct cvmx_gmxx_rxx_adr_cam0_s cn31xx;
443 struct cvmx_gmxx_rxx_adr_cam0_s cn38xx;
444 struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2;
445 struct cvmx_gmxx_rxx_adr_cam0_s cn50xx;
446 struct cvmx_gmxx_rxx_adr_cam0_s cn52xx;
447 struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1;
448 struct cvmx_gmxx_rxx_adr_cam0_s cn56xx;
449 struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1;
450 struct cvmx_gmxx_rxx_adr_cam0_s cn58xx;
451 struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1;
452};
453
454union cvmx_gmxx_rxx_adr_cam1 {
455 uint64_t u64;
456 struct cvmx_gmxx_rxx_adr_cam1_s {
457 uint64_t adr:64;
458 } s;
459 struct cvmx_gmxx_rxx_adr_cam1_s cn30xx;
460 struct cvmx_gmxx_rxx_adr_cam1_s cn31xx;
461 struct cvmx_gmxx_rxx_adr_cam1_s cn38xx;
462 struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2;
463 struct cvmx_gmxx_rxx_adr_cam1_s cn50xx;
464 struct cvmx_gmxx_rxx_adr_cam1_s cn52xx;
465 struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1;
466 struct cvmx_gmxx_rxx_adr_cam1_s cn56xx;
467 struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1;
468 struct cvmx_gmxx_rxx_adr_cam1_s cn58xx;
469 struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1;
470};
471
472union cvmx_gmxx_rxx_adr_cam2 {
473 uint64_t u64;
474 struct cvmx_gmxx_rxx_adr_cam2_s {
475 uint64_t adr:64;
476 } s;
477 struct cvmx_gmxx_rxx_adr_cam2_s cn30xx;
478 struct cvmx_gmxx_rxx_adr_cam2_s cn31xx;
479 struct cvmx_gmxx_rxx_adr_cam2_s cn38xx;
480 struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2;
481 struct cvmx_gmxx_rxx_adr_cam2_s cn50xx;
482 struct cvmx_gmxx_rxx_adr_cam2_s cn52xx;
483 struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1;
484 struct cvmx_gmxx_rxx_adr_cam2_s cn56xx;
485 struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1;
486 struct cvmx_gmxx_rxx_adr_cam2_s cn58xx;
487 struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1;
488};
489
490union cvmx_gmxx_rxx_adr_cam3 {
491 uint64_t u64;
492 struct cvmx_gmxx_rxx_adr_cam3_s {
493 uint64_t adr:64;
494 } s;
495 struct cvmx_gmxx_rxx_adr_cam3_s cn30xx;
496 struct cvmx_gmxx_rxx_adr_cam3_s cn31xx;
497 struct cvmx_gmxx_rxx_adr_cam3_s cn38xx;
498 struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2;
499 struct cvmx_gmxx_rxx_adr_cam3_s cn50xx;
500 struct cvmx_gmxx_rxx_adr_cam3_s cn52xx;
501 struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1;
502 struct cvmx_gmxx_rxx_adr_cam3_s cn56xx;
503 struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1;
504 struct cvmx_gmxx_rxx_adr_cam3_s cn58xx;
505 struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1;
506};
507
508union cvmx_gmxx_rxx_adr_cam4 {
509 uint64_t u64;
510 struct cvmx_gmxx_rxx_adr_cam4_s {
511 uint64_t adr:64;
512 } s;
513 struct cvmx_gmxx_rxx_adr_cam4_s cn30xx;
514 struct cvmx_gmxx_rxx_adr_cam4_s cn31xx;
515 struct cvmx_gmxx_rxx_adr_cam4_s cn38xx;
516 struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2;
517 struct cvmx_gmxx_rxx_adr_cam4_s cn50xx;
518 struct cvmx_gmxx_rxx_adr_cam4_s cn52xx;
519 struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1;
520 struct cvmx_gmxx_rxx_adr_cam4_s cn56xx;
521 struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1;
522 struct cvmx_gmxx_rxx_adr_cam4_s cn58xx;
523 struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1;
524};
525
526union cvmx_gmxx_rxx_adr_cam5 {
527 uint64_t u64;
528 struct cvmx_gmxx_rxx_adr_cam5_s {
529 uint64_t adr:64;
530 } s;
531 struct cvmx_gmxx_rxx_adr_cam5_s cn30xx;
532 struct cvmx_gmxx_rxx_adr_cam5_s cn31xx;
533 struct cvmx_gmxx_rxx_adr_cam5_s cn38xx;
534 struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2;
535 struct cvmx_gmxx_rxx_adr_cam5_s cn50xx;
536 struct cvmx_gmxx_rxx_adr_cam5_s cn52xx;
537 struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1;
538 struct cvmx_gmxx_rxx_adr_cam5_s cn56xx;
539 struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1;
540 struct cvmx_gmxx_rxx_adr_cam5_s cn58xx;
541 struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1;
542};
543
544union cvmx_gmxx_rxx_adr_cam_en {
545 uint64_t u64;
546 struct cvmx_gmxx_rxx_adr_cam_en_s {
547 uint64_t reserved_8_63:56;
548 uint64_t en:8;
549 } s;
550 struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx;
551 struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx;
552 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx;
553 struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2;
554 struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx;
555 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx;
556 struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1;
557 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx;
558 struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1;
559 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx;
560 struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1;
561};
562
563union cvmx_gmxx_rxx_adr_ctl {
564 uint64_t u64;
565 struct cvmx_gmxx_rxx_adr_ctl_s {
566 uint64_t reserved_4_63:60;
567 uint64_t cam_mode:1;
568 uint64_t mcst:2;
569 uint64_t bcst:1;
570 } s;
571 struct cvmx_gmxx_rxx_adr_ctl_s cn30xx;
572 struct cvmx_gmxx_rxx_adr_ctl_s cn31xx;
573 struct cvmx_gmxx_rxx_adr_ctl_s cn38xx;
574 struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2;
575 struct cvmx_gmxx_rxx_adr_ctl_s cn50xx;
576 struct cvmx_gmxx_rxx_adr_ctl_s cn52xx;
577 struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1;
578 struct cvmx_gmxx_rxx_adr_ctl_s cn56xx;
579 struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1;
580 struct cvmx_gmxx_rxx_adr_ctl_s cn58xx;
581 struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1;
582};
583
584union cvmx_gmxx_rxx_decision {
585 uint64_t u64;
586 struct cvmx_gmxx_rxx_decision_s {
587 uint64_t reserved_5_63:59;
588 uint64_t cnt:5;
589 } s;
590 struct cvmx_gmxx_rxx_decision_s cn30xx;
591 struct cvmx_gmxx_rxx_decision_s cn31xx;
592 struct cvmx_gmxx_rxx_decision_s cn38xx;
593 struct cvmx_gmxx_rxx_decision_s cn38xxp2;
594 struct cvmx_gmxx_rxx_decision_s cn50xx;
595 struct cvmx_gmxx_rxx_decision_s cn52xx;
596 struct cvmx_gmxx_rxx_decision_s cn52xxp1;
597 struct cvmx_gmxx_rxx_decision_s cn56xx;
598 struct cvmx_gmxx_rxx_decision_s cn56xxp1;
599 struct cvmx_gmxx_rxx_decision_s cn58xx;
600 struct cvmx_gmxx_rxx_decision_s cn58xxp1;
601};
602
603union cvmx_gmxx_rxx_frm_chk {
604 uint64_t u64;
605 struct cvmx_gmxx_rxx_frm_chk_s {
606 uint64_t reserved_10_63:54;
607 uint64_t niberr:1;
608 uint64_t skperr:1;
609 uint64_t rcverr:1;
610 uint64_t lenerr:1;
611 uint64_t alnerr:1;
612 uint64_t fcserr:1;
613 uint64_t jabber:1;
614 uint64_t maxerr:1;
615 uint64_t carext:1;
616 uint64_t minerr:1;
617 } s;
618 struct cvmx_gmxx_rxx_frm_chk_s cn30xx;
619 struct cvmx_gmxx_rxx_frm_chk_s cn31xx;
620 struct cvmx_gmxx_rxx_frm_chk_s cn38xx;
621 struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2;
622 struct cvmx_gmxx_rxx_frm_chk_cn50xx {
623 uint64_t reserved_10_63:54;
624 uint64_t niberr:1;
625 uint64_t skperr:1;
626 uint64_t rcverr:1;
627 uint64_t reserved_6_6:1;
628 uint64_t alnerr:1;
629 uint64_t fcserr:1;
630 uint64_t jabber:1;
631 uint64_t reserved_2_2:1;
632 uint64_t carext:1;
633 uint64_t reserved_0_0:1;
634 } cn50xx;
635 struct cvmx_gmxx_rxx_frm_chk_cn52xx {
636 uint64_t reserved_9_63:55;
637 uint64_t skperr:1;
638 uint64_t rcverr:1;
639 uint64_t reserved_5_6:2;
640 uint64_t fcserr:1;
641 uint64_t jabber:1;
642 uint64_t reserved_2_2:1;
643 uint64_t carext:1;
644 uint64_t reserved_0_0:1;
645 } cn52xx;
646 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1;
647 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx;
648 struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1;
649 struct cvmx_gmxx_rxx_frm_chk_s cn58xx;
650 struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1;
651};
652
653union cvmx_gmxx_rxx_frm_ctl {
654 uint64_t u64;
655 struct cvmx_gmxx_rxx_frm_ctl_s {
656 uint64_t reserved_11_63:53;
657 uint64_t null_dis:1;
658 uint64_t pre_align:1;
659 uint64_t pad_len:1;
660 uint64_t vlan_len:1;
661 uint64_t pre_free:1;
662 uint64_t ctl_smac:1;
663 uint64_t ctl_mcst:1;
664 uint64_t ctl_bck:1;
665 uint64_t ctl_drp:1;
666 uint64_t pre_strp:1;
667 uint64_t pre_chk:1;
668 } s;
669 struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
670 uint64_t reserved_9_63:55;
671 uint64_t pad_len:1;
672 uint64_t vlan_len:1;
673 uint64_t pre_free:1;
674 uint64_t ctl_smac:1;
675 uint64_t ctl_mcst:1;
676 uint64_t ctl_bck:1;
677 uint64_t ctl_drp:1;
678 uint64_t pre_strp:1;
679 uint64_t pre_chk:1;
680 } cn30xx;
681 struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
682 uint64_t reserved_8_63:56;
683 uint64_t vlan_len:1;
684 uint64_t pre_free:1;
685 uint64_t ctl_smac:1;
686 uint64_t ctl_mcst:1;
687 uint64_t ctl_bck:1;
688 uint64_t ctl_drp:1;
689 uint64_t pre_strp:1;
690 uint64_t pre_chk:1;
691 } cn31xx;
692 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx;
693 struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2;
694 struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
695 uint64_t reserved_11_63:53;
696 uint64_t null_dis:1;
697 uint64_t pre_align:1;
698 uint64_t reserved_7_8:2;
699 uint64_t pre_free:1;
700 uint64_t ctl_smac:1;
701 uint64_t ctl_mcst:1;
702 uint64_t ctl_bck:1;
703 uint64_t ctl_drp:1;
704 uint64_t pre_strp:1;
705 uint64_t pre_chk:1;
706 } cn50xx;
707 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx;
708 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1;
709 struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx;
710 struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
711 uint64_t reserved_10_63:54;
712 uint64_t pre_align:1;
713 uint64_t reserved_7_8:2;
714 uint64_t pre_free:1;
715 uint64_t ctl_smac:1;
716 uint64_t ctl_mcst:1;
717 uint64_t ctl_bck:1;
718 uint64_t ctl_drp:1;
719 uint64_t pre_strp:1;
720 uint64_t pre_chk:1;
721 } cn56xxp1;
722 struct cvmx_gmxx_rxx_frm_ctl_s cn58xx;
723 struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1;
724};
725
726union cvmx_gmxx_rxx_frm_max {
727 uint64_t u64;
728 struct cvmx_gmxx_rxx_frm_max_s {
729 uint64_t reserved_16_63:48;
730 uint64_t len:16;
731 } s;
732 struct cvmx_gmxx_rxx_frm_max_s cn30xx;
733 struct cvmx_gmxx_rxx_frm_max_s cn31xx;
734 struct cvmx_gmxx_rxx_frm_max_s cn38xx;
735 struct cvmx_gmxx_rxx_frm_max_s cn38xxp2;
736 struct cvmx_gmxx_rxx_frm_max_s cn58xx;
737 struct cvmx_gmxx_rxx_frm_max_s cn58xxp1;
738};
739
740union cvmx_gmxx_rxx_frm_min {
741 uint64_t u64;
742 struct cvmx_gmxx_rxx_frm_min_s {
743 uint64_t reserved_16_63:48;
744 uint64_t len:16;
745 } s;
746 struct cvmx_gmxx_rxx_frm_min_s cn30xx;
747 struct cvmx_gmxx_rxx_frm_min_s cn31xx;
748 struct cvmx_gmxx_rxx_frm_min_s cn38xx;
749 struct cvmx_gmxx_rxx_frm_min_s cn38xxp2;
750 struct cvmx_gmxx_rxx_frm_min_s cn58xx;
751 struct cvmx_gmxx_rxx_frm_min_s cn58xxp1;
752};
753
754union cvmx_gmxx_rxx_ifg {
755 uint64_t u64;
756 struct cvmx_gmxx_rxx_ifg_s {
757 uint64_t reserved_4_63:60;
758 uint64_t ifg:4;
759 } s;
760 struct cvmx_gmxx_rxx_ifg_s cn30xx;
761 struct cvmx_gmxx_rxx_ifg_s cn31xx;
762 struct cvmx_gmxx_rxx_ifg_s cn38xx;
763 struct cvmx_gmxx_rxx_ifg_s cn38xxp2;
764 struct cvmx_gmxx_rxx_ifg_s cn50xx;
765 struct cvmx_gmxx_rxx_ifg_s cn52xx;
766 struct cvmx_gmxx_rxx_ifg_s cn52xxp1;
767 struct cvmx_gmxx_rxx_ifg_s cn56xx;
768 struct cvmx_gmxx_rxx_ifg_s cn56xxp1;
769 struct cvmx_gmxx_rxx_ifg_s cn58xx;
770 struct cvmx_gmxx_rxx_ifg_s cn58xxp1;
771};
772
773union cvmx_gmxx_rxx_int_en {
774 uint64_t u64;
775 struct cvmx_gmxx_rxx_int_en_s {
776 uint64_t reserved_29_63:35;
777 uint64_t hg2cc:1;
778 uint64_t hg2fld:1;
779 uint64_t undat:1;
780 uint64_t uneop:1;
781 uint64_t unsop:1;
782 uint64_t bad_term:1;
783 uint64_t bad_seq:1;
784 uint64_t rem_fault:1;
785 uint64_t loc_fault:1;
786 uint64_t pause_drp:1;
787 uint64_t phy_dupx:1;
788 uint64_t phy_spd:1;
789 uint64_t phy_link:1;
790 uint64_t ifgerr:1;
791 uint64_t coldet:1;
792 uint64_t falerr:1;
793 uint64_t rsverr:1;
794 uint64_t pcterr:1;
795 uint64_t ovrerr:1;
796 uint64_t niberr:1;
797 uint64_t skperr:1;
798 uint64_t rcverr:1;
799 uint64_t lenerr:1;
800 uint64_t alnerr:1;
801 uint64_t fcserr:1;
802 uint64_t jabber:1;
803 uint64_t maxerr:1;
804 uint64_t carext:1;
805 uint64_t minerr:1;
806 } s;
807 struct cvmx_gmxx_rxx_int_en_cn30xx {
808 uint64_t reserved_19_63:45;
809 uint64_t phy_dupx:1;
810 uint64_t phy_spd:1;
811 uint64_t phy_link:1;
812 uint64_t ifgerr:1;
813 uint64_t coldet:1;
814 uint64_t falerr:1;
815 uint64_t rsverr:1;
816 uint64_t pcterr:1;
817 uint64_t ovrerr:1;
818 uint64_t niberr:1;
819 uint64_t skperr:1;
820 uint64_t rcverr:1;
821 uint64_t lenerr:1;
822 uint64_t alnerr:1;
823 uint64_t fcserr:1;
824 uint64_t jabber:1;
825 uint64_t maxerr:1;
826 uint64_t carext:1;
827 uint64_t minerr:1;
828 } cn30xx;
829 struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx;
830 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx;
831 struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2;
832 struct cvmx_gmxx_rxx_int_en_cn50xx {
833 uint64_t reserved_20_63:44;
834 uint64_t pause_drp:1;
835 uint64_t phy_dupx:1;
836 uint64_t phy_spd:1;
837 uint64_t phy_link:1;
838 uint64_t ifgerr:1;
839 uint64_t coldet:1;
840 uint64_t falerr:1;
841 uint64_t rsverr:1;
842 uint64_t pcterr:1;
843 uint64_t ovrerr:1;
844 uint64_t niberr:1;
845 uint64_t skperr:1;
846 uint64_t rcverr:1;
847 uint64_t reserved_6_6:1;
848 uint64_t alnerr:1;
849 uint64_t fcserr:1;
850 uint64_t jabber:1;
851 uint64_t reserved_2_2:1;
852 uint64_t carext:1;
853 uint64_t reserved_0_0:1;
854 } cn50xx;
855 struct cvmx_gmxx_rxx_int_en_cn52xx {
856 uint64_t reserved_29_63:35;
857 uint64_t hg2cc:1;
858 uint64_t hg2fld:1;
859 uint64_t undat:1;
860 uint64_t uneop:1;
861 uint64_t unsop:1;
862 uint64_t bad_term:1;
863 uint64_t bad_seq:1;
864 uint64_t rem_fault:1;
865 uint64_t loc_fault:1;
866 uint64_t pause_drp:1;
867 uint64_t reserved_16_18:3;
868 uint64_t ifgerr:1;
869 uint64_t coldet:1;
870 uint64_t falerr:1;
871 uint64_t rsverr:1;
872 uint64_t pcterr:1;
873 uint64_t ovrerr:1;
874 uint64_t reserved_9_9:1;
875 uint64_t skperr:1;
876 uint64_t rcverr:1;
877 uint64_t reserved_5_6:2;
878 uint64_t fcserr:1;
879 uint64_t jabber:1;
880 uint64_t reserved_2_2:1;
881 uint64_t carext:1;
882 uint64_t reserved_0_0:1;
883 } cn52xx;
884 struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1;
885 struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx;
886 struct cvmx_gmxx_rxx_int_en_cn56xxp1 {
887 uint64_t reserved_27_63:37;
888 uint64_t undat:1;
889 uint64_t uneop:1;
890 uint64_t unsop:1;
891 uint64_t bad_term:1;
892 uint64_t bad_seq:1;
893 uint64_t rem_fault:1;
894 uint64_t loc_fault:1;
895 uint64_t pause_drp:1;
896 uint64_t reserved_16_18:3;
897 uint64_t ifgerr:1;
898 uint64_t coldet:1;
899 uint64_t falerr:1;
900 uint64_t rsverr:1;
901 uint64_t pcterr:1;
902 uint64_t ovrerr:1;
903 uint64_t reserved_9_9:1;
904 uint64_t skperr:1;
905 uint64_t rcverr:1;
906 uint64_t reserved_5_6:2;
907 uint64_t fcserr:1;
908 uint64_t jabber:1;
909 uint64_t reserved_2_2:1;
910 uint64_t carext:1;
911 uint64_t reserved_0_0:1;
912 } cn56xxp1;
913 struct cvmx_gmxx_rxx_int_en_cn58xx {
914 uint64_t reserved_20_63:44;
915 uint64_t pause_drp:1;
916 uint64_t phy_dupx:1;
917 uint64_t phy_spd:1;
918 uint64_t phy_link:1;
919 uint64_t ifgerr:1;
920 uint64_t coldet:1;
921 uint64_t falerr:1;
922 uint64_t rsverr:1;
923 uint64_t pcterr:1;
924 uint64_t ovrerr:1;
925 uint64_t niberr:1;
926 uint64_t skperr:1;
927 uint64_t rcverr:1;
928 uint64_t lenerr:1;
929 uint64_t alnerr:1;
930 uint64_t fcserr:1;
931 uint64_t jabber:1;
932 uint64_t maxerr:1;
933 uint64_t carext:1;
934 uint64_t minerr:1;
935 } cn58xx;
936 struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1;
937};
938
939union cvmx_gmxx_rxx_int_reg {
940 uint64_t u64;
941 struct cvmx_gmxx_rxx_int_reg_s {
942 uint64_t reserved_29_63:35;
943 uint64_t hg2cc:1;
944 uint64_t hg2fld:1;
945 uint64_t undat:1;
946 uint64_t uneop:1;
947 uint64_t unsop:1;
948 uint64_t bad_term:1;
949 uint64_t bad_seq:1;
950 uint64_t rem_fault:1;
951 uint64_t loc_fault:1;
952 uint64_t pause_drp:1;
953 uint64_t phy_dupx:1;
954 uint64_t phy_spd:1;
955 uint64_t phy_link:1;
956 uint64_t ifgerr:1;
957 uint64_t coldet:1;
958 uint64_t falerr:1;
959 uint64_t rsverr:1;
960 uint64_t pcterr:1;
961 uint64_t ovrerr:1;
962 uint64_t niberr:1;
963 uint64_t skperr:1;
964 uint64_t rcverr:1;
965 uint64_t lenerr:1;
966 uint64_t alnerr:1;
967 uint64_t fcserr:1;
968 uint64_t jabber:1;
969 uint64_t maxerr:1;
970 uint64_t carext:1;
971 uint64_t minerr:1;
972 } s;
973 struct cvmx_gmxx_rxx_int_reg_cn30xx {
974 uint64_t reserved_19_63:45;
975 uint64_t phy_dupx:1;
976 uint64_t phy_spd:1;
977 uint64_t phy_link:1;
978 uint64_t ifgerr:1;
979 uint64_t coldet:1;
980 uint64_t falerr:1;
981 uint64_t rsverr:1;
982 uint64_t pcterr:1;
983 uint64_t ovrerr:1;
984 uint64_t niberr:1;
985 uint64_t skperr:1;
986 uint64_t rcverr:1;
987 uint64_t lenerr:1;
988 uint64_t alnerr:1;
989 uint64_t fcserr:1;
990 uint64_t jabber:1;
991 uint64_t maxerr:1;
992 uint64_t carext:1;
993 uint64_t minerr:1;
994 } cn30xx;
995 struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx;
996 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx;
997 struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2;
998 struct cvmx_gmxx_rxx_int_reg_cn50xx {
999 uint64_t reserved_20_63:44;
1000 uint64_t pause_drp:1;
1001 uint64_t phy_dupx:1;
1002 uint64_t phy_spd:1;
1003 uint64_t phy_link:1;
1004 uint64_t ifgerr:1;
1005 uint64_t coldet:1;
1006 uint64_t falerr:1;
1007 uint64_t rsverr:1;
1008 uint64_t pcterr:1;
1009 uint64_t ovrerr:1;
1010 uint64_t niberr:1;
1011 uint64_t skperr:1;
1012 uint64_t rcverr:1;
1013 uint64_t reserved_6_6:1;
1014 uint64_t alnerr:1;
1015 uint64_t fcserr:1;
1016 uint64_t jabber:1;
1017 uint64_t reserved_2_2:1;
1018 uint64_t carext:1;
1019 uint64_t reserved_0_0:1;
1020 } cn50xx;
1021 struct cvmx_gmxx_rxx_int_reg_cn52xx {
1022 uint64_t reserved_29_63:35;
1023 uint64_t hg2cc:1;
1024 uint64_t hg2fld:1;
1025 uint64_t undat:1;
1026 uint64_t uneop:1;
1027 uint64_t unsop:1;
1028 uint64_t bad_term:1;
1029 uint64_t bad_seq:1;
1030 uint64_t rem_fault:1;
1031 uint64_t loc_fault:1;
1032 uint64_t pause_drp:1;
1033 uint64_t reserved_16_18:3;
1034 uint64_t ifgerr:1;
1035 uint64_t coldet:1;
1036 uint64_t falerr:1;
1037 uint64_t rsverr:1;
1038 uint64_t pcterr:1;
1039 uint64_t ovrerr:1;
1040 uint64_t reserved_9_9:1;
1041 uint64_t skperr:1;
1042 uint64_t rcverr:1;
1043 uint64_t reserved_5_6:2;
1044 uint64_t fcserr:1;
1045 uint64_t jabber:1;
1046 uint64_t reserved_2_2:1;
1047 uint64_t carext:1;
1048 uint64_t reserved_0_0:1;
1049 } cn52xx;
1050 struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1;
1051 struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx;
1052 struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
1053 uint64_t reserved_27_63:37;
1054 uint64_t undat:1;
1055 uint64_t uneop:1;
1056 uint64_t unsop:1;
1057 uint64_t bad_term:1;
1058 uint64_t bad_seq:1;
1059 uint64_t rem_fault:1;
1060 uint64_t loc_fault:1;
1061 uint64_t pause_drp:1;
1062 uint64_t reserved_16_18:3;
1063 uint64_t ifgerr:1;
1064 uint64_t coldet:1;
1065 uint64_t falerr:1;
1066 uint64_t rsverr:1;
1067 uint64_t pcterr:1;
1068 uint64_t ovrerr:1;
1069 uint64_t reserved_9_9:1;
1070 uint64_t skperr:1;
1071 uint64_t rcverr:1;
1072 uint64_t reserved_5_6:2;
1073 uint64_t fcserr:1;
1074 uint64_t jabber:1;
1075 uint64_t reserved_2_2:1;
1076 uint64_t carext:1;
1077 uint64_t reserved_0_0:1;
1078 } cn56xxp1;
1079 struct cvmx_gmxx_rxx_int_reg_cn58xx {
1080 uint64_t reserved_20_63:44;
1081 uint64_t pause_drp:1;
1082 uint64_t phy_dupx:1;
1083 uint64_t phy_spd:1;
1084 uint64_t phy_link:1;
1085 uint64_t ifgerr:1;
1086 uint64_t coldet:1;
1087 uint64_t falerr:1;
1088 uint64_t rsverr:1;
1089 uint64_t pcterr:1;
1090 uint64_t ovrerr:1;
1091 uint64_t niberr:1;
1092 uint64_t skperr:1;
1093 uint64_t rcverr:1;
1094 uint64_t lenerr:1;
1095 uint64_t alnerr:1;
1096 uint64_t fcserr:1;
1097 uint64_t jabber:1;
1098 uint64_t maxerr:1;
1099 uint64_t carext:1;
1100 uint64_t minerr:1;
1101 } cn58xx;
1102 struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1;
1103};
1104
1105union cvmx_gmxx_rxx_jabber {
1106 uint64_t u64;
1107 struct cvmx_gmxx_rxx_jabber_s {
1108 uint64_t reserved_16_63:48;
1109 uint64_t cnt:16;
1110 } s;
1111 struct cvmx_gmxx_rxx_jabber_s cn30xx;
1112 struct cvmx_gmxx_rxx_jabber_s cn31xx;
1113 struct cvmx_gmxx_rxx_jabber_s cn38xx;
1114 struct cvmx_gmxx_rxx_jabber_s cn38xxp2;
1115 struct cvmx_gmxx_rxx_jabber_s cn50xx;
1116 struct cvmx_gmxx_rxx_jabber_s cn52xx;
1117 struct cvmx_gmxx_rxx_jabber_s cn52xxp1;
1118 struct cvmx_gmxx_rxx_jabber_s cn56xx;
1119 struct cvmx_gmxx_rxx_jabber_s cn56xxp1;
1120 struct cvmx_gmxx_rxx_jabber_s cn58xx;
1121 struct cvmx_gmxx_rxx_jabber_s cn58xxp1;
1122};
1123
1124union cvmx_gmxx_rxx_pause_drop_time {
1125 uint64_t u64;
1126 struct cvmx_gmxx_rxx_pause_drop_time_s {
1127 uint64_t reserved_16_63:48;
1128 uint64_t status:16;
1129 } s;
1130 struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx;
1131 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx;
1132 struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1;
1133 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx;
1134 struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1;
1135 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx;
1136 struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1;
1137};
1138
1139union cvmx_gmxx_rxx_rx_inbnd {
1140 uint64_t u64;
1141 struct cvmx_gmxx_rxx_rx_inbnd_s {
1142 uint64_t reserved_4_63:60;
1143 uint64_t duplex:1;
1144 uint64_t speed:2;
1145 uint64_t status:1;
1146 } s;
1147 struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx;
1148 struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx;
1149 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx;
1150 struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2;
1151 struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx;
1152 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx;
1153 struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1;
1154};
1155
1156union cvmx_gmxx_rxx_stats_ctl {
1157 uint64_t u64;
1158 struct cvmx_gmxx_rxx_stats_ctl_s {
1159 uint64_t reserved_1_63:63;
1160 uint64_t rd_clr:1;
1161 } s;
1162 struct cvmx_gmxx_rxx_stats_ctl_s cn30xx;
1163 struct cvmx_gmxx_rxx_stats_ctl_s cn31xx;
1164 struct cvmx_gmxx_rxx_stats_ctl_s cn38xx;
1165 struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2;
1166 struct cvmx_gmxx_rxx_stats_ctl_s cn50xx;
1167 struct cvmx_gmxx_rxx_stats_ctl_s cn52xx;
1168 struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1;
1169 struct cvmx_gmxx_rxx_stats_ctl_s cn56xx;
1170 struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1;
1171 struct cvmx_gmxx_rxx_stats_ctl_s cn58xx;
1172 struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1;
1173};
1174
1175union cvmx_gmxx_rxx_stats_octs {
1176 uint64_t u64;
1177 struct cvmx_gmxx_rxx_stats_octs_s {
1178 uint64_t reserved_48_63:16;
1179 uint64_t cnt:48;
1180 } s;
1181 struct cvmx_gmxx_rxx_stats_octs_s cn30xx;
1182 struct cvmx_gmxx_rxx_stats_octs_s cn31xx;
1183 struct cvmx_gmxx_rxx_stats_octs_s cn38xx;
1184 struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2;
1185 struct cvmx_gmxx_rxx_stats_octs_s cn50xx;
1186 struct cvmx_gmxx_rxx_stats_octs_s cn52xx;
1187 struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1;
1188 struct cvmx_gmxx_rxx_stats_octs_s cn56xx;
1189 struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1;
1190 struct cvmx_gmxx_rxx_stats_octs_s cn58xx;
1191 struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1;
1192};
1193
1194union cvmx_gmxx_rxx_stats_octs_ctl {
1195 uint64_t u64;
1196 struct cvmx_gmxx_rxx_stats_octs_ctl_s {
1197 uint64_t reserved_48_63:16;
1198 uint64_t cnt:48;
1199 } s;
1200 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx;
1201 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx;
1202 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx;
1203 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2;
1204 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx;
1205 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx;
1206 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1;
1207 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx;
1208 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1;
1209 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx;
1210 struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1;
1211};
1212
1213union cvmx_gmxx_rxx_stats_octs_dmac {
1214 uint64_t u64;
1215 struct cvmx_gmxx_rxx_stats_octs_dmac_s {
1216 uint64_t reserved_48_63:16;
1217 uint64_t cnt:48;
1218 } s;
1219 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx;
1220 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx;
1221 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx;
1222 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2;
1223 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx;
1224 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx;
1225 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1;
1226 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx;
1227 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1;
1228 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx;
1229 struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1;
1230};
1231
1232union cvmx_gmxx_rxx_stats_octs_drp {
1233 uint64_t u64;
1234 struct cvmx_gmxx_rxx_stats_octs_drp_s {
1235 uint64_t reserved_48_63:16;
1236 uint64_t cnt:48;
1237 } s;
1238 struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx;
1239 struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx;
1240 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx;
1241 struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2;
1242 struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx;
1243 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx;
1244 struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1;
1245 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx;
1246 struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1;
1247 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx;
1248 struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1;
1249};
1250
1251union cvmx_gmxx_rxx_stats_pkts {
1252 uint64_t u64;
1253 struct cvmx_gmxx_rxx_stats_pkts_s {
1254 uint64_t reserved_32_63:32;
1255 uint64_t cnt:32;
1256 } s;
1257 struct cvmx_gmxx_rxx_stats_pkts_s cn30xx;
1258 struct cvmx_gmxx_rxx_stats_pkts_s cn31xx;
1259 struct cvmx_gmxx_rxx_stats_pkts_s cn38xx;
1260 struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2;
1261 struct cvmx_gmxx_rxx_stats_pkts_s cn50xx;
1262 struct cvmx_gmxx_rxx_stats_pkts_s cn52xx;
1263 struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1;
1264 struct cvmx_gmxx_rxx_stats_pkts_s cn56xx;
1265 struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1;
1266 struct cvmx_gmxx_rxx_stats_pkts_s cn58xx;
1267 struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1;
1268};
1269
1270union cvmx_gmxx_rxx_stats_pkts_bad {
1271 uint64_t u64;
1272 struct cvmx_gmxx_rxx_stats_pkts_bad_s {
1273 uint64_t reserved_32_63:32;
1274 uint64_t cnt:32;
1275 } s;
1276 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx;
1277 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx;
1278 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx;
1279 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2;
1280 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx;
1281 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx;
1282 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1;
1283 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx;
1284 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1;
1285 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx;
1286 struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1;
1287};
1288
1289union cvmx_gmxx_rxx_stats_pkts_ctl {
1290 uint64_t u64;
1291 struct cvmx_gmxx_rxx_stats_pkts_ctl_s {
1292 uint64_t reserved_32_63:32;
1293 uint64_t cnt:32;
1294 } s;
1295 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx;
1296 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx;
1297 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx;
1298 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2;
1299 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx;
1300 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx;
1301 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1;
1302 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx;
1303 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1;
1304 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx;
1305 struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1;
1306};
1307
1308union cvmx_gmxx_rxx_stats_pkts_dmac {
1309 uint64_t u64;
1310 struct cvmx_gmxx_rxx_stats_pkts_dmac_s {
1311 uint64_t reserved_32_63:32;
1312 uint64_t cnt:32;
1313 } s;
1314 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx;
1315 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx;
1316 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx;
1317 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2;
1318 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx;
1319 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx;
1320 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1;
1321 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx;
1322 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1;
1323 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx;
1324 struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1;
1325};
1326
1327union cvmx_gmxx_rxx_stats_pkts_drp {
1328 uint64_t u64;
1329 struct cvmx_gmxx_rxx_stats_pkts_drp_s {
1330 uint64_t reserved_32_63:32;
1331 uint64_t cnt:32;
1332 } s;
1333 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx;
1334 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx;
1335 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx;
1336 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2;
1337 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx;
1338 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx;
1339 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1;
1340 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx;
1341 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1;
1342 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx;
1343 struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1;
1344};
1345
1346union cvmx_gmxx_rxx_udd_skp {
1347 uint64_t u64;
1348 struct cvmx_gmxx_rxx_udd_skp_s {
1349 uint64_t reserved_9_63:55;
1350 uint64_t fcssel:1;
1351 uint64_t reserved_7_7:1;
1352 uint64_t len:7;
1353 } s;
1354 struct cvmx_gmxx_rxx_udd_skp_s cn30xx;
1355 struct cvmx_gmxx_rxx_udd_skp_s cn31xx;
1356 struct cvmx_gmxx_rxx_udd_skp_s cn38xx;
1357 struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2;
1358 struct cvmx_gmxx_rxx_udd_skp_s cn50xx;
1359 struct cvmx_gmxx_rxx_udd_skp_s cn52xx;
1360 struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1;
1361 struct cvmx_gmxx_rxx_udd_skp_s cn56xx;
1362 struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1;
1363 struct cvmx_gmxx_rxx_udd_skp_s cn58xx;
1364 struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1;
1365};
1366
1367union cvmx_gmxx_rx_bp_dropx {
1368 uint64_t u64;
1369 struct cvmx_gmxx_rx_bp_dropx_s {
1370 uint64_t reserved_6_63:58;
1371 uint64_t mark:6;
1372 } s;
1373 struct cvmx_gmxx_rx_bp_dropx_s cn30xx;
1374 struct cvmx_gmxx_rx_bp_dropx_s cn31xx;
1375 struct cvmx_gmxx_rx_bp_dropx_s cn38xx;
1376 struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2;
1377 struct cvmx_gmxx_rx_bp_dropx_s cn50xx;
1378 struct cvmx_gmxx_rx_bp_dropx_s cn52xx;
1379 struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1;
1380 struct cvmx_gmxx_rx_bp_dropx_s cn56xx;
1381 struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1;
1382 struct cvmx_gmxx_rx_bp_dropx_s cn58xx;
1383 struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1;
1384};
1385
1386union cvmx_gmxx_rx_bp_offx {
1387 uint64_t u64;
1388 struct cvmx_gmxx_rx_bp_offx_s {
1389 uint64_t reserved_6_63:58;
1390 uint64_t mark:6;
1391 } s;
1392 struct cvmx_gmxx_rx_bp_offx_s cn30xx;
1393 struct cvmx_gmxx_rx_bp_offx_s cn31xx;
1394 struct cvmx_gmxx_rx_bp_offx_s cn38xx;
1395 struct cvmx_gmxx_rx_bp_offx_s cn38xxp2;
1396 struct cvmx_gmxx_rx_bp_offx_s cn50xx;
1397 struct cvmx_gmxx_rx_bp_offx_s cn52xx;
1398 struct cvmx_gmxx_rx_bp_offx_s cn52xxp1;
1399 struct cvmx_gmxx_rx_bp_offx_s cn56xx;
1400 struct cvmx_gmxx_rx_bp_offx_s cn56xxp1;
1401 struct cvmx_gmxx_rx_bp_offx_s cn58xx;
1402 struct cvmx_gmxx_rx_bp_offx_s cn58xxp1;
1403};
1404
1405union cvmx_gmxx_rx_bp_onx {
1406 uint64_t u64;
1407 struct cvmx_gmxx_rx_bp_onx_s {
1408 uint64_t reserved_9_63:55;
1409 uint64_t mark:9;
1410 } s;
1411 struct cvmx_gmxx_rx_bp_onx_s cn30xx;
1412 struct cvmx_gmxx_rx_bp_onx_s cn31xx;
1413 struct cvmx_gmxx_rx_bp_onx_s cn38xx;
1414 struct cvmx_gmxx_rx_bp_onx_s cn38xxp2;
1415 struct cvmx_gmxx_rx_bp_onx_s cn50xx;
1416 struct cvmx_gmxx_rx_bp_onx_s cn52xx;
1417 struct cvmx_gmxx_rx_bp_onx_s cn52xxp1;
1418 struct cvmx_gmxx_rx_bp_onx_s cn56xx;
1419 struct cvmx_gmxx_rx_bp_onx_s cn56xxp1;
1420 struct cvmx_gmxx_rx_bp_onx_s cn58xx;
1421 struct cvmx_gmxx_rx_bp_onx_s cn58xxp1;
1422};
1423
1424union cvmx_gmxx_rx_hg2_status {
1425 uint64_t u64;
1426 struct cvmx_gmxx_rx_hg2_status_s {
1427 uint64_t reserved_48_63:16;
1428 uint64_t phtim2go:16;
1429 uint64_t xof:16;
1430 uint64_t lgtim2go:16;
1431 } s;
1432 struct cvmx_gmxx_rx_hg2_status_s cn52xx;
1433 struct cvmx_gmxx_rx_hg2_status_s cn52xxp1;
1434 struct cvmx_gmxx_rx_hg2_status_s cn56xx;
1435};
1436
1437union cvmx_gmxx_rx_pass_en {
1438 uint64_t u64;
1439 struct cvmx_gmxx_rx_pass_en_s {
1440 uint64_t reserved_16_63:48;
1441 uint64_t en:16;
1442 } s;
1443 struct cvmx_gmxx_rx_pass_en_s cn38xx;
1444 struct cvmx_gmxx_rx_pass_en_s cn38xxp2;
1445 struct cvmx_gmxx_rx_pass_en_s cn58xx;
1446 struct cvmx_gmxx_rx_pass_en_s cn58xxp1;
1447};
1448
1449union cvmx_gmxx_rx_pass_mapx {
1450 uint64_t u64;
1451 struct cvmx_gmxx_rx_pass_mapx_s {
1452 uint64_t reserved_4_63:60;
1453 uint64_t dprt:4;
1454 } s;
1455 struct cvmx_gmxx_rx_pass_mapx_s cn38xx;
1456 struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2;
1457 struct cvmx_gmxx_rx_pass_mapx_s cn58xx;
1458 struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1;
1459};
1460
1461union cvmx_gmxx_rx_prt_info {
1462 uint64_t u64;
1463 struct cvmx_gmxx_rx_prt_info_s {
1464 uint64_t reserved_32_63:32;
1465 uint64_t drop:16;
1466 uint64_t commit:16;
1467 } s;
1468 struct cvmx_gmxx_rx_prt_info_cn30xx {
1469 uint64_t reserved_19_63:45;
1470 uint64_t drop:3;
1471 uint64_t reserved_3_15:13;
1472 uint64_t commit:3;
1473 } cn30xx;
1474 struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx;
1475 struct cvmx_gmxx_rx_prt_info_s cn38xx;
1476 struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx;
1477 struct cvmx_gmxx_rx_prt_info_cn52xx {
1478 uint64_t reserved_20_63:44;
1479 uint64_t drop:4;
1480 uint64_t reserved_4_15:12;
1481 uint64_t commit:4;
1482 } cn52xx;
1483 struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1;
1484 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx;
1485 struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1;
1486 struct cvmx_gmxx_rx_prt_info_s cn58xx;
1487 struct cvmx_gmxx_rx_prt_info_s cn58xxp1;
1488};
1489
1490union cvmx_gmxx_rx_prts {
1491 uint64_t u64;
1492 struct cvmx_gmxx_rx_prts_s {
1493 uint64_t reserved_3_63:61;
1494 uint64_t prts:3;
1495 } s;
1496 struct cvmx_gmxx_rx_prts_s cn30xx;
1497 struct cvmx_gmxx_rx_prts_s cn31xx;
1498 struct cvmx_gmxx_rx_prts_s cn38xx;
1499 struct cvmx_gmxx_rx_prts_s cn38xxp2;
1500 struct cvmx_gmxx_rx_prts_s cn50xx;
1501 struct cvmx_gmxx_rx_prts_s cn52xx;
1502 struct cvmx_gmxx_rx_prts_s cn52xxp1;
1503 struct cvmx_gmxx_rx_prts_s cn56xx;
1504 struct cvmx_gmxx_rx_prts_s cn56xxp1;
1505 struct cvmx_gmxx_rx_prts_s cn58xx;
1506 struct cvmx_gmxx_rx_prts_s cn58xxp1;
1507};
1508
1509union cvmx_gmxx_rx_tx_status {
1510 uint64_t u64;
1511 struct cvmx_gmxx_rx_tx_status_s {
1512 uint64_t reserved_7_63:57;
1513 uint64_t tx:3;
1514 uint64_t reserved_3_3:1;
1515 uint64_t rx:3;
1516 } s;
1517 struct cvmx_gmxx_rx_tx_status_s cn30xx;
1518 struct cvmx_gmxx_rx_tx_status_s cn31xx;
1519 struct cvmx_gmxx_rx_tx_status_s cn50xx;
1520};
1521
1522union cvmx_gmxx_rx_xaui_bad_col {
1523 uint64_t u64;
1524 struct cvmx_gmxx_rx_xaui_bad_col_s {
1525 uint64_t reserved_40_63:24;
1526 uint64_t val:1;
1527 uint64_t state:3;
1528 uint64_t lane_rxc:4;
1529 uint64_t lane_rxd:32;
1530 } s;
1531 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx;
1532 struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1;
1533 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx;
1534 struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1;
1535};
1536
1537union cvmx_gmxx_rx_xaui_ctl {
1538 uint64_t u64;
1539 struct cvmx_gmxx_rx_xaui_ctl_s {
1540 uint64_t reserved_2_63:62;
1541 uint64_t status:2;
1542 } s;
1543 struct cvmx_gmxx_rx_xaui_ctl_s cn52xx;
1544 struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1;
1545 struct cvmx_gmxx_rx_xaui_ctl_s cn56xx;
1546 struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1;
1547};
1548
1549union cvmx_gmxx_smacx {
1550 uint64_t u64;
1551 struct cvmx_gmxx_smacx_s {
1552 uint64_t reserved_48_63:16;
1553 uint64_t smac:48;
1554 } s;
1555 struct cvmx_gmxx_smacx_s cn30xx;
1556 struct cvmx_gmxx_smacx_s cn31xx;
1557 struct cvmx_gmxx_smacx_s cn38xx;
1558 struct cvmx_gmxx_smacx_s cn38xxp2;
1559 struct cvmx_gmxx_smacx_s cn50xx;
1560 struct cvmx_gmxx_smacx_s cn52xx;
1561 struct cvmx_gmxx_smacx_s cn52xxp1;
1562 struct cvmx_gmxx_smacx_s cn56xx;
1563 struct cvmx_gmxx_smacx_s cn56xxp1;
1564 struct cvmx_gmxx_smacx_s cn58xx;
1565 struct cvmx_gmxx_smacx_s cn58xxp1;
1566};
1567
1568union cvmx_gmxx_stat_bp {
1569 uint64_t u64;
1570 struct cvmx_gmxx_stat_bp_s {
1571 uint64_t reserved_17_63:47;
1572 uint64_t bp:1;
1573 uint64_t cnt:16;
1574 } s;
1575 struct cvmx_gmxx_stat_bp_s cn30xx;
1576 struct cvmx_gmxx_stat_bp_s cn31xx;
1577 struct cvmx_gmxx_stat_bp_s cn38xx;
1578 struct cvmx_gmxx_stat_bp_s cn38xxp2;
1579 struct cvmx_gmxx_stat_bp_s cn50xx;
1580 struct cvmx_gmxx_stat_bp_s cn52xx;
1581 struct cvmx_gmxx_stat_bp_s cn52xxp1;
1582 struct cvmx_gmxx_stat_bp_s cn56xx;
1583 struct cvmx_gmxx_stat_bp_s cn56xxp1;
1584 struct cvmx_gmxx_stat_bp_s cn58xx;
1585 struct cvmx_gmxx_stat_bp_s cn58xxp1;
1586};
1587
1588union cvmx_gmxx_txx_append {
1589 uint64_t u64;
1590 struct cvmx_gmxx_txx_append_s {
1591 uint64_t reserved_4_63:60;
1592 uint64_t force_fcs:1;
1593 uint64_t fcs:1;
1594 uint64_t pad:1;
1595 uint64_t preamble:1;
1596 } s;
1597 struct cvmx_gmxx_txx_append_s cn30xx;
1598 struct cvmx_gmxx_txx_append_s cn31xx;
1599 struct cvmx_gmxx_txx_append_s cn38xx;
1600 struct cvmx_gmxx_txx_append_s cn38xxp2;
1601 struct cvmx_gmxx_txx_append_s cn50xx;
1602 struct cvmx_gmxx_txx_append_s cn52xx;
1603 struct cvmx_gmxx_txx_append_s cn52xxp1;
1604 struct cvmx_gmxx_txx_append_s cn56xx;
1605 struct cvmx_gmxx_txx_append_s cn56xxp1;
1606 struct cvmx_gmxx_txx_append_s cn58xx;
1607 struct cvmx_gmxx_txx_append_s cn58xxp1;
1608};
1609
1610union cvmx_gmxx_txx_burst {
1611 uint64_t u64;
1612 struct cvmx_gmxx_txx_burst_s {
1613 uint64_t reserved_16_63:48;
1614 uint64_t burst:16;
1615 } s;
1616 struct cvmx_gmxx_txx_burst_s cn30xx;
1617 struct cvmx_gmxx_txx_burst_s cn31xx;
1618 struct cvmx_gmxx_txx_burst_s cn38xx;
1619 struct cvmx_gmxx_txx_burst_s cn38xxp2;
1620 struct cvmx_gmxx_txx_burst_s cn50xx;
1621 struct cvmx_gmxx_txx_burst_s cn52xx;
1622 struct cvmx_gmxx_txx_burst_s cn52xxp1;
1623 struct cvmx_gmxx_txx_burst_s cn56xx;
1624 struct cvmx_gmxx_txx_burst_s cn56xxp1;
1625 struct cvmx_gmxx_txx_burst_s cn58xx;
1626 struct cvmx_gmxx_txx_burst_s cn58xxp1;
1627};
1628
1629union cvmx_gmxx_txx_cbfc_xoff {
1630 uint64_t u64;
1631 struct cvmx_gmxx_txx_cbfc_xoff_s {
1632 uint64_t reserved_16_63:48;
1633 uint64_t xoff:16;
1634 } s;
1635 struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx;
1636 struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx;
1637};
1638
1639union cvmx_gmxx_txx_cbfc_xon {
1640 uint64_t u64;
1641 struct cvmx_gmxx_txx_cbfc_xon_s {
1642 uint64_t reserved_16_63:48;
1643 uint64_t xon:16;
1644 } s;
1645 struct cvmx_gmxx_txx_cbfc_xon_s cn52xx;
1646 struct cvmx_gmxx_txx_cbfc_xon_s cn56xx;
1647};
1648
1649union cvmx_gmxx_txx_clk {
1650 uint64_t u64;
1651 struct cvmx_gmxx_txx_clk_s {
1652 uint64_t reserved_6_63:58;
1653 uint64_t clk_cnt:6;
1654 } s;
1655 struct cvmx_gmxx_txx_clk_s cn30xx;
1656 struct cvmx_gmxx_txx_clk_s cn31xx;
1657 struct cvmx_gmxx_txx_clk_s cn38xx;
1658 struct cvmx_gmxx_txx_clk_s cn38xxp2;
1659 struct cvmx_gmxx_txx_clk_s cn50xx;
1660 struct cvmx_gmxx_txx_clk_s cn58xx;
1661 struct cvmx_gmxx_txx_clk_s cn58xxp1;
1662};
1663
1664union cvmx_gmxx_txx_ctl {
1665 uint64_t u64;
1666 struct cvmx_gmxx_txx_ctl_s {
1667 uint64_t reserved_2_63:62;
1668 uint64_t xsdef_en:1;
1669 uint64_t xscol_en:1;
1670 } s;
1671 struct cvmx_gmxx_txx_ctl_s cn30xx;
1672 struct cvmx_gmxx_txx_ctl_s cn31xx;
1673 struct cvmx_gmxx_txx_ctl_s cn38xx;
1674 struct cvmx_gmxx_txx_ctl_s cn38xxp2;
1675 struct cvmx_gmxx_txx_ctl_s cn50xx;
1676 struct cvmx_gmxx_txx_ctl_s cn52xx;
1677 struct cvmx_gmxx_txx_ctl_s cn52xxp1;
1678 struct cvmx_gmxx_txx_ctl_s cn56xx;
1679 struct cvmx_gmxx_txx_ctl_s cn56xxp1;
1680 struct cvmx_gmxx_txx_ctl_s cn58xx;
1681 struct cvmx_gmxx_txx_ctl_s cn58xxp1;
1682};
1683
1684union cvmx_gmxx_txx_min_pkt {
1685 uint64_t u64;
1686 struct cvmx_gmxx_txx_min_pkt_s {
1687 uint64_t reserved_8_63:56;
1688 uint64_t min_size:8;
1689 } s;
1690 struct cvmx_gmxx_txx_min_pkt_s cn30xx;
1691 struct cvmx_gmxx_txx_min_pkt_s cn31xx;
1692 struct cvmx_gmxx_txx_min_pkt_s cn38xx;
1693 struct cvmx_gmxx_txx_min_pkt_s cn38xxp2;
1694 struct cvmx_gmxx_txx_min_pkt_s cn50xx;
1695 struct cvmx_gmxx_txx_min_pkt_s cn52xx;
1696 struct cvmx_gmxx_txx_min_pkt_s cn52xxp1;
1697 struct cvmx_gmxx_txx_min_pkt_s cn56xx;
1698 struct cvmx_gmxx_txx_min_pkt_s cn56xxp1;
1699 struct cvmx_gmxx_txx_min_pkt_s cn58xx;
1700 struct cvmx_gmxx_txx_min_pkt_s cn58xxp1;
1701};
1702
1703union cvmx_gmxx_txx_pause_pkt_interval {
1704 uint64_t u64;
1705 struct cvmx_gmxx_txx_pause_pkt_interval_s {
1706 uint64_t reserved_16_63:48;
1707 uint64_t interval:16;
1708 } s;
1709 struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx;
1710 struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx;
1711 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx;
1712 struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2;
1713 struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx;
1714 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx;
1715 struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1;
1716 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx;
1717 struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1;
1718 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx;
1719 struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1;
1720};
1721
1722union cvmx_gmxx_txx_pause_pkt_time {
1723 uint64_t u64;
1724 struct cvmx_gmxx_txx_pause_pkt_time_s {
1725 uint64_t reserved_16_63:48;
1726 uint64_t time:16;
1727 } s;
1728 struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx;
1729 struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx;
1730 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx;
1731 struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2;
1732 struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx;
1733 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx;
1734 struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1;
1735 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx;
1736 struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1;
1737 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx;
1738 struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1;
1739};
1740
1741union cvmx_gmxx_txx_pause_togo {
1742 uint64_t u64;
1743 struct cvmx_gmxx_txx_pause_togo_s {
1744 uint64_t reserved_32_63:32;
1745 uint64_t msg_time:16;
1746 uint64_t time:16;
1747 } s;
1748 struct cvmx_gmxx_txx_pause_togo_cn30xx {
1749 uint64_t reserved_16_63:48;
1750 uint64_t time:16;
1751 } cn30xx;
1752 struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx;
1753 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx;
1754 struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2;
1755 struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx;
1756 struct cvmx_gmxx_txx_pause_togo_s cn52xx;
1757 struct cvmx_gmxx_txx_pause_togo_s cn52xxp1;
1758 struct cvmx_gmxx_txx_pause_togo_s cn56xx;
1759 struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1;
1760 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx;
1761 struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1;
1762};
1763
1764union cvmx_gmxx_txx_pause_zero {
1765 uint64_t u64;
1766 struct cvmx_gmxx_txx_pause_zero_s {
1767 uint64_t reserved_1_63:63;
1768 uint64_t send:1;
1769 } s;
1770 struct cvmx_gmxx_txx_pause_zero_s cn30xx;
1771 struct cvmx_gmxx_txx_pause_zero_s cn31xx;
1772 struct cvmx_gmxx_txx_pause_zero_s cn38xx;
1773 struct cvmx_gmxx_txx_pause_zero_s cn38xxp2;
1774 struct cvmx_gmxx_txx_pause_zero_s cn50xx;
1775 struct cvmx_gmxx_txx_pause_zero_s cn52xx;
1776 struct cvmx_gmxx_txx_pause_zero_s cn52xxp1;
1777 struct cvmx_gmxx_txx_pause_zero_s cn56xx;
1778 struct cvmx_gmxx_txx_pause_zero_s cn56xxp1;
1779 struct cvmx_gmxx_txx_pause_zero_s cn58xx;
1780 struct cvmx_gmxx_txx_pause_zero_s cn58xxp1;
1781};
1782
1783union cvmx_gmxx_txx_sgmii_ctl {
1784 uint64_t u64;
1785 struct cvmx_gmxx_txx_sgmii_ctl_s {
1786 uint64_t reserved_1_63:63;
1787 uint64_t align:1;
1788 } s;
1789 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx;
1790 struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1;
1791 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx;
1792 struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1;
1793};
1794
1795union cvmx_gmxx_txx_slot {
1796 uint64_t u64;
1797 struct cvmx_gmxx_txx_slot_s {
1798 uint64_t reserved_10_63:54;
1799 uint64_t slot:10;
1800 } s;
1801 struct cvmx_gmxx_txx_slot_s cn30xx;
1802 struct cvmx_gmxx_txx_slot_s cn31xx;
1803 struct cvmx_gmxx_txx_slot_s cn38xx;
1804 struct cvmx_gmxx_txx_slot_s cn38xxp2;
1805 struct cvmx_gmxx_txx_slot_s cn50xx;
1806 struct cvmx_gmxx_txx_slot_s cn52xx;
1807 struct cvmx_gmxx_txx_slot_s cn52xxp1;
1808 struct cvmx_gmxx_txx_slot_s cn56xx;
1809 struct cvmx_gmxx_txx_slot_s cn56xxp1;
1810 struct cvmx_gmxx_txx_slot_s cn58xx;
1811 struct cvmx_gmxx_txx_slot_s cn58xxp1;
1812};
1813
1814union cvmx_gmxx_txx_soft_pause {
1815 uint64_t u64;
1816 struct cvmx_gmxx_txx_soft_pause_s {
1817 uint64_t reserved_16_63:48;
1818 uint64_t time:16;
1819 } s;
1820 struct cvmx_gmxx_txx_soft_pause_s cn30xx;
1821 struct cvmx_gmxx_txx_soft_pause_s cn31xx;
1822 struct cvmx_gmxx_txx_soft_pause_s cn38xx;
1823 struct cvmx_gmxx_txx_soft_pause_s cn38xxp2;
1824 struct cvmx_gmxx_txx_soft_pause_s cn50xx;
1825 struct cvmx_gmxx_txx_soft_pause_s cn52xx;
1826 struct cvmx_gmxx_txx_soft_pause_s cn52xxp1;
1827 struct cvmx_gmxx_txx_soft_pause_s cn56xx;
1828 struct cvmx_gmxx_txx_soft_pause_s cn56xxp1;
1829 struct cvmx_gmxx_txx_soft_pause_s cn58xx;
1830 struct cvmx_gmxx_txx_soft_pause_s cn58xxp1;
1831};
1832
1833union cvmx_gmxx_txx_stat0 {
1834 uint64_t u64;
1835 struct cvmx_gmxx_txx_stat0_s {
1836 uint64_t xsdef:32;
1837 uint64_t xscol:32;
1838 } s;
1839 struct cvmx_gmxx_txx_stat0_s cn30xx;
1840 struct cvmx_gmxx_txx_stat0_s cn31xx;
1841 struct cvmx_gmxx_txx_stat0_s cn38xx;
1842 struct cvmx_gmxx_txx_stat0_s cn38xxp2;
1843 struct cvmx_gmxx_txx_stat0_s cn50xx;
1844 struct cvmx_gmxx_txx_stat0_s cn52xx;
1845 struct cvmx_gmxx_txx_stat0_s cn52xxp1;
1846 struct cvmx_gmxx_txx_stat0_s cn56xx;
1847 struct cvmx_gmxx_txx_stat0_s cn56xxp1;
1848 struct cvmx_gmxx_txx_stat0_s cn58xx;
1849 struct cvmx_gmxx_txx_stat0_s cn58xxp1;
1850};
1851
1852union cvmx_gmxx_txx_stat1 {
1853 uint64_t u64;
1854 struct cvmx_gmxx_txx_stat1_s {
1855 uint64_t scol:32;
1856 uint64_t mcol:32;
1857 } s;
1858 struct cvmx_gmxx_txx_stat1_s cn30xx;
1859 struct cvmx_gmxx_txx_stat1_s cn31xx;
1860 struct cvmx_gmxx_txx_stat1_s cn38xx;
1861 struct cvmx_gmxx_txx_stat1_s cn38xxp2;
1862 struct cvmx_gmxx_txx_stat1_s cn50xx;
1863 struct cvmx_gmxx_txx_stat1_s cn52xx;
1864 struct cvmx_gmxx_txx_stat1_s cn52xxp1;
1865 struct cvmx_gmxx_txx_stat1_s cn56xx;
1866 struct cvmx_gmxx_txx_stat1_s cn56xxp1;
1867 struct cvmx_gmxx_txx_stat1_s cn58xx;
1868 struct cvmx_gmxx_txx_stat1_s cn58xxp1;
1869};
1870
1871union cvmx_gmxx_txx_stat2 {
1872 uint64_t u64;
1873 struct cvmx_gmxx_txx_stat2_s {
1874 uint64_t reserved_48_63:16;
1875 uint64_t octs:48;
1876 } s;
1877 struct cvmx_gmxx_txx_stat2_s cn30xx;
1878 struct cvmx_gmxx_txx_stat2_s cn31xx;
1879 struct cvmx_gmxx_txx_stat2_s cn38xx;
1880 struct cvmx_gmxx_txx_stat2_s cn38xxp2;
1881 struct cvmx_gmxx_txx_stat2_s cn50xx;
1882 struct cvmx_gmxx_txx_stat2_s cn52xx;
1883 struct cvmx_gmxx_txx_stat2_s cn52xxp1;
1884 struct cvmx_gmxx_txx_stat2_s cn56xx;
1885 struct cvmx_gmxx_txx_stat2_s cn56xxp1;
1886 struct cvmx_gmxx_txx_stat2_s cn58xx;
1887 struct cvmx_gmxx_txx_stat2_s cn58xxp1;
1888};
1889
1890union cvmx_gmxx_txx_stat3 {
1891 uint64_t u64;
1892 struct cvmx_gmxx_txx_stat3_s {
1893 uint64_t reserved_32_63:32;
1894 uint64_t pkts:32;
1895 } s;
1896 struct cvmx_gmxx_txx_stat3_s cn30xx;
1897 struct cvmx_gmxx_txx_stat3_s cn31xx;
1898 struct cvmx_gmxx_txx_stat3_s cn38xx;
1899 struct cvmx_gmxx_txx_stat3_s cn38xxp2;
1900 struct cvmx_gmxx_txx_stat3_s cn50xx;
1901 struct cvmx_gmxx_txx_stat3_s cn52xx;
1902 struct cvmx_gmxx_txx_stat3_s cn52xxp1;
1903 struct cvmx_gmxx_txx_stat3_s cn56xx;
1904 struct cvmx_gmxx_txx_stat3_s cn56xxp1;
1905 struct cvmx_gmxx_txx_stat3_s cn58xx;
1906 struct cvmx_gmxx_txx_stat3_s cn58xxp1;
1907};
1908
1909union cvmx_gmxx_txx_stat4 {
1910 uint64_t u64;
1911 struct cvmx_gmxx_txx_stat4_s {
1912 uint64_t hist1:32;
1913 uint64_t hist0:32;
1914 } s;
1915 struct cvmx_gmxx_txx_stat4_s cn30xx;
1916 struct cvmx_gmxx_txx_stat4_s cn31xx;
1917 struct cvmx_gmxx_txx_stat4_s cn38xx;
1918 struct cvmx_gmxx_txx_stat4_s cn38xxp2;
1919 struct cvmx_gmxx_txx_stat4_s cn50xx;
1920 struct cvmx_gmxx_txx_stat4_s cn52xx;
1921 struct cvmx_gmxx_txx_stat4_s cn52xxp1;
1922 struct cvmx_gmxx_txx_stat4_s cn56xx;
1923 struct cvmx_gmxx_txx_stat4_s cn56xxp1;
1924 struct cvmx_gmxx_txx_stat4_s cn58xx;
1925 struct cvmx_gmxx_txx_stat4_s cn58xxp1;
1926};
1927
1928union cvmx_gmxx_txx_stat5 {
1929 uint64_t u64;
1930 struct cvmx_gmxx_txx_stat5_s {
1931 uint64_t hist3:32;
1932 uint64_t hist2:32;
1933 } s;
1934 struct cvmx_gmxx_txx_stat5_s cn30xx;
1935 struct cvmx_gmxx_txx_stat5_s cn31xx;
1936 struct cvmx_gmxx_txx_stat5_s cn38xx;
1937 struct cvmx_gmxx_txx_stat5_s cn38xxp2;
1938 struct cvmx_gmxx_txx_stat5_s cn50xx;
1939 struct cvmx_gmxx_txx_stat5_s cn52xx;
1940 struct cvmx_gmxx_txx_stat5_s cn52xxp1;
1941 struct cvmx_gmxx_txx_stat5_s cn56xx;
1942 struct cvmx_gmxx_txx_stat5_s cn56xxp1;
1943 struct cvmx_gmxx_txx_stat5_s cn58xx;
1944 struct cvmx_gmxx_txx_stat5_s cn58xxp1;
1945};
1946
1947union cvmx_gmxx_txx_stat6 {
1948 uint64_t u64;
1949 struct cvmx_gmxx_txx_stat6_s {
1950 uint64_t hist5:32;
1951 uint64_t hist4:32;
1952 } s;
1953 struct cvmx_gmxx_txx_stat6_s cn30xx;
1954 struct cvmx_gmxx_txx_stat6_s cn31xx;
1955 struct cvmx_gmxx_txx_stat6_s cn38xx;
1956 struct cvmx_gmxx_txx_stat6_s cn38xxp2;
1957 struct cvmx_gmxx_txx_stat6_s cn50xx;
1958 struct cvmx_gmxx_txx_stat6_s cn52xx;
1959 struct cvmx_gmxx_txx_stat6_s cn52xxp1;
1960 struct cvmx_gmxx_txx_stat6_s cn56xx;
1961 struct cvmx_gmxx_txx_stat6_s cn56xxp1;
1962 struct cvmx_gmxx_txx_stat6_s cn58xx;
1963 struct cvmx_gmxx_txx_stat6_s cn58xxp1;
1964};
1965
1966union cvmx_gmxx_txx_stat7 {
1967 uint64_t u64;
1968 struct cvmx_gmxx_txx_stat7_s {
1969 uint64_t hist7:32;
1970 uint64_t hist6:32;
1971 } s;
1972 struct cvmx_gmxx_txx_stat7_s cn30xx;
1973 struct cvmx_gmxx_txx_stat7_s cn31xx;
1974 struct cvmx_gmxx_txx_stat7_s cn38xx;
1975 struct cvmx_gmxx_txx_stat7_s cn38xxp2;
1976 struct cvmx_gmxx_txx_stat7_s cn50xx;
1977 struct cvmx_gmxx_txx_stat7_s cn52xx;
1978 struct cvmx_gmxx_txx_stat7_s cn52xxp1;
1979 struct cvmx_gmxx_txx_stat7_s cn56xx;
1980 struct cvmx_gmxx_txx_stat7_s cn56xxp1;
1981 struct cvmx_gmxx_txx_stat7_s cn58xx;
1982 struct cvmx_gmxx_txx_stat7_s cn58xxp1;
1983};
1984
1985union cvmx_gmxx_txx_stat8 {
1986 uint64_t u64;
1987 struct cvmx_gmxx_txx_stat8_s {
1988 uint64_t mcst:32;
1989 uint64_t bcst:32;
1990 } s;
1991 struct cvmx_gmxx_txx_stat8_s cn30xx;
1992 struct cvmx_gmxx_txx_stat8_s cn31xx;
1993 struct cvmx_gmxx_txx_stat8_s cn38xx;
1994 struct cvmx_gmxx_txx_stat8_s cn38xxp2;
1995 struct cvmx_gmxx_txx_stat8_s cn50xx;
1996 struct cvmx_gmxx_txx_stat8_s cn52xx;
1997 struct cvmx_gmxx_txx_stat8_s cn52xxp1;
1998 struct cvmx_gmxx_txx_stat8_s cn56xx;
1999 struct cvmx_gmxx_txx_stat8_s cn56xxp1;
2000 struct cvmx_gmxx_txx_stat8_s cn58xx;
2001 struct cvmx_gmxx_txx_stat8_s cn58xxp1;
2002};
2003
2004union cvmx_gmxx_txx_stat9 {
2005 uint64_t u64;
2006 struct cvmx_gmxx_txx_stat9_s {
2007 uint64_t undflw:32;
2008 uint64_t ctl:32;
2009 } s;
2010 struct cvmx_gmxx_txx_stat9_s cn30xx;
2011 struct cvmx_gmxx_txx_stat9_s cn31xx;
2012 struct cvmx_gmxx_txx_stat9_s cn38xx;
2013 struct cvmx_gmxx_txx_stat9_s cn38xxp2;
2014 struct cvmx_gmxx_txx_stat9_s cn50xx;
2015 struct cvmx_gmxx_txx_stat9_s cn52xx;
2016 struct cvmx_gmxx_txx_stat9_s cn52xxp1;
2017 struct cvmx_gmxx_txx_stat9_s cn56xx;
2018 struct cvmx_gmxx_txx_stat9_s cn56xxp1;
2019 struct cvmx_gmxx_txx_stat9_s cn58xx;
2020 struct cvmx_gmxx_txx_stat9_s cn58xxp1;
2021};
2022
2023union cvmx_gmxx_txx_stats_ctl {
2024 uint64_t u64;
2025 struct cvmx_gmxx_txx_stats_ctl_s {
2026 uint64_t reserved_1_63:63;
2027 uint64_t rd_clr:1;
2028 } s;
2029 struct cvmx_gmxx_txx_stats_ctl_s cn30xx;
2030 struct cvmx_gmxx_txx_stats_ctl_s cn31xx;
2031 struct cvmx_gmxx_txx_stats_ctl_s cn38xx;
2032 struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2;
2033 struct cvmx_gmxx_txx_stats_ctl_s cn50xx;
2034 struct cvmx_gmxx_txx_stats_ctl_s cn52xx;
2035 struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1;
2036 struct cvmx_gmxx_txx_stats_ctl_s cn56xx;
2037 struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1;
2038 struct cvmx_gmxx_txx_stats_ctl_s cn58xx;
2039 struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1;
2040};
2041
2042union cvmx_gmxx_txx_thresh {
2043 uint64_t u64;
2044 struct cvmx_gmxx_txx_thresh_s {
2045 uint64_t reserved_9_63:55;
2046 uint64_t cnt:9;
2047 } s;
2048 struct cvmx_gmxx_txx_thresh_cn30xx {
2049 uint64_t reserved_7_63:57;
2050 uint64_t cnt:7;
2051 } cn30xx;
2052 struct cvmx_gmxx_txx_thresh_cn30xx cn31xx;
2053 struct cvmx_gmxx_txx_thresh_s cn38xx;
2054 struct cvmx_gmxx_txx_thresh_s cn38xxp2;
2055 struct cvmx_gmxx_txx_thresh_cn30xx cn50xx;
2056 struct cvmx_gmxx_txx_thresh_s cn52xx;
2057 struct cvmx_gmxx_txx_thresh_s cn52xxp1;
2058 struct cvmx_gmxx_txx_thresh_s cn56xx;
2059 struct cvmx_gmxx_txx_thresh_s cn56xxp1;
2060 struct cvmx_gmxx_txx_thresh_s cn58xx;
2061 struct cvmx_gmxx_txx_thresh_s cn58xxp1;
2062};
2063
2064union cvmx_gmxx_tx_bp {
2065 uint64_t u64;
2066 struct cvmx_gmxx_tx_bp_s {
2067 uint64_t reserved_4_63:60;
2068 uint64_t bp:4;
2069 } s;
2070 struct cvmx_gmxx_tx_bp_cn30xx {
2071 uint64_t reserved_3_63:61;
2072 uint64_t bp:3;
2073 } cn30xx;
2074 struct cvmx_gmxx_tx_bp_cn30xx cn31xx;
2075 struct cvmx_gmxx_tx_bp_s cn38xx;
2076 struct cvmx_gmxx_tx_bp_s cn38xxp2;
2077 struct cvmx_gmxx_tx_bp_cn30xx cn50xx;
2078 struct cvmx_gmxx_tx_bp_s cn52xx;
2079 struct cvmx_gmxx_tx_bp_s cn52xxp1;
2080 struct cvmx_gmxx_tx_bp_s cn56xx;
2081 struct cvmx_gmxx_tx_bp_s cn56xxp1;
2082 struct cvmx_gmxx_tx_bp_s cn58xx;
2083 struct cvmx_gmxx_tx_bp_s cn58xxp1;
2084};
2085
2086union cvmx_gmxx_tx_clk_mskx {
2087 uint64_t u64;
2088 struct cvmx_gmxx_tx_clk_mskx_s {
2089 uint64_t reserved_1_63:63;
2090 uint64_t msk:1;
2091 } s;
2092 struct cvmx_gmxx_tx_clk_mskx_s cn30xx;
2093 struct cvmx_gmxx_tx_clk_mskx_s cn50xx;
2094};
2095
2096union cvmx_gmxx_tx_col_attempt {
2097 uint64_t u64;
2098 struct cvmx_gmxx_tx_col_attempt_s {
2099 uint64_t reserved_5_63:59;
2100 uint64_t limit:5;
2101 } s;
2102 struct cvmx_gmxx_tx_col_attempt_s cn30xx;
2103 struct cvmx_gmxx_tx_col_attempt_s cn31xx;
2104 struct cvmx_gmxx_tx_col_attempt_s cn38xx;
2105 struct cvmx_gmxx_tx_col_attempt_s cn38xxp2;
2106 struct cvmx_gmxx_tx_col_attempt_s cn50xx;
2107 struct cvmx_gmxx_tx_col_attempt_s cn52xx;
2108 struct cvmx_gmxx_tx_col_attempt_s cn52xxp1;
2109 struct cvmx_gmxx_tx_col_attempt_s cn56xx;
2110 struct cvmx_gmxx_tx_col_attempt_s cn56xxp1;
2111 struct cvmx_gmxx_tx_col_attempt_s cn58xx;
2112 struct cvmx_gmxx_tx_col_attempt_s cn58xxp1;
2113};
2114
2115union cvmx_gmxx_tx_corrupt {
2116 uint64_t u64;
2117 struct cvmx_gmxx_tx_corrupt_s {
2118 uint64_t reserved_4_63:60;
2119 uint64_t corrupt:4;
2120 } s;
2121 struct cvmx_gmxx_tx_corrupt_cn30xx {
2122 uint64_t reserved_3_63:61;
2123 uint64_t corrupt:3;
2124 } cn30xx;
2125 struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx;
2126 struct cvmx_gmxx_tx_corrupt_s cn38xx;
2127 struct cvmx_gmxx_tx_corrupt_s cn38xxp2;
2128 struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx;
2129 struct cvmx_gmxx_tx_corrupt_s cn52xx;
2130 struct cvmx_gmxx_tx_corrupt_s cn52xxp1;
2131 struct cvmx_gmxx_tx_corrupt_s cn56xx;
2132 struct cvmx_gmxx_tx_corrupt_s cn56xxp1;
2133 struct cvmx_gmxx_tx_corrupt_s cn58xx;
2134 struct cvmx_gmxx_tx_corrupt_s cn58xxp1;
2135};
2136
2137union cvmx_gmxx_tx_hg2_reg1 {
2138 uint64_t u64;
2139 struct cvmx_gmxx_tx_hg2_reg1_s {
2140 uint64_t reserved_16_63:48;
2141 uint64_t tx_xof:16;
2142 } s;
2143 struct cvmx_gmxx_tx_hg2_reg1_s cn52xx;
2144 struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1;
2145 struct cvmx_gmxx_tx_hg2_reg1_s cn56xx;
2146};
2147
2148union cvmx_gmxx_tx_hg2_reg2 {
2149 uint64_t u64;
2150 struct cvmx_gmxx_tx_hg2_reg2_s {
2151 uint64_t reserved_16_63:48;
2152 uint64_t tx_xon:16;
2153 } s;
2154 struct cvmx_gmxx_tx_hg2_reg2_s cn52xx;
2155 struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1;
2156 struct cvmx_gmxx_tx_hg2_reg2_s cn56xx;
2157};
2158
2159union cvmx_gmxx_tx_ifg {
2160 uint64_t u64;
2161 struct cvmx_gmxx_tx_ifg_s {
2162 uint64_t reserved_8_63:56;
2163 uint64_t ifg2:4;
2164 uint64_t ifg1:4;
2165 } s;
2166 struct cvmx_gmxx_tx_ifg_s cn30xx;
2167 struct cvmx_gmxx_tx_ifg_s cn31xx;
2168 struct cvmx_gmxx_tx_ifg_s cn38xx;
2169 struct cvmx_gmxx_tx_ifg_s cn38xxp2;
2170 struct cvmx_gmxx_tx_ifg_s cn50xx;
2171 struct cvmx_gmxx_tx_ifg_s cn52xx;
2172 struct cvmx_gmxx_tx_ifg_s cn52xxp1;
2173 struct cvmx_gmxx_tx_ifg_s cn56xx;
2174 struct cvmx_gmxx_tx_ifg_s cn56xxp1;
2175 struct cvmx_gmxx_tx_ifg_s cn58xx;
2176 struct cvmx_gmxx_tx_ifg_s cn58xxp1;
2177};
2178
2179union cvmx_gmxx_tx_int_en {
2180 uint64_t u64;
2181 struct cvmx_gmxx_tx_int_en_s {
2182 uint64_t reserved_20_63:44;
2183 uint64_t late_col:4;
2184 uint64_t xsdef:4;
2185 uint64_t xscol:4;
2186 uint64_t reserved_6_7:2;
2187 uint64_t undflw:4;
2188 uint64_t ncb_nxa:1;
2189 uint64_t pko_nxa:1;
2190 } s;
2191 struct cvmx_gmxx_tx_int_en_cn30xx {
2192 uint64_t reserved_19_63:45;
2193 uint64_t late_col:3;
2194 uint64_t reserved_15_15:1;
2195 uint64_t xsdef:3;
2196 uint64_t reserved_11_11:1;
2197 uint64_t xscol:3;
2198 uint64_t reserved_5_7:3;
2199 uint64_t undflw:3;
2200 uint64_t reserved_1_1:1;
2201 uint64_t pko_nxa:1;
2202 } cn30xx;
2203 struct cvmx_gmxx_tx_int_en_cn31xx {
2204 uint64_t reserved_15_63:49;
2205 uint64_t xsdef:3;
2206 uint64_t reserved_11_11:1;
2207 uint64_t xscol:3;
2208 uint64_t reserved_5_7:3;
2209 uint64_t undflw:3;
2210 uint64_t reserved_1_1:1;
2211 uint64_t pko_nxa:1;
2212 } cn31xx;
2213 struct cvmx_gmxx_tx_int_en_s cn38xx;
2214 struct cvmx_gmxx_tx_int_en_cn38xxp2 {
2215 uint64_t reserved_16_63:48;
2216 uint64_t xsdef:4;
2217 uint64_t xscol:4;
2218 uint64_t reserved_6_7:2;
2219 uint64_t undflw:4;
2220 uint64_t ncb_nxa:1;
2221 uint64_t pko_nxa:1;
2222 } cn38xxp2;
2223 struct cvmx_gmxx_tx_int_en_cn30xx cn50xx;
2224 struct cvmx_gmxx_tx_int_en_cn52xx {
2225 uint64_t reserved_20_63:44;
2226 uint64_t late_col:4;
2227 uint64_t xsdef:4;
2228 uint64_t xscol:4;
2229 uint64_t reserved_6_7:2;
2230 uint64_t undflw:4;
2231 uint64_t reserved_1_1:1;
2232 uint64_t pko_nxa:1;
2233 } cn52xx;
2234 struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1;
2235 struct cvmx_gmxx_tx_int_en_cn52xx cn56xx;
2236 struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1;
2237 struct cvmx_gmxx_tx_int_en_s cn58xx;
2238 struct cvmx_gmxx_tx_int_en_s cn58xxp1;
2239};
2240
2241union cvmx_gmxx_tx_int_reg {
2242 uint64_t u64;
2243 struct cvmx_gmxx_tx_int_reg_s {
2244 uint64_t reserved_20_63:44;
2245 uint64_t late_col:4;
2246 uint64_t xsdef:4;
2247 uint64_t xscol:4;
2248 uint64_t reserved_6_7:2;
2249 uint64_t undflw:4;
2250 uint64_t ncb_nxa:1;
2251 uint64_t pko_nxa:1;
2252 } s;
2253 struct cvmx_gmxx_tx_int_reg_cn30xx {
2254 uint64_t reserved_19_63:45;
2255 uint64_t late_col:3;
2256 uint64_t reserved_15_15:1;
2257 uint64_t xsdef:3;
2258 uint64_t reserved_11_11:1;
2259 uint64_t xscol:3;
2260 uint64_t reserved_5_7:3;
2261 uint64_t undflw:3;
2262 uint64_t reserved_1_1:1;
2263 uint64_t pko_nxa:1;
2264 } cn30xx;
2265 struct cvmx_gmxx_tx_int_reg_cn31xx {
2266 uint64_t reserved_15_63:49;
2267 uint64_t xsdef:3;
2268 uint64_t reserved_11_11:1;
2269 uint64_t xscol:3;
2270 uint64_t reserved_5_7:3;
2271 uint64_t undflw:3;
2272 uint64_t reserved_1_1:1;
2273 uint64_t pko_nxa:1;
2274 } cn31xx;
2275 struct cvmx_gmxx_tx_int_reg_s cn38xx;
2276 struct cvmx_gmxx_tx_int_reg_cn38xxp2 {
2277 uint64_t reserved_16_63:48;
2278 uint64_t xsdef:4;
2279 uint64_t xscol:4;
2280 uint64_t reserved_6_7:2;
2281 uint64_t undflw:4;
2282 uint64_t ncb_nxa:1;
2283 uint64_t pko_nxa:1;
2284 } cn38xxp2;
2285 struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx;
2286 struct cvmx_gmxx_tx_int_reg_cn52xx {
2287 uint64_t reserved_20_63:44;
2288 uint64_t late_col:4;
2289 uint64_t xsdef:4;
2290 uint64_t xscol:4;
2291 uint64_t reserved_6_7:2;
2292 uint64_t undflw:4;
2293 uint64_t reserved_1_1:1;
2294 uint64_t pko_nxa:1;
2295 } cn52xx;
2296 struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1;
2297 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx;
2298 struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1;
2299 struct cvmx_gmxx_tx_int_reg_s cn58xx;
2300 struct cvmx_gmxx_tx_int_reg_s cn58xxp1;
2301};
2302
2303union cvmx_gmxx_tx_jam {
2304 uint64_t u64;
2305 struct cvmx_gmxx_tx_jam_s {
2306 uint64_t reserved_8_63:56;
2307 uint64_t jam:8;
2308 } s;
2309 struct cvmx_gmxx_tx_jam_s cn30xx;
2310 struct cvmx_gmxx_tx_jam_s cn31xx;
2311 struct cvmx_gmxx_tx_jam_s cn38xx;
2312 struct cvmx_gmxx_tx_jam_s cn38xxp2;
2313 struct cvmx_gmxx_tx_jam_s cn50xx;
2314 struct cvmx_gmxx_tx_jam_s cn52xx;
2315 struct cvmx_gmxx_tx_jam_s cn52xxp1;
2316 struct cvmx_gmxx_tx_jam_s cn56xx;
2317 struct cvmx_gmxx_tx_jam_s cn56xxp1;
2318 struct cvmx_gmxx_tx_jam_s cn58xx;
2319 struct cvmx_gmxx_tx_jam_s cn58xxp1;
2320};
2321
2322union cvmx_gmxx_tx_lfsr {
2323 uint64_t u64;
2324 struct cvmx_gmxx_tx_lfsr_s {
2325 uint64_t reserved_16_63:48;
2326 uint64_t lfsr:16;
2327 } s;
2328 struct cvmx_gmxx_tx_lfsr_s cn30xx;
2329 struct cvmx_gmxx_tx_lfsr_s cn31xx;
2330 struct cvmx_gmxx_tx_lfsr_s cn38xx;
2331 struct cvmx_gmxx_tx_lfsr_s cn38xxp2;
2332 struct cvmx_gmxx_tx_lfsr_s cn50xx;
2333 struct cvmx_gmxx_tx_lfsr_s cn52xx;
2334 struct cvmx_gmxx_tx_lfsr_s cn52xxp1;
2335 struct cvmx_gmxx_tx_lfsr_s cn56xx;
2336 struct cvmx_gmxx_tx_lfsr_s cn56xxp1;
2337 struct cvmx_gmxx_tx_lfsr_s cn58xx;
2338 struct cvmx_gmxx_tx_lfsr_s cn58xxp1;
2339};
2340
2341union cvmx_gmxx_tx_ovr_bp {
2342 uint64_t u64;
2343 struct cvmx_gmxx_tx_ovr_bp_s {
2344 uint64_t reserved_48_63:16;
2345 uint64_t tx_prt_bp:16;
2346 uint64_t reserved_12_31:20;
2347 uint64_t en:4;
2348 uint64_t bp:4;
2349 uint64_t ign_full:4;
2350 } s;
2351 struct cvmx_gmxx_tx_ovr_bp_cn30xx {
2352 uint64_t reserved_11_63:53;
2353 uint64_t en:3;
2354 uint64_t reserved_7_7:1;
2355 uint64_t bp:3;
2356 uint64_t reserved_3_3:1;
2357 uint64_t ign_full:3;
2358 } cn30xx;
2359 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx;
2360 struct cvmx_gmxx_tx_ovr_bp_cn38xx {
2361 uint64_t reserved_12_63:52;
2362 uint64_t en:4;
2363 uint64_t bp:4;
2364 uint64_t ign_full:4;
2365 } cn38xx;
2366 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2;
2367 struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx;
2368 struct cvmx_gmxx_tx_ovr_bp_s cn52xx;
2369 struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1;
2370 struct cvmx_gmxx_tx_ovr_bp_s cn56xx;
2371 struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1;
2372 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx;
2373 struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1;
2374};
2375
2376union cvmx_gmxx_tx_pause_pkt_dmac {
2377 uint64_t u64;
2378 struct cvmx_gmxx_tx_pause_pkt_dmac_s {
2379 uint64_t reserved_48_63:16;
2380 uint64_t dmac:48;
2381 } s;
2382 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx;
2383 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx;
2384 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx;
2385 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2;
2386 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx;
2387 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx;
2388 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1;
2389 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx;
2390 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1;
2391 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx;
2392 struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1;
2393};
2394
2395union cvmx_gmxx_tx_pause_pkt_type {
2396 uint64_t u64;
2397 struct cvmx_gmxx_tx_pause_pkt_type_s {
2398 uint64_t reserved_16_63:48;
2399 uint64_t type:16;
2400 } s;
2401 struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx;
2402 struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx;
2403 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx;
2404 struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2;
2405 struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx;
2406 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx;
2407 struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1;
2408 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx;
2409 struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1;
2410 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx;
2411 struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1;
2412};
2413
2414union cvmx_gmxx_tx_prts {
2415 uint64_t u64;
2416 struct cvmx_gmxx_tx_prts_s {
2417 uint64_t reserved_5_63:59;
2418 uint64_t prts:5;
2419 } s;
2420 struct cvmx_gmxx_tx_prts_s cn30xx;
2421 struct cvmx_gmxx_tx_prts_s cn31xx;
2422 struct cvmx_gmxx_tx_prts_s cn38xx;
2423 struct cvmx_gmxx_tx_prts_s cn38xxp2;
2424 struct cvmx_gmxx_tx_prts_s cn50xx;
2425 struct cvmx_gmxx_tx_prts_s cn52xx;
2426 struct cvmx_gmxx_tx_prts_s cn52xxp1;
2427 struct cvmx_gmxx_tx_prts_s cn56xx;
2428 struct cvmx_gmxx_tx_prts_s cn56xxp1;
2429 struct cvmx_gmxx_tx_prts_s cn58xx;
2430 struct cvmx_gmxx_tx_prts_s cn58xxp1;
2431};
2432
2433union cvmx_gmxx_tx_spi_ctl {
2434 uint64_t u64;
2435 struct cvmx_gmxx_tx_spi_ctl_s {
2436 uint64_t reserved_2_63:62;
2437 uint64_t tpa_clr:1;
2438 uint64_t cont_pkt:1;
2439 } s;
2440 struct cvmx_gmxx_tx_spi_ctl_s cn38xx;
2441 struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2;
2442 struct cvmx_gmxx_tx_spi_ctl_s cn58xx;
2443 struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1;
2444};
2445
2446union cvmx_gmxx_tx_spi_drain {
2447 uint64_t u64;
2448 struct cvmx_gmxx_tx_spi_drain_s {
2449 uint64_t reserved_16_63:48;
2450 uint64_t drain:16;
2451 } s;
2452 struct cvmx_gmxx_tx_spi_drain_s cn38xx;
2453 struct cvmx_gmxx_tx_spi_drain_s cn58xx;
2454 struct cvmx_gmxx_tx_spi_drain_s cn58xxp1;
2455};
2456
2457union cvmx_gmxx_tx_spi_max {
2458 uint64_t u64;
2459 struct cvmx_gmxx_tx_spi_max_s {
2460 uint64_t reserved_23_63:41;
2461 uint64_t slice:7;
2462 uint64_t max2:8;
2463 uint64_t max1:8;
2464 } s;
2465 struct cvmx_gmxx_tx_spi_max_cn38xx {
2466 uint64_t reserved_16_63:48;
2467 uint64_t max2:8;
2468 uint64_t max1:8;
2469 } cn38xx;
2470 struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2;
2471 struct cvmx_gmxx_tx_spi_max_s cn58xx;
2472 struct cvmx_gmxx_tx_spi_max_s cn58xxp1;
2473};
2474
2475union cvmx_gmxx_tx_spi_roundx {
2476 uint64_t u64;
2477 struct cvmx_gmxx_tx_spi_roundx_s {
2478 uint64_t reserved_16_63:48;
2479 uint64_t round:16;
2480 } s;
2481 struct cvmx_gmxx_tx_spi_roundx_s cn58xx;
2482 struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1;
2483};
2484
2485union cvmx_gmxx_tx_spi_thresh {
2486 uint64_t u64;
2487 struct cvmx_gmxx_tx_spi_thresh_s {
2488 uint64_t reserved_6_63:58;
2489 uint64_t thresh:6;
2490 } s;
2491 struct cvmx_gmxx_tx_spi_thresh_s cn38xx;
2492 struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2;
2493 struct cvmx_gmxx_tx_spi_thresh_s cn58xx;
2494 struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1;
2495};
2496
2497union cvmx_gmxx_tx_xaui_ctl {
2498 uint64_t u64;
2499 struct cvmx_gmxx_tx_xaui_ctl_s {
2500 uint64_t reserved_11_63:53;
2501 uint64_t hg_pause_hgi:2;
2502 uint64_t hg_en:1;
2503 uint64_t reserved_7_7:1;
2504 uint64_t ls_byp:1;
2505 uint64_t ls:2;
2506 uint64_t reserved_2_3:2;
2507 uint64_t uni_en:1;
2508 uint64_t dic_en:1;
2509 } s;
2510 struct cvmx_gmxx_tx_xaui_ctl_s cn52xx;
2511 struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1;
2512 struct cvmx_gmxx_tx_xaui_ctl_s cn56xx;
2513 struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1;
2514};
2515
2516union cvmx_gmxx_xaui_ext_loopback {
2517 uint64_t u64;
2518 struct cvmx_gmxx_xaui_ext_loopback_s {
2519 uint64_t reserved_5_63:59;
2520 uint64_t en:1;
2521 uint64_t thresh:4;
2522 } s;
2523 struct cvmx_gmxx_xaui_ext_loopback_s cn52xx;
2524 struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1;
2525 struct cvmx_gmxx_xaui_ext_loopback_s cn56xx;
2526 struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1;
2527};
2528
2529#endif