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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_BARRIER_H
9#define __ASM_BARRIER_H
10
11#include <asm/addrspace.h>
12#include <asm/sync.h>
13
14static inline void __sync(void)
15{
16 asm volatile(__SYNC(full, always) ::: "memory");
17}
18
19static inline void rmb(void)
20{
21 asm volatile(__SYNC(rmb, always) ::: "memory");
22}
23#define rmb rmb
24
25static inline void wmb(void)
26{
27 asm volatile(__SYNC(wmb, always) ::: "memory");
28}
29#define wmb wmb
30
31#define fast_mb() __sync()
32
33#define __fast_iob() \
34 __asm__ __volatile__( \
35 ".set push\n\t" \
36 ".set noreorder\n\t" \
37 "lw $0,%0\n\t" \
38 "nop\n\t" \
39 ".set pop" \
40 : /* no output */ \
41 : "m" (*(int *)CKSEG1) \
42 : "memory")
43#ifdef CONFIG_CPU_CAVIUM_OCTEON
44# define fast_iob() do { } while (0)
45#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
46# ifdef CONFIG_SGI_IP28
47# define fast_iob() \
48 __asm__ __volatile__( \
49 ".set push\n\t" \
50 ".set noreorder\n\t" \
51 "lw $0,%0\n\t" \
52 "sync\n\t" \
53 "lw $0,%0\n\t" \
54 ".set pop" \
55 : /* no output */ \
56 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
57 : "memory")
58# else
59# define fast_iob() \
60 do { \
61 __sync(); \
62 __fast_iob(); \
63 } while (0)
64# endif
65#endif /* CONFIG_CPU_CAVIUM_OCTEON */
66
67#ifdef CONFIG_CPU_HAS_WB
68
69#include <asm/wbflush.h>
70
71#define mb() wbflush()
72#define iob() wbflush()
73
74#else /* !CONFIG_CPU_HAS_WB */
75
76#define mb() fast_mb()
77#define iob() fast_iob()
78
79#endif /* !CONFIG_CPU_HAS_WB */
80
81#if defined(CONFIG_WEAK_ORDERING)
82# define __smp_mb() __sync()
83# define __smp_rmb() rmb()
84# define __smp_wmb() wmb()
85#else
86# define __smp_mb() barrier()
87# define __smp_rmb() barrier()
88# define __smp_wmb() barrier()
89#endif
90
91/*
92 * When LL/SC does imply order, it must also be a compiler barrier to avoid the
93 * compiler from reordering where the CPU will not. When it does not imply
94 * order, the compiler is also free to reorder across the LL/SC loop and
95 * ordering will be done by smp_llsc_mb() and friends.
96 */
97#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
98# define __WEAK_LLSC_MB sync
99# define smp_llsc_mb() \
100 __asm__ __volatile__(__stringify(__WEAK_LLSC_MB) : : :"memory")
101# define __LLSC_CLOBBER
102#else
103# define __WEAK_LLSC_MB
104# define smp_llsc_mb() do { } while (0)
105# define __LLSC_CLOBBER "memory"
106#endif
107
108#ifdef CONFIG_CPU_CAVIUM_OCTEON
109#define smp_mb__before_llsc() smp_wmb()
110#define __smp_mb__before_llsc() __smp_wmb()
111/* Cause previous writes to become visible on all CPUs as soon as possible */
112#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
113 ".set arch=octeon\n\t" \
114 "syncw\n\t" \
115 ".set pop" : : : "memory")
116#else
117#define smp_mb__before_llsc() smp_llsc_mb()
118#define __smp_mb__before_llsc() smp_llsc_mb()
119#define nudge_writes() mb()
120#endif
121
122/*
123 * In the Loongson3 LL/SC workaround case, all of our LL/SC loops already have
124 * a completion barrier immediately preceding the LL instruction. Therefore we
125 * can skip emitting a barrier from __smp_mb__before_atomic().
126 */
127#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS
128# define __smp_mb__before_atomic()
129#else
130# define __smp_mb__before_atomic() __smp_mb__before_llsc()
131#endif
132
133#define __smp_mb__after_atomic() smp_llsc_mb()
134
135static inline void sync_ginv(void)
136{
137 asm volatile(__SYNC(ginv, always));
138}
139
140#include <asm-generic/barrier.h>
141
142#endif /* __ASM_BARRIER_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_BARRIER_H
9#define __ASM_BARRIER_H
10
11#include <asm/addrspace.h>
12
13/*
14 * read_barrier_depends - Flush all pending reads that subsequents reads
15 * depend on.
16 *
17 * No data-dependent reads from memory-like regions are ever reordered
18 * over this barrier. All reads preceding this primitive are guaranteed
19 * to access memory (but not necessarily other CPUs' caches) before any
20 * reads following this primitive that depend on the data return by
21 * any of the preceding reads. This primitive is much lighter weight than
22 * rmb() on most CPUs, and is never heavier weight than is
23 * rmb().
24 *
25 * These ordering constraints are respected by both the local CPU
26 * and the compiler.
27 *
28 * Ordering is not guaranteed by anything other than these primitives,
29 * not even by data dependencies. See the documentation for
30 * memory_barrier() for examples and URLs to more information.
31 *
32 * For example, the following code would force ordering (the initial
33 * value of "a" is zero, "b" is one, and "p" is "&a"):
34 *
35 * <programlisting>
36 * CPU 0 CPU 1
37 *
38 * b = 2;
39 * memory_barrier();
40 * p = &b; q = p;
41 * read_barrier_depends();
42 * d = *q;
43 * </programlisting>
44 *
45 * because the read of "*q" depends on the read of "p" and these
46 * two reads are separated by a read_barrier_depends(). However,
47 * the following code, with the same initial values for "a" and "b":
48 *
49 * <programlisting>
50 * CPU 0 CPU 1
51 *
52 * a = 2;
53 * memory_barrier();
54 * b = 3; y = b;
55 * read_barrier_depends();
56 * x = a;
57 * </programlisting>
58 *
59 * does not enforce ordering, since there is no data dependency between
60 * the read of "a" and the read of "b". Therefore, on some CPUs, such
61 * as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
62 * in cases like this where there are no data dependencies.
63 */
64
65#define read_barrier_depends() do { } while(0)
66#define smp_read_barrier_depends() do { } while(0)
67
68#ifdef CONFIG_CPU_HAS_SYNC
69#define __sync() \
70 __asm__ __volatile__( \
71 ".set push\n\t" \
72 ".set noreorder\n\t" \
73 ".set mips2\n\t" \
74 "sync\n\t" \
75 ".set pop" \
76 : /* no output */ \
77 : /* no input */ \
78 : "memory")
79#else
80#define __sync() do { } while(0)
81#endif
82
83#define __fast_iob() \
84 __asm__ __volatile__( \
85 ".set push\n\t" \
86 ".set noreorder\n\t" \
87 "lw $0,%0\n\t" \
88 "nop\n\t" \
89 ".set pop" \
90 : /* no output */ \
91 : "m" (*(int *)CKSEG1) \
92 : "memory")
93#ifdef CONFIG_CPU_CAVIUM_OCTEON
94# define OCTEON_SYNCW_STR ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
95# define __syncw() __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
96
97# define fast_wmb() __syncw()
98# define fast_rmb() barrier()
99# define fast_mb() __sync()
100# define fast_iob() do { } while (0)
101#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
102# define fast_wmb() __sync()
103# define fast_rmb() __sync()
104# define fast_mb() __sync()
105# ifdef CONFIG_SGI_IP28
106# define fast_iob() \
107 __asm__ __volatile__( \
108 ".set push\n\t" \
109 ".set noreorder\n\t" \
110 "lw $0,%0\n\t" \
111 "sync\n\t" \
112 "lw $0,%0\n\t" \
113 ".set pop" \
114 : /* no output */ \
115 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
116 : "memory")
117# else
118# define fast_iob() \
119 do { \
120 __sync(); \
121 __fast_iob(); \
122 } while (0)
123# endif
124#endif /* CONFIG_CPU_CAVIUM_OCTEON */
125
126#ifdef CONFIG_CPU_HAS_WB
127
128#include <asm/wbflush.h>
129
130#define wmb() fast_wmb()
131#define rmb() fast_rmb()
132#define mb() wbflush()
133#define iob() wbflush()
134
135#else /* !CONFIG_CPU_HAS_WB */
136
137#define wmb() fast_wmb()
138#define rmb() fast_rmb()
139#define mb() fast_mb()
140#define iob() fast_iob()
141
142#endif /* !CONFIG_CPU_HAS_WB */
143
144#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
145# ifdef CONFIG_CPU_CAVIUM_OCTEON
146# define smp_mb() __sync()
147# define smp_rmb() barrier()
148# define smp_wmb() __syncw()
149# else
150# define smp_mb() __asm__ __volatile__("sync" : : :"memory")
151# define smp_rmb() __asm__ __volatile__("sync" : : :"memory")
152# define smp_wmb() __asm__ __volatile__("sync" : : :"memory")
153# endif
154#else
155#define smp_mb() barrier()
156#define smp_rmb() barrier()
157#define smp_wmb() barrier()
158#endif
159
160#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
161#define __WEAK_LLSC_MB " sync \n"
162#else
163#define __WEAK_LLSC_MB " \n"
164#endif
165
166#define set_mb(var, value) \
167 do { var = value; smp_mb(); } while (0)
168
169#define smp_llsc_mb() __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
170
171#ifdef CONFIG_CPU_CAVIUM_OCTEON
172#define smp_mb__before_llsc() smp_wmb()
173/* Cause previous writes to become visible on all CPUs as soon as possible */
174#define nudge_writes() __asm__ __volatile__(".set push\n\t" \
175 ".set arch=octeon\n\t" \
176 "syncw\n\t" \
177 ".set pop" : : : "memory")
178#else
179#define smp_mb__before_llsc() smp_llsc_mb()
180#define nudge_writes() mb()
181#endif
182
183#endif /* __ASM_BARRIER_H */