1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
  4 */
  5
  6/*
  7 * Device tree for AXC003 CPU card: HS38x UP configuration
  8 */
  9
 10/include/ "skeleton_hs.dtsi"
 11
 12/ {
 13	compatible = "snps,arc";
 14	#address-cells = <2>;
 15	#size-cells = <2>;
 16
 17	cpu_card {
 18		compatible = "simple-bus";
 19		#address-cells = <1>;
 20		#size-cells = <1>;
 21
 22		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
 23
 24		input_clk: input-clk {
 25			#clock-cells = <0>;
 26			compatible = "fixed-clock";
 27			clock-frequency = <33333333>;
 28		};
 29
 30		core_clk: core-clk@80 {
 31			compatible = "snps,axs10x-arc-pll-clock";
 32			reg = <0x80 0x10>, <0x100 0x10>;
 33			#clock-cells = <0>;
 34			clocks = <&input_clk>;
 35
 36			/*
 37			 * Set initial core pll output frequency to 90MHz.
 38			 * It will be applied at the core pll driver probing
 39			 * on early boot.
 40			 */
 41			assigned-clocks = <&core_clk>;
 42			assigned-clock-rates = <90000000>;
 43		};
 44
 45		core_intc: archs-intc@cpu {
 46			compatible = "snps,archs-intc";
 47			interrupt-controller;
 48			#interrupt-cells = <1>;
 49		};
 50
 51		/*
 52		 * this GPIO block ORs all interrupts on CPU card (creg,..)
 53		 * to uplink only 1 IRQ to ARC core intc
 54		 */
 55		dw-apb-gpio@2000 {
 56			compatible = "snps,dw-apb-gpio";
 57			reg = < 0x2000 0x80 >;
 58			#address-cells = <1>;
 59			#size-cells = <0>;
 60
 61			ictl_intc: gpio-controller@0 {
 62				compatible = "snps,dw-apb-gpio-port";
 63				gpio-controller;
 64				#gpio-cells = <2>;
 65				snps,nr-gpios = <30>;
 66				reg = <0>;
 67				interrupt-controller;
 68				#interrupt-cells = <2>;
 69				interrupt-parent = <&core_intc>;
 70				interrupts = <25>;
 71			};
 72		};
 73
 74		debug_uart: dw-apb-uart@5000 {
 75			compatible = "snps,dw-apb-uart";
 76			reg = <0x5000 0x100>;
 77			clock-frequency = <33333000>;
 78			interrupt-parent = <&ictl_intc>;
 79			interrupts = <2 4>;
 80			baud = <115200>;
 81			reg-shift = <2>;
 82			reg-io-width = <4>;
 83		};
 84
 85		arcpct0: pct {
 86			compatible = "snps,archs-pct";
 87			#interrupt-cells = <1>;
 88			interrupt-parent = <&core_intc>;
 89			interrupts = <20>;
 90		};
 91	};
 92
 93	/*
 94	 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
 95	 * it via overlay because peripherals defined in axs10x_mb.dtsi are
 96	 * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
 97	 * only AXS103 board has HW-coherent DMA peripherals)
 98	 * We don't need to mark pgu@17000 as dma-coherent because it uses
 99	 * external DMA buffer located outside of IOC aperture.
100	 */
101	axs10x_mb {
102		ethernet@18000 {
103			dma-coherent;
104		};
105
106		usb@40000 {
107			dma-coherent;
108		};
109
110		usb@60000 {
111			dma-coherent;
112		};
113
114		mmc@15000 {
115			dma-coherent;
116		};
117	};
118
119	/*
120	 * The DW APB ICTL intc on MB is connected to CPU intc via a
121	 * DT "invisible" DW APB GPIO block, configured to simply pass thru
122	 * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
123	 *
124	 * So here we mimic a direct connection betwen them, ignoring the
125	 * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
126	 * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
127	 *
128	 * This intc actually resides on MB, but we move it here to
129	 * avoid duplicating the MB dtsi file given that IRQ from
130	 * this intc to cpu intc are different for axs101 and axs103
131	 */
132	mb_intc: interrupt-controller@e0012000 {
133		#interrupt-cells = <1>;
134		compatible = "snps,dw-apb-ictl";
135		reg = < 0x0 0xe0012000 0x0 0x200 >;
136		interrupt-controller;
137		interrupt-parent = <&core_intc>;
138		interrupts = < 24 >;
139	};
140
141	memory {
142		device_type = "memory";
143		/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
144		reg = <0x0 0x80000000 0x0 0x20000000	/* 512 MiB low mem */
145		       0x1 0xc0000000 0x0 0x40000000>;	/* 1 GiB highmem */
146	};
147
148	reserved-memory {
149		#address-cells = <2>;
150		#size-cells = <2>;
151		ranges;
152		/*
153		 * Move frame buffer out of IOC aperture (0x8z-0xaz).
154		 */
155		frame_buffer: frame_buffer@be000000 {
156			compatible = "shared-dma-pool";
157			reg = <0x0 0xbe000000 0x0 0x2000000>;
158			no-map;
159		};
160	};
161};