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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * omap_wdt.c
4 *
5 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
6 *
7 * Author: MontaVista Software, Inc.
8 * <gdavis@mvista.com> or <source@mvista.com>
9 *
10 * 2003 (c) MontaVista Software, Inc.
11 *
12 * History:
13 *
14 * 20030527: George G. Davis <gdavis@mvista.com>
15 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
16 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
17 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
18 *
19 * Copyright (c) 2004 Texas Instruments.
20 * 1. Modified to support OMAP1610 32-KHz watchdog timer
21 * 2. Ported to 2.6 kernel
22 *
23 * Copyright (c) 2005 David Brownell
24 * Use the driver model and standard identifiers; handle bigger timeouts.
25 */
26
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28
29#include <linux/module.h>
30#include <linux/mod_devicetable.h>
31#include <linux/types.h>
32#include <linux/kernel.h>
33#include <linux/mm.h>
34#include <linux/watchdog.h>
35#include <linux/reboot.h>
36#include <linux/err.h>
37#include <linux/platform_device.h>
38#include <linux/moduleparam.h>
39#include <linux/io.h>
40#include <linux/slab.h>
41#include <linux/pm_runtime.h>
42#include <linux/platform_data/omap-wd-timer.h>
43
44#include "omap_wdt.h"
45
46static bool nowayout = WATCHDOG_NOWAYOUT;
47module_param(nowayout, bool, 0);
48MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
49 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
50
51static unsigned timer_margin;
52module_param(timer_margin, uint, 0);
53MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
54
55#define to_omap_wdt_dev(_wdog) container_of(_wdog, struct omap_wdt_dev, wdog)
56
57static bool early_enable;
58module_param(early_enable, bool, 0);
59MODULE_PARM_DESC(early_enable,
60 "Watchdog is started on module insertion (default=0)");
61
62struct omap_wdt_dev {
63 struct watchdog_device wdog;
64 void __iomem *base; /* physical */
65 struct device *dev;
66 bool omap_wdt_users;
67 int wdt_trgr_pattern;
68 struct mutex lock; /* to avoid races with PM */
69};
70
71static void omap_wdt_reload(struct omap_wdt_dev *wdev)
72{
73 void __iomem *base = wdev->base;
74
75 /* wait for posted write to complete */
76 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
77 cpu_relax();
78
79 wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
80 writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
81
82 /* wait for posted write to complete */
83 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
84 cpu_relax();
85 /* reloaded WCRR from WLDR */
86}
87
88static void omap_wdt_enable(struct omap_wdt_dev *wdev)
89{
90 void __iomem *base = wdev->base;
91
92 /* Sequence to enable the watchdog */
93 writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
94 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
95 cpu_relax();
96
97 writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
98 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
99 cpu_relax();
100}
101
102static void omap_wdt_disable(struct omap_wdt_dev *wdev)
103{
104 void __iomem *base = wdev->base;
105
106 /* sequence required to disable watchdog */
107 writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
108 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
109 cpu_relax();
110
111 writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
112 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
113 cpu_relax();
114}
115
116static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
117 unsigned int timeout)
118{
119 u32 pre_margin = GET_WLDR_VAL(timeout);
120 void __iomem *base = wdev->base;
121
122 /* just count up at 32 KHz */
123 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
124 cpu_relax();
125
126 writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
127 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
128 cpu_relax();
129}
130
131static int omap_wdt_start(struct watchdog_device *wdog)
132{
133 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
134 void __iomem *base = wdev->base;
135
136 mutex_lock(&wdev->lock);
137
138 wdev->omap_wdt_users = true;
139
140 pm_runtime_get_sync(wdev->dev);
141
142 /*
143 * Make sure the watchdog is disabled. This is unfortunately required
144 * because writing to various registers with the watchdog running has no
145 * effect.
146 */
147 omap_wdt_disable(wdev);
148
149 /* initialize prescaler */
150 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
151 cpu_relax();
152
153 writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
154 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
155 cpu_relax();
156
157 omap_wdt_set_timer(wdev, wdog->timeout);
158 omap_wdt_reload(wdev); /* trigger loading of new timeout value */
159 omap_wdt_enable(wdev);
160
161 mutex_unlock(&wdev->lock);
162
163 return 0;
164}
165
166static int omap_wdt_stop(struct watchdog_device *wdog)
167{
168 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
169
170 mutex_lock(&wdev->lock);
171 omap_wdt_disable(wdev);
172 pm_runtime_put_sync(wdev->dev);
173 wdev->omap_wdt_users = false;
174 mutex_unlock(&wdev->lock);
175 return 0;
176}
177
178static int omap_wdt_ping(struct watchdog_device *wdog)
179{
180 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
181
182 mutex_lock(&wdev->lock);
183 omap_wdt_reload(wdev);
184 mutex_unlock(&wdev->lock);
185
186 return 0;
187}
188
189static int omap_wdt_set_timeout(struct watchdog_device *wdog,
190 unsigned int timeout)
191{
192 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
193
194 mutex_lock(&wdev->lock);
195 omap_wdt_disable(wdev);
196 omap_wdt_set_timer(wdev, timeout);
197 omap_wdt_enable(wdev);
198 omap_wdt_reload(wdev);
199 wdog->timeout = timeout;
200 mutex_unlock(&wdev->lock);
201
202 return 0;
203}
204
205static unsigned int omap_wdt_get_timeleft(struct watchdog_device *wdog)
206{
207 struct omap_wdt_dev *wdev = to_omap_wdt_dev(wdog);
208 void __iomem *base = wdev->base;
209 u32 value;
210
211 value = readl_relaxed(base + OMAP_WATCHDOG_CRR);
212 return GET_WCCR_SECS(value);
213}
214
215static const struct watchdog_info omap_wdt_info = {
216 .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
217 .identity = "OMAP Watchdog",
218};
219
220static const struct watchdog_ops omap_wdt_ops = {
221 .owner = THIS_MODULE,
222 .start = omap_wdt_start,
223 .stop = omap_wdt_stop,
224 .ping = omap_wdt_ping,
225 .set_timeout = omap_wdt_set_timeout,
226 .get_timeleft = omap_wdt_get_timeleft,
227};
228
229static int omap_wdt_probe(struct platform_device *pdev)
230{
231 struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
232 struct omap_wdt_dev *wdev;
233 int ret;
234
235 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
236 if (!wdev)
237 return -ENOMEM;
238
239 wdev->omap_wdt_users = false;
240 wdev->dev = &pdev->dev;
241 wdev->wdt_trgr_pattern = 0x1234;
242 mutex_init(&wdev->lock);
243
244 /* reserve static register mappings */
245 wdev->base = devm_platform_ioremap_resource(pdev, 0);
246 if (IS_ERR(wdev->base))
247 return PTR_ERR(wdev->base);
248
249 wdev->wdog.info = &omap_wdt_info;
250 wdev->wdog.ops = &omap_wdt_ops;
251 wdev->wdog.min_timeout = TIMER_MARGIN_MIN;
252 wdev->wdog.max_timeout = TIMER_MARGIN_MAX;
253 wdev->wdog.timeout = TIMER_MARGIN_DEFAULT;
254 wdev->wdog.parent = &pdev->dev;
255
256 watchdog_init_timeout(&wdev->wdog, timer_margin, &pdev->dev);
257
258 watchdog_set_nowayout(&wdev->wdog, nowayout);
259
260 platform_set_drvdata(pdev, wdev);
261
262 pm_runtime_enable(wdev->dev);
263 pm_runtime_get_sync(wdev->dev);
264
265 if (pdata && pdata->read_reset_sources) {
266 u32 rs = pdata->read_reset_sources();
267 if (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT))
268 wdev->wdog.bootstatus = WDIOF_CARDRESET;
269 }
270
271 if (early_enable) {
272 omap_wdt_start(&wdev->wdog);
273 set_bit(WDOG_HW_RUNNING, &wdev->wdog.status);
274 } else {
275 omap_wdt_disable(wdev);
276 }
277
278 ret = watchdog_register_device(&wdev->wdog);
279 if (ret) {
280 pm_runtime_put(wdev->dev);
281 pm_runtime_disable(wdev->dev);
282 return ret;
283 }
284
285 pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
286 readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
287 wdev->wdog.timeout);
288
289 if (early_enable)
290 omap_wdt_start(&wdev->wdog);
291
292 pm_runtime_put(wdev->dev);
293
294 return 0;
295}
296
297static void omap_wdt_shutdown(struct platform_device *pdev)
298{
299 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
300
301 mutex_lock(&wdev->lock);
302 if (wdev->omap_wdt_users) {
303 omap_wdt_disable(wdev);
304 pm_runtime_put_sync(wdev->dev);
305 }
306 mutex_unlock(&wdev->lock);
307}
308
309static void omap_wdt_remove(struct platform_device *pdev)
310{
311 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
312
313 pm_runtime_disable(wdev->dev);
314 watchdog_unregister_device(&wdev->wdog);
315}
316
317/* REVISIT ... not clear this is the best way to handle system suspend; and
318 * it's very inappropriate for selective device suspend (e.g. suspending this
319 * through sysfs rather than by stopping the watchdog daemon). Also, this
320 * may not play well enough with NOWAYOUT...
321 */
322
323static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
324{
325 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
326
327 mutex_lock(&wdev->lock);
328 if (wdev->omap_wdt_users) {
329 omap_wdt_disable(wdev);
330 pm_runtime_put_sync(wdev->dev);
331 }
332 mutex_unlock(&wdev->lock);
333
334 return 0;
335}
336
337static int omap_wdt_resume(struct platform_device *pdev)
338{
339 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
340
341 mutex_lock(&wdev->lock);
342 if (wdev->omap_wdt_users) {
343 pm_runtime_get_sync(wdev->dev);
344 omap_wdt_enable(wdev);
345 omap_wdt_reload(wdev);
346 }
347 mutex_unlock(&wdev->lock);
348
349 return 0;
350}
351
352static const struct of_device_id omap_wdt_of_match[] = {
353 { .compatible = "ti,omap3-wdt", },
354 {},
355};
356MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
357
358static struct platform_driver omap_wdt_driver = {
359 .probe = omap_wdt_probe,
360 .remove_new = omap_wdt_remove,
361 .shutdown = omap_wdt_shutdown,
362 .suspend = pm_ptr(omap_wdt_suspend),
363 .resume = pm_ptr(omap_wdt_resume),
364 .driver = {
365 .name = "omap_wdt",
366 .of_match_table = omap_wdt_of_match,
367 },
368};
369
370module_platform_driver(omap_wdt_driver);
371
372MODULE_AUTHOR("George G. Davis");
373MODULE_LICENSE("GPL");
374MODULE_ALIAS("platform:omap_wdt");
1/*
2 * omap_wdt.c
3 *
4 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
5 *
6 * Author: MontaVista Software, Inc.
7 * <gdavis@mvista.com> or <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * History:
15 *
16 * 20030527: George G. Davis <gdavis@mvista.com>
17 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
18 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
19 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
20 *
21 * Copyright (c) 2004 Texas Instruments.
22 * 1. Modified to support OMAP1610 32-KHz watchdog timer
23 * 2. Ported to 2.6 kernel
24 *
25 * Copyright (c) 2005 David Brownell
26 * Use the driver model and standard identifiers; handle bigger timeouts.
27 */
28
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/kernel.h>
34#include <linux/fs.h>
35#include <linux/mm.h>
36#include <linux/miscdevice.h>
37#include <linux/watchdog.h>
38#include <linux/reboot.h>
39#include <linux/init.h>
40#include <linux/err.h>
41#include <linux/platform_device.h>
42#include <linux/moduleparam.h>
43#include <linux/bitops.h>
44#include <linux/io.h>
45#include <linux/uaccess.h>
46#include <linux/slab.h>
47#include <linux/pm_runtime.h>
48#include <mach/hardware.h>
49#include <plat/prcm.h>
50
51#include "omap_wdt.h"
52
53static struct platform_device *omap_wdt_dev;
54
55static unsigned timer_margin;
56module_param(timer_margin, uint, 0);
57MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
58
59static unsigned int wdt_trgr_pattern = 0x1234;
60static DEFINE_SPINLOCK(wdt_lock);
61
62struct omap_wdt_dev {
63 void __iomem *base; /* physical */
64 struct device *dev;
65 int omap_wdt_users;
66 struct resource *mem;
67 struct miscdevice omap_wdt_miscdev;
68};
69
70static void omap_wdt_ping(struct omap_wdt_dev *wdev)
71{
72 void __iomem *base = wdev->base;
73
74 /* wait for posted write to complete */
75 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
76 cpu_relax();
77
78 wdt_trgr_pattern = ~wdt_trgr_pattern;
79 __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
80
81 /* wait for posted write to complete */
82 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
83 cpu_relax();
84 /* reloaded WCRR from WLDR */
85}
86
87static void omap_wdt_enable(struct omap_wdt_dev *wdev)
88{
89 void __iomem *base = wdev->base;
90
91 /* Sequence to enable the watchdog */
92 __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
93 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
94 cpu_relax();
95
96 __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
97 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
98 cpu_relax();
99}
100
101static void omap_wdt_disable(struct omap_wdt_dev *wdev)
102{
103 void __iomem *base = wdev->base;
104
105 /* sequence required to disable watchdog */
106 __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
107 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
108 cpu_relax();
109
110 __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
111 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
112 cpu_relax();
113}
114
115static void omap_wdt_adjust_timeout(unsigned new_timeout)
116{
117 if (new_timeout < TIMER_MARGIN_MIN)
118 new_timeout = TIMER_MARGIN_DEFAULT;
119 if (new_timeout > TIMER_MARGIN_MAX)
120 new_timeout = TIMER_MARGIN_MAX;
121 timer_margin = new_timeout;
122}
123
124static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
125{
126 u32 pre_margin = GET_WLDR_VAL(timer_margin);
127 void __iomem *base = wdev->base;
128
129 pm_runtime_get_sync(wdev->dev);
130
131 /* just count up at 32 KHz */
132 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
133 cpu_relax();
134
135 __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
136 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
137 cpu_relax();
138
139 pm_runtime_put_sync(wdev->dev);
140}
141
142/*
143 * Allow only one task to hold it open
144 */
145static int omap_wdt_open(struct inode *inode, struct file *file)
146{
147 struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
148 void __iomem *base = wdev->base;
149
150 if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
151 return -EBUSY;
152
153 pm_runtime_get_sync(wdev->dev);
154
155 /* initialize prescaler */
156 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
157 cpu_relax();
158
159 __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
160 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
161 cpu_relax();
162
163 file->private_data = (void *) wdev;
164
165 omap_wdt_set_timeout(wdev);
166 omap_wdt_ping(wdev); /* trigger loading of new timeout value */
167 omap_wdt_enable(wdev);
168
169 pm_runtime_put_sync(wdev->dev);
170
171 return nonseekable_open(inode, file);
172}
173
174static int omap_wdt_release(struct inode *inode, struct file *file)
175{
176 struct omap_wdt_dev *wdev = file->private_data;
177
178 /*
179 * Shut off the timer unless NOWAYOUT is defined.
180 */
181#ifndef CONFIG_WATCHDOG_NOWAYOUT
182 pm_runtime_get_sync(wdev->dev);
183
184 omap_wdt_disable(wdev);
185
186 pm_runtime_put_sync(wdev->dev);
187#else
188 pr_crit("Unexpected close, not stopping!\n");
189#endif
190 wdev->omap_wdt_users = 0;
191
192 return 0;
193}
194
195static ssize_t omap_wdt_write(struct file *file, const char __user *data,
196 size_t len, loff_t *ppos)
197{
198 struct omap_wdt_dev *wdev = file->private_data;
199
200 /* Refresh LOAD_TIME. */
201 if (len) {
202 pm_runtime_get_sync(wdev->dev);
203 spin_lock(&wdt_lock);
204 omap_wdt_ping(wdev);
205 spin_unlock(&wdt_lock);
206 pm_runtime_put_sync(wdev->dev);
207 }
208 return len;
209}
210
211static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
212 unsigned long arg)
213{
214 struct omap_wdt_dev *wdev;
215 int new_margin;
216 static const struct watchdog_info ident = {
217 .identity = "OMAP Watchdog",
218 .options = WDIOF_SETTIMEOUT,
219 .firmware_version = 0,
220 };
221
222 wdev = file->private_data;
223
224 switch (cmd) {
225 case WDIOC_GETSUPPORT:
226 return copy_to_user((struct watchdog_info __user *)arg, &ident,
227 sizeof(ident));
228 case WDIOC_GETSTATUS:
229 return put_user(0, (int __user *)arg);
230 case WDIOC_GETBOOTSTATUS:
231 if (cpu_is_omap16xx())
232 return put_user(__raw_readw(ARM_SYSST),
233 (int __user *)arg);
234 if (cpu_is_omap24xx())
235 return put_user(omap_prcm_get_reset_sources(),
236 (int __user *)arg);
237 return put_user(0, (int __user *)arg);
238 case WDIOC_KEEPALIVE:
239 pm_runtime_get_sync(wdev->dev);
240 spin_lock(&wdt_lock);
241 omap_wdt_ping(wdev);
242 spin_unlock(&wdt_lock);
243 pm_runtime_put_sync(wdev->dev);
244 return 0;
245 case WDIOC_SETTIMEOUT:
246 if (get_user(new_margin, (int __user *)arg))
247 return -EFAULT;
248 omap_wdt_adjust_timeout(new_margin);
249
250 pm_runtime_get_sync(wdev->dev);
251 spin_lock(&wdt_lock);
252 omap_wdt_disable(wdev);
253 omap_wdt_set_timeout(wdev);
254 omap_wdt_enable(wdev);
255
256 omap_wdt_ping(wdev);
257 spin_unlock(&wdt_lock);
258 pm_runtime_put_sync(wdev->dev);
259 /* Fall */
260 case WDIOC_GETTIMEOUT:
261 return put_user(timer_margin, (int __user *)arg);
262 default:
263 return -ENOTTY;
264 }
265}
266
267static const struct file_operations omap_wdt_fops = {
268 .owner = THIS_MODULE,
269 .write = omap_wdt_write,
270 .unlocked_ioctl = omap_wdt_ioctl,
271 .open = omap_wdt_open,
272 .release = omap_wdt_release,
273 .llseek = no_llseek,
274};
275
276static int __devinit omap_wdt_probe(struct platform_device *pdev)
277{
278 struct resource *res, *mem;
279 struct omap_wdt_dev *wdev;
280 int ret;
281
282 /* reserve static register mappings */
283 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
284 if (!res) {
285 ret = -ENOENT;
286 goto err_get_resource;
287 }
288
289 if (omap_wdt_dev) {
290 ret = -EBUSY;
291 goto err_busy;
292 }
293
294 mem = request_mem_region(res->start, resource_size(res), pdev->name);
295 if (!mem) {
296 ret = -EBUSY;
297 goto err_busy;
298 }
299
300 wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
301 if (!wdev) {
302 ret = -ENOMEM;
303 goto err_kzalloc;
304 }
305
306 wdev->omap_wdt_users = 0;
307 wdev->mem = mem;
308 wdev->dev = &pdev->dev;
309
310 wdev->base = ioremap(res->start, resource_size(res));
311 if (!wdev->base) {
312 ret = -ENOMEM;
313 goto err_ioremap;
314 }
315
316 platform_set_drvdata(pdev, wdev);
317
318 pm_runtime_enable(wdev->dev);
319 pm_runtime_get_sync(wdev->dev);
320
321 omap_wdt_disable(wdev);
322 omap_wdt_adjust_timeout(timer_margin);
323
324 wdev->omap_wdt_miscdev.parent = &pdev->dev;
325 wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
326 wdev->omap_wdt_miscdev.name = "watchdog";
327 wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
328
329 ret = misc_register(&(wdev->omap_wdt_miscdev));
330 if (ret)
331 goto err_misc;
332
333 pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
334 __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
335 timer_margin);
336
337 pm_runtime_put_sync(wdev->dev);
338
339 omap_wdt_dev = pdev;
340
341 return 0;
342
343err_misc:
344 pm_runtime_disable(wdev->dev);
345 platform_set_drvdata(pdev, NULL);
346 iounmap(wdev->base);
347
348err_ioremap:
349 wdev->base = NULL;
350 kfree(wdev);
351
352err_kzalloc:
353 release_mem_region(res->start, resource_size(res));
354
355err_busy:
356err_get_resource:
357
358 return ret;
359}
360
361static void omap_wdt_shutdown(struct platform_device *pdev)
362{
363 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
364
365 if (wdev->omap_wdt_users) {
366 pm_runtime_get_sync(wdev->dev);
367 omap_wdt_disable(wdev);
368 pm_runtime_put_sync(wdev->dev);
369 }
370}
371
372static int __devexit omap_wdt_remove(struct platform_device *pdev)
373{
374 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
375 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
376
377 pm_runtime_disable(wdev->dev);
378 if (!res)
379 return -ENOENT;
380
381 misc_deregister(&(wdev->omap_wdt_miscdev));
382 release_mem_region(res->start, resource_size(res));
383 platform_set_drvdata(pdev, NULL);
384
385 iounmap(wdev->base);
386
387 kfree(wdev);
388 omap_wdt_dev = NULL;
389
390 return 0;
391}
392
393#ifdef CONFIG_PM
394
395/* REVISIT ... not clear this is the best way to handle system suspend; and
396 * it's very inappropriate for selective device suspend (e.g. suspending this
397 * through sysfs rather than by stopping the watchdog daemon). Also, this
398 * may not play well enough with NOWAYOUT...
399 */
400
401static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
402{
403 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
404
405 if (wdev->omap_wdt_users) {
406 pm_runtime_get_sync(wdev->dev);
407 omap_wdt_disable(wdev);
408 pm_runtime_put_sync(wdev->dev);
409 }
410
411 return 0;
412}
413
414static int omap_wdt_resume(struct platform_device *pdev)
415{
416 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
417
418 if (wdev->omap_wdt_users) {
419 pm_runtime_get_sync(wdev->dev);
420 omap_wdt_enable(wdev);
421 omap_wdt_ping(wdev);
422 pm_runtime_put_sync(wdev->dev);
423 }
424
425 return 0;
426}
427
428#else
429#define omap_wdt_suspend NULL
430#define omap_wdt_resume NULL
431#endif
432
433static struct platform_driver omap_wdt_driver = {
434 .probe = omap_wdt_probe,
435 .remove = __devexit_p(omap_wdt_remove),
436 .shutdown = omap_wdt_shutdown,
437 .suspend = omap_wdt_suspend,
438 .resume = omap_wdt_resume,
439 .driver = {
440 .owner = THIS_MODULE,
441 .name = "omap_wdt",
442 },
443};
444
445module_platform_driver(omap_wdt_driver);
446
447MODULE_AUTHOR("George G. Davis");
448MODULE_LICENSE("GPL");
449MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
450MODULE_ALIAS("platform:omap_wdt");