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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Enhanced Host Controller Interface (EHCI) driver for USB.
4 *
5 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 *
7 * Copyright (c) 2000-2004 by David Brownell
8 */
9
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/dmapool.h>
13#include <linux/kernel.h>
14#include <linux/delay.h>
15#include <linux/ioport.h>
16#include <linux/sched.h>
17#include <linux/vmalloc.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/hrtimer.h>
21#include <linux/list.h>
22#include <linux/interrupt.h>
23#include <linux/usb.h>
24#include <linux/usb/hcd.h>
25#include <linux/usb/otg.h>
26#include <linux/moduleparam.h>
27#include <linux/dma-mapping.h>
28#include <linux/debugfs.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31
32#include <asm/byteorder.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/unaligned.h>
36
37#if defined(CONFIG_PPC_PS3)
38#include <asm/firmware.h>
39#endif
40
41/*-------------------------------------------------------------------------*/
42
43/*
44 * EHCI hc_driver implementation ... experimental, incomplete.
45 * Based on the final 1.0 register interface specification.
46 *
47 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
48 * First was PCMCIA, like ISA; then CardBus, which is PCI.
49 * Next comes "CardBay", using USB 2.0 signals.
50 *
51 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
52 * Special thanks to Intel and VIA for providing host controllers to
53 * test this driver on, and Cypress (including In-System Design) for
54 * providing early devices for those host controllers to talk to!
55 */
56
57#define DRIVER_AUTHOR "David Brownell"
58#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
59
60static const char hcd_name [] = "ehci_hcd";
61
62
63#undef EHCI_URB_TRACE
64
65/* magic numbers that can affect system performance */
66#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
67#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
68#define EHCI_TUNE_RL_TT 0
69#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
70#define EHCI_TUNE_MULT_TT 1
71/*
72 * Some drivers think it's safe to schedule isochronous transfers more than
73 * 256 ms into the future (partly as a result of an old bug in the scheduling
74 * code). In an attempt to avoid trouble, we will use a minimum scheduling
75 * length of 512 frames instead of 256.
76 */
77#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
78
79/* Initial IRQ latency: faster than hw default */
80static int log2_irq_thresh; // 0 to 6
81module_param (log2_irq_thresh, int, S_IRUGO);
82MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
83
84/* initial park setting: slower than hw default */
85static unsigned park;
86module_param (park, uint, S_IRUGO);
87MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
88
89/* for flakey hardware, ignore overcurrent indicators */
90static bool ignore_oc;
91module_param (ignore_oc, bool, S_IRUGO);
92MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
93
94#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
95
96/*-------------------------------------------------------------------------*/
97
98#include "ehci.h"
99#include "pci-quirks.h"
100
101static void compute_tt_budget(u8 budget_table[EHCI_BANDWIDTH_SIZE],
102 struct ehci_tt *tt);
103
104/*
105 * The MosChip MCS9990 controller updates its microframe counter
106 * a little before the frame counter, and occasionally we will read
107 * the invalid intermediate value. Avoid problems by checking the
108 * microframe number (the low-order 3 bits); if they are 0 then
109 * re-read the register to get the correct value.
110 */
111static unsigned ehci_moschip_read_frame_index(struct ehci_hcd *ehci)
112{
113 unsigned uf;
114
115 uf = ehci_readl(ehci, &ehci->regs->frame_index);
116 if (unlikely((uf & 7) == 0))
117 uf = ehci_readl(ehci, &ehci->regs->frame_index);
118 return uf;
119}
120
121static inline unsigned ehci_read_frame_index(struct ehci_hcd *ehci)
122{
123 if (ehci->frame_index_bug)
124 return ehci_moschip_read_frame_index(ehci);
125 return ehci_readl(ehci, &ehci->regs->frame_index);
126}
127
128#include "ehci-dbg.c"
129
130/*-------------------------------------------------------------------------*/
131
132/*
133 * ehci_handshake - spin reading hc until handshake completes or fails
134 * @ptr: address of hc register to be read
135 * @mask: bits to look at in result of read
136 * @done: value of those bits when handshake succeeds
137 * @usec: timeout in microseconds
138 *
139 * Returns negative errno, or zero on success
140 *
141 * Success happens when the "mask" bits have the specified value (hardware
142 * handshake done). There are two failure modes: "usec" have passed (major
143 * hardware flakeout), or the register reads as all-ones (hardware removed).
144 *
145 * That last failure should_only happen in cases like physical cardbus eject
146 * before driver shutdown. But it also seems to be caused by bugs in cardbus
147 * bridge shutdown: shutting down the bridge before the devices using it.
148 */
149int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
150 u32 mask, u32 done, int usec)
151{
152 u32 result;
153
154 do {
155 result = ehci_readl(ehci, ptr);
156 if (result == ~(u32)0) /* card removed */
157 return -ENODEV;
158 result &= mask;
159 if (result == done)
160 return 0;
161 udelay (1);
162 usec--;
163 } while (usec > 0);
164 return -ETIMEDOUT;
165}
166EXPORT_SYMBOL_GPL(ehci_handshake);
167
168/* check TDI/ARC silicon is in host mode */
169static int tdi_in_host_mode (struct ehci_hcd *ehci)
170{
171 u32 tmp;
172
173 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
174 return (tmp & 3) == USBMODE_CM_HC;
175}
176
177/*
178 * Force HC to halt state from unknown (EHCI spec section 2.3).
179 * Must be called with interrupts enabled and the lock not held.
180 */
181static int ehci_halt (struct ehci_hcd *ehci)
182{
183 u32 temp;
184
185 spin_lock_irq(&ehci->lock);
186
187 /* disable any irqs left enabled by previous code */
188 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
189
190 if (ehci_is_TDI(ehci) && !tdi_in_host_mode(ehci)) {
191 spin_unlock_irq(&ehci->lock);
192 return 0;
193 }
194
195 /*
196 * This routine gets called during probe before ehci->command
197 * has been initialized, so we can't rely on its value.
198 */
199 ehci->command &= ~CMD_RUN;
200 temp = ehci_readl(ehci, &ehci->regs->command);
201 temp &= ~(CMD_RUN | CMD_IAAD);
202 ehci_writel(ehci, temp, &ehci->regs->command);
203
204 spin_unlock_irq(&ehci->lock);
205 synchronize_irq(ehci_to_hcd(ehci)->irq);
206
207 return ehci_handshake(ehci, &ehci->regs->status,
208 STS_HALT, STS_HALT, 16 * 125);
209}
210
211/* put TDI/ARC silicon into EHCI mode */
212static void tdi_reset (struct ehci_hcd *ehci)
213{
214 u32 tmp;
215
216 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
217 tmp |= USBMODE_CM_HC;
218 /* The default byte access to MMR space is LE after
219 * controller reset. Set the required endian mode
220 * for transfer buffers to match the host microprocessor
221 */
222 if (ehci_big_endian_mmio(ehci))
223 tmp |= USBMODE_BE;
224 ehci_writel(ehci, tmp, &ehci->regs->usbmode);
225}
226
227/*
228 * Reset a non-running (STS_HALT == 1) controller.
229 * Must be called with interrupts enabled and the lock not held.
230 */
231int ehci_reset(struct ehci_hcd *ehci)
232{
233 int retval;
234 u32 command = ehci_readl(ehci, &ehci->regs->command);
235
236 /* If the EHCI debug controller is active, special care must be
237 * taken before and after a host controller reset */
238 if (ehci->debug && !dbgp_reset_prep(ehci_to_hcd(ehci)))
239 ehci->debug = NULL;
240
241 command |= CMD_RESET;
242 dbg_cmd (ehci, "reset", command);
243 ehci_writel(ehci, command, &ehci->regs->command);
244 ehci->rh_state = EHCI_RH_HALTED;
245 ehci->next_statechange = jiffies;
246 retval = ehci_handshake(ehci, &ehci->regs->command,
247 CMD_RESET, 0, 250 * 1000);
248
249 if (ehci->has_hostpc) {
250 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
251 &ehci->regs->usbmode_ex);
252 ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
253 }
254 if (retval)
255 return retval;
256
257 if (ehci_is_TDI(ehci))
258 tdi_reset (ehci);
259
260 if (ehci->debug)
261 dbgp_external_startup(ehci_to_hcd(ehci));
262
263 ehci->port_c_suspend = ehci->suspended_ports =
264 ehci->resuming_ports = 0;
265 return retval;
266}
267EXPORT_SYMBOL_GPL(ehci_reset);
268
269/*
270 * Idle the controller (turn off the schedules).
271 * Must be called with interrupts enabled and the lock not held.
272 */
273static void ehci_quiesce (struct ehci_hcd *ehci)
274{
275 u32 temp;
276
277 if (ehci->rh_state != EHCI_RH_RUNNING)
278 return;
279
280 /* wait for any schedule enables/disables to take effect */
281 temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
282 ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp,
283 16 * 125);
284
285 /* then disable anything that's still active */
286 spin_lock_irq(&ehci->lock);
287 ehci->command &= ~(CMD_ASE | CMD_PSE);
288 ehci_writel(ehci, ehci->command, &ehci->regs->command);
289 spin_unlock_irq(&ehci->lock);
290
291 /* hardware can take 16 microframes to turn off ... */
292 ehci_handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0,
293 16 * 125);
294}
295
296/*-------------------------------------------------------------------------*/
297
298static void end_iaa_cycle(struct ehci_hcd *ehci);
299static void end_unlink_async(struct ehci_hcd *ehci);
300static void unlink_empty_async(struct ehci_hcd *ehci);
301static void ehci_work(struct ehci_hcd *ehci);
302static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
303static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
304static int ehci_port_power(struct ehci_hcd *ehci, int portnum, bool enable);
305
306#include "ehci-timer.c"
307#include "ehci-hub.c"
308#include "ehci-mem.c"
309#include "ehci-q.c"
310#include "ehci-sched.c"
311#include "ehci-sysfs.c"
312
313/*-------------------------------------------------------------------------*/
314
315/* On some systems, leaving remote wakeup enabled prevents system shutdown.
316 * The firmware seems to think that powering off is a wakeup event!
317 * This routine turns off remote wakeup and everything else, on all ports.
318 */
319static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
320{
321 int port = HCS_N_PORTS(ehci->hcs_params);
322
323 while (port--) {
324 spin_unlock_irq(&ehci->lock);
325 ehci_port_power(ehci, port, false);
326 spin_lock_irq(&ehci->lock);
327 ehci_writel(ehci, PORT_RWC_BITS,
328 &ehci->regs->port_status[port]);
329 }
330}
331
332/*
333 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
334 * Must be called with interrupts enabled and the lock not held.
335 */
336static void ehci_silence_controller(struct ehci_hcd *ehci)
337{
338 ehci_halt(ehci);
339
340 spin_lock_irq(&ehci->lock);
341 ehci->rh_state = EHCI_RH_HALTED;
342 ehci_turn_off_all_ports(ehci);
343
344 /* make BIOS/etc use companion controller during reboot */
345 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
346
347 /* unblock posted writes */
348 ehci_readl(ehci, &ehci->regs->configured_flag);
349 spin_unlock_irq(&ehci->lock);
350}
351
352/* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
353 * This forcibly disables dma and IRQs, helping kexec and other cases
354 * where the next system software may expect clean state.
355 */
356static void ehci_shutdown(struct usb_hcd *hcd)
357{
358 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
359
360 /**
361 * Protect the system from crashing at system shutdown in cases where
362 * usb host is not added yet from OTG controller driver.
363 * As ehci_setup() not done yet, so stop accessing registers or
364 * variables initialized in ehci_setup()
365 */
366 if (!ehci->sbrn)
367 return;
368
369 spin_lock_irq(&ehci->lock);
370 ehci->shutdown = true;
371 ehci->rh_state = EHCI_RH_STOPPING;
372 ehci->enabled_hrtimer_events = 0;
373 spin_unlock_irq(&ehci->lock);
374
375 ehci_silence_controller(ehci);
376
377 hrtimer_cancel(&ehci->hrtimer);
378}
379
380/*-------------------------------------------------------------------------*/
381
382/*
383 * ehci_work is called from some interrupts, timers, and so on.
384 * it calls driver completion functions, after dropping ehci->lock.
385 */
386static void ehci_work (struct ehci_hcd *ehci)
387{
388 /* another CPU may drop ehci->lock during a schedule scan while
389 * it reports urb completions. this flag guards against bogus
390 * attempts at re-entrant schedule scanning.
391 */
392 if (ehci->scanning) {
393 ehci->need_rescan = true;
394 return;
395 }
396 ehci->scanning = true;
397
398 rescan:
399 ehci->need_rescan = false;
400 if (ehci->async_count)
401 scan_async(ehci);
402 if (ehci->intr_count > 0)
403 scan_intr(ehci);
404 if (ehci->isoc_count > 0)
405 scan_isoc(ehci);
406 if (ehci->need_rescan)
407 goto rescan;
408 ehci->scanning = false;
409
410 /* the IO watchdog guards against hardware or driver bugs that
411 * misplace IRQs, and should let us run completely without IRQs.
412 * such lossage has been observed on both VT6202 and VT8235.
413 */
414 turn_on_io_watchdog(ehci);
415}
416
417/*
418 * Called when the ehci_hcd module is removed.
419 */
420static void ehci_stop (struct usb_hcd *hcd)
421{
422 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
423
424 ehci_dbg (ehci, "stop\n");
425
426 /* no more interrupts ... */
427
428 spin_lock_irq(&ehci->lock);
429 ehci->enabled_hrtimer_events = 0;
430 spin_unlock_irq(&ehci->lock);
431
432 ehci_quiesce(ehci);
433 ehci_silence_controller(ehci);
434 ehci_reset (ehci);
435
436 hrtimer_cancel(&ehci->hrtimer);
437 remove_sysfs_files(ehci);
438 remove_debug_files (ehci);
439
440 /* root hub is shut down separately (first, when possible) */
441 spin_lock_irq (&ehci->lock);
442 end_free_itds(ehci);
443 spin_unlock_irq (&ehci->lock);
444 ehci_mem_cleanup (ehci);
445
446 if (ehci->amd_pll_fix == 1)
447 usb_amd_dev_put();
448
449 dbg_status (ehci, "ehci_stop completed",
450 ehci_readl(ehci, &ehci->regs->status));
451}
452
453/* one-time init, only for memory state */
454static int ehci_init(struct usb_hcd *hcd)
455{
456 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
457 u32 temp;
458 int retval;
459 u32 hcc_params;
460 struct ehci_qh_hw *hw;
461
462 spin_lock_init(&ehci->lock);
463
464 /*
465 * keep io watchdog by default, those good HCDs could turn off it later
466 */
467 ehci->need_io_watchdog = 1;
468
469 hrtimer_init(&ehci->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
470 ehci->hrtimer.function = ehci_hrtimer_func;
471 ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT;
472
473 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
474
475 /*
476 * by default set standard 80% (== 100 usec/uframe) max periodic
477 * bandwidth as required by USB 2.0
478 */
479 ehci->uframe_periodic_max = 100;
480
481 /*
482 * hw default: 1K periodic list heads, one per frame.
483 * periodic_size can shrink by USBCMD update if hcc_params allows.
484 */
485 ehci->periodic_size = DEFAULT_I_TDPS;
486 INIT_LIST_HEAD(&ehci->async_unlink);
487 INIT_LIST_HEAD(&ehci->async_idle);
488 INIT_LIST_HEAD(&ehci->intr_unlink_wait);
489 INIT_LIST_HEAD(&ehci->intr_unlink);
490 INIT_LIST_HEAD(&ehci->intr_qh_list);
491 INIT_LIST_HEAD(&ehci->cached_itd_list);
492 INIT_LIST_HEAD(&ehci->cached_sitd_list);
493 INIT_LIST_HEAD(&ehci->tt_list);
494
495 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
496 /* periodic schedule size can be smaller than default */
497 switch (EHCI_TUNE_FLS) {
498 case 0: ehci->periodic_size = 1024; break;
499 case 1: ehci->periodic_size = 512; break;
500 case 2: ehci->periodic_size = 256; break;
501 default: BUG();
502 }
503 }
504 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
505 return retval;
506
507 /* controllers may cache some of the periodic schedule ... */
508 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
509 ehci->i_thresh = 0;
510 else // N microframes cached
511 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
512
513 /*
514 * dedicate a qh for the async ring head, since we couldn't unlink
515 * a 'real' qh without stopping the async schedule [4.8]. use it
516 * as the 'reclamation list head' too.
517 * its dummy is used in hw_alt_next of many tds, to prevent the qh
518 * from automatically advancing to the next td after short reads.
519 */
520 ehci->async->qh_next.qh = NULL;
521 hw = ehci->async->hw;
522 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
523 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
524#if defined(CONFIG_PPC_PS3)
525 hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE);
526#endif
527 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
528 hw->hw_qtd_next = EHCI_LIST_END(ehci);
529 ehci->async->qh_state = QH_STATE_LINKED;
530 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
531
532 /* clear interrupt enables, set irq latency */
533 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
534 log2_irq_thresh = 0;
535 temp = 1 << (16 + log2_irq_thresh);
536 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
537 ehci->has_ppcd = 1;
538 ehci_dbg(ehci, "enable per-port change event\n");
539 temp |= CMD_PPCEE;
540 }
541 if (HCC_CANPARK(hcc_params)) {
542 /* HW default park == 3, on hardware that supports it (like
543 * NVidia and ALI silicon), maximizes throughput on the async
544 * schedule by avoiding QH fetches between transfers.
545 *
546 * With fast usb storage devices and NForce2, "park" seems to
547 * make problems: throughput reduction (!), data errors...
548 */
549 if (park) {
550 park = min(park, (unsigned) 3);
551 temp |= CMD_PARK;
552 temp |= park << 8;
553 }
554 ehci_dbg(ehci, "park %d\n", park);
555 }
556 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
557 /* periodic schedule size can be smaller than default */
558 temp &= ~(3 << 2);
559 temp |= (EHCI_TUNE_FLS << 2);
560 }
561 ehci->command = temp;
562
563 /* Accept arbitrarily long scatter-gather lists */
564 if (!hcd->localmem_pool)
565 hcd->self.sg_tablesize = ~0;
566
567 /* Prepare for unlinking active QHs */
568 ehci->old_current = ~0;
569 return 0;
570}
571
572/* start HC running; it's halted, ehci_init() has been run (once) */
573static int ehci_run (struct usb_hcd *hcd)
574{
575 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
576 u32 temp;
577 u32 hcc_params;
578 int rc;
579
580 hcd->uses_new_polling = 1;
581
582 /* EHCI spec section 4.1 */
583
584 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
585 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
586
587 /*
588 * hcc_params controls whether ehci->regs->segment must (!!!)
589 * be used; it constrains QH/ITD/SITD and QTD locations.
590 * dma_pool consistent memory always uses segment zero.
591 * streaming mappings for I/O buffers, like dma_map_single(),
592 * can return segments above 4GB, if the device allows.
593 *
594 * NOTE: the dma mask is visible through dev->dma_mask, so
595 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
596 * Scsi_Host.highmem_io, and so forth. It's readonly to all
597 * host side drivers though.
598 */
599 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
600 if (HCC_64BIT_ADDR(hcc_params)) {
601 ehci_writel(ehci, 0, &ehci->regs->segment);
602#if 0
603// this is deeply broken on almost all architectures
604 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
605 ehci_info(ehci, "enabled 64bit DMA\n");
606#endif
607 }
608
609
610 // Philips, Intel, and maybe others need CMD_RUN before the
611 // root hub will detect new devices (why?); NEC doesn't
612 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
613 ehci->command |= CMD_RUN;
614 ehci_writel(ehci, ehci->command, &ehci->regs->command);
615 dbg_cmd (ehci, "init", ehci->command);
616
617 /*
618 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
619 * are explicitly handed to companion controller(s), so no TT is
620 * involved with the root hub. (Except where one is integrated,
621 * and there's no companion controller unless maybe for USB OTG.)
622 *
623 * Turning on the CF flag will transfer ownership of all ports
624 * from the companions to the EHCI controller. If any of the
625 * companions are in the middle of a port reset at the time, it
626 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
627 * guarantees that no resets are in progress. After we set CF,
628 * a short delay lets the hardware catch up; new resets shouldn't
629 * be started before the port switching actions could complete.
630 */
631 down_write(&ehci_cf_port_reset_rwsem);
632 ehci->rh_state = EHCI_RH_RUNNING;
633 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
634
635 /* Wait until HC become operational */
636 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
637 msleep(5);
638
639 /* For Aspeed, STS_HALT also depends on ASS/PSS status.
640 * Check CMD_RUN instead.
641 */
642 if (ehci->is_aspeed)
643 rc = ehci_handshake(ehci, &ehci->regs->command, CMD_RUN,
644 1, 100 * 1000);
645 else
646 rc = ehci_handshake(ehci, &ehci->regs->status, STS_HALT,
647 0, 100 * 1000);
648
649 up_write(&ehci_cf_port_reset_rwsem);
650
651 if (rc) {
652 ehci_err(ehci, "USB %x.%x, controller refused to start: %d\n",
653 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), rc);
654 return rc;
655 }
656
657 ehci->last_periodic_enable = ktime_get_real();
658
659 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
660 ehci_info (ehci,
661 "USB %x.%x started, EHCI %x.%02x%s\n",
662 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
663 temp >> 8, temp & 0xff,
664 (ignore_oc || ehci->spurious_oc) ? ", overcurrent ignored" : "");
665
666 ehci_writel(ehci, INTR_MASK,
667 &ehci->regs->intr_enable); /* Turn On Interrupts */
668
669 /* GRR this is run-once init(), being done every time the HC starts.
670 * So long as they're part of class devices, we can't do it init()
671 * since the class device isn't created that early.
672 */
673 create_debug_files(ehci);
674 create_sysfs_files(ehci);
675
676 return 0;
677}
678
679int ehci_setup(struct usb_hcd *hcd)
680{
681 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
682 int retval;
683
684 ehci->regs = (void __iomem *)ehci->caps +
685 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
686 dbg_hcs_params(ehci, "reset");
687 dbg_hcc_params(ehci, "reset");
688
689 /* cache this readonly data; minimize chip reads */
690 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
691
692 ehci->sbrn = HCD_USB2;
693
694 /* data structure init */
695 retval = ehci_init(hcd);
696 if (retval)
697 return retval;
698
699 retval = ehci_halt(ehci);
700 if (retval) {
701 ehci_mem_cleanup(ehci);
702 return retval;
703 }
704
705 ehci_reset(ehci);
706
707 return 0;
708}
709EXPORT_SYMBOL_GPL(ehci_setup);
710
711/*-------------------------------------------------------------------------*/
712
713static irqreturn_t ehci_irq (struct usb_hcd *hcd)
714{
715 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
716 u32 status, current_status, masked_status, pcd_status = 0;
717 u32 cmd;
718 int bh;
719
720 spin_lock(&ehci->lock);
721
722 status = 0;
723 current_status = ehci_readl(ehci, &ehci->regs->status);
724restart:
725
726 /* e.g. cardbus physical eject */
727 if (current_status == ~(u32) 0) {
728 ehci_dbg (ehci, "device removed\n");
729 goto dead;
730 }
731 status |= current_status;
732
733 /*
734 * We don't use STS_FLR, but some controllers don't like it to
735 * remain on, so mask it out along with the other status bits.
736 */
737 masked_status = current_status & (INTR_MASK | STS_FLR);
738
739 /* Shared IRQ? */
740 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
741 spin_unlock(&ehci->lock);
742 return IRQ_NONE;
743 }
744
745 /* clear (just) interrupts */
746 ehci_writel(ehci, masked_status, &ehci->regs->status);
747
748 /* For edge interrupts, don't race with an interrupt bit being raised */
749 current_status = ehci_readl(ehci, &ehci->regs->status);
750 if (current_status & INTR_MASK)
751 goto restart;
752
753 cmd = ehci_readl(ehci, &ehci->regs->command);
754 bh = 0;
755
756 /* normal [4.15.1.2] or error [4.15.1.1] completion */
757 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
758 if (likely ((status & STS_ERR) == 0)) {
759 INCR(ehci->stats.normal);
760 } else {
761 /* Force to check port status */
762 if (ehci->has_ci_pec_bug)
763 status |= STS_PCD;
764 INCR(ehci->stats.error);
765 }
766 bh = 1;
767 }
768
769 /* complete the unlinking of some qh [4.15.2.3] */
770 if (status & STS_IAA) {
771
772 /* Turn off the IAA watchdog */
773 ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG);
774
775 /*
776 * Mild optimization: Allow another IAAD to reset the
777 * hrtimer, if one occurs before the next expiration.
778 * In theory we could always cancel the hrtimer, but
779 * tests show that about half the time it will be reset
780 * for some other event anyway.
781 */
782 if (ehci->next_hrtimer_event == EHCI_HRTIMER_IAA_WATCHDOG)
783 ++ehci->next_hrtimer_event;
784
785 /* guard against (alleged) silicon errata */
786 if (cmd & CMD_IAAD)
787 ehci_dbg(ehci, "IAA with IAAD still set?\n");
788 if (ehci->iaa_in_progress)
789 INCR(ehci->stats.iaa);
790 end_iaa_cycle(ehci);
791 }
792
793 /* remote wakeup [4.3.1] */
794 if (status & STS_PCD) {
795 unsigned i = HCS_N_PORTS (ehci->hcs_params);
796 u32 ppcd = ~0;
797
798 /* kick root hub later */
799 pcd_status = status;
800
801 /* resume root hub? */
802 if (ehci->rh_state == EHCI_RH_SUSPENDED)
803 usb_hcd_resume_root_hub(hcd);
804
805 /* get per-port change detect bits */
806 if (ehci->has_ppcd)
807 ppcd = status >> 16;
808
809 while (i--) {
810 int pstatus;
811
812 /* leverage per-port change bits feature */
813 if (!(ppcd & (1 << i)))
814 continue;
815 pstatus = ehci_readl(ehci,
816 &ehci->regs->port_status[i]);
817
818 if (pstatus & PORT_OWNER)
819 continue;
820 if (!(test_bit(i, &ehci->suspended_ports) &&
821 ((pstatus & PORT_RESUME) ||
822 !(pstatus & PORT_SUSPEND)) &&
823 (pstatus & PORT_PE) &&
824 ehci->reset_done[i] == 0))
825 continue;
826
827 /* start USB_RESUME_TIMEOUT msec resume signaling from
828 * this port, and make hub_wq collect
829 * PORT_STAT_C_SUSPEND to stop that signaling.
830 */
831 ehci->reset_done[i] = jiffies +
832 msecs_to_jiffies(USB_RESUME_TIMEOUT);
833 set_bit(i, &ehci->resuming_ports);
834 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
835 usb_hcd_start_port_resume(&hcd->self, i);
836 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
837 }
838 }
839
840 /* PCI errors [4.15.2.4] */
841 if (unlikely ((status & STS_FATAL) != 0)) {
842 ehci_err(ehci, "fatal error\n");
843 dbg_cmd(ehci, "fatal", cmd);
844 dbg_status(ehci, "fatal", status);
845dead:
846 usb_hc_died(hcd);
847
848 /* Don't let the controller do anything more */
849 ehci->shutdown = true;
850 ehci->rh_state = EHCI_RH_STOPPING;
851 ehci->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
852 ehci_writel(ehci, ehci->command, &ehci->regs->command);
853 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
854 ehci_handle_controller_death(ehci);
855
856 /* Handle completions when the controller stops */
857 bh = 0;
858 }
859
860 if (bh)
861 ehci_work (ehci);
862 spin_unlock(&ehci->lock);
863 if (pcd_status)
864 usb_hcd_poll_rh_status(hcd);
865 return IRQ_HANDLED;
866}
867
868/*-------------------------------------------------------------------------*/
869
870/*
871 * non-error returns are a promise to giveback() the urb later
872 * we drop ownership so next owner (or urb unlink) can get it
873 *
874 * urb + dev is in hcd.self.controller.urb_list
875 * we're queueing TDs onto software and hardware lists
876 *
877 * hcd-specific init for hcpriv hasn't been done yet
878 *
879 * NOTE: control, bulk, and interrupt share the same code to append TDs
880 * to a (possibly active) QH, and the same QH scanning code.
881 */
882static int ehci_urb_enqueue (
883 struct usb_hcd *hcd,
884 struct urb *urb,
885 gfp_t mem_flags
886) {
887 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
888 struct list_head qtd_list;
889
890 INIT_LIST_HEAD (&qtd_list);
891
892 switch (usb_pipetype (urb->pipe)) {
893 case PIPE_CONTROL:
894 /* qh_completions() code doesn't handle all the fault cases
895 * in multi-TD control transfers. Even 1KB is rare anyway.
896 */
897 if (urb->transfer_buffer_length > (16 * 1024))
898 return -EMSGSIZE;
899 fallthrough;
900 /* case PIPE_BULK: */
901 default:
902 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
903 return -ENOMEM;
904 return submit_async(ehci, urb, &qtd_list, mem_flags);
905
906 case PIPE_INTERRUPT:
907 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
908 return -ENOMEM;
909 return intr_submit(ehci, urb, &qtd_list, mem_flags);
910
911 case PIPE_ISOCHRONOUS:
912 if (urb->dev->speed == USB_SPEED_HIGH)
913 return itd_submit (ehci, urb, mem_flags);
914 else
915 return sitd_submit (ehci, urb, mem_flags);
916 }
917}
918
919/* remove from hardware lists
920 * completions normally happen asynchronously
921 */
922
923static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
924{
925 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
926 struct ehci_qh *qh;
927 unsigned long flags;
928 int rc;
929
930 spin_lock_irqsave (&ehci->lock, flags);
931 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
932 if (rc)
933 goto done;
934
935 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
936 /*
937 * We don't expedite dequeue for isochronous URBs.
938 * Just wait until they complete normally or their
939 * time slot expires.
940 */
941 } else {
942 qh = (struct ehci_qh *) urb->hcpriv;
943 qh->unlink_reason |= QH_UNLINK_REQUESTED;
944 switch (qh->qh_state) {
945 case QH_STATE_LINKED:
946 if (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)
947 start_unlink_intr(ehci, qh);
948 else
949 start_unlink_async(ehci, qh);
950 break;
951 case QH_STATE_COMPLETING:
952 qh->dequeue_during_giveback = 1;
953 break;
954 case QH_STATE_UNLINK:
955 case QH_STATE_UNLINK_WAIT:
956 /* already started */
957 break;
958 case QH_STATE_IDLE:
959 /* QH might be waiting for a Clear-TT-Buffer */
960 qh_completions(ehci, qh);
961 break;
962 }
963 }
964done:
965 spin_unlock_irqrestore (&ehci->lock, flags);
966 return rc;
967}
968
969/*-------------------------------------------------------------------------*/
970
971// bulk qh holds the data toggle
972
973static void
974ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
975{
976 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
977 unsigned long flags;
978 struct ehci_qh *qh;
979
980 /* ASSERT: any requests/urbs are being unlinked */
981 /* ASSERT: nobody can be submitting urbs for this any more */
982
983rescan:
984 spin_lock_irqsave (&ehci->lock, flags);
985 qh = ep->hcpriv;
986 if (!qh)
987 goto done;
988
989 /* endpoints can be iso streams. for now, we don't
990 * accelerate iso completions ... so spin a while.
991 */
992 if (qh->hw == NULL) {
993 struct ehci_iso_stream *stream = ep->hcpriv;
994
995 if (!list_empty(&stream->td_list))
996 goto idle_timeout;
997
998 /* BUG_ON(!list_empty(&stream->free_list)); */
999 reserve_release_iso_bandwidth(ehci, stream, -1);
1000 kfree(stream);
1001 goto done;
1002 }
1003
1004 qh->unlink_reason |= QH_UNLINK_REQUESTED;
1005 switch (qh->qh_state) {
1006 case QH_STATE_LINKED:
1007 if (list_empty(&qh->qtd_list))
1008 qh->unlink_reason |= QH_UNLINK_QUEUE_EMPTY;
1009 else
1010 WARN_ON(1);
1011 if (usb_endpoint_type(&ep->desc) != USB_ENDPOINT_XFER_INT)
1012 start_unlink_async(ehci, qh);
1013 else
1014 start_unlink_intr(ehci, qh);
1015 fallthrough;
1016 case QH_STATE_COMPLETING: /* already in unlinking */
1017 case QH_STATE_UNLINK: /* wait for hw to finish? */
1018 case QH_STATE_UNLINK_WAIT:
1019idle_timeout:
1020 spin_unlock_irqrestore (&ehci->lock, flags);
1021 schedule_timeout_uninterruptible(1);
1022 goto rescan;
1023 case QH_STATE_IDLE: /* fully unlinked */
1024 if (qh->clearing_tt)
1025 goto idle_timeout;
1026 if (list_empty (&qh->qtd_list)) {
1027 if (qh->ps.bw_uperiod)
1028 reserve_release_intr_bandwidth(ehci, qh, -1);
1029 qh_destroy(ehci, qh);
1030 break;
1031 }
1032 fallthrough;
1033 default:
1034 /* caller was supposed to have unlinked any requests;
1035 * that's not our job. just leak this memory.
1036 */
1037 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1038 qh, ep->desc.bEndpointAddress, qh->qh_state,
1039 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1040 break;
1041 }
1042 done:
1043 ep->hcpriv = NULL;
1044 spin_unlock_irqrestore (&ehci->lock, flags);
1045}
1046
1047static void
1048ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1049{
1050 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1051 struct ehci_qh *qh;
1052 int eptype = usb_endpoint_type(&ep->desc);
1053 int epnum = usb_endpoint_num(&ep->desc);
1054 int is_out = usb_endpoint_dir_out(&ep->desc);
1055 unsigned long flags;
1056
1057 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1058 return;
1059
1060 spin_lock_irqsave(&ehci->lock, flags);
1061 qh = ep->hcpriv;
1062
1063 /* For Bulk and Interrupt endpoints we maintain the toggle state
1064 * in the hardware; the toggle bits in udev aren't used at all.
1065 * When an endpoint is reset by usb_clear_halt() we must reset
1066 * the toggle bit in the QH.
1067 */
1068 if (qh) {
1069 if (!list_empty(&qh->qtd_list)) {
1070 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1071 } else {
1072 /* The toggle value in the QH can't be updated
1073 * while the QH is active. Unlink it now;
1074 * re-linking will call qh_refresh().
1075 */
1076 usb_settoggle(qh->ps.udev, epnum, is_out, 0);
1077 qh->unlink_reason |= QH_UNLINK_REQUESTED;
1078 if (eptype == USB_ENDPOINT_XFER_BULK)
1079 start_unlink_async(ehci, qh);
1080 else
1081 start_unlink_intr(ehci, qh);
1082 }
1083 }
1084 spin_unlock_irqrestore(&ehci->lock, flags);
1085}
1086
1087static int ehci_get_frame (struct usb_hcd *hcd)
1088{
1089 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1090 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1091}
1092
1093/*-------------------------------------------------------------------------*/
1094
1095/* Device addition and removal */
1096
1097static void ehci_remove_device(struct usb_hcd *hcd, struct usb_device *udev)
1098{
1099 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1100
1101 spin_lock_irq(&ehci->lock);
1102 drop_tt(udev);
1103 spin_unlock_irq(&ehci->lock);
1104}
1105
1106/*-------------------------------------------------------------------------*/
1107
1108#ifdef CONFIG_PM
1109
1110/* Clear wakeup signal locked in zhaoxin platform when device plug in. */
1111static void ehci_zx_wakeup_clear(struct ehci_hcd *ehci)
1112{
1113 u32 __iomem *reg = &ehci->regs->port_status[4];
1114 u32 t1 = ehci_readl(ehci, reg);
1115
1116 t1 &= (u32)~0xf0000;
1117 t1 |= PORT_TEST_FORCE;
1118 ehci_writel(ehci, t1, reg);
1119 t1 = ehci_readl(ehci, reg);
1120 msleep(1);
1121 t1 &= (u32)~0xf0000;
1122 ehci_writel(ehci, t1, reg);
1123 ehci_readl(ehci, reg);
1124 msleep(1);
1125 t1 = ehci_readl(ehci, reg);
1126 ehci_writel(ehci, t1 | PORT_CSC, reg);
1127 ehci_readl(ehci, reg);
1128}
1129
1130/* suspend/resume, section 4.3 */
1131
1132/* These routines handle the generic parts of controller suspend/resume */
1133
1134int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1135{
1136 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1137
1138 if (time_before(jiffies, ehci->next_statechange))
1139 msleep(10);
1140
1141 /*
1142 * Root hub was already suspended. Disable IRQ emission and
1143 * mark HW unaccessible. The PM and USB cores make sure that
1144 * the root hub is either suspended or stopped.
1145 */
1146 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
1147
1148 spin_lock_irq(&ehci->lock);
1149 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
1150 (void) ehci_readl(ehci, &ehci->regs->intr_enable);
1151
1152 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1153 spin_unlock_irq(&ehci->lock);
1154
1155 synchronize_irq(hcd->irq);
1156
1157 /* Check for race with a wakeup request */
1158 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1159 ehci_resume(hcd, false);
1160 return -EBUSY;
1161 }
1162
1163 return 0;
1164}
1165EXPORT_SYMBOL_GPL(ehci_suspend);
1166
1167/* Returns 0 if power was preserved, 1 if power was lost */
1168int ehci_resume(struct usb_hcd *hcd, bool force_reset)
1169{
1170 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1171
1172 if (time_before(jiffies, ehci->next_statechange))
1173 msleep(100);
1174
1175 /* Mark hardware accessible again as we are back to full power by now */
1176 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1177
1178 if (ehci->shutdown)
1179 return 0; /* Controller is dead */
1180
1181 if (ehci->zx_wakeup_clear_needed)
1182 ehci_zx_wakeup_clear(ehci);
1183
1184 /*
1185 * If CF is still set and reset isn't forced
1186 * then we maintained suspend power.
1187 * Just undo the effect of ehci_suspend().
1188 */
1189 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
1190 !force_reset) {
1191 int mask = INTR_MASK;
1192
1193 ehci_prepare_ports_for_controller_resume(ehci);
1194
1195 spin_lock_irq(&ehci->lock);
1196 if (ehci->shutdown)
1197 goto skip;
1198
1199 if (!hcd->self.root_hub->do_remote_wakeup)
1200 mask &= ~STS_PCD;
1201 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
1202 ehci_readl(ehci, &ehci->regs->intr_enable);
1203 skip:
1204 spin_unlock_irq(&ehci->lock);
1205 return 0;
1206 }
1207
1208 /*
1209 * Else reset, to cope with power loss or resume from hibernation
1210 * having let the firmware kick in during reboot.
1211 */
1212 usb_root_hub_lost_power(hcd->self.root_hub);
1213 (void) ehci_halt(ehci);
1214 (void) ehci_reset(ehci);
1215
1216 spin_lock_irq(&ehci->lock);
1217 if (ehci->shutdown)
1218 goto skip;
1219
1220 ehci_writel(ehci, ehci->command, &ehci->regs->command);
1221 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
1222 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
1223
1224 ehci->rh_state = EHCI_RH_SUSPENDED;
1225 spin_unlock_irq(&ehci->lock);
1226
1227 return 1;
1228}
1229EXPORT_SYMBOL_GPL(ehci_resume);
1230
1231#endif
1232
1233/*-------------------------------------------------------------------------*/
1234
1235/*
1236 * Generic structure: This gets copied for platform drivers so that
1237 * individual entries can be overridden as needed.
1238 */
1239
1240static const struct hc_driver ehci_hc_driver = {
1241 .description = hcd_name,
1242 .product_desc = "EHCI Host Controller",
1243 .hcd_priv_size = sizeof(struct ehci_hcd),
1244
1245 /*
1246 * generic hardware linkage
1247 */
1248 .irq = ehci_irq,
1249 .flags = HCD_MEMORY | HCD_DMA | HCD_USB2 | HCD_BH,
1250
1251 /*
1252 * basic lifecycle operations
1253 */
1254 .reset = ehci_setup,
1255 .start = ehci_run,
1256 .stop = ehci_stop,
1257 .shutdown = ehci_shutdown,
1258
1259 /*
1260 * managing i/o requests and associated device resources
1261 */
1262 .urb_enqueue = ehci_urb_enqueue,
1263 .urb_dequeue = ehci_urb_dequeue,
1264 .endpoint_disable = ehci_endpoint_disable,
1265 .endpoint_reset = ehci_endpoint_reset,
1266 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
1267
1268 /*
1269 * scheduling support
1270 */
1271 .get_frame_number = ehci_get_frame,
1272
1273 /*
1274 * root hub support
1275 */
1276 .hub_status_data = ehci_hub_status_data,
1277 .hub_control = ehci_hub_control,
1278 .bus_suspend = ehci_bus_suspend,
1279 .bus_resume = ehci_bus_resume,
1280 .relinquish_port = ehci_relinquish_port,
1281 .port_handed_over = ehci_port_handed_over,
1282 .get_resuming_ports = ehci_get_resuming_ports,
1283
1284 /*
1285 * device support
1286 */
1287 .free_dev = ehci_remove_device,
1288#ifdef CONFIG_USB_HCD_TEST_MODE
1289 /* EH SINGLE_STEP_SET_FEATURE test support */
1290 .submit_single_step_set_feature = ehci_submit_single_step_set_feature,
1291#endif
1292};
1293
1294void ehci_init_driver(struct hc_driver *drv,
1295 const struct ehci_driver_overrides *over)
1296{
1297 /* Copy the generic table to drv and then apply the overrides */
1298 *drv = ehci_hc_driver;
1299
1300 if (over) {
1301 drv->hcd_priv_size += over->extra_priv_size;
1302 if (over->reset)
1303 drv->reset = over->reset;
1304 if (over->port_power)
1305 drv->port_power = over->port_power;
1306 }
1307}
1308EXPORT_SYMBOL_GPL(ehci_init_driver);
1309
1310/*-------------------------------------------------------------------------*/
1311
1312MODULE_DESCRIPTION(DRIVER_DESC);
1313MODULE_AUTHOR (DRIVER_AUTHOR);
1314MODULE_LICENSE ("GPL");
1315
1316#ifdef CONFIG_USB_EHCI_SH
1317#include "ehci-sh.c"
1318#endif
1319
1320#ifdef CONFIG_PPC_PS3
1321#include "ehci-ps3.c"
1322#endif
1323
1324#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1325#include "ehci-ppc-of.c"
1326#endif
1327
1328#ifdef CONFIG_XPS_USB_HCD_XILINX
1329#include "ehci-xilinx-of.c"
1330#endif
1331
1332#ifdef CONFIG_SPARC_LEON
1333#include "ehci-grlib.c"
1334#endif
1335
1336static struct platform_driver * const platform_drivers[] = {
1337#ifdef CONFIG_USB_EHCI_SH
1338 &ehci_hcd_sh_driver,
1339#endif
1340#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1341 &ehci_hcd_ppc_of_driver,
1342#endif
1343#ifdef CONFIG_XPS_USB_HCD_XILINX
1344 &ehci_hcd_xilinx_of_driver,
1345#endif
1346#ifdef CONFIG_SPARC_LEON
1347 &ehci_grlib_driver,
1348#endif
1349};
1350
1351static int __init ehci_hcd_init(void)
1352{
1353 int retval = 0;
1354
1355 if (usb_disabled())
1356 return -ENODEV;
1357
1358 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1359 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1360 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1361 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1362 " before uhci_hcd and ohci_hcd, not after\n");
1363
1364 pr_debug("%s: block sizes: qh %zd qtd %zd itd %zd sitd %zd\n",
1365 hcd_name,
1366 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1367 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1368
1369#ifdef CONFIG_DYNAMIC_DEBUG
1370 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1371#endif
1372
1373 retval = platform_register_drivers(platform_drivers, ARRAY_SIZE(platform_drivers));
1374 if (retval < 0)
1375 goto clean0;
1376
1377#ifdef CONFIG_PPC_PS3
1378 retval = ps3_ehci_driver_register(&ps3_ehci_driver);
1379 if (retval < 0)
1380 goto clean1;
1381#endif
1382
1383 return 0;
1384
1385#ifdef CONFIG_PPC_PS3
1386clean1:
1387#endif
1388 platform_unregister_drivers(platform_drivers, ARRAY_SIZE(platform_drivers));
1389clean0:
1390#ifdef CONFIG_DYNAMIC_DEBUG
1391 debugfs_remove(ehci_debug_root);
1392 ehci_debug_root = NULL;
1393#endif
1394 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1395 return retval;
1396}
1397module_init(ehci_hcd_init);
1398
1399static void __exit ehci_hcd_cleanup(void)
1400{
1401#ifdef CONFIG_PPC_PS3
1402 ps3_ehci_driver_unregister(&ps3_ehci_driver);
1403#endif
1404 platform_unregister_drivers(platform_drivers, ARRAY_SIZE(platform_drivers));
1405#ifdef CONFIG_DYNAMIC_DEBUG
1406 debugfs_remove(ehci_debug_root);
1407#endif
1408 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1409}
1410module_exit(ehci_hcd_cleanup);
1/*
2 * Enhanced Host Controller Interface (EHCI) driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * Copyright (c) 2000-2004 by David Brownell
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/dmapool.h>
26#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/ioport.h>
29#include <linux/sched.h>
30#include <linux/vmalloc.h>
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/timer.h>
34#include <linux/ktime.h>
35#include <linux/list.h>
36#include <linux/interrupt.h>
37#include <linux/usb.h>
38#include <linux/usb/hcd.h>
39#include <linux/moduleparam.h>
40#include <linux/dma-mapping.h>
41#include <linux/debugfs.h>
42#include <linux/slab.h>
43#include <linux/uaccess.h>
44
45#include <asm/byteorder.h>
46#include <asm/io.h>
47#include <asm/irq.h>
48#include <asm/unaligned.h>
49
50#if defined(CONFIG_PPC_PS3)
51#include <asm/firmware.h>
52#endif
53
54/*-------------------------------------------------------------------------*/
55
56/*
57 * EHCI hc_driver implementation ... experimental, incomplete.
58 * Based on the final 1.0 register interface specification.
59 *
60 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
61 * First was PCMCIA, like ISA; then CardBus, which is PCI.
62 * Next comes "CardBay", using USB 2.0 signals.
63 *
64 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
65 * Special thanks to Intel and VIA for providing host controllers to
66 * test this driver on, and Cypress (including In-System Design) for
67 * providing early devices for those host controllers to talk to!
68 */
69
70#define DRIVER_AUTHOR "David Brownell"
71#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
72
73static const char hcd_name [] = "ehci_hcd";
74
75
76#undef VERBOSE_DEBUG
77#undef EHCI_URB_TRACE
78
79#ifdef DEBUG
80#define EHCI_STATS
81#endif
82
83/* magic numbers that can affect system performance */
84#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
85#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
86#define EHCI_TUNE_RL_TT 0
87#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
88#define EHCI_TUNE_MULT_TT 1
89/*
90 * Some drivers think it's safe to schedule isochronous transfers more than
91 * 256 ms into the future (partly as a result of an old bug in the scheduling
92 * code). In an attempt to avoid trouble, we will use a minimum scheduling
93 * length of 512 frames instead of 256.
94 */
95#define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
96
97#define EHCI_IAA_MSECS 10 /* arbitrary */
98#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
99#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
100#define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1)
101 /* 5-ms async qh unlink delay */
102
103/* Initial IRQ latency: faster than hw default */
104static int log2_irq_thresh = 0; // 0 to 6
105module_param (log2_irq_thresh, int, S_IRUGO);
106MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
107
108/* initial park setting: slower than hw default */
109static unsigned park = 0;
110module_param (park, uint, S_IRUGO);
111MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
112
113/* for flakey hardware, ignore overcurrent indicators */
114static bool ignore_oc = 0;
115module_param (ignore_oc, bool, S_IRUGO);
116MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
117
118/* for link power management(LPM) feature */
119static unsigned int hird;
120module_param(hird, int, S_IRUGO);
121MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
122
123#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
124
125/*-------------------------------------------------------------------------*/
126
127#include "ehci.h"
128#include "ehci-dbg.c"
129#include "pci-quirks.h"
130
131/*-------------------------------------------------------------------------*/
132
133static void
134timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
135{
136 /* Don't override timeouts which shrink or (later) disable
137 * the async ring; just the I/O watchdog. Note that if a
138 * SHRINK were pending, OFF would never be requested.
139 */
140 if (timer_pending(&ehci->watchdog)
141 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
142 & ehci->actions))
143 return;
144
145 if (!test_and_set_bit(action, &ehci->actions)) {
146 unsigned long t;
147
148 switch (action) {
149 case TIMER_IO_WATCHDOG:
150 if (!ehci->need_io_watchdog)
151 return;
152 t = EHCI_IO_JIFFIES;
153 break;
154 case TIMER_ASYNC_OFF:
155 t = EHCI_ASYNC_JIFFIES;
156 break;
157 /* case TIMER_ASYNC_SHRINK: */
158 default:
159 t = EHCI_SHRINK_JIFFIES;
160 break;
161 }
162 mod_timer(&ehci->watchdog, t + jiffies);
163 }
164}
165
166/*-------------------------------------------------------------------------*/
167
168/*
169 * handshake - spin reading hc until handshake completes or fails
170 * @ptr: address of hc register to be read
171 * @mask: bits to look at in result of read
172 * @done: value of those bits when handshake succeeds
173 * @usec: timeout in microseconds
174 *
175 * Returns negative errno, or zero on success
176 *
177 * Success happens when the "mask" bits have the specified value (hardware
178 * handshake done). There are two failure modes: "usec" have passed (major
179 * hardware flakeout), or the register reads as all-ones (hardware removed).
180 *
181 * That last failure should_only happen in cases like physical cardbus eject
182 * before driver shutdown. But it also seems to be caused by bugs in cardbus
183 * bridge shutdown: shutting down the bridge before the devices using it.
184 */
185static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
186 u32 mask, u32 done, int usec)
187{
188 u32 result;
189
190 do {
191 result = ehci_readl(ehci, ptr);
192 if (result == ~(u32)0) /* card removed */
193 return -ENODEV;
194 result &= mask;
195 if (result == done)
196 return 0;
197 udelay (1);
198 usec--;
199 } while (usec > 0);
200 return -ETIMEDOUT;
201}
202
203/* check TDI/ARC silicon is in host mode */
204static int tdi_in_host_mode (struct ehci_hcd *ehci)
205{
206 u32 __iomem *reg_ptr;
207 u32 tmp;
208
209 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
210 tmp = ehci_readl(ehci, reg_ptr);
211 return (tmp & 3) == USBMODE_CM_HC;
212}
213
214/* force HC to halt state from unknown (EHCI spec section 2.3) */
215static int ehci_halt (struct ehci_hcd *ehci)
216{
217 u32 temp = ehci_readl(ehci, &ehci->regs->status);
218
219 /* disable any irqs left enabled by previous code */
220 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
221
222 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) {
223 return 0;
224 }
225
226 if ((temp & STS_HALT) != 0)
227 return 0;
228
229 /*
230 * This routine gets called during probe before ehci->command
231 * has been initialized, so we can't rely on its value.
232 */
233 ehci->command &= ~CMD_RUN;
234 temp = ehci_readl(ehci, &ehci->regs->command);
235 temp &= ~(CMD_RUN | CMD_IAAD);
236 ehci_writel(ehci, temp, &ehci->regs->command);
237 return handshake (ehci, &ehci->regs->status,
238 STS_HALT, STS_HALT, 16 * 125);
239}
240
241#if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_PPC_PS3)
242
243/*
244 * The EHCI controller of the Cell Super Companion Chip used in the
245 * PS3 will stop the root hub after all root hub ports are suspended.
246 * When in this condition handshake will return -ETIMEDOUT. The
247 * STS_HLT bit will not be set, so inspection of the frame index is
248 * used here to test for the condition. If the condition is found
249 * return success to allow the USB suspend to complete.
250 */
251
252static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
253 void __iomem *ptr, u32 mask, u32 done,
254 int usec)
255{
256 unsigned int old_index;
257 int error;
258
259 if (!firmware_has_feature(FW_FEATURE_PS3_LV1))
260 return -ETIMEDOUT;
261
262 old_index = ehci_read_frame_index(ehci);
263
264 error = handshake(ehci, ptr, mask, done, usec);
265
266 if (error == -ETIMEDOUT && ehci_read_frame_index(ehci) == old_index)
267 return 0;
268
269 return error;
270}
271
272#else
273
274static int handshake_for_broken_root_hub(struct ehci_hcd *ehci,
275 void __iomem *ptr, u32 mask, u32 done,
276 int usec)
277{
278 return -ETIMEDOUT;
279}
280
281#endif
282
283static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
284 u32 mask, u32 done, int usec)
285{
286 int error;
287
288 error = handshake(ehci, ptr, mask, done, usec);
289 if (error == -ETIMEDOUT)
290 error = handshake_for_broken_root_hub(ehci, ptr, mask, done,
291 usec);
292
293 if (error) {
294 ehci_halt(ehci);
295 ehci->rh_state = EHCI_RH_HALTED;
296 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
297 ptr, mask, done, error);
298 }
299
300 return error;
301}
302
303/* put TDI/ARC silicon into EHCI mode */
304static void tdi_reset (struct ehci_hcd *ehci)
305{
306 u32 __iomem *reg_ptr;
307 u32 tmp;
308
309 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
310 tmp = ehci_readl(ehci, reg_ptr);
311 tmp |= USBMODE_CM_HC;
312 /* The default byte access to MMR space is LE after
313 * controller reset. Set the required endian mode
314 * for transfer buffers to match the host microprocessor
315 */
316 if (ehci_big_endian_mmio(ehci))
317 tmp |= USBMODE_BE;
318 ehci_writel(ehci, tmp, reg_ptr);
319}
320
321/* reset a non-running (STS_HALT == 1) controller */
322static int ehci_reset (struct ehci_hcd *ehci)
323{
324 int retval;
325 u32 command = ehci_readl(ehci, &ehci->regs->command);
326
327 /* If the EHCI debug controller is active, special care must be
328 * taken before and after a host controller reset */
329 if (ehci->debug && !dbgp_reset_prep())
330 ehci->debug = NULL;
331
332 command |= CMD_RESET;
333 dbg_cmd (ehci, "reset", command);
334 ehci_writel(ehci, command, &ehci->regs->command);
335 ehci->rh_state = EHCI_RH_HALTED;
336 ehci->next_statechange = jiffies;
337 retval = handshake (ehci, &ehci->regs->command,
338 CMD_RESET, 0, 250 * 1000);
339
340 if (ehci->has_hostpc) {
341 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
342 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
343 ehci_writel(ehci, TXFIFO_DEFAULT,
344 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
345 }
346 if (retval)
347 return retval;
348
349 if (ehci_is_TDI(ehci))
350 tdi_reset (ehci);
351
352 if (ehci->debug)
353 dbgp_external_startup();
354
355 ehci->port_c_suspend = ehci->suspended_ports =
356 ehci->resuming_ports = 0;
357 return retval;
358}
359
360/* idle the controller (from running) */
361static void ehci_quiesce (struct ehci_hcd *ehci)
362{
363 u32 temp;
364
365#ifdef DEBUG
366 if (ehci->rh_state != EHCI_RH_RUNNING)
367 BUG ();
368#endif
369
370 /* wait for any schedule enables/disables to take effect */
371 temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
372 if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
373 STS_ASS | STS_PSS, temp, 16 * 125))
374 return;
375
376 /* then disable anything that's still active */
377 ehci->command &= ~(CMD_ASE | CMD_PSE);
378 ehci_writel(ehci, ehci->command, &ehci->regs->command);
379
380 /* hardware can take 16 microframes to turn off ... */
381 handshake_on_error_set_halt(ehci, &ehci->regs->status,
382 STS_ASS | STS_PSS, 0, 16 * 125);
383}
384
385/*-------------------------------------------------------------------------*/
386
387static void end_unlink_async(struct ehci_hcd *ehci);
388static void ehci_work(struct ehci_hcd *ehci);
389
390#include "ehci-hub.c"
391#include "ehci-lpm.c"
392#include "ehci-mem.c"
393#include "ehci-q.c"
394#include "ehci-sched.c"
395#include "ehci-sysfs.c"
396
397/*-------------------------------------------------------------------------*/
398
399static void ehci_iaa_watchdog(unsigned long param)
400{
401 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
402 unsigned long flags;
403
404 spin_lock_irqsave (&ehci->lock, flags);
405
406 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
407 * So we need this watchdog, but must protect it against both
408 * (a) SMP races against real IAA firing and retriggering, and
409 * (b) clean HC shutdown, when IAA watchdog was pending.
410 */
411 if (ehci->reclaim
412 && !timer_pending(&ehci->iaa_watchdog)
413 && ehci->rh_state == EHCI_RH_RUNNING) {
414 u32 cmd, status;
415
416 /* If we get here, IAA is *REALLY* late. It's barely
417 * conceivable that the system is so busy that CMD_IAAD
418 * is still legitimately set, so let's be sure it's
419 * clear before we read STS_IAA. (The HC should clear
420 * CMD_IAAD when it sets STS_IAA.)
421 */
422 cmd = ehci_readl(ehci, &ehci->regs->command);
423
424 /* If IAA is set here it either legitimately triggered
425 * before we cleared IAAD above (but _way_ late, so we'll
426 * still count it as lost) ... or a silicon erratum:
427 * - VIA seems to set IAA without triggering the IRQ;
428 * - IAAD potentially cleared without setting IAA.
429 */
430 status = ehci_readl(ehci, &ehci->regs->status);
431 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
432 COUNT (ehci->stats.lost_iaa);
433 ehci_writel(ehci, STS_IAA, &ehci->regs->status);
434 }
435
436 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
437 status, cmd);
438 end_unlink_async(ehci);
439 }
440
441 spin_unlock_irqrestore(&ehci->lock, flags);
442}
443
444static void ehci_watchdog(unsigned long param)
445{
446 struct ehci_hcd *ehci = (struct ehci_hcd *) param;
447 unsigned long flags;
448
449 spin_lock_irqsave(&ehci->lock, flags);
450
451 /* stop async processing after it's idled a bit */
452 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
453 start_unlink_async (ehci, ehci->async);
454
455 /* ehci could run by timer, without IRQs ... */
456 ehci_work (ehci);
457
458 spin_unlock_irqrestore (&ehci->lock, flags);
459}
460
461/* On some systems, leaving remote wakeup enabled prevents system shutdown.
462 * The firmware seems to think that powering off is a wakeup event!
463 * This routine turns off remote wakeup and everything else, on all ports.
464 */
465static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
466{
467 int port = HCS_N_PORTS(ehci->hcs_params);
468
469 while (port--)
470 ehci_writel(ehci, PORT_RWC_BITS,
471 &ehci->regs->port_status[port]);
472}
473
474/*
475 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
476 * Should be called with ehci->lock held.
477 */
478static void ehci_silence_controller(struct ehci_hcd *ehci)
479{
480 ehci_halt(ehci);
481 ehci_turn_off_all_ports(ehci);
482
483 /* make BIOS/etc use companion controller during reboot */
484 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
485
486 /* unblock posted writes */
487 ehci_readl(ehci, &ehci->regs->configured_flag);
488}
489
490/* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
491 * This forcibly disables dma and IRQs, helping kexec and other cases
492 * where the next system software may expect clean state.
493 */
494static void ehci_shutdown(struct usb_hcd *hcd)
495{
496 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
497
498 del_timer_sync(&ehci->watchdog);
499 del_timer_sync(&ehci->iaa_watchdog);
500
501 spin_lock_irq(&ehci->lock);
502 ehci_silence_controller(ehci);
503 spin_unlock_irq(&ehci->lock);
504}
505
506static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
507{
508 unsigned port;
509
510 if (!HCS_PPC (ehci->hcs_params))
511 return;
512
513 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
514 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
515 (void) ehci_hub_control(ehci_to_hcd(ehci),
516 is_on ? SetPortFeature : ClearPortFeature,
517 USB_PORT_FEAT_POWER,
518 port--, NULL, 0);
519 /* Flush those writes */
520 ehci_readl(ehci, &ehci->regs->command);
521 msleep(20);
522}
523
524/*-------------------------------------------------------------------------*/
525
526/*
527 * ehci_work is called from some interrupts, timers, and so on.
528 * it calls driver completion functions, after dropping ehci->lock.
529 */
530static void ehci_work (struct ehci_hcd *ehci)
531{
532 timer_action_done (ehci, TIMER_IO_WATCHDOG);
533
534 /* another CPU may drop ehci->lock during a schedule scan while
535 * it reports urb completions. this flag guards against bogus
536 * attempts at re-entrant schedule scanning.
537 */
538 if (ehci->scanning)
539 return;
540 ehci->scanning = 1;
541 scan_async (ehci);
542 if (ehci->next_uframe != -1)
543 scan_periodic (ehci);
544 ehci->scanning = 0;
545
546 /* the IO watchdog guards against hardware or driver bugs that
547 * misplace IRQs, and should let us run completely without IRQs.
548 * such lossage has been observed on both VT6202 and VT8235.
549 */
550 if (ehci->rh_state == EHCI_RH_RUNNING &&
551 (ehci->async->qh_next.ptr != NULL ||
552 ehci->periodic_sched != 0))
553 timer_action (ehci, TIMER_IO_WATCHDOG);
554}
555
556/*
557 * Called when the ehci_hcd module is removed.
558 */
559static void ehci_stop (struct usb_hcd *hcd)
560{
561 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
562
563 ehci_dbg (ehci, "stop\n");
564
565 /* no more interrupts ... */
566 del_timer_sync (&ehci->watchdog);
567 del_timer_sync(&ehci->iaa_watchdog);
568
569 spin_lock_irq(&ehci->lock);
570 if (ehci->rh_state == EHCI_RH_RUNNING)
571 ehci_quiesce (ehci);
572
573 ehci_silence_controller(ehci);
574 ehci_reset (ehci);
575 spin_unlock_irq(&ehci->lock);
576
577 remove_sysfs_files(ehci);
578 remove_debug_files (ehci);
579
580 /* root hub is shut down separately (first, when possible) */
581 spin_lock_irq (&ehci->lock);
582 if (ehci->async)
583 ehci_work (ehci);
584 spin_unlock_irq (&ehci->lock);
585 ehci_mem_cleanup (ehci);
586
587 if (ehci->amd_pll_fix == 1)
588 usb_amd_dev_put();
589
590#ifdef EHCI_STATS
591 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
592 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
593 ehci->stats.lost_iaa);
594 ehci_dbg (ehci, "complete %ld unlink %ld\n",
595 ehci->stats.complete, ehci->stats.unlink);
596#endif
597
598 dbg_status (ehci, "ehci_stop completed",
599 ehci_readl(ehci, &ehci->regs->status));
600}
601
602/* one-time init, only for memory state */
603static int ehci_init(struct usb_hcd *hcd)
604{
605 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
606 u32 temp;
607 int retval;
608 u32 hcc_params;
609 struct ehci_qh_hw *hw;
610
611 spin_lock_init(&ehci->lock);
612
613 /*
614 * keep io watchdog by default, those good HCDs could turn off it later
615 */
616 ehci->need_io_watchdog = 1;
617 init_timer(&ehci->watchdog);
618 ehci->watchdog.function = ehci_watchdog;
619 ehci->watchdog.data = (unsigned long) ehci;
620
621 init_timer(&ehci->iaa_watchdog);
622 ehci->iaa_watchdog.function = ehci_iaa_watchdog;
623 ehci->iaa_watchdog.data = (unsigned long) ehci;
624
625 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
626
627 /*
628 * by default set standard 80% (== 100 usec/uframe) max periodic
629 * bandwidth as required by USB 2.0
630 */
631 ehci->uframe_periodic_max = 100;
632
633 /*
634 * hw default: 1K periodic list heads, one per frame.
635 * periodic_size can shrink by USBCMD update if hcc_params allows.
636 */
637 ehci->periodic_size = DEFAULT_I_TDPS;
638 INIT_LIST_HEAD(&ehci->cached_itd_list);
639 INIT_LIST_HEAD(&ehci->cached_sitd_list);
640
641 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
642 /* periodic schedule size can be smaller than default */
643 switch (EHCI_TUNE_FLS) {
644 case 0: ehci->periodic_size = 1024; break;
645 case 1: ehci->periodic_size = 512; break;
646 case 2: ehci->periodic_size = 256; break;
647 default: BUG();
648 }
649 }
650 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
651 return retval;
652
653 /* controllers may cache some of the periodic schedule ... */
654 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
655 ehci->i_thresh = 2 + 8;
656 else // N microframes cached
657 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
658
659 ehci->reclaim = NULL;
660 ehci->next_uframe = -1;
661 ehci->clock_frame = -1;
662
663 /*
664 * dedicate a qh for the async ring head, since we couldn't unlink
665 * a 'real' qh without stopping the async schedule [4.8]. use it
666 * as the 'reclamation list head' too.
667 * its dummy is used in hw_alt_next of many tds, to prevent the qh
668 * from automatically advancing to the next td after short reads.
669 */
670 ehci->async->qh_next.qh = NULL;
671 hw = ehci->async->hw;
672 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
673 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
674#if defined(CONFIG_PPC_PS3)
675 hw->hw_info1 |= cpu_to_hc32(ehci, (1 << 7)); /* I = 1 */
676#endif
677 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
678 hw->hw_qtd_next = EHCI_LIST_END(ehci);
679 ehci->async->qh_state = QH_STATE_LINKED;
680 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
681
682 /* clear interrupt enables, set irq latency */
683 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
684 log2_irq_thresh = 0;
685 temp = 1 << (16 + log2_irq_thresh);
686 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
687 ehci->has_ppcd = 1;
688 ehci_dbg(ehci, "enable per-port change event\n");
689 temp |= CMD_PPCEE;
690 }
691 if (HCC_CANPARK(hcc_params)) {
692 /* HW default park == 3, on hardware that supports it (like
693 * NVidia and ALI silicon), maximizes throughput on the async
694 * schedule by avoiding QH fetches between transfers.
695 *
696 * With fast usb storage devices and NForce2, "park" seems to
697 * make problems: throughput reduction (!), data errors...
698 */
699 if (park) {
700 park = min(park, (unsigned) 3);
701 temp |= CMD_PARK;
702 temp |= park << 8;
703 }
704 ehci_dbg(ehci, "park %d\n", park);
705 }
706 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
707 /* periodic schedule size can be smaller than default */
708 temp &= ~(3 << 2);
709 temp |= (EHCI_TUNE_FLS << 2);
710 }
711 if (HCC_LPM(hcc_params)) {
712 /* support link power management EHCI 1.1 addendum */
713 ehci_dbg(ehci, "support lpm\n");
714 ehci->has_lpm = 1;
715 if (hird > 0xf) {
716 ehci_dbg(ehci, "hird %d invalid, use default 0",
717 hird);
718 hird = 0;
719 }
720 temp |= hird << 24;
721 }
722 ehci->command = temp;
723
724 /* Accept arbitrarily long scatter-gather lists */
725 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
726 hcd->self.sg_tablesize = ~0;
727 return 0;
728}
729
730/* start HC running; it's halted, ehci_init() has been run (once) */
731static int ehci_run (struct usb_hcd *hcd)
732{
733 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
734 u32 temp;
735 u32 hcc_params;
736
737 hcd->uses_new_polling = 1;
738
739 /* EHCI spec section 4.1 */
740
741 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
742 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
743
744 /*
745 * hcc_params controls whether ehci->regs->segment must (!!!)
746 * be used; it constrains QH/ITD/SITD and QTD locations.
747 * pci_pool consistent memory always uses segment zero.
748 * streaming mappings for I/O buffers, like pci_map_single(),
749 * can return segments above 4GB, if the device allows.
750 *
751 * NOTE: the dma mask is visible through dma_supported(), so
752 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
753 * Scsi_Host.highmem_io, and so forth. It's readonly to all
754 * host side drivers though.
755 */
756 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
757 if (HCC_64BIT_ADDR(hcc_params)) {
758 ehci_writel(ehci, 0, &ehci->regs->segment);
759#if 0
760// this is deeply broken on almost all architectures
761 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
762 ehci_info(ehci, "enabled 64bit DMA\n");
763#endif
764 }
765
766
767 // Philips, Intel, and maybe others need CMD_RUN before the
768 // root hub will detect new devices (why?); NEC doesn't
769 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
770 ehci->command |= CMD_RUN;
771 ehci_writel(ehci, ehci->command, &ehci->regs->command);
772 dbg_cmd (ehci, "init", ehci->command);
773
774 /*
775 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
776 * are explicitly handed to companion controller(s), so no TT is
777 * involved with the root hub. (Except where one is integrated,
778 * and there's no companion controller unless maybe for USB OTG.)
779 *
780 * Turning on the CF flag will transfer ownership of all ports
781 * from the companions to the EHCI controller. If any of the
782 * companions are in the middle of a port reset at the time, it
783 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
784 * guarantees that no resets are in progress. After we set CF,
785 * a short delay lets the hardware catch up; new resets shouldn't
786 * be started before the port switching actions could complete.
787 */
788 down_write(&ehci_cf_port_reset_rwsem);
789 ehci->rh_state = EHCI_RH_RUNNING;
790 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
791 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
792 msleep(5);
793 up_write(&ehci_cf_port_reset_rwsem);
794 ehci->last_periodic_enable = ktime_get_real();
795
796 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
797 ehci_info (ehci,
798 "USB %x.%x started, EHCI %x.%02x%s\n",
799 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
800 temp >> 8, temp & 0xff,
801 ignore_oc ? ", overcurrent ignored" : "");
802
803 ehci_writel(ehci, INTR_MASK,
804 &ehci->regs->intr_enable); /* Turn On Interrupts */
805
806 /* GRR this is run-once init(), being done every time the HC starts.
807 * So long as they're part of class devices, we can't do it init()
808 * since the class device isn't created that early.
809 */
810 create_debug_files(ehci);
811 create_sysfs_files(ehci);
812
813 return 0;
814}
815
816static int __maybe_unused ehci_setup (struct usb_hcd *hcd)
817{
818 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
819 int retval;
820
821 ehci->regs = (void __iomem *)ehci->caps +
822 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
823 dbg_hcs_params(ehci, "reset");
824 dbg_hcc_params(ehci, "reset");
825
826 /* cache this readonly data; minimize chip reads */
827 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
828
829 ehci->sbrn = HCD_USB2;
830
831 retval = ehci_halt(ehci);
832 if (retval)
833 return retval;
834
835 /* data structure init */
836 retval = ehci_init(hcd);
837 if (retval)
838 return retval;
839
840 ehci_reset(ehci);
841
842 return 0;
843}
844
845/*-------------------------------------------------------------------------*/
846
847static irqreturn_t ehci_irq (struct usb_hcd *hcd)
848{
849 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
850 u32 status, masked_status, pcd_status = 0, cmd;
851 int bh;
852
853 spin_lock (&ehci->lock);
854
855 status = ehci_readl(ehci, &ehci->regs->status);
856
857 /* e.g. cardbus physical eject */
858 if (status == ~(u32) 0) {
859 ehci_dbg (ehci, "device removed\n");
860 goto dead;
861 }
862
863 /*
864 * We don't use STS_FLR, but some controllers don't like it to
865 * remain on, so mask it out along with the other status bits.
866 */
867 masked_status = status & (INTR_MASK | STS_FLR);
868
869 /* Shared IRQ? */
870 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
871 spin_unlock(&ehci->lock);
872 return IRQ_NONE;
873 }
874
875 /* clear (just) interrupts */
876 ehci_writel(ehci, masked_status, &ehci->regs->status);
877 cmd = ehci_readl(ehci, &ehci->regs->command);
878 bh = 0;
879
880#ifdef VERBOSE_DEBUG
881 /* unrequested/ignored: Frame List Rollover */
882 dbg_status (ehci, "irq", status);
883#endif
884
885 /* INT, ERR, and IAA interrupt rates can be throttled */
886
887 /* normal [4.15.1.2] or error [4.15.1.1] completion */
888 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
889 if (likely ((status & STS_ERR) == 0))
890 COUNT (ehci->stats.normal);
891 else
892 COUNT (ehci->stats.error);
893 bh = 1;
894 }
895
896 /* complete the unlinking of some qh [4.15.2.3] */
897 if (status & STS_IAA) {
898 /* guard against (alleged) silicon errata */
899 if (cmd & CMD_IAAD)
900 ehci_dbg(ehci, "IAA with IAAD still set?\n");
901 if (ehci->reclaim) {
902 COUNT(ehci->stats.reclaim);
903 end_unlink_async(ehci);
904 } else
905 ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
906 }
907
908 /* remote wakeup [4.3.1] */
909 if (status & STS_PCD) {
910 unsigned i = HCS_N_PORTS (ehci->hcs_params);
911 u32 ppcd = 0;
912
913 /* kick root hub later */
914 pcd_status = status;
915
916 /* resume root hub? */
917 if (ehci->rh_state == EHCI_RH_SUSPENDED)
918 usb_hcd_resume_root_hub(hcd);
919
920 /* get per-port change detect bits */
921 if (ehci->has_ppcd)
922 ppcd = status >> 16;
923
924 while (i--) {
925 int pstatus;
926
927 /* leverage per-port change bits feature */
928 if (ehci->has_ppcd && !(ppcd & (1 << i)))
929 continue;
930 pstatus = ehci_readl(ehci,
931 &ehci->regs->port_status[i]);
932
933 if (pstatus & PORT_OWNER)
934 continue;
935 if (!(test_bit(i, &ehci->suspended_ports) &&
936 ((pstatus & PORT_RESUME) ||
937 !(pstatus & PORT_SUSPEND)) &&
938 (pstatus & PORT_PE) &&
939 ehci->reset_done[i] == 0))
940 continue;
941
942 /* start 20 msec resume signaling from this port,
943 * and make khubd collect PORT_STAT_C_SUSPEND to
944 * stop that signaling. Use 5 ms extra for safety,
945 * like usb_port_resume() does.
946 */
947 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
948 set_bit(i, &ehci->resuming_ports);
949 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
950 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
951 }
952 }
953
954 /* PCI errors [4.15.2.4] */
955 if (unlikely ((status & STS_FATAL) != 0)) {
956 ehci_err(ehci, "fatal error\n");
957 dbg_cmd(ehci, "fatal", cmd);
958 dbg_status(ehci, "fatal", status);
959 ehci_halt(ehci);
960dead:
961 ehci_reset(ehci);
962 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
963 usb_hc_died(hcd);
964 /* generic layer kills/unlinks all urbs, then
965 * uses ehci_stop to clean up the rest
966 */
967 bh = 1;
968 }
969
970 if (bh)
971 ehci_work (ehci);
972 spin_unlock (&ehci->lock);
973 if (pcd_status)
974 usb_hcd_poll_rh_status(hcd);
975 return IRQ_HANDLED;
976}
977
978/*-------------------------------------------------------------------------*/
979
980/*
981 * non-error returns are a promise to giveback() the urb later
982 * we drop ownership so next owner (or urb unlink) can get it
983 *
984 * urb + dev is in hcd.self.controller.urb_list
985 * we're queueing TDs onto software and hardware lists
986 *
987 * hcd-specific init for hcpriv hasn't been done yet
988 *
989 * NOTE: control, bulk, and interrupt share the same code to append TDs
990 * to a (possibly active) QH, and the same QH scanning code.
991 */
992static int ehci_urb_enqueue (
993 struct usb_hcd *hcd,
994 struct urb *urb,
995 gfp_t mem_flags
996) {
997 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
998 struct list_head qtd_list;
999
1000 INIT_LIST_HEAD (&qtd_list);
1001
1002 switch (usb_pipetype (urb->pipe)) {
1003 case PIPE_CONTROL:
1004 /* qh_completions() code doesn't handle all the fault cases
1005 * in multi-TD control transfers. Even 1KB is rare anyway.
1006 */
1007 if (urb->transfer_buffer_length > (16 * 1024))
1008 return -EMSGSIZE;
1009 /* FALLTHROUGH */
1010 /* case PIPE_BULK: */
1011 default:
1012 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1013 return -ENOMEM;
1014 return submit_async(ehci, urb, &qtd_list, mem_flags);
1015
1016 case PIPE_INTERRUPT:
1017 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
1018 return -ENOMEM;
1019 return intr_submit(ehci, urb, &qtd_list, mem_flags);
1020
1021 case PIPE_ISOCHRONOUS:
1022 if (urb->dev->speed == USB_SPEED_HIGH)
1023 return itd_submit (ehci, urb, mem_flags);
1024 else
1025 return sitd_submit (ehci, urb, mem_flags);
1026 }
1027}
1028
1029static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
1030{
1031 /* failfast */
1032 if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim)
1033 end_unlink_async(ehci);
1034
1035 /* If the QH isn't linked then there's nothing we can do
1036 * unless we were called during a giveback, in which case
1037 * qh_completions() has to deal with it.
1038 */
1039 if (qh->qh_state != QH_STATE_LINKED) {
1040 if (qh->qh_state == QH_STATE_COMPLETING)
1041 qh->needs_rescan = 1;
1042 return;
1043 }
1044
1045 /* defer till later if busy */
1046 if (ehci->reclaim) {
1047 struct ehci_qh *last;
1048
1049 for (last = ehci->reclaim;
1050 last->reclaim;
1051 last = last->reclaim)
1052 continue;
1053 qh->qh_state = QH_STATE_UNLINK_WAIT;
1054 last->reclaim = qh;
1055
1056 /* start IAA cycle */
1057 } else
1058 start_unlink_async (ehci, qh);
1059}
1060
1061/* remove from hardware lists
1062 * completions normally happen asynchronously
1063 */
1064
1065static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1066{
1067 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1068 struct ehci_qh *qh;
1069 unsigned long flags;
1070 int rc;
1071
1072 spin_lock_irqsave (&ehci->lock, flags);
1073 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
1074 if (rc)
1075 goto done;
1076
1077 switch (usb_pipetype (urb->pipe)) {
1078 // case PIPE_CONTROL:
1079 // case PIPE_BULK:
1080 default:
1081 qh = (struct ehci_qh *) urb->hcpriv;
1082 if (!qh)
1083 break;
1084 switch (qh->qh_state) {
1085 case QH_STATE_LINKED:
1086 case QH_STATE_COMPLETING:
1087 unlink_async(ehci, qh);
1088 break;
1089 case QH_STATE_UNLINK:
1090 case QH_STATE_UNLINK_WAIT:
1091 /* already started */
1092 break;
1093 case QH_STATE_IDLE:
1094 /* QH might be waiting for a Clear-TT-Buffer */
1095 qh_completions(ehci, qh);
1096 break;
1097 }
1098 break;
1099
1100 case PIPE_INTERRUPT:
1101 qh = (struct ehci_qh *) urb->hcpriv;
1102 if (!qh)
1103 break;
1104 switch (qh->qh_state) {
1105 case QH_STATE_LINKED:
1106 case QH_STATE_COMPLETING:
1107 intr_deschedule (ehci, qh);
1108 break;
1109 case QH_STATE_IDLE:
1110 qh_completions (ehci, qh);
1111 break;
1112 default:
1113 ehci_dbg (ehci, "bogus qh %p state %d\n",
1114 qh, qh->qh_state);
1115 goto done;
1116 }
1117 break;
1118
1119 case PIPE_ISOCHRONOUS:
1120 // itd or sitd ...
1121
1122 // wait till next completion, do it then.
1123 // completion irqs can wait up to 1024 msec,
1124 break;
1125 }
1126done:
1127 spin_unlock_irqrestore (&ehci->lock, flags);
1128 return rc;
1129}
1130
1131/*-------------------------------------------------------------------------*/
1132
1133// bulk qh holds the data toggle
1134
1135static void
1136ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1137{
1138 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1139 unsigned long flags;
1140 struct ehci_qh *qh, *tmp;
1141
1142 /* ASSERT: any requests/urbs are being unlinked */
1143 /* ASSERT: nobody can be submitting urbs for this any more */
1144
1145rescan:
1146 spin_lock_irqsave (&ehci->lock, flags);
1147 qh = ep->hcpriv;
1148 if (!qh)
1149 goto done;
1150
1151 /* endpoints can be iso streams. for now, we don't
1152 * accelerate iso completions ... so spin a while.
1153 */
1154 if (qh->hw == NULL) {
1155 ehci_vdbg (ehci, "iso delay\n");
1156 goto idle_timeout;
1157 }
1158
1159 if (ehci->rh_state != EHCI_RH_RUNNING)
1160 qh->qh_state = QH_STATE_IDLE;
1161 switch (qh->qh_state) {
1162 case QH_STATE_LINKED:
1163 case QH_STATE_COMPLETING:
1164 for (tmp = ehci->async->qh_next.qh;
1165 tmp && tmp != qh;
1166 tmp = tmp->qh_next.qh)
1167 continue;
1168 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1169 * may already be unlinked.
1170 */
1171 if (tmp)
1172 unlink_async(ehci, qh);
1173 /* FALL THROUGH */
1174 case QH_STATE_UNLINK: /* wait for hw to finish? */
1175 case QH_STATE_UNLINK_WAIT:
1176idle_timeout:
1177 spin_unlock_irqrestore (&ehci->lock, flags);
1178 schedule_timeout_uninterruptible(1);
1179 goto rescan;
1180 case QH_STATE_IDLE: /* fully unlinked */
1181 if (qh->clearing_tt)
1182 goto idle_timeout;
1183 if (list_empty (&qh->qtd_list)) {
1184 qh_put (qh);
1185 break;
1186 }
1187 /* else FALL THROUGH */
1188 default:
1189 /* caller was supposed to have unlinked any requests;
1190 * that's not our job. just leak this memory.
1191 */
1192 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1193 qh, ep->desc.bEndpointAddress, qh->qh_state,
1194 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1195 break;
1196 }
1197 ep->hcpriv = NULL;
1198done:
1199 spin_unlock_irqrestore (&ehci->lock, flags);
1200}
1201
1202static void
1203ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1204{
1205 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1206 struct ehci_qh *qh;
1207 int eptype = usb_endpoint_type(&ep->desc);
1208 int epnum = usb_endpoint_num(&ep->desc);
1209 int is_out = usb_endpoint_dir_out(&ep->desc);
1210 unsigned long flags;
1211
1212 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1213 return;
1214
1215 spin_lock_irqsave(&ehci->lock, flags);
1216 qh = ep->hcpriv;
1217
1218 /* For Bulk and Interrupt endpoints we maintain the toggle state
1219 * in the hardware; the toggle bits in udev aren't used at all.
1220 * When an endpoint is reset by usb_clear_halt() we must reset
1221 * the toggle bit in the QH.
1222 */
1223 if (qh) {
1224 usb_settoggle(qh->dev, epnum, is_out, 0);
1225 if (!list_empty(&qh->qtd_list)) {
1226 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1227 } else if (qh->qh_state == QH_STATE_LINKED ||
1228 qh->qh_state == QH_STATE_COMPLETING) {
1229
1230 /* The toggle value in the QH can't be updated
1231 * while the QH is active. Unlink it now;
1232 * re-linking will call qh_refresh().
1233 */
1234 if (eptype == USB_ENDPOINT_XFER_BULK)
1235 unlink_async(ehci, qh);
1236 else
1237 intr_deschedule(ehci, qh);
1238 }
1239 }
1240 spin_unlock_irqrestore(&ehci->lock, flags);
1241}
1242
1243static int ehci_get_frame (struct usb_hcd *hcd)
1244{
1245 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1246 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1247}
1248
1249/*-------------------------------------------------------------------------*/
1250/*
1251 * The EHCI in ChipIdea HDRC cannot be a separate module or device,
1252 * because its registers (and irq) are shared between host/gadget/otg
1253 * functions and in order to facilitate role switching we cannot
1254 * give the ehci driver exclusive access to those.
1255 */
1256#ifndef CHIPIDEA_EHCI
1257
1258MODULE_DESCRIPTION(DRIVER_DESC);
1259MODULE_AUTHOR (DRIVER_AUTHOR);
1260MODULE_LICENSE ("GPL");
1261
1262#ifdef CONFIG_PCI
1263#include "ehci-pci.c"
1264#define PCI_DRIVER ehci_pci_driver
1265#endif
1266
1267#ifdef CONFIG_USB_EHCI_FSL
1268#include "ehci-fsl.c"
1269#define PLATFORM_DRIVER ehci_fsl_driver
1270#endif
1271
1272#ifdef CONFIG_USB_EHCI_MXC
1273#include "ehci-mxc.c"
1274#define PLATFORM_DRIVER ehci_mxc_driver
1275#endif
1276
1277#ifdef CONFIG_USB_EHCI_SH
1278#include "ehci-sh.c"
1279#define PLATFORM_DRIVER ehci_hcd_sh_driver
1280#endif
1281
1282#ifdef CONFIG_MIPS_ALCHEMY
1283#include "ehci-au1xxx.c"
1284#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1285#endif
1286
1287#ifdef CONFIG_USB_EHCI_HCD_OMAP
1288#include "ehci-omap.c"
1289#define PLATFORM_DRIVER ehci_hcd_omap_driver
1290#endif
1291
1292#ifdef CONFIG_PPC_PS3
1293#include "ehci-ps3.c"
1294#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1295#endif
1296
1297#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1298#include "ehci-ppc-of.c"
1299#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1300#endif
1301
1302#ifdef CONFIG_XPS_USB_HCD_XILINX
1303#include "ehci-xilinx-of.c"
1304#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1305#endif
1306
1307#ifdef CONFIG_PLAT_ORION
1308#include "ehci-orion.c"
1309#define PLATFORM_DRIVER ehci_orion_driver
1310#endif
1311
1312#ifdef CONFIG_ARCH_IXP4XX
1313#include "ehci-ixp4xx.c"
1314#define PLATFORM_DRIVER ixp4xx_ehci_driver
1315#endif
1316
1317#ifdef CONFIG_USB_W90X900_EHCI
1318#include "ehci-w90x900.c"
1319#define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1320#endif
1321
1322#ifdef CONFIG_ARCH_AT91
1323#include "ehci-atmel.c"
1324#define PLATFORM_DRIVER ehci_atmel_driver
1325#endif
1326
1327#ifdef CONFIG_USB_OCTEON_EHCI
1328#include "ehci-octeon.c"
1329#define PLATFORM_DRIVER ehci_octeon_driver
1330#endif
1331
1332#ifdef CONFIG_USB_CNS3XXX_EHCI
1333#include "ehci-cns3xxx.c"
1334#define PLATFORM_DRIVER cns3xxx_ehci_driver
1335#endif
1336
1337#ifdef CONFIG_ARCH_VT8500
1338#include "ehci-vt8500.c"
1339#define PLATFORM_DRIVER vt8500_ehci_driver
1340#endif
1341
1342#ifdef CONFIG_PLAT_SPEAR
1343#include "ehci-spear.c"
1344#define PLATFORM_DRIVER spear_ehci_hcd_driver
1345#endif
1346
1347#ifdef CONFIG_USB_EHCI_MSM
1348#include "ehci-msm.c"
1349#define PLATFORM_DRIVER ehci_msm_driver
1350#endif
1351
1352#ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1353#include "ehci-pmcmsp.c"
1354#define PLATFORM_DRIVER ehci_hcd_msp_driver
1355#endif
1356
1357#ifdef CONFIG_USB_EHCI_TEGRA
1358#include "ehci-tegra.c"
1359#define PLATFORM_DRIVER tegra_ehci_driver
1360#endif
1361
1362#ifdef CONFIG_USB_EHCI_S5P
1363#include "ehci-s5p.c"
1364#define PLATFORM_DRIVER s5p_ehci_driver
1365#endif
1366
1367#ifdef CONFIG_SPARC_LEON
1368#include "ehci-grlib.c"
1369#define PLATFORM_DRIVER ehci_grlib_driver
1370#endif
1371
1372#ifdef CONFIG_CPU_XLR
1373#include "ehci-xls.c"
1374#define PLATFORM_DRIVER ehci_xls_driver
1375#endif
1376
1377#ifdef CONFIG_USB_EHCI_MV
1378#include "ehci-mv.c"
1379#define PLATFORM_DRIVER ehci_mv_driver
1380#endif
1381
1382#ifdef CONFIG_MACH_LOONGSON1
1383#include "ehci-ls1x.c"
1384#define PLATFORM_DRIVER ehci_ls1x_driver
1385#endif
1386
1387#ifdef CONFIG_MIPS_SEAD3
1388#include "ehci-sead3.c"
1389#define PLATFORM_DRIVER ehci_hcd_sead3_driver
1390#endif
1391
1392#ifdef CONFIG_USB_EHCI_HCD_PLATFORM
1393#include "ehci-platform.c"
1394#define PLATFORM_DRIVER ehci_platform_driver
1395#endif
1396
1397#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1398 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1399 !defined(XILINX_OF_PLATFORM_DRIVER)
1400#error "missing bus glue for ehci-hcd"
1401#endif
1402
1403static int __init ehci_hcd_init(void)
1404{
1405 int retval = 0;
1406
1407 if (usb_disabled())
1408 return -ENODEV;
1409
1410 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1411 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1412 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1413 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1414 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1415 " before uhci_hcd and ohci_hcd, not after\n");
1416
1417 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1418 hcd_name,
1419 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1420 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1421
1422#ifdef DEBUG
1423 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1424 if (!ehci_debug_root) {
1425 retval = -ENOENT;
1426 goto err_debug;
1427 }
1428#endif
1429
1430#ifdef PLATFORM_DRIVER
1431 retval = platform_driver_register(&PLATFORM_DRIVER);
1432 if (retval < 0)
1433 goto clean0;
1434#endif
1435
1436#ifdef PCI_DRIVER
1437 retval = pci_register_driver(&PCI_DRIVER);
1438 if (retval < 0)
1439 goto clean1;
1440#endif
1441
1442#ifdef PS3_SYSTEM_BUS_DRIVER
1443 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1444 if (retval < 0)
1445 goto clean2;
1446#endif
1447
1448#ifdef OF_PLATFORM_DRIVER
1449 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1450 if (retval < 0)
1451 goto clean3;
1452#endif
1453
1454#ifdef XILINX_OF_PLATFORM_DRIVER
1455 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1456 if (retval < 0)
1457 goto clean4;
1458#endif
1459 return retval;
1460
1461#ifdef XILINX_OF_PLATFORM_DRIVER
1462 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1463clean4:
1464#endif
1465#ifdef OF_PLATFORM_DRIVER
1466 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1467clean3:
1468#endif
1469#ifdef PS3_SYSTEM_BUS_DRIVER
1470 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1471clean2:
1472#endif
1473#ifdef PCI_DRIVER
1474 pci_unregister_driver(&PCI_DRIVER);
1475clean1:
1476#endif
1477#ifdef PLATFORM_DRIVER
1478 platform_driver_unregister(&PLATFORM_DRIVER);
1479clean0:
1480#endif
1481#ifdef DEBUG
1482 debugfs_remove(ehci_debug_root);
1483 ehci_debug_root = NULL;
1484err_debug:
1485#endif
1486 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1487 return retval;
1488}
1489module_init(ehci_hcd_init);
1490
1491static void __exit ehci_hcd_cleanup(void)
1492{
1493#ifdef XILINX_OF_PLATFORM_DRIVER
1494 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1495#endif
1496#ifdef OF_PLATFORM_DRIVER
1497 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1498#endif
1499#ifdef PLATFORM_DRIVER
1500 platform_driver_unregister(&PLATFORM_DRIVER);
1501#endif
1502#ifdef PCI_DRIVER
1503 pci_unregister_driver(&PCI_DRIVER);
1504#endif
1505#ifdef PS3_SYSTEM_BUS_DRIVER
1506 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1507#endif
1508#ifdef DEBUG
1509 debugfs_remove(ehci_debug_root);
1510#endif
1511 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1512}
1513module_exit(ehci_hcd_cleanup);
1514
1515#endif /* CHIPIDEA_EHCI */