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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * uartlite.c: Serial driver for Xilinx uartlite serial controller
4 *
5 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
6 * Copyright (C) 2007 Secret Lab Technologies Ltd.
7 */
8
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/bitfield.h>
12#include <linux/console.h>
13#include <linux/serial.h>
14#include <linux/serial_core.h>
15#include <linux/tty.h>
16#include <linux/tty_flip.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/iopoll.h>
22#include <linux/of.h>
23#include <linux/clk.h>
24#include <linux/pm_runtime.h>
25
26#define ULITE_NAME "ttyUL"
27#if CONFIG_SERIAL_UARTLITE_NR_UARTS > 4
28#define ULITE_MAJOR 0 /* use dynamic node allocation */
29#define ULITE_MINOR 0
30#else
31#define ULITE_MAJOR 204
32#define ULITE_MINOR 187
33#endif
34#define ULITE_NR_UARTS CONFIG_SERIAL_UARTLITE_NR_UARTS
35
36/* ---------------------------------------------------------------------
37 * Register definitions
38 *
39 * For register details see datasheet:
40 * https://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
41 */
42
43#define ULITE_RX 0x00
44#define ULITE_TX 0x04
45#define ULITE_STATUS 0x08
46#define ULITE_CONTROL 0x0c
47
48#define ULITE_REGION 16
49
50#define ULITE_STATUS_RXVALID 0x01
51#define ULITE_STATUS_RXFULL 0x02
52#define ULITE_STATUS_TXEMPTY 0x04
53#define ULITE_STATUS_TXFULL 0x08
54#define ULITE_STATUS_IE 0x10
55#define ULITE_STATUS_OVERRUN 0x20
56#define ULITE_STATUS_FRAME 0x40
57#define ULITE_STATUS_PARITY 0x80
58
59#define ULITE_CONTROL_RST_TX 0x01
60#define ULITE_CONTROL_RST_RX 0x02
61#define ULITE_CONTROL_IE 0x10
62#define UART_AUTOSUSPEND_TIMEOUT 3000 /* ms */
63
64/* Static pointer to console port */
65#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
66static struct uart_port *console_port;
67#endif
68
69/**
70 * struct uartlite_data - Driver private data
71 * @reg_ops: Functions to read/write registers
72 * @clk: Our parent clock, if present
73 * @baud: The baud rate configured when this device was synthesized
74 * @cflags: The cflags for parity and data bits
75 */
76struct uartlite_data {
77 const struct uartlite_reg_ops *reg_ops;
78 struct clk *clk;
79 unsigned int baud;
80 tcflag_t cflags;
81};
82
83struct uartlite_reg_ops {
84 u32 (*in)(void __iomem *addr);
85 void (*out)(u32 val, void __iomem *addr);
86};
87
88static u32 uartlite_inbe32(void __iomem *addr)
89{
90 return ioread32be(addr);
91}
92
93static void uartlite_outbe32(u32 val, void __iomem *addr)
94{
95 iowrite32be(val, addr);
96}
97
98static const struct uartlite_reg_ops uartlite_be = {
99 .in = uartlite_inbe32,
100 .out = uartlite_outbe32,
101};
102
103static u32 uartlite_inle32(void __iomem *addr)
104{
105 return ioread32(addr);
106}
107
108static void uartlite_outle32(u32 val, void __iomem *addr)
109{
110 iowrite32(val, addr);
111}
112
113static const struct uartlite_reg_ops uartlite_le = {
114 .in = uartlite_inle32,
115 .out = uartlite_outle32,
116};
117
118static inline u32 uart_in32(u32 offset, struct uart_port *port)
119{
120 struct uartlite_data *pdata = port->private_data;
121
122 return pdata->reg_ops->in(port->membase + offset);
123}
124
125static inline void uart_out32(u32 val, u32 offset, struct uart_port *port)
126{
127 struct uartlite_data *pdata = port->private_data;
128
129 pdata->reg_ops->out(val, port->membase + offset);
130}
131
132static struct uart_port ulite_ports[ULITE_NR_UARTS];
133
134static struct uart_driver ulite_uart_driver;
135
136/* ---------------------------------------------------------------------
137 * Core UART driver operations
138 */
139
140static int ulite_receive(struct uart_port *port, int stat)
141{
142 struct tty_port *tport = &port->state->port;
143 unsigned char ch = 0;
144 char flag = TTY_NORMAL;
145
146 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
147 | ULITE_STATUS_FRAME)) == 0)
148 return 0;
149
150 /* stats */
151 if (stat & ULITE_STATUS_RXVALID) {
152 port->icount.rx++;
153 ch = uart_in32(ULITE_RX, port);
154
155 if (stat & ULITE_STATUS_PARITY)
156 port->icount.parity++;
157 }
158
159 if (stat & ULITE_STATUS_OVERRUN)
160 port->icount.overrun++;
161
162 if (stat & ULITE_STATUS_FRAME)
163 port->icount.frame++;
164
165
166 /* drop byte with parity error if IGNPAR specificed */
167 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
168 stat &= ~ULITE_STATUS_RXVALID;
169
170 stat &= port->read_status_mask;
171
172 if (stat & ULITE_STATUS_PARITY)
173 flag = TTY_PARITY;
174
175
176 stat &= ~port->ignore_status_mask;
177
178 if (stat & ULITE_STATUS_RXVALID)
179 tty_insert_flip_char(tport, ch, flag);
180
181 if (stat & ULITE_STATUS_FRAME)
182 tty_insert_flip_char(tport, 0, TTY_FRAME);
183
184 if (stat & ULITE_STATUS_OVERRUN)
185 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
186
187 return 1;
188}
189
190static int ulite_transmit(struct uart_port *port, int stat)
191{
192 struct circ_buf *xmit = &port->state->xmit;
193
194 if (stat & ULITE_STATUS_TXFULL)
195 return 0;
196
197 if (port->x_char) {
198 uart_out32(port->x_char, ULITE_TX, port);
199 port->x_char = 0;
200 port->icount.tx++;
201 return 1;
202 }
203
204 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
205 return 0;
206
207 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port);
208 uart_xmit_advance(port, 1);
209
210 /* wake up */
211 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
212 uart_write_wakeup(port);
213
214 return 1;
215}
216
217static irqreturn_t ulite_isr(int irq, void *dev_id)
218{
219 struct uart_port *port = dev_id;
220 int stat, busy, n = 0;
221 unsigned long flags;
222
223 do {
224 uart_port_lock_irqsave(port, &flags);
225 stat = uart_in32(ULITE_STATUS, port);
226 busy = ulite_receive(port, stat);
227 busy |= ulite_transmit(port, stat);
228 uart_port_unlock_irqrestore(port, flags);
229 n++;
230 } while (busy);
231
232 /* work done? */
233 if (n > 1) {
234 tty_flip_buffer_push(&port->state->port);
235 return IRQ_HANDLED;
236 } else {
237 return IRQ_NONE;
238 }
239}
240
241static unsigned int ulite_tx_empty(struct uart_port *port)
242{
243 unsigned long flags;
244 unsigned int ret;
245
246 uart_port_lock_irqsave(port, &flags);
247 ret = uart_in32(ULITE_STATUS, port);
248 uart_port_unlock_irqrestore(port, flags);
249
250 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
251}
252
253static unsigned int ulite_get_mctrl(struct uart_port *port)
254{
255 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
256}
257
258static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
259{
260 /* N/A */
261}
262
263static void ulite_stop_tx(struct uart_port *port)
264{
265 /* N/A */
266}
267
268static void ulite_start_tx(struct uart_port *port)
269{
270 ulite_transmit(port, uart_in32(ULITE_STATUS, port));
271}
272
273static void ulite_stop_rx(struct uart_port *port)
274{
275 /* don't forward any more data (like !CREAD) */
276 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
277 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
278}
279
280static void ulite_break_ctl(struct uart_port *port, int ctl)
281{
282 /* N/A */
283}
284
285static int ulite_startup(struct uart_port *port)
286{
287 struct uartlite_data *pdata = port->private_data;
288 int ret;
289
290 ret = clk_enable(pdata->clk);
291 if (ret) {
292 dev_err(port->dev, "Failed to enable clock\n");
293 return ret;
294 }
295
296 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING,
297 "uartlite", port);
298 if (ret)
299 return ret;
300
301 uart_out32(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
302 ULITE_CONTROL, port);
303 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
304
305 return 0;
306}
307
308static void ulite_shutdown(struct uart_port *port)
309{
310 struct uartlite_data *pdata = port->private_data;
311
312 uart_out32(0, ULITE_CONTROL, port);
313 uart_in32(ULITE_CONTROL, port); /* dummy */
314 free_irq(port->irq, port);
315 clk_disable(pdata->clk);
316}
317
318static void ulite_set_termios(struct uart_port *port,
319 struct ktermios *termios,
320 const struct ktermios *old)
321{
322 unsigned long flags;
323 struct uartlite_data *pdata = port->private_data;
324
325 /* Set termios to what the hardware supports */
326 termios->c_iflag &= ~BRKINT;
327 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CSIZE);
328 termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE);
329 tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud);
330
331 uart_port_lock_irqsave(port, &flags);
332
333 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
334 | ULITE_STATUS_TXFULL;
335
336 if (termios->c_iflag & INPCK)
337 port->read_status_mask |=
338 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
339
340 port->ignore_status_mask = 0;
341 if (termios->c_iflag & IGNPAR)
342 port->ignore_status_mask |= ULITE_STATUS_PARITY
343 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
344
345 /* ignore all characters if CREAD is not set */
346 if ((termios->c_cflag & CREAD) == 0)
347 port->ignore_status_mask |=
348 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
349 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
350
351 /* update timeout */
352 uart_update_timeout(port, termios->c_cflag, pdata->baud);
353
354 uart_port_unlock_irqrestore(port, flags);
355}
356
357static const char *ulite_type(struct uart_port *port)
358{
359 return port->type == PORT_UARTLITE ? "uartlite" : NULL;
360}
361
362static void ulite_release_port(struct uart_port *port)
363{
364 release_mem_region(port->mapbase, ULITE_REGION);
365 iounmap(port->membase);
366 port->membase = NULL;
367}
368
369static int ulite_request_port(struct uart_port *port)
370{
371 struct uartlite_data *pdata = port->private_data;
372 int ret;
373
374 pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
375 port, (unsigned long long) port->mapbase);
376
377 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
378 dev_err(port->dev, "Memory region busy\n");
379 return -EBUSY;
380 }
381
382 port->membase = ioremap(port->mapbase, ULITE_REGION);
383 if (!port->membase) {
384 dev_err(port->dev, "Unable to map registers\n");
385 release_mem_region(port->mapbase, ULITE_REGION);
386 return -EBUSY;
387 }
388
389 pdata->reg_ops = &uartlite_be;
390 ret = uart_in32(ULITE_CONTROL, port);
391 uart_out32(ULITE_CONTROL_RST_TX, ULITE_CONTROL, port);
392 ret = uart_in32(ULITE_STATUS, port);
393 /* Endianess detection */
394 if ((ret & ULITE_STATUS_TXEMPTY) != ULITE_STATUS_TXEMPTY)
395 pdata->reg_ops = &uartlite_le;
396
397 return 0;
398}
399
400static void ulite_config_port(struct uart_port *port, int flags)
401{
402 if (!ulite_request_port(port))
403 port->type = PORT_UARTLITE;
404}
405
406static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
407{
408 /* we don't want the core code to modify any port params */
409 return -EINVAL;
410}
411
412static void ulite_pm(struct uart_port *port, unsigned int state,
413 unsigned int oldstate)
414{
415 int ret;
416
417 if (!state) {
418 ret = pm_runtime_get_sync(port->dev);
419 if (ret < 0)
420 dev_err(port->dev, "Failed to enable clocks\n");
421 } else {
422 pm_runtime_mark_last_busy(port->dev);
423 pm_runtime_put_autosuspend(port->dev);
424 }
425}
426
427#ifdef CONFIG_CONSOLE_POLL
428static int ulite_get_poll_char(struct uart_port *port)
429{
430 if (!(uart_in32(ULITE_STATUS, port) & ULITE_STATUS_RXVALID))
431 return NO_POLL_CHAR;
432
433 return uart_in32(ULITE_RX, port);
434}
435
436static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
437{
438 while (uart_in32(ULITE_STATUS, port) & ULITE_STATUS_TXFULL)
439 cpu_relax();
440
441 /* write char to device */
442 uart_out32(ch, ULITE_TX, port);
443}
444#endif
445
446static const struct uart_ops ulite_ops = {
447 .tx_empty = ulite_tx_empty,
448 .set_mctrl = ulite_set_mctrl,
449 .get_mctrl = ulite_get_mctrl,
450 .stop_tx = ulite_stop_tx,
451 .start_tx = ulite_start_tx,
452 .stop_rx = ulite_stop_rx,
453 .break_ctl = ulite_break_ctl,
454 .startup = ulite_startup,
455 .shutdown = ulite_shutdown,
456 .set_termios = ulite_set_termios,
457 .type = ulite_type,
458 .release_port = ulite_release_port,
459 .request_port = ulite_request_port,
460 .config_port = ulite_config_port,
461 .verify_port = ulite_verify_port,
462 .pm = ulite_pm,
463#ifdef CONFIG_CONSOLE_POLL
464 .poll_get_char = ulite_get_poll_char,
465 .poll_put_char = ulite_put_poll_char,
466#endif
467};
468
469/* ---------------------------------------------------------------------
470 * Console driver operations
471 */
472
473#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
474static void ulite_console_wait_tx(struct uart_port *port)
475{
476 u8 val;
477
478 /*
479 * Spin waiting for TX fifo to have space available.
480 * When using the Microblaze Debug Module this can take up to 1s
481 */
482 if (read_poll_timeout_atomic(uart_in32, val, !(val & ULITE_STATUS_TXFULL),
483 0, 1000000, false, ULITE_STATUS, port))
484 dev_warn(port->dev,
485 "timeout waiting for TX buffer empty\n");
486}
487
488static void ulite_console_putchar(struct uart_port *port, unsigned char ch)
489{
490 ulite_console_wait_tx(port);
491 uart_out32(ch, ULITE_TX, port);
492}
493
494static void ulite_console_write(struct console *co, const char *s,
495 unsigned int count)
496{
497 struct uart_port *port = console_port;
498 unsigned long flags;
499 unsigned int ier;
500 int locked = 1;
501
502 if (oops_in_progress) {
503 locked = uart_port_trylock_irqsave(port, &flags);
504 } else
505 uart_port_lock_irqsave(port, &flags);
506
507 /* save and disable interrupt */
508 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE;
509 uart_out32(0, ULITE_CONTROL, port);
510
511 uart_console_write(port, s, count, ulite_console_putchar);
512
513 ulite_console_wait_tx(port);
514
515 /* restore interrupt state */
516 if (ier)
517 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port);
518
519 if (locked)
520 uart_port_unlock_irqrestore(port, flags);
521}
522
523static int ulite_console_setup(struct console *co, char *options)
524{
525 struct uart_port *port = NULL;
526 int baud = 9600;
527 int bits = 8;
528 int parity = 'n';
529 int flow = 'n';
530
531 if (co->index >= 0 && co->index < ULITE_NR_UARTS)
532 port = ulite_ports + co->index;
533
534 /* Has the device been initialized yet? */
535 if (!port || !port->mapbase) {
536 pr_debug("console on ttyUL%i not present\n", co->index);
537 return -ENODEV;
538 }
539
540 console_port = port;
541
542 /* not initialized yet? */
543 if (!port->membase) {
544 if (ulite_request_port(port))
545 return -ENODEV;
546 }
547
548 if (options)
549 uart_parse_options(options, &baud, &parity, &bits, &flow);
550
551 return uart_set_options(port, co, baud, parity, bits, flow);
552}
553
554static struct console ulite_console = {
555 .name = ULITE_NAME,
556 .write = ulite_console_write,
557 .device = uart_console_device,
558 .setup = ulite_console_setup,
559 .flags = CON_PRINTBUFFER,
560 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
561 .data = &ulite_uart_driver,
562};
563
564static void early_uartlite_putc(struct uart_port *port, unsigned char c)
565{
566 /*
567 * Limit how many times we'll spin waiting for TX FIFO status.
568 * This will prevent lockups if the base address is incorrectly
569 * set, or any other issue on the UARTLITE.
570 * This limit is pretty arbitrary, unless we are at about 10 baud
571 * we'll never timeout on a working UART.
572 */
573 unsigned retries = 1000000;
574
575 while (--retries &&
576 (readl(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL))
577 ;
578
579 /* Only attempt the iowrite if we didn't timeout */
580 if (retries)
581 writel(c & 0xff, port->membase + ULITE_TX);
582}
583
584static void early_uartlite_write(struct console *console,
585 const char *s, unsigned n)
586{
587 struct earlycon_device *device = console->data;
588 uart_console_write(&device->port, s, n, early_uartlite_putc);
589}
590
591static int __init early_uartlite_setup(struct earlycon_device *device,
592 const char *options)
593{
594 if (!device->port.membase)
595 return -ENODEV;
596
597 device->con->write = early_uartlite_write;
598 return 0;
599}
600EARLYCON_DECLARE(uartlite, early_uartlite_setup);
601OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup);
602OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup);
603
604#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
605
606static struct uart_driver ulite_uart_driver = {
607 .owner = THIS_MODULE,
608 .driver_name = "uartlite",
609 .dev_name = ULITE_NAME,
610 .major = ULITE_MAJOR,
611 .minor = ULITE_MINOR,
612 .nr = ULITE_NR_UARTS,
613#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
614 .cons = &ulite_console,
615#endif
616};
617
618/* ---------------------------------------------------------------------
619 * Port assignment functions (mapping devices to uart_port structures)
620 */
621
622/** ulite_assign: register a uartlite device with the driver
623 *
624 * @dev: pointer to device structure
625 * @id: requested id number. Pass -1 for automatic port assignment
626 * @base: base address of uartlite registers
627 * @irq: irq number for uartlite
628 * @pdata: private data for uartlite
629 *
630 * Returns: 0 on success, <0 otherwise
631 */
632static int ulite_assign(struct device *dev, int id, phys_addr_t base, int irq,
633 struct uartlite_data *pdata)
634{
635 struct uart_port *port;
636 int rc;
637
638 /* if id = -1; then scan for a free id and use that */
639 if (id < 0) {
640 for (id = 0; id < ULITE_NR_UARTS; id++)
641 if (ulite_ports[id].mapbase == 0)
642 break;
643 }
644 if (id < 0 || id >= ULITE_NR_UARTS) {
645 dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
646 return -EINVAL;
647 }
648
649 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
650 dev_err(dev, "cannot assign to %s%i; it is already in use\n",
651 ULITE_NAME, id);
652 return -EBUSY;
653 }
654
655 port = &ulite_ports[id];
656
657 spin_lock_init(&port->lock);
658 port->fifosize = 16;
659 port->regshift = 2;
660 port->iotype = UPIO_MEM;
661 port->iobase = 1; /* mark port in use */
662 port->mapbase = base;
663 port->membase = NULL;
664 port->ops = &ulite_ops;
665 port->irq = irq;
666 port->flags = UPF_BOOT_AUTOCONF;
667 port->dev = dev;
668 port->type = PORT_UNKNOWN;
669 port->line = id;
670 port->private_data = pdata;
671
672 dev_set_drvdata(dev, port);
673
674 /* Register the port */
675 rc = uart_add_one_port(&ulite_uart_driver, port);
676 if (rc) {
677 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
678 port->mapbase = 0;
679 dev_set_drvdata(dev, NULL);
680 return rc;
681 }
682
683 return 0;
684}
685
686/** ulite_release: register a uartlite device with the driver
687 *
688 * @dev: pointer to device structure
689 */
690static void ulite_release(struct device *dev)
691{
692 struct uart_port *port = dev_get_drvdata(dev);
693
694 if (port) {
695 uart_remove_one_port(&ulite_uart_driver, port);
696 dev_set_drvdata(dev, NULL);
697 port->mapbase = 0;
698 }
699}
700
701/**
702 * ulite_suspend - Stop the device.
703 *
704 * @dev: handle to the device structure.
705 * Return: 0 always.
706 */
707static int __maybe_unused ulite_suspend(struct device *dev)
708{
709 struct uart_port *port = dev_get_drvdata(dev);
710
711 if (port)
712 uart_suspend_port(&ulite_uart_driver, port);
713
714 return 0;
715}
716
717/**
718 * ulite_resume - Resume the device.
719 *
720 * @dev: handle to the device structure.
721 * Return: 0 on success, errno otherwise.
722 */
723static int __maybe_unused ulite_resume(struct device *dev)
724{
725 struct uart_port *port = dev_get_drvdata(dev);
726
727 if (port)
728 uart_resume_port(&ulite_uart_driver, port);
729
730 return 0;
731}
732
733static int __maybe_unused ulite_runtime_suspend(struct device *dev)
734{
735 struct uart_port *port = dev_get_drvdata(dev);
736 struct uartlite_data *pdata = port->private_data;
737
738 clk_disable(pdata->clk);
739 return 0;
740};
741
742static int __maybe_unused ulite_runtime_resume(struct device *dev)
743{
744 struct uart_port *port = dev_get_drvdata(dev);
745 struct uartlite_data *pdata = port->private_data;
746 int ret;
747
748 ret = clk_enable(pdata->clk);
749 if (ret) {
750 dev_err(dev, "Cannot enable clock.\n");
751 return ret;
752 }
753 return 0;
754}
755
756/* ---------------------------------------------------------------------
757 * Platform bus binding
758 */
759
760static const struct dev_pm_ops ulite_pm_ops = {
761 SET_SYSTEM_SLEEP_PM_OPS(ulite_suspend, ulite_resume)
762 SET_RUNTIME_PM_OPS(ulite_runtime_suspend,
763 ulite_runtime_resume, NULL)
764};
765
766#if defined(CONFIG_OF)
767/* Match table for of_platform binding */
768static const struct of_device_id ulite_of_match[] = {
769 { .compatible = "xlnx,opb-uartlite-1.00.b", },
770 { .compatible = "xlnx,xps-uartlite-1.00.a", },
771 {}
772};
773MODULE_DEVICE_TABLE(of, ulite_of_match);
774#endif /* CONFIG_OF */
775
776static int ulite_probe(struct platform_device *pdev)
777{
778 struct resource *res;
779 struct uartlite_data *pdata;
780 int irq, ret;
781 int id = pdev->id;
782
783 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data),
784 GFP_KERNEL);
785 if (!pdata)
786 return -ENOMEM;
787
788 if (IS_ENABLED(CONFIG_OF)) {
789 const char *prop;
790 struct device_node *np = pdev->dev.of_node;
791 u32 val = 0;
792
793 prop = "port-number";
794 ret = of_property_read_u32(np, prop, &id);
795 if (ret && ret != -EINVAL)
796of_err:
797 return dev_err_probe(&pdev->dev, ret,
798 "could not read %s\n", prop);
799
800 prop = "current-speed";
801 ret = of_property_read_u32(np, prop, &pdata->baud);
802 if (ret)
803 goto of_err;
804
805 prop = "xlnx,use-parity";
806 ret = of_property_read_u32(np, prop, &val);
807 if (ret && ret != -EINVAL)
808 goto of_err;
809
810 if (val) {
811 prop = "xlnx,odd-parity";
812 ret = of_property_read_u32(np, prop, &val);
813 if (ret)
814 goto of_err;
815
816 if (val)
817 pdata->cflags |= PARODD;
818 pdata->cflags |= PARENB;
819 }
820
821 val = 8;
822 prop = "xlnx,data-bits";
823 ret = of_property_read_u32(np, prop, &val);
824 if (ret && ret != -EINVAL)
825 goto of_err;
826
827 switch (val) {
828 case 5:
829 pdata->cflags |= CS5;
830 break;
831 case 6:
832 pdata->cflags |= CS6;
833 break;
834 case 7:
835 pdata->cflags |= CS7;
836 break;
837 case 8:
838 pdata->cflags |= CS8;
839 break;
840 default:
841 return dev_err_probe(&pdev->dev, -EINVAL,
842 "bad data bits %d\n", val);
843 }
844 } else {
845 pdata->baud = 9600;
846 pdata->cflags = CS8;
847 }
848
849 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
850 if (!res)
851 return -ENODEV;
852
853 irq = platform_get_irq(pdev, 0);
854 if (irq < 0)
855 return irq;
856
857 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
858 if (IS_ERR(pdata->clk)) {
859 if (PTR_ERR(pdata->clk) != -ENOENT)
860 return PTR_ERR(pdata->clk);
861
862 /*
863 * Clock framework support is optional, continue on
864 * anyways if we don't find a matching clock.
865 */
866 pdata->clk = NULL;
867 }
868
869 ret = clk_prepare_enable(pdata->clk);
870 if (ret) {
871 dev_err(&pdev->dev, "Failed to prepare clock\n");
872 return ret;
873 }
874
875 pm_runtime_use_autosuspend(&pdev->dev);
876 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
877 pm_runtime_set_active(&pdev->dev);
878 pm_runtime_enable(&pdev->dev);
879
880 if (!ulite_uart_driver.state) {
881 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n");
882 ret = uart_register_driver(&ulite_uart_driver);
883 if (ret < 0) {
884 dev_err(&pdev->dev, "Failed to register driver\n");
885 clk_disable_unprepare(pdata->clk);
886 return ret;
887 }
888 }
889
890 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata);
891
892 pm_runtime_mark_last_busy(&pdev->dev);
893 pm_runtime_put_autosuspend(&pdev->dev);
894
895 return ret;
896}
897
898static void ulite_remove(struct platform_device *pdev)
899{
900 struct uart_port *port = dev_get_drvdata(&pdev->dev);
901 struct uartlite_data *pdata = port->private_data;
902
903 clk_disable_unprepare(pdata->clk);
904 ulite_release(&pdev->dev);
905 pm_runtime_disable(&pdev->dev);
906 pm_runtime_set_suspended(&pdev->dev);
907 pm_runtime_dont_use_autosuspend(&pdev->dev);
908}
909
910/* work with hotplug and coldplug */
911MODULE_ALIAS("platform:uartlite");
912
913static struct platform_driver ulite_platform_driver = {
914 .probe = ulite_probe,
915 .remove_new = ulite_remove,
916 .driver = {
917 .name = "uartlite",
918 .of_match_table = of_match_ptr(ulite_of_match),
919 .pm = &ulite_pm_ops,
920 },
921};
922
923/* ---------------------------------------------------------------------
924 * Module setup/teardown
925 */
926
927static int __init ulite_init(void)
928{
929
930 pr_debug("uartlite: calling platform_driver_register()\n");
931 return platform_driver_register(&ulite_platform_driver);
932}
933
934static void __exit ulite_exit(void)
935{
936 platform_driver_unregister(&ulite_platform_driver);
937 if (ulite_uart_driver.state)
938 uart_unregister_driver(&ulite_uart_driver);
939}
940
941module_init(ulite_init);
942module_exit(ulite_exit);
943
944MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
945MODULE_DESCRIPTION("Xilinx uartlite serial driver");
946MODULE_LICENSE("GPL");
1/*
2 * uartlite.c: Serial driver for Xilinx uartlite serial controller
3 *
4 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2007 Secret Lab Technologies Ltd.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/platform_device.h>
13#include <linux/module.h>
14#include <linux/console.h>
15#include <linux/serial.h>
16#include <linux/serial_core.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/delay.h>
20#include <linux/interrupt.h>
21#include <linux/init.h>
22#include <asm/io.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/of_device.h>
26#include <linux/of_platform.h>
27
28#define ULITE_NAME "ttyUL"
29#define ULITE_MAJOR 204
30#define ULITE_MINOR 187
31#define ULITE_NR_UARTS 4
32
33/* ---------------------------------------------------------------------
34 * Register definitions
35 *
36 * For register details see datasheet:
37 * http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
38 */
39
40#define ULITE_RX 0x00
41#define ULITE_TX 0x04
42#define ULITE_STATUS 0x08
43#define ULITE_CONTROL 0x0c
44
45#define ULITE_REGION 16
46
47#define ULITE_STATUS_RXVALID 0x01
48#define ULITE_STATUS_RXFULL 0x02
49#define ULITE_STATUS_TXEMPTY 0x04
50#define ULITE_STATUS_TXFULL 0x08
51#define ULITE_STATUS_IE 0x10
52#define ULITE_STATUS_OVERRUN 0x20
53#define ULITE_STATUS_FRAME 0x40
54#define ULITE_STATUS_PARITY 0x80
55
56#define ULITE_CONTROL_RST_TX 0x01
57#define ULITE_CONTROL_RST_RX 0x02
58#define ULITE_CONTROL_IE 0x10
59
60
61static struct uart_port ulite_ports[ULITE_NR_UARTS];
62
63/* ---------------------------------------------------------------------
64 * Core UART driver operations
65 */
66
67static int ulite_receive(struct uart_port *port, int stat)
68{
69 struct tty_struct *tty = port->state->port.tty;
70 unsigned char ch = 0;
71 char flag = TTY_NORMAL;
72
73 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
74 | ULITE_STATUS_FRAME)) == 0)
75 return 0;
76
77 /* stats */
78 if (stat & ULITE_STATUS_RXVALID) {
79 port->icount.rx++;
80 ch = ioread32be(port->membase + ULITE_RX);
81
82 if (stat & ULITE_STATUS_PARITY)
83 port->icount.parity++;
84 }
85
86 if (stat & ULITE_STATUS_OVERRUN)
87 port->icount.overrun++;
88
89 if (stat & ULITE_STATUS_FRAME)
90 port->icount.frame++;
91
92
93 /* drop byte with parity error if IGNPAR specificed */
94 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
95 stat &= ~ULITE_STATUS_RXVALID;
96
97 stat &= port->read_status_mask;
98
99 if (stat & ULITE_STATUS_PARITY)
100 flag = TTY_PARITY;
101
102
103 stat &= ~port->ignore_status_mask;
104
105 if (stat & ULITE_STATUS_RXVALID)
106 tty_insert_flip_char(tty, ch, flag);
107
108 if (stat & ULITE_STATUS_FRAME)
109 tty_insert_flip_char(tty, 0, TTY_FRAME);
110
111 if (stat & ULITE_STATUS_OVERRUN)
112 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
113
114 return 1;
115}
116
117static int ulite_transmit(struct uart_port *port, int stat)
118{
119 struct circ_buf *xmit = &port->state->xmit;
120
121 if (stat & ULITE_STATUS_TXFULL)
122 return 0;
123
124 if (port->x_char) {
125 iowrite32be(port->x_char, port->membase + ULITE_TX);
126 port->x_char = 0;
127 port->icount.tx++;
128 return 1;
129 }
130
131 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
132 return 0;
133
134 iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
135 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
136 port->icount.tx++;
137
138 /* wake up */
139 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
140 uart_write_wakeup(port);
141
142 return 1;
143}
144
145static irqreturn_t ulite_isr(int irq, void *dev_id)
146{
147 struct uart_port *port = dev_id;
148 int busy, n = 0;
149
150 do {
151 int stat = ioread32be(port->membase + ULITE_STATUS);
152 busy = ulite_receive(port, stat);
153 busy |= ulite_transmit(port, stat);
154 n++;
155 } while (busy);
156
157 /* work done? */
158 if (n > 1) {
159 tty_flip_buffer_push(port->state->port.tty);
160 return IRQ_HANDLED;
161 } else {
162 return IRQ_NONE;
163 }
164}
165
166static unsigned int ulite_tx_empty(struct uart_port *port)
167{
168 unsigned long flags;
169 unsigned int ret;
170
171 spin_lock_irqsave(&port->lock, flags);
172 ret = ioread32be(port->membase + ULITE_STATUS);
173 spin_unlock_irqrestore(&port->lock, flags);
174
175 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
176}
177
178static unsigned int ulite_get_mctrl(struct uart_port *port)
179{
180 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
181}
182
183static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
184{
185 /* N/A */
186}
187
188static void ulite_stop_tx(struct uart_port *port)
189{
190 /* N/A */
191}
192
193static void ulite_start_tx(struct uart_port *port)
194{
195 ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS));
196}
197
198static void ulite_stop_rx(struct uart_port *port)
199{
200 /* don't forward any more data (like !CREAD) */
201 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
202 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
203}
204
205static void ulite_enable_ms(struct uart_port *port)
206{
207 /* N/A */
208}
209
210static void ulite_break_ctl(struct uart_port *port, int ctl)
211{
212 /* N/A */
213}
214
215static int ulite_startup(struct uart_port *port)
216{
217 int ret;
218
219 ret = request_irq(port->irq, ulite_isr,
220 IRQF_SHARED | IRQF_SAMPLE_RANDOM, "uartlite", port);
221 if (ret)
222 return ret;
223
224 iowrite32be(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
225 port->membase + ULITE_CONTROL);
226 iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
227
228 return 0;
229}
230
231static void ulite_shutdown(struct uart_port *port)
232{
233 iowrite32be(0, port->membase + ULITE_CONTROL);
234 ioread32be(port->membase + ULITE_CONTROL); /* dummy */
235 free_irq(port->irq, port);
236}
237
238static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
239 struct ktermios *old)
240{
241 unsigned long flags;
242 unsigned int baud;
243
244 spin_lock_irqsave(&port->lock, flags);
245
246 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
247 | ULITE_STATUS_TXFULL;
248
249 if (termios->c_iflag & INPCK)
250 port->read_status_mask |=
251 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
252
253 port->ignore_status_mask = 0;
254 if (termios->c_iflag & IGNPAR)
255 port->ignore_status_mask |= ULITE_STATUS_PARITY
256 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
257
258 /* ignore all characters if CREAD is not set */
259 if ((termios->c_cflag & CREAD) == 0)
260 port->ignore_status_mask |=
261 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
262 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
263
264 /* update timeout */
265 baud = uart_get_baud_rate(port, termios, old, 0, 460800);
266 uart_update_timeout(port, termios->c_cflag, baud);
267
268 spin_unlock_irqrestore(&port->lock, flags);
269}
270
271static const char *ulite_type(struct uart_port *port)
272{
273 return port->type == PORT_UARTLITE ? "uartlite" : NULL;
274}
275
276static void ulite_release_port(struct uart_port *port)
277{
278 release_mem_region(port->mapbase, ULITE_REGION);
279 iounmap(port->membase);
280 port->membase = NULL;
281}
282
283static int ulite_request_port(struct uart_port *port)
284{
285 pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
286 port, (unsigned long long) port->mapbase);
287
288 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
289 dev_err(port->dev, "Memory region busy\n");
290 return -EBUSY;
291 }
292
293 port->membase = ioremap(port->mapbase, ULITE_REGION);
294 if (!port->membase) {
295 dev_err(port->dev, "Unable to map registers\n");
296 release_mem_region(port->mapbase, ULITE_REGION);
297 return -EBUSY;
298 }
299
300 return 0;
301}
302
303static void ulite_config_port(struct uart_port *port, int flags)
304{
305 if (!ulite_request_port(port))
306 port->type = PORT_UARTLITE;
307}
308
309static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
310{
311 /* we don't want the core code to modify any port params */
312 return -EINVAL;
313}
314
315#ifdef CONFIG_CONSOLE_POLL
316static int ulite_get_poll_char(struct uart_port *port)
317{
318 if (!(ioread32be(port->membase + ULITE_STATUS)
319 & ULITE_STATUS_RXVALID))
320 return NO_POLL_CHAR;
321
322 return ioread32be(port->membase + ULITE_RX);
323}
324
325static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
326{
327 while (ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)
328 cpu_relax();
329
330 /* write char to device */
331 iowrite32be(ch, port->membase + ULITE_TX);
332}
333#endif
334
335static struct uart_ops ulite_ops = {
336 .tx_empty = ulite_tx_empty,
337 .set_mctrl = ulite_set_mctrl,
338 .get_mctrl = ulite_get_mctrl,
339 .stop_tx = ulite_stop_tx,
340 .start_tx = ulite_start_tx,
341 .stop_rx = ulite_stop_rx,
342 .enable_ms = ulite_enable_ms,
343 .break_ctl = ulite_break_ctl,
344 .startup = ulite_startup,
345 .shutdown = ulite_shutdown,
346 .set_termios = ulite_set_termios,
347 .type = ulite_type,
348 .release_port = ulite_release_port,
349 .request_port = ulite_request_port,
350 .config_port = ulite_config_port,
351 .verify_port = ulite_verify_port,
352#ifdef CONFIG_CONSOLE_POLL
353 .poll_get_char = ulite_get_poll_char,
354 .poll_put_char = ulite_put_poll_char,
355#endif
356};
357
358/* ---------------------------------------------------------------------
359 * Console driver operations
360 */
361
362#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
363static void ulite_console_wait_tx(struct uart_port *port)
364{
365 int i;
366 u8 val;
367
368 /* Spin waiting for TX fifo to have space available */
369 for (i = 0; i < 100000; i++) {
370 val = ioread32be(port->membase + ULITE_STATUS);
371 if ((val & ULITE_STATUS_TXFULL) == 0)
372 break;
373 cpu_relax();
374 }
375}
376
377static void ulite_console_putchar(struct uart_port *port, int ch)
378{
379 ulite_console_wait_tx(port);
380 iowrite32be(ch, port->membase + ULITE_TX);
381}
382
383static void ulite_console_write(struct console *co, const char *s,
384 unsigned int count)
385{
386 struct uart_port *port = &ulite_ports[co->index];
387 unsigned long flags;
388 unsigned int ier;
389 int locked = 1;
390
391 if (oops_in_progress) {
392 locked = spin_trylock_irqsave(&port->lock, flags);
393 } else
394 spin_lock_irqsave(&port->lock, flags);
395
396 /* save and disable interrupt */
397 ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
398 iowrite32be(0, port->membase + ULITE_CONTROL);
399
400 uart_console_write(port, s, count, ulite_console_putchar);
401
402 ulite_console_wait_tx(port);
403
404 /* restore interrupt state */
405 if (ier)
406 iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
407
408 if (locked)
409 spin_unlock_irqrestore(&port->lock, flags);
410}
411
412static int __devinit ulite_console_setup(struct console *co, char *options)
413{
414 struct uart_port *port;
415 int baud = 9600;
416 int bits = 8;
417 int parity = 'n';
418 int flow = 'n';
419
420 if (co->index < 0 || co->index >= ULITE_NR_UARTS)
421 return -EINVAL;
422
423 port = &ulite_ports[co->index];
424
425 /* Has the device been initialized yet? */
426 if (!port->mapbase) {
427 pr_debug("console on ttyUL%i not present\n", co->index);
428 return -ENODEV;
429 }
430
431 /* not initialized yet? */
432 if (!port->membase) {
433 if (ulite_request_port(port))
434 return -ENODEV;
435 }
436
437 if (options)
438 uart_parse_options(options, &baud, &parity, &bits, &flow);
439
440 return uart_set_options(port, co, baud, parity, bits, flow);
441}
442
443static struct uart_driver ulite_uart_driver;
444
445static struct console ulite_console = {
446 .name = ULITE_NAME,
447 .write = ulite_console_write,
448 .device = uart_console_device,
449 .setup = ulite_console_setup,
450 .flags = CON_PRINTBUFFER,
451 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
452 .data = &ulite_uart_driver,
453};
454
455static int __init ulite_console_init(void)
456{
457 register_console(&ulite_console);
458 return 0;
459}
460
461console_initcall(ulite_console_init);
462
463#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
464
465static struct uart_driver ulite_uart_driver = {
466 .owner = THIS_MODULE,
467 .driver_name = "uartlite",
468 .dev_name = ULITE_NAME,
469 .major = ULITE_MAJOR,
470 .minor = ULITE_MINOR,
471 .nr = ULITE_NR_UARTS,
472#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
473 .cons = &ulite_console,
474#endif
475};
476
477/* ---------------------------------------------------------------------
478 * Port assignment functions (mapping devices to uart_port structures)
479 */
480
481/** ulite_assign: register a uartlite device with the driver
482 *
483 * @dev: pointer to device structure
484 * @id: requested id number. Pass -1 for automatic port assignment
485 * @base: base address of uartlite registers
486 * @irq: irq number for uartlite
487 *
488 * Returns: 0 on success, <0 otherwise
489 */
490static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
491{
492 struct uart_port *port;
493 int rc;
494
495 /* if id = -1; then scan for a free id and use that */
496 if (id < 0) {
497 for (id = 0; id < ULITE_NR_UARTS; id++)
498 if (ulite_ports[id].mapbase == 0)
499 break;
500 }
501 if (id < 0 || id >= ULITE_NR_UARTS) {
502 dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
503 return -EINVAL;
504 }
505
506 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
507 dev_err(dev, "cannot assign to %s%i; it is already in use\n",
508 ULITE_NAME, id);
509 return -EBUSY;
510 }
511
512 port = &ulite_ports[id];
513
514 spin_lock_init(&port->lock);
515 port->fifosize = 16;
516 port->regshift = 2;
517 port->iotype = UPIO_MEM;
518 port->iobase = 1; /* mark port in use */
519 port->mapbase = base;
520 port->membase = NULL;
521 port->ops = &ulite_ops;
522 port->irq = irq;
523 port->flags = UPF_BOOT_AUTOCONF;
524 port->dev = dev;
525 port->type = PORT_UNKNOWN;
526 port->line = id;
527
528 dev_set_drvdata(dev, port);
529
530 /* Register the port */
531 rc = uart_add_one_port(&ulite_uart_driver, port);
532 if (rc) {
533 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
534 port->mapbase = 0;
535 dev_set_drvdata(dev, NULL);
536 return rc;
537 }
538
539 return 0;
540}
541
542/** ulite_release: register a uartlite device with the driver
543 *
544 * @dev: pointer to device structure
545 */
546static int __devexit ulite_release(struct device *dev)
547{
548 struct uart_port *port = dev_get_drvdata(dev);
549 int rc = 0;
550
551 if (port) {
552 rc = uart_remove_one_port(&ulite_uart_driver, port);
553 dev_set_drvdata(dev, NULL);
554 port->mapbase = 0;
555 }
556
557 return rc;
558}
559
560/* ---------------------------------------------------------------------
561 * Platform bus binding
562 */
563
564#if defined(CONFIG_OF)
565/* Match table for of_platform binding */
566static struct of_device_id ulite_of_match[] __devinitdata = {
567 { .compatible = "xlnx,opb-uartlite-1.00.b", },
568 { .compatible = "xlnx,xps-uartlite-1.00.a", },
569 {}
570};
571MODULE_DEVICE_TABLE(of, ulite_of_match);
572#endif /* CONFIG_OF */
573
574static int __devinit ulite_probe(struct platform_device *pdev)
575{
576 struct resource *res, *res2;
577 int id = pdev->id;
578#ifdef CONFIG_OF
579 const __be32 *prop;
580
581 prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
582 if (prop)
583 id = be32_to_cpup(prop);
584#endif
585
586 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
587 if (!res)
588 return -ENODEV;
589
590 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
591 if (!res2)
592 return -ENODEV;
593
594 return ulite_assign(&pdev->dev, id, res->start, res2->start);
595}
596
597static int __devexit ulite_remove(struct platform_device *pdev)
598{
599 return ulite_release(&pdev->dev);
600}
601
602/* work with hotplug and coldplug */
603MODULE_ALIAS("platform:uartlite");
604
605static struct platform_driver ulite_platform_driver = {
606 .probe = ulite_probe,
607 .remove = __devexit_p(ulite_remove),
608 .driver = {
609 .owner = THIS_MODULE,
610 .name = "uartlite",
611 .of_match_table = of_match_ptr(ulite_of_match),
612 },
613};
614
615/* ---------------------------------------------------------------------
616 * Module setup/teardown
617 */
618
619int __init ulite_init(void)
620{
621 int ret;
622
623 pr_debug("uartlite: calling uart_register_driver()\n");
624 ret = uart_register_driver(&ulite_uart_driver);
625 if (ret)
626 goto err_uart;
627
628 pr_debug("uartlite: calling platform_driver_register()\n");
629 ret = platform_driver_register(&ulite_platform_driver);
630 if (ret)
631 goto err_plat;
632
633 return 0;
634
635err_plat:
636 uart_unregister_driver(&ulite_uart_driver);
637err_uart:
638 printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
639 return ret;
640}
641
642void __exit ulite_exit(void)
643{
644 platform_driver_unregister(&ulite_platform_driver);
645 uart_unregister_driver(&ulite_uart_driver);
646}
647
648module_init(ulite_init);
649module_exit(ulite_exit);
650
651MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
652MODULE_DESCRIPTION("Xilinx uartlite serial driver");
653MODULE_LICENSE("GPL");