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1/*
2 * m32r_sio.c
3 *
4 * Driver for M32R serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Based on drivers/serial/8250.c.
8 *
9 * Copyright (C) 2001 Russell King.
10 * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/*
19 * A note about mapbase / membase
20 *
21 * mapbase is the physical address of the IO port. Currently, we don't
22 * support this very well, and it may well be dropped from this driver
23 * in future. As such, mapbase should be NULL.
24 *
25 * membase is an 'ioremapped' cookie. This is compatible with the old
26 * serial.c driver, and is currently the preferred form.
27 */
28
29#if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30#define SUPPORT_SYSRQ
31#endif
32
33#include <linux/module.h>
34#include <linux/tty.h>
35#include <linux/tty_flip.h>
36#include <linux/ioport.h>
37#include <linux/init.h>
38#include <linux/console.h>
39#include <linux/sysrq.h>
40#include <linux/serial.h>
41#include <linux/delay.h>
42
43#include <asm/m32r.h>
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#define PORT_M32R_BASE PORT_M32R_SIO
48#define PORT_INDEX(x) (x - PORT_M32R_BASE + 1)
49#define BAUD_RATE 115200
50
51#include <linux/serial_core.h>
52#include "m32r_sio.h"
53#include "m32r_sio_reg.h"
54
55/*
56 * Debugging.
57 */
58#if 0
59#define DEBUG_AUTOCONF(fmt...) printk(fmt)
60#else
61#define DEBUG_AUTOCONF(fmt...) do { } while (0)
62#endif
63
64#if 0
65#define DEBUG_INTR(fmt...) printk(fmt)
66#else
67#define DEBUG_INTR(fmt...) do { } while (0)
68#endif
69
70#define PASS_LIMIT 256
71
72#define BASE_BAUD 115200
73
74/* Standard COM flags */
75#define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
76
77/*
78 * SERIAL_PORT_DFNS tells us about built-in ports that have no
79 * standard enumeration mechanism. Platforms that can find all
80 * serial ports via mechanisms like ACPI or PCI need not supply it.
81 */
82#if defined(CONFIG_PLAT_USRV)
83
84#define SERIAL_PORT_DFNS \
85 /* UART CLK PORT IRQ FLAGS */ \
86 { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \
87 { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */
88
89#else /* !CONFIG_PLAT_USRV */
90
91#if defined(CONFIG_SERIAL_M32R_PLDSIO)
92#define SERIAL_PORT_DFNS \
93 { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \
94 STD_COM_FLAGS }, /* ttyS0 */
95#else
96#define SERIAL_PORT_DFNS \
97 { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \
98 STD_COM_FLAGS }, /* ttyS0 */
99#endif
100
101#endif /* !CONFIG_PLAT_USRV */
102
103static struct old_serial_port old_serial_port[] = {
104 SERIAL_PORT_DFNS
105};
106
107#define UART_NR ARRAY_SIZE(old_serial_port)
108
109struct uart_sio_port {
110 struct uart_port port;
111 struct timer_list timer; /* "no irq" timer */
112 struct list_head list; /* ports on this IRQ */
113 unsigned short rev;
114 unsigned char acr;
115 unsigned char ier;
116 unsigned char lcr;
117 unsigned char mcr_mask; /* mask of user bits */
118 unsigned char mcr_force; /* mask of forced bits */
119 unsigned char lsr_break_flag;
120
121 /*
122 * We provide a per-port pm hook.
123 */
124 void (*pm)(struct uart_port *port,
125 unsigned int state, unsigned int old);
126};
127
128struct irq_info {
129 spinlock_t lock;
130 struct list_head *head;
131};
132
133static struct irq_info irq_lists[NR_IRQS];
134
135/*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138static const struct serial_uart_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .dfl_xmit_fifo_size = 1,
142 .flags = 0,
143 },
144 [PORT_INDEX(PORT_M32R_SIO)] = {
145 .name = "M32RSIO",
146 .dfl_xmit_fifo_size = 1,
147 .flags = 0,
148 },
149};
150
151#ifdef CONFIG_SERIAL_M32R_PLDSIO
152
153#define __sio_in(x) inw((unsigned long)(x))
154#define __sio_out(v,x) outw((v),(unsigned long)(x))
155
156static inline void sio_set_baud_rate(unsigned long baud)
157{
158 unsigned short sbaud;
159 sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1;
160 __sio_out(sbaud, PLD_ESIO0BAUR);
161}
162
163static void sio_reset(void)
164{
165 unsigned short tmp;
166
167 tmp = __sio_in(PLD_ESIO0RXB);
168 tmp = __sio_in(PLD_ESIO0RXB);
169 tmp = __sio_in(PLD_ESIO0CR);
170 sio_set_baud_rate(BAUD_RATE);
171 __sio_out(0x0300, PLD_ESIO0CR);
172 __sio_out(0x0003, PLD_ESIO0CR);
173}
174
175static void sio_init(void)
176{
177 unsigned short tmp;
178
179 tmp = __sio_in(PLD_ESIO0RXB);
180 tmp = __sio_in(PLD_ESIO0RXB);
181 tmp = __sio_in(PLD_ESIO0CR);
182 __sio_out(0x0300, PLD_ESIO0CR);
183 __sio_out(0x0003, PLD_ESIO0CR);
184}
185
186static void sio_error(int *status)
187{
188 printk("SIO0 error[%04x]\n", *status);
189 do {
190 sio_init();
191 } while ((*status = __sio_in(PLD_ESIO0CR)) != 3);
192}
193
194#else /* not CONFIG_SERIAL_M32R_PLDSIO */
195
196#define __sio_in(x) inl(x)
197#define __sio_out(v,x) outl((v),(x))
198
199static inline void sio_set_baud_rate(unsigned long baud)
200{
201 unsigned long i, j;
202
203 i = boot_cpu_data.bus_clock / (baud * 16);
204 j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud;
205 i -= 1;
206 j = (j + 1) >> 1;
207
208 __sio_out(i, M32R_SIO0_BAUR_PORTL);
209 __sio_out(j, M32R_SIO0_RBAUR_PORTL);
210}
211
212static void sio_reset(void)
213{
214 __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */
215 __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */
216 __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */
217 sio_set_baud_rate(BAUD_RATE);
218 __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL);
219 __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */
220}
221
222static void sio_init(void)
223{
224 unsigned int tmp;
225
226 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
227 tmp = __sio_in(M32R_SIO0_RXB_PORTL);
228 tmp = __sio_in(M32R_SIO0_STS_PORTL);
229 __sio_out(0x00000003, M32R_SIO0_CR_PORTL);
230}
231
232static void sio_error(int *status)
233{
234 printk("SIO0 error[%04x]\n", *status);
235 do {
236 sio_init();
237 } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3);
238}
239
240#endif /* CONFIG_SERIAL_M32R_PLDSIO */
241
242static unsigned int sio_in(struct uart_sio_port *up, int offset)
243{
244 return __sio_in(up->port.iobase + offset);
245}
246
247static void sio_out(struct uart_sio_port *up, int offset, int value)
248{
249 __sio_out(value, up->port.iobase + offset);
250}
251
252static unsigned int serial_in(struct uart_sio_port *up, int offset)
253{
254 if (!offset)
255 return 0;
256
257 return __sio_in(offset);
258}
259
260static void serial_out(struct uart_sio_port *up, int offset, int value)
261{
262 if (!offset)
263 return;
264
265 __sio_out(value, offset);
266}
267
268static void m32r_sio_stop_tx(struct uart_port *port)
269{
270 struct uart_sio_port *up = (struct uart_sio_port *)port;
271
272 if (up->ier & UART_IER_THRI) {
273 up->ier &= ~UART_IER_THRI;
274 serial_out(up, UART_IER, up->ier);
275 }
276}
277
278static void m32r_sio_start_tx(struct uart_port *port)
279{
280#ifdef CONFIG_SERIAL_M32R_PLDSIO
281 struct uart_sio_port *up = (struct uart_sio_port *)port;
282 struct circ_buf *xmit = &up->port.state->xmit;
283
284 if (!(up->ier & UART_IER_THRI)) {
285 up->ier |= UART_IER_THRI;
286 serial_out(up, UART_IER, up->ier);
287 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
288 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
289 up->port.icount.tx++;
290 }
291 while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY);
292#else
293 struct uart_sio_port *up = (struct uart_sio_port *)port;
294
295 if (!(up->ier & UART_IER_THRI)) {
296 up->ier |= UART_IER_THRI;
297 serial_out(up, UART_IER, up->ier);
298 }
299#endif
300}
301
302static void m32r_sio_stop_rx(struct uart_port *port)
303{
304 struct uart_sio_port *up = (struct uart_sio_port *)port;
305
306 up->ier &= ~UART_IER_RLSI;
307 up->port.read_status_mask &= ~UART_LSR_DR;
308 serial_out(up, UART_IER, up->ier);
309}
310
311static void m32r_sio_enable_ms(struct uart_port *port)
312{
313 struct uart_sio_port *up = (struct uart_sio_port *)port;
314
315 up->ier |= UART_IER_MSI;
316 serial_out(up, UART_IER, up->ier);
317}
318
319static void receive_chars(struct uart_sio_port *up, int *status)
320{
321 struct tty_struct *tty = up->port.state->port.tty;
322 unsigned char ch;
323 unsigned char flag;
324 int max_count = 256;
325
326 do {
327 ch = sio_in(up, SIORXB);
328 flag = TTY_NORMAL;
329 up->port.icount.rx++;
330
331 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
332 UART_LSR_FE | UART_LSR_OE))) {
333 /*
334 * For statistics only
335 */
336 if (*status & UART_LSR_BI) {
337 *status &= ~(UART_LSR_FE | UART_LSR_PE);
338 up->port.icount.brk++;
339 /*
340 * We do the SysRQ and SAK checking
341 * here because otherwise the break
342 * may get masked by ignore_status_mask
343 * or read_status_mask.
344 */
345 if (uart_handle_break(&up->port))
346 goto ignore_char;
347 } else if (*status & UART_LSR_PE)
348 up->port.icount.parity++;
349 else if (*status & UART_LSR_FE)
350 up->port.icount.frame++;
351 if (*status & UART_LSR_OE)
352 up->port.icount.overrun++;
353
354 /*
355 * Mask off conditions which should be ingored.
356 */
357 *status &= up->port.read_status_mask;
358
359 if (up->port.line == up->port.cons->index) {
360 /* Recover the break flag from console xmit */
361 *status |= up->lsr_break_flag;
362 up->lsr_break_flag = 0;
363 }
364
365 if (*status & UART_LSR_BI) {
366 DEBUG_INTR("handling break....");
367 flag = TTY_BREAK;
368 } else if (*status & UART_LSR_PE)
369 flag = TTY_PARITY;
370 else if (*status & UART_LSR_FE)
371 flag = TTY_FRAME;
372 }
373 if (uart_handle_sysrq_char(&up->port, ch))
374 goto ignore_char;
375 if ((*status & up->port.ignore_status_mask) == 0)
376 tty_insert_flip_char(tty, ch, flag);
377
378 if (*status & UART_LSR_OE) {
379 /*
380 * Overrun is special, since it's reported
381 * immediately, and doesn't affect the current
382 * character.
383 */
384 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
385 }
386 ignore_char:
387 *status = serial_in(up, UART_LSR);
388 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
389 tty_flip_buffer_push(tty);
390}
391
392static void transmit_chars(struct uart_sio_port *up)
393{
394 struct circ_buf *xmit = &up->port.state->xmit;
395 int count;
396
397 if (up->port.x_char) {
398#ifndef CONFIG_SERIAL_M32R_PLDSIO /* XXX */
399 serial_out(up, UART_TX, up->port.x_char);
400#endif
401 up->port.icount.tx++;
402 up->port.x_char = 0;
403 return;
404 }
405 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
406 m32r_sio_stop_tx(&up->port);
407 return;
408 }
409
410 count = up->port.fifosize;
411 do {
412 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
413 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
414 up->port.icount.tx++;
415 if (uart_circ_empty(xmit))
416 break;
417 while (!(serial_in(up, UART_LSR) & UART_LSR_THRE));
418
419 } while (--count > 0);
420
421 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
422 uart_write_wakeup(&up->port);
423
424 DEBUG_INTR("THRE...");
425
426 if (uart_circ_empty(xmit))
427 m32r_sio_stop_tx(&up->port);
428}
429
430/*
431 * This handles the interrupt from one port.
432 */
433static inline void m32r_sio_handle_port(struct uart_sio_port *up,
434 unsigned int status)
435{
436 DEBUG_INTR("status = %x...", status);
437
438 if (status & 0x04)
439 receive_chars(up, &status);
440 if (status & 0x01)
441 transmit_chars(up);
442}
443
444/*
445 * This is the serial driver's interrupt routine.
446 *
447 * Arjan thinks the old way was overly complex, so it got simplified.
448 * Alan disagrees, saying that need the complexity to handle the weird
449 * nature of ISA shared interrupts. (This is a special exception.)
450 *
451 * In order to handle ISA shared interrupts properly, we need to check
452 * that all ports have been serviced, and therefore the ISA interrupt
453 * line has been de-asserted.
454 *
455 * This means we need to loop through all ports. checking that they
456 * don't have an interrupt pending.
457 */
458static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id)
459{
460 struct irq_info *i = dev_id;
461 struct list_head *l, *end = NULL;
462 int pass_counter = 0;
463
464 DEBUG_INTR("m32r_sio_interrupt(%d)...", irq);
465
466#ifdef CONFIG_SERIAL_M32R_PLDSIO
467// if (irq == PLD_IRQ_SIO0_SND)
468// irq = PLD_IRQ_SIO0_RCV;
469#else
470 if (irq == M32R_IRQ_SIO0_S)
471 irq = M32R_IRQ_SIO0_R;
472#endif
473
474 spin_lock(&i->lock);
475
476 l = i->head;
477 do {
478 struct uart_sio_port *up;
479 unsigned int sts;
480
481 up = list_entry(l, struct uart_sio_port, list);
482
483 sts = sio_in(up, SIOSTS);
484 if (sts & 0x5) {
485 spin_lock(&up->port.lock);
486 m32r_sio_handle_port(up, sts);
487 spin_unlock(&up->port.lock);
488
489 end = NULL;
490 } else if (end == NULL)
491 end = l;
492
493 l = l->next;
494
495 if (l == i->head && pass_counter++ > PASS_LIMIT) {
496 if (sts & 0xe0)
497 sio_error(&sts);
498 break;
499 }
500 } while (l != end);
501
502 spin_unlock(&i->lock);
503
504 DEBUG_INTR("end.\n");
505
506 return IRQ_HANDLED;
507}
508
509/*
510 * To support ISA shared interrupts, we need to have one interrupt
511 * handler that ensures that the IRQ line has been deasserted
512 * before returning. Failing to do this will result in the IRQ
513 * line being stuck active, and, since ISA irqs are edge triggered,
514 * no more IRQs will be seen.
515 */
516static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up)
517{
518 spin_lock_irq(&i->lock);
519
520 if (!list_empty(i->head)) {
521 if (i->head == &up->list)
522 i->head = i->head->next;
523 list_del(&up->list);
524 } else {
525 BUG_ON(i->head != &up->list);
526 i->head = NULL;
527 }
528
529 spin_unlock_irq(&i->lock);
530}
531
532static int serial_link_irq_chain(struct uart_sio_port *up)
533{
534 struct irq_info *i = irq_lists + up->port.irq;
535 int ret, irq_flags = 0;
536
537 spin_lock_irq(&i->lock);
538
539 if (i->head) {
540 list_add(&up->list, i->head);
541 spin_unlock_irq(&i->lock);
542
543 ret = 0;
544 } else {
545 INIT_LIST_HEAD(&up->list);
546 i->head = &up->list;
547 spin_unlock_irq(&i->lock);
548
549 ret = request_irq(up->port.irq, m32r_sio_interrupt,
550 irq_flags, "SIO0-RX", i);
551 ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt,
552 irq_flags, "SIO0-TX", i);
553 if (ret < 0)
554 serial_do_unlink(i, up);
555 }
556
557 return ret;
558}
559
560static void serial_unlink_irq_chain(struct uart_sio_port *up)
561{
562 struct irq_info *i = irq_lists + up->port.irq;
563
564 BUG_ON(i->head == NULL);
565
566 if (list_empty(i->head)) {
567 free_irq(up->port.irq, i);
568 free_irq(up->port.irq + 1, i);
569 }
570
571 serial_do_unlink(i, up);
572}
573
574/*
575 * This function is used to handle ports that do not have an interrupt.
576 */
577static void m32r_sio_timeout(unsigned long data)
578{
579 struct uart_sio_port *up = (struct uart_sio_port *)data;
580 unsigned int timeout;
581 unsigned int sts;
582
583 sts = sio_in(up, SIOSTS);
584 if (sts & 0x5) {
585 spin_lock(&up->port.lock);
586 m32r_sio_handle_port(up, sts);
587 spin_unlock(&up->port.lock);
588 }
589
590 timeout = up->port.timeout;
591 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
592 mod_timer(&up->timer, jiffies + timeout);
593}
594
595static unsigned int m32r_sio_tx_empty(struct uart_port *port)
596{
597 struct uart_sio_port *up = (struct uart_sio_port *)port;
598 unsigned long flags;
599 unsigned int ret;
600
601 spin_lock_irqsave(&up->port.lock, flags);
602 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
603 spin_unlock_irqrestore(&up->port.lock, flags);
604
605 return ret;
606}
607
608static unsigned int m32r_sio_get_mctrl(struct uart_port *port)
609{
610 return 0;
611}
612
613static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl)
614{
615
616}
617
618static void m32r_sio_break_ctl(struct uart_port *port, int break_state)
619{
620
621}
622
623static int m32r_sio_startup(struct uart_port *port)
624{
625 struct uart_sio_port *up = (struct uart_sio_port *)port;
626 int retval;
627
628 sio_init();
629
630 /*
631 * If the "interrupt" for this port doesn't correspond with any
632 * hardware interrupt, we use a timer-based system. The original
633 * driver used to do this with IRQ0.
634 */
635 if (!up->port.irq) {
636 unsigned int timeout = up->port.timeout;
637
638 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
639
640 up->timer.data = (unsigned long)up;
641 mod_timer(&up->timer, jiffies + timeout);
642 } else {
643 retval = serial_link_irq_chain(up);
644 if (retval)
645 return retval;
646 }
647
648 /*
649 * Finally, enable interrupts. Note: Modem status interrupts
650 * are set via set_termios(), which will be occurring imminently
651 * anyway, so we don't enable them here.
652 * - M32R_SIO: 0x0c
653 * - M32R_PLDSIO: 0x04
654 */
655 up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
656 sio_out(up, SIOTRCR, up->ier);
657
658 /*
659 * And clear the interrupt registers again for luck.
660 */
661 sio_reset();
662
663 return 0;
664}
665
666static void m32r_sio_shutdown(struct uart_port *port)
667{
668 struct uart_sio_port *up = (struct uart_sio_port *)port;
669
670 /*
671 * Disable interrupts from this port
672 */
673 up->ier = 0;
674 sio_out(up, SIOTRCR, 0);
675
676 /*
677 * Disable break condition and FIFOs
678 */
679
680 sio_init();
681
682 if (!up->port.irq)
683 del_timer_sync(&up->timer);
684 else
685 serial_unlink_irq_chain(up);
686}
687
688static unsigned int m32r_sio_get_divisor(struct uart_port *port,
689 unsigned int baud)
690{
691 return uart_get_divisor(port, baud);
692}
693
694static void m32r_sio_set_termios(struct uart_port *port,
695 struct ktermios *termios, struct ktermios *old)
696{
697 struct uart_sio_port *up = (struct uart_sio_port *)port;
698 unsigned char cval = 0;
699 unsigned long flags;
700 unsigned int baud, quot;
701
702 switch (termios->c_cflag & CSIZE) {
703 case CS5:
704 cval = UART_LCR_WLEN5;
705 break;
706 case CS6:
707 cval = UART_LCR_WLEN6;
708 break;
709 case CS7:
710 cval = UART_LCR_WLEN7;
711 break;
712 default:
713 case CS8:
714 cval = UART_LCR_WLEN8;
715 break;
716 }
717
718 if (termios->c_cflag & CSTOPB)
719 cval |= UART_LCR_STOP;
720 if (termios->c_cflag & PARENB)
721 cval |= UART_LCR_PARITY;
722 if (!(termios->c_cflag & PARODD))
723 cval |= UART_LCR_EPAR;
724#ifdef CMSPAR
725 if (termios->c_cflag & CMSPAR)
726 cval |= UART_LCR_SPAR;
727#endif
728
729 /*
730 * Ask the core to calculate the divisor for us.
731 */
732#ifdef CONFIG_SERIAL_M32R_PLDSIO
733 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4);
734#else
735 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
736#endif
737 quot = m32r_sio_get_divisor(port, baud);
738
739 /*
740 * Ok, we're now changing the port state. Do it with
741 * interrupts disabled.
742 */
743 spin_lock_irqsave(&up->port.lock, flags);
744
745 sio_set_baud_rate(baud);
746
747 /*
748 * Update the per-port timeout.
749 */
750 uart_update_timeout(port, termios->c_cflag, baud);
751
752 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
753 if (termios->c_iflag & INPCK)
754 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
755 if (termios->c_iflag & (BRKINT | PARMRK))
756 up->port.read_status_mask |= UART_LSR_BI;
757
758 /*
759 * Characteres to ignore
760 */
761 up->port.ignore_status_mask = 0;
762 if (termios->c_iflag & IGNPAR)
763 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
764 if (termios->c_iflag & IGNBRK) {
765 up->port.ignore_status_mask |= UART_LSR_BI;
766 /*
767 * If we're ignoring parity and break indicators,
768 * ignore overruns too (for real raw support).
769 */
770 if (termios->c_iflag & IGNPAR)
771 up->port.ignore_status_mask |= UART_LSR_OE;
772 }
773
774 /*
775 * ignore all characters if CREAD is not set
776 */
777 if ((termios->c_cflag & CREAD) == 0)
778 up->port.ignore_status_mask |= UART_LSR_DR;
779
780 /*
781 * CTS flow control flag and modem status interrupts
782 */
783 up->ier &= ~UART_IER_MSI;
784 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
785 up->ier |= UART_IER_MSI;
786
787 serial_out(up, UART_IER, up->ier);
788
789 up->lcr = cval; /* Save LCR */
790 spin_unlock_irqrestore(&up->port.lock, flags);
791}
792
793static void m32r_sio_pm(struct uart_port *port, unsigned int state,
794 unsigned int oldstate)
795{
796 struct uart_sio_port *up = (struct uart_sio_port *)port;
797
798 if (up->pm)
799 up->pm(port, state, oldstate);
800}
801
802/*
803 * Resource handling. This is complicated by the fact that resources
804 * depend on the port type. Maybe we should be claiming the standard
805 * 8250 ports, and then trying to get other resources as necessary?
806 */
807static int
808m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res)
809{
810 unsigned int size = 8 << up->port.regshift;
811#ifndef CONFIG_SERIAL_M32R_PLDSIO
812 unsigned long start;
813#endif
814 int ret = 0;
815
816 switch (up->port.iotype) {
817 case UPIO_MEM:
818 if (up->port.mapbase) {
819#ifdef CONFIG_SERIAL_M32R_PLDSIO
820 *res = request_mem_region(up->port.mapbase, size, "serial");
821#else
822 start = up->port.mapbase;
823 *res = request_mem_region(start, size, "serial");
824#endif
825 if (!*res)
826 ret = -EBUSY;
827 }
828 break;
829
830 case UPIO_PORT:
831 *res = request_region(up->port.iobase, size, "serial");
832 if (!*res)
833 ret = -EBUSY;
834 break;
835 }
836 return ret;
837}
838
839static void m32r_sio_release_port(struct uart_port *port)
840{
841 struct uart_sio_port *up = (struct uart_sio_port *)port;
842 unsigned long start, offset = 0, size = 0;
843
844 size <<= up->port.regshift;
845
846 switch (up->port.iotype) {
847 case UPIO_MEM:
848 if (up->port.mapbase) {
849 /*
850 * Unmap the area.
851 */
852 iounmap(up->port.membase);
853 up->port.membase = NULL;
854
855 start = up->port.mapbase;
856
857 if (size)
858 release_mem_region(start + offset, size);
859 release_mem_region(start, 8 << up->port.regshift);
860 }
861 break;
862
863 case UPIO_PORT:
864 start = up->port.iobase;
865
866 if (size)
867 release_region(start + offset, size);
868 release_region(start + offset, 8 << up->port.regshift);
869 break;
870
871 default:
872 break;
873 }
874}
875
876static int m32r_sio_request_port(struct uart_port *port)
877{
878 struct uart_sio_port *up = (struct uart_sio_port *)port;
879 struct resource *res = NULL;
880 int ret = 0;
881
882 ret = m32r_sio_request_std_resource(up, &res);
883
884 /*
885 * If we have a mapbase, then request that as well.
886 */
887 if (ret == 0 && up->port.flags & UPF_IOREMAP) {
888 int size = resource_size(res);
889
890 up->port.membase = ioremap(up->port.mapbase, size);
891 if (!up->port.membase)
892 ret = -ENOMEM;
893 }
894
895 if (ret < 0) {
896 if (res)
897 release_resource(res);
898 }
899
900 return ret;
901}
902
903static void m32r_sio_config_port(struct uart_port *port, int unused)
904{
905 struct uart_sio_port *up = (struct uart_sio_port *)port;
906 unsigned long flags;
907
908 spin_lock_irqsave(&up->port.lock, flags);
909
910 up->port.type = (PORT_M32R_SIO - PORT_M32R_BASE + 1);
911 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
912
913 spin_unlock_irqrestore(&up->port.lock, flags);
914}
915
916static int
917m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser)
918{
919 if (ser->irq >= nr_irqs || ser->irq < 0 ||
920 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
921 ser->type >= ARRAY_SIZE(uart_config))
922 return -EINVAL;
923 return 0;
924}
925
926static const char *
927m32r_sio_type(struct uart_port *port)
928{
929 int type = port->type;
930
931 if (type >= ARRAY_SIZE(uart_config))
932 type = 0;
933 return uart_config[type].name;
934}
935
936static struct uart_ops m32r_sio_pops = {
937 .tx_empty = m32r_sio_tx_empty,
938 .set_mctrl = m32r_sio_set_mctrl,
939 .get_mctrl = m32r_sio_get_mctrl,
940 .stop_tx = m32r_sio_stop_tx,
941 .start_tx = m32r_sio_start_tx,
942 .stop_rx = m32r_sio_stop_rx,
943 .enable_ms = m32r_sio_enable_ms,
944 .break_ctl = m32r_sio_break_ctl,
945 .startup = m32r_sio_startup,
946 .shutdown = m32r_sio_shutdown,
947 .set_termios = m32r_sio_set_termios,
948 .pm = m32r_sio_pm,
949 .type = m32r_sio_type,
950 .release_port = m32r_sio_release_port,
951 .request_port = m32r_sio_request_port,
952 .config_port = m32r_sio_config_port,
953 .verify_port = m32r_sio_verify_port,
954};
955
956static struct uart_sio_port m32r_sio_ports[UART_NR];
957
958static void __init m32r_sio_init_ports(void)
959{
960 struct uart_sio_port *up;
961 static int first = 1;
962 int i;
963
964 if (!first)
965 return;
966 first = 0;
967
968 for (i = 0, up = m32r_sio_ports; i < ARRAY_SIZE(old_serial_port);
969 i++, up++) {
970 up->port.iobase = old_serial_port[i].port;
971 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
972 up->port.uartclk = old_serial_port[i].baud_base * 16;
973 up->port.flags = old_serial_port[i].flags;
974 up->port.membase = old_serial_port[i].iomem_base;
975 up->port.iotype = old_serial_port[i].io_type;
976 up->port.regshift = old_serial_port[i].iomem_reg_shift;
977 up->port.ops = &m32r_sio_pops;
978 }
979}
980
981static void __init m32r_sio_register_ports(struct uart_driver *drv)
982{
983 int i;
984
985 m32r_sio_init_ports();
986
987 for (i = 0; i < UART_NR; i++) {
988 struct uart_sio_port *up = &m32r_sio_ports[i];
989
990 up->port.line = i;
991 up->port.ops = &m32r_sio_pops;
992 init_timer(&up->timer);
993 up->timer.function = m32r_sio_timeout;
994
995 up->mcr_mask = ~0;
996 up->mcr_force = 0;
997
998 uart_add_one_port(drv, &up->port);
999 }
1000}
1001
1002#ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE
1003
1004/*
1005 * Wait for transmitter & holding register to empty
1006 */
1007static inline void wait_for_xmitr(struct uart_sio_port *up)
1008{
1009 unsigned int status, tmout = 10000;
1010
1011 /* Wait up to 10ms for the character(s) to be sent. */
1012 do {
1013 status = sio_in(up, SIOSTS);
1014
1015 if (--tmout == 0)
1016 break;
1017 udelay(1);
1018 } while ((status & UART_EMPTY) != UART_EMPTY);
1019
1020 /* Wait up to 1s for flow control if necessary */
1021 if (up->port.flags & UPF_CONS_FLOW) {
1022 tmout = 1000000;
1023 while (--tmout)
1024 udelay(1);
1025 }
1026}
1027
1028static void m32r_sio_console_putchar(struct uart_port *port, int ch)
1029{
1030 struct uart_sio_port *up = (struct uart_sio_port *)port;
1031
1032 wait_for_xmitr(up);
1033 sio_out(up, SIOTXB, ch);
1034}
1035
1036/*
1037 * Print a string to the serial port trying not to disturb
1038 * any possible real use of the port...
1039 *
1040 * The console_lock must be held when we get here.
1041 */
1042static void m32r_sio_console_write(struct console *co, const char *s,
1043 unsigned int count)
1044{
1045 struct uart_sio_port *up = &m32r_sio_ports[co->index];
1046 unsigned int ier;
1047
1048 /*
1049 * First save the UER then disable the interrupts
1050 */
1051 ier = sio_in(up, SIOTRCR);
1052 sio_out(up, SIOTRCR, 0);
1053
1054 uart_console_write(&up->port, s, count, m32r_sio_console_putchar);
1055
1056 /*
1057 * Finally, wait for transmitter to become empty
1058 * and restore the IER
1059 */
1060 wait_for_xmitr(up);
1061 sio_out(up, SIOTRCR, ier);
1062}
1063
1064static int __init m32r_sio_console_setup(struct console *co, char *options)
1065{
1066 struct uart_port *port;
1067 int baud = 9600;
1068 int bits = 8;
1069 int parity = 'n';
1070 int flow = 'n';
1071
1072 /*
1073 * Check whether an invalid uart number has been specified, and
1074 * if so, search for the first available port that does have
1075 * console support.
1076 */
1077 if (co->index >= UART_NR)
1078 co->index = 0;
1079 port = &m32r_sio_ports[co->index].port;
1080
1081 /*
1082 * Temporary fix.
1083 */
1084 spin_lock_init(&port->lock);
1085
1086 if (options)
1087 uart_parse_options(options, &baud, &parity, &bits, &flow);
1088
1089 return uart_set_options(port, co, baud, parity, bits, flow);
1090}
1091
1092static struct uart_driver m32r_sio_reg;
1093static struct console m32r_sio_console = {
1094 .name = "ttyS",
1095 .write = m32r_sio_console_write,
1096 .device = uart_console_device,
1097 .setup = m32r_sio_console_setup,
1098 .flags = CON_PRINTBUFFER,
1099 .index = -1,
1100 .data = &m32r_sio_reg,
1101};
1102
1103static int __init m32r_sio_console_init(void)
1104{
1105 sio_reset();
1106 sio_init();
1107 m32r_sio_init_ports();
1108 register_console(&m32r_sio_console);
1109 return 0;
1110}
1111console_initcall(m32r_sio_console_init);
1112
1113#define M32R_SIO_CONSOLE &m32r_sio_console
1114#else
1115#define M32R_SIO_CONSOLE NULL
1116#endif
1117
1118static struct uart_driver m32r_sio_reg = {
1119 .owner = THIS_MODULE,
1120 .driver_name = "sio",
1121 .dev_name = "ttyS",
1122 .major = TTY_MAJOR,
1123 .minor = 64,
1124 .nr = UART_NR,
1125 .cons = M32R_SIO_CONSOLE,
1126};
1127
1128/**
1129 * m32r_sio_suspend_port - suspend one serial port
1130 * @line: serial line number
1131 *
1132 * Suspend one serial port.
1133 */
1134void m32r_sio_suspend_port(int line)
1135{
1136 uart_suspend_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1137}
1138
1139/**
1140 * m32r_sio_resume_port - resume one serial port
1141 * @line: serial line number
1142 *
1143 * Resume one serial port.
1144 */
1145void m32r_sio_resume_port(int line)
1146{
1147 uart_resume_port(&m32r_sio_reg, &m32r_sio_ports[line].port);
1148}
1149
1150static int __init m32r_sio_init(void)
1151{
1152 int ret, i;
1153
1154 printk(KERN_INFO "Serial: M32R SIO driver\n");
1155
1156 for (i = 0; i < nr_irqs; i++)
1157 spin_lock_init(&irq_lists[i].lock);
1158
1159 ret = uart_register_driver(&m32r_sio_reg);
1160 if (ret >= 0)
1161 m32r_sio_register_ports(&m32r_sio_reg);
1162
1163 return ret;
1164}
1165
1166static void __exit m32r_sio_exit(void)
1167{
1168 int i;
1169
1170 for (i = 0; i < UART_NR; i++)
1171 uart_remove_one_port(&m32r_sio_reg, &m32r_sio_ports[i].port);
1172
1173 uart_unregister_driver(&m32r_sio_reg);
1174}
1175
1176module_init(m32r_sio_init);
1177module_exit(m32r_sio_exit);
1178
1179EXPORT_SYMBOL(m32r_sio_suspend_port);
1180EXPORT_SYMBOL(m32r_sio_resume_port);
1181
1182MODULE_LICENSE("GPL");
1183MODULE_DESCRIPTION("Generic M32R SIO serial driver");