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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Broadcom BCM63xx SPI controller support
4 *
5 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
6 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
7 */
8
9#include <linux/kernel.h>
10#include <linux/clk.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/platform_device.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/spi/spi.h>
17#include <linux/completion.h>
18#include <linux/err.h>
19#include <linux/pm_runtime.h>
20#include <linux/of.h>
21#include <linux/reset.h>
22
23/* BCM 6338/6348 SPI core */
24#define SPI_6348_RSET_SIZE 64
25#define SPI_6348_CMD 0x00 /* 16-bits register */
26#define SPI_6348_INT_STATUS 0x02
27#define SPI_6348_INT_MASK_ST 0x03
28#define SPI_6348_INT_MASK 0x04
29#define SPI_6348_ST 0x05
30#define SPI_6348_CLK_CFG 0x06
31#define SPI_6348_FILL_BYTE 0x07
32#define SPI_6348_MSG_TAIL 0x09
33#define SPI_6348_RX_TAIL 0x0b
34#define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
35#define SPI_6348_MSG_CTL_WIDTH 8
36#define SPI_6348_MSG_DATA 0x41
37#define SPI_6348_MSG_DATA_SIZE 0x3f
38#define SPI_6348_RX_DATA 0x80
39#define SPI_6348_RX_DATA_SIZE 0x3f
40
41/* BCM 3368/6358/6262/6368 SPI core */
42#define SPI_6358_RSET_SIZE 1804
43#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
44#define SPI_6358_MSG_CTL_WIDTH 16
45#define SPI_6358_MSG_DATA 0x02
46#define SPI_6358_MSG_DATA_SIZE 0x21e
47#define SPI_6358_RX_DATA 0x400
48#define SPI_6358_RX_DATA_SIZE 0x220
49#define SPI_6358_CMD 0x700 /* 16-bits register */
50#define SPI_6358_INT_STATUS 0x702
51#define SPI_6358_INT_MASK_ST 0x703
52#define SPI_6358_INT_MASK 0x704
53#define SPI_6358_ST 0x705
54#define SPI_6358_CLK_CFG 0x706
55#define SPI_6358_FILL_BYTE 0x707
56#define SPI_6358_MSG_TAIL 0x709
57#define SPI_6358_RX_TAIL 0x70B
58
59/* Shared SPI definitions */
60
61/* Message configuration */
62#define SPI_FD_RW 0x00
63#define SPI_HD_W 0x01
64#define SPI_HD_R 0x02
65#define SPI_BYTE_CNT_SHIFT 0
66#define SPI_6348_MSG_TYPE_SHIFT 6
67#define SPI_6358_MSG_TYPE_SHIFT 14
68
69/* Command */
70#define SPI_CMD_NOOP 0x00
71#define SPI_CMD_SOFT_RESET 0x01
72#define SPI_CMD_HARD_RESET 0x02
73#define SPI_CMD_START_IMMEDIATE 0x03
74#define SPI_CMD_COMMAND_SHIFT 0
75#define SPI_CMD_COMMAND_MASK 0x000f
76#define SPI_CMD_DEVICE_ID_SHIFT 4
77#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
78#define SPI_CMD_ONE_BYTE_SHIFT 11
79#define SPI_CMD_ONE_WIRE_SHIFT 12
80#define SPI_DEV_ID_0 0
81#define SPI_DEV_ID_1 1
82#define SPI_DEV_ID_2 2
83#define SPI_DEV_ID_3 3
84
85/* Interrupt mask */
86#define SPI_INTR_CMD_DONE 0x01
87#define SPI_INTR_RX_OVERFLOW 0x02
88#define SPI_INTR_TX_UNDERFLOW 0x04
89#define SPI_INTR_TX_OVERFLOW 0x08
90#define SPI_INTR_RX_UNDERFLOW 0x10
91#define SPI_INTR_CLEAR_ALL 0x1f
92
93/* Status */
94#define SPI_RX_EMPTY 0x02
95#define SPI_CMD_BUSY 0x04
96#define SPI_SERIAL_BUSY 0x08
97
98/* Clock configuration */
99#define SPI_CLK_20MHZ 0x00
100#define SPI_CLK_0_391MHZ 0x01
101#define SPI_CLK_0_781MHZ 0x02 /* default */
102#define SPI_CLK_1_563MHZ 0x03
103#define SPI_CLK_3_125MHZ 0x04
104#define SPI_CLK_6_250MHZ 0x05
105#define SPI_CLK_12_50MHZ 0x06
106#define SPI_CLK_MASK 0x07
107#define SPI_SSOFFTIME_MASK 0x38
108#define SPI_SSOFFTIME_SHIFT 3
109#define SPI_BYTE_SWAP 0x80
110
111enum bcm63xx_regs_spi {
112 SPI_CMD,
113 SPI_INT_STATUS,
114 SPI_INT_MASK_ST,
115 SPI_INT_MASK,
116 SPI_ST,
117 SPI_CLK_CFG,
118 SPI_FILL_BYTE,
119 SPI_MSG_TAIL,
120 SPI_RX_TAIL,
121 SPI_MSG_CTL,
122 SPI_MSG_DATA,
123 SPI_RX_DATA,
124 SPI_MSG_TYPE_SHIFT,
125 SPI_MSG_CTL_WIDTH,
126 SPI_MSG_DATA_SIZE,
127};
128
129#define BCM63XX_SPI_MAX_PREPEND 7
130
131#define BCM63XX_SPI_MAX_CS 8
132#define BCM63XX_SPI_BUS_NUM 0
133
134struct bcm63xx_spi {
135 struct completion done;
136
137 void __iomem *regs;
138 int irq;
139
140 /* Platform data */
141 const unsigned long *reg_offsets;
142 unsigned int fifo_size;
143 unsigned int msg_type_shift;
144 unsigned int msg_ctl_width;
145
146 /* data iomem */
147 u8 __iomem *tx_io;
148 const u8 __iomem *rx_io;
149
150 struct clk *clk;
151 struct platform_device *pdev;
152};
153
154static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
155 unsigned int offset)
156{
157 return readb(bs->regs + bs->reg_offsets[offset]);
158}
159
160static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
161 u8 value, unsigned int offset)
162{
163 writeb(value, bs->regs + bs->reg_offsets[offset]);
164}
165
166static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
167 u16 value, unsigned int offset)
168{
169#ifdef CONFIG_CPU_BIG_ENDIAN
170 iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
171#else
172 writew(value, bs->regs + bs->reg_offsets[offset]);
173#endif
174}
175
176static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
177 { 20000000, SPI_CLK_20MHZ },
178 { 12500000, SPI_CLK_12_50MHZ },
179 { 6250000, SPI_CLK_6_250MHZ },
180 { 3125000, SPI_CLK_3_125MHZ },
181 { 1563000, SPI_CLK_1_563MHZ },
182 { 781000, SPI_CLK_0_781MHZ },
183 { 391000, SPI_CLK_0_391MHZ }
184};
185
186static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
187 struct spi_transfer *t)
188{
189 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
190 u8 clk_cfg, reg;
191 int i;
192
193 /* Default to lowest clock configuration */
194 clk_cfg = SPI_CLK_0_391MHZ;
195
196 /* Find the closest clock configuration */
197 for (i = 0; i < SPI_CLK_MASK; i++) {
198 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
199 clk_cfg = bcm63xx_spi_freq_table[i][1];
200 break;
201 }
202 }
203
204 /* clear existing clock configuration bits of the register */
205 reg = bcm_spi_readb(bs, SPI_CLK_CFG);
206 reg &= ~SPI_CLK_MASK;
207 reg |= clk_cfg;
208
209 bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
210 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
211 clk_cfg, t->speed_hz);
212}
213
214/* the spi->mode bits understood by this driver: */
215#define MODEBITS (SPI_CPOL | SPI_CPHA)
216
217static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
218 unsigned int num_transfers)
219{
220 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
221 u16 msg_ctl;
222 u16 cmd;
223 unsigned int i, timeout = 0, prepend_len = 0, len = 0;
224 struct spi_transfer *t = first;
225 bool do_rx = false;
226 bool do_tx = false;
227
228 /* Disable the CMD_DONE interrupt */
229 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
230
231 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
232 t->tx_buf, t->rx_buf, t->len);
233
234 if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
235 prepend_len = t->len;
236
237 /* prepare the buffer */
238 for (i = 0; i < num_transfers; i++) {
239 if (t->tx_buf) {
240 do_tx = true;
241 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
242
243 /* don't prepend more than one tx */
244 if (t != first)
245 prepend_len = 0;
246 }
247
248 if (t->rx_buf) {
249 do_rx = true;
250 /* prepend is half-duplex write only */
251 if (t == first)
252 prepend_len = 0;
253 }
254
255 len += t->len;
256
257 t = list_entry(t->transfer_list.next, struct spi_transfer,
258 transfer_list);
259 }
260
261 reinit_completion(&bs->done);
262
263 /* Fill in the Message control register */
264 msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
265
266 if (do_rx && do_tx && prepend_len == 0)
267 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
268 else if (do_rx)
269 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
270 else if (do_tx)
271 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
272
273 switch (bs->msg_ctl_width) {
274 case 8:
275 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
276 break;
277 case 16:
278 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
279 break;
280 }
281
282 /* Issue the transfer */
283 cmd = SPI_CMD_START_IMMEDIATE;
284 cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
285 cmd |= (spi_get_chipselect(spi, 0) << SPI_CMD_DEVICE_ID_SHIFT);
286 bcm_spi_writew(bs, cmd, SPI_CMD);
287
288 /* Enable the CMD_DONE interrupt */
289 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
290
291 timeout = wait_for_completion_timeout(&bs->done, HZ);
292 if (!timeout)
293 return -ETIMEDOUT;
294
295 if (!do_rx)
296 return 0;
297
298 len = 0;
299 t = first;
300 /* Read out all the data */
301 for (i = 0; i < num_transfers; i++) {
302 if (t->rx_buf)
303 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
304
305 if (t != first || prepend_len == 0)
306 len += t->len;
307
308 t = list_entry(t->transfer_list.next, struct spi_transfer,
309 transfer_list);
310 }
311
312 return 0;
313}
314
315static int bcm63xx_spi_transfer_one(struct spi_controller *host,
316 struct spi_message *m)
317{
318 struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
319 struct spi_transfer *t, *first = NULL;
320 struct spi_device *spi = m->spi;
321 int status = 0;
322 unsigned int n_transfers = 0, total_len = 0;
323 bool can_use_prepend = false;
324
325 /*
326 * This SPI controller does not support keeping CS active after a
327 * transfer.
328 * Work around this by merging as many transfers we can into one big
329 * full-duplex transfers.
330 */
331 list_for_each_entry(t, &m->transfers, transfer_list) {
332 if (!first)
333 first = t;
334
335 n_transfers++;
336 total_len += t->len;
337
338 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
339 first->len <= BCM63XX_SPI_MAX_PREPEND)
340 can_use_prepend = true;
341 else if (can_use_prepend && t->tx_buf)
342 can_use_prepend = false;
343
344 /* we can only transfer one fifo worth of data */
345 if ((can_use_prepend &&
346 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
347 (!can_use_prepend && total_len > bs->fifo_size)) {
348 dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
349 total_len, bs->fifo_size);
350 status = -EINVAL;
351 goto exit;
352 }
353
354 /* all combined transfers have to have the same speed */
355 if (t->speed_hz != first->speed_hz) {
356 dev_err(&spi->dev, "unable to change speed between transfers\n");
357 status = -EINVAL;
358 goto exit;
359 }
360
361 /* CS will be deasserted directly after transfer */
362 if (t->delay.value) {
363 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
364 status = -EINVAL;
365 goto exit;
366 }
367
368 if (t->cs_change ||
369 list_is_last(&t->transfer_list, &m->transfers)) {
370 /* configure adapter for a new transfer */
371 bcm63xx_spi_setup_transfer(spi, first);
372
373 /* send the data */
374 status = bcm63xx_txrx_bufs(spi, first, n_transfers);
375 if (status)
376 goto exit;
377
378 m->actual_length += total_len;
379
380 first = NULL;
381 n_transfers = 0;
382 total_len = 0;
383 can_use_prepend = false;
384 }
385 }
386exit:
387 m->status = status;
388 spi_finalize_current_message(host);
389
390 return 0;
391}
392
393/* This driver supports single host mode only. Hence
394 * CMD_DONE is the only interrupt we care about
395 */
396static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
397{
398 struct spi_controller *host = (struct spi_controller *)dev_id;
399 struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
400 u8 intr;
401
402 /* Read interupts and clear them immediately */
403 intr = bcm_spi_readb(bs, SPI_INT_STATUS);
404 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
405 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
406
407 /* A transfer completed */
408 if (intr & SPI_INTR_CMD_DONE)
409 complete(&bs->done);
410
411 return IRQ_HANDLED;
412}
413
414static size_t bcm63xx_spi_max_length(struct spi_device *spi)
415{
416 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
417
418 return bs->fifo_size;
419}
420
421static const unsigned long bcm6348_spi_reg_offsets[] = {
422 [SPI_CMD] = SPI_6348_CMD,
423 [SPI_INT_STATUS] = SPI_6348_INT_STATUS,
424 [SPI_INT_MASK_ST] = SPI_6348_INT_MASK_ST,
425 [SPI_INT_MASK] = SPI_6348_INT_MASK,
426 [SPI_ST] = SPI_6348_ST,
427 [SPI_CLK_CFG] = SPI_6348_CLK_CFG,
428 [SPI_FILL_BYTE] = SPI_6348_FILL_BYTE,
429 [SPI_MSG_TAIL] = SPI_6348_MSG_TAIL,
430 [SPI_RX_TAIL] = SPI_6348_RX_TAIL,
431 [SPI_MSG_CTL] = SPI_6348_MSG_CTL,
432 [SPI_MSG_DATA] = SPI_6348_MSG_DATA,
433 [SPI_RX_DATA] = SPI_6348_RX_DATA,
434 [SPI_MSG_TYPE_SHIFT] = SPI_6348_MSG_TYPE_SHIFT,
435 [SPI_MSG_CTL_WIDTH] = SPI_6348_MSG_CTL_WIDTH,
436 [SPI_MSG_DATA_SIZE] = SPI_6348_MSG_DATA_SIZE,
437};
438
439static const unsigned long bcm6358_spi_reg_offsets[] = {
440 [SPI_CMD] = SPI_6358_CMD,
441 [SPI_INT_STATUS] = SPI_6358_INT_STATUS,
442 [SPI_INT_MASK_ST] = SPI_6358_INT_MASK_ST,
443 [SPI_INT_MASK] = SPI_6358_INT_MASK,
444 [SPI_ST] = SPI_6358_ST,
445 [SPI_CLK_CFG] = SPI_6358_CLK_CFG,
446 [SPI_FILL_BYTE] = SPI_6358_FILL_BYTE,
447 [SPI_MSG_TAIL] = SPI_6358_MSG_TAIL,
448 [SPI_RX_TAIL] = SPI_6358_RX_TAIL,
449 [SPI_MSG_CTL] = SPI_6358_MSG_CTL,
450 [SPI_MSG_DATA] = SPI_6358_MSG_DATA,
451 [SPI_RX_DATA] = SPI_6358_RX_DATA,
452 [SPI_MSG_TYPE_SHIFT] = SPI_6358_MSG_TYPE_SHIFT,
453 [SPI_MSG_CTL_WIDTH] = SPI_6358_MSG_CTL_WIDTH,
454 [SPI_MSG_DATA_SIZE] = SPI_6358_MSG_DATA_SIZE,
455};
456
457static const struct platform_device_id bcm63xx_spi_dev_match[] = {
458 {
459 .name = "bcm6348-spi",
460 .driver_data = (unsigned long)bcm6348_spi_reg_offsets,
461 },
462 {
463 .name = "bcm6358-spi",
464 .driver_data = (unsigned long)bcm6358_spi_reg_offsets,
465 },
466 {
467 },
468};
469
470static const struct of_device_id bcm63xx_spi_of_match[] = {
471 { .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets },
472 { .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets },
473 { },
474};
475
476static int bcm63xx_spi_probe(struct platform_device *pdev)
477{
478 struct resource *r;
479 const unsigned long *bcm63xx_spireg;
480 struct device *dev = &pdev->dev;
481 int irq, bus_num;
482 struct spi_controller *host;
483 struct clk *clk;
484 struct bcm63xx_spi *bs;
485 int ret;
486 u32 num_cs = BCM63XX_SPI_MAX_CS;
487 struct reset_control *reset;
488
489 if (dev->of_node) {
490 const struct of_device_id *match;
491
492 match = of_match_node(bcm63xx_spi_of_match, dev->of_node);
493 if (!match)
494 return -EINVAL;
495 bcm63xx_spireg = match->data;
496
497 of_property_read_u32(dev->of_node, "num-cs", &num_cs);
498 if (num_cs > BCM63XX_SPI_MAX_CS) {
499 dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
500 num_cs);
501 num_cs = BCM63XX_SPI_MAX_CS;
502 }
503
504 bus_num = -1;
505 } else if (pdev->id_entry->driver_data) {
506 const struct platform_device_id *match = pdev->id_entry;
507
508 bcm63xx_spireg = (const unsigned long *)match->driver_data;
509 bus_num = BCM63XX_SPI_BUS_NUM;
510 } else {
511 return -EINVAL;
512 }
513
514 irq = platform_get_irq(pdev, 0);
515 if (irq < 0)
516 return irq;
517
518 clk = devm_clk_get(dev, "spi");
519 if (IS_ERR(clk)) {
520 dev_err(dev, "no clock for device\n");
521 return PTR_ERR(clk);
522 }
523
524 reset = devm_reset_control_get_optional_exclusive(dev, NULL);
525 if (IS_ERR(reset))
526 return PTR_ERR(reset);
527
528 host = spi_alloc_host(dev, sizeof(*bs));
529 if (!host) {
530 dev_err(dev, "out of memory\n");
531 return -ENOMEM;
532 }
533
534 bs = spi_controller_get_devdata(host);
535 init_completion(&bs->done);
536
537 platform_set_drvdata(pdev, host);
538 bs->pdev = pdev;
539
540 bs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
541 if (IS_ERR(bs->regs)) {
542 ret = PTR_ERR(bs->regs);
543 goto out_err;
544 }
545
546 bs->irq = irq;
547 bs->clk = clk;
548 bs->reg_offsets = bcm63xx_spireg;
549 bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
550
551 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
552 pdev->name, host);
553 if (ret) {
554 dev_err(dev, "unable to request irq\n");
555 goto out_err;
556 }
557
558 host->dev.of_node = dev->of_node;
559 host->bus_num = bus_num;
560 host->num_chipselect = num_cs;
561 host->transfer_one_message = bcm63xx_spi_transfer_one;
562 host->mode_bits = MODEBITS;
563 host->bits_per_word_mask = SPI_BPW_MASK(8);
564 host->max_transfer_size = bcm63xx_spi_max_length;
565 host->max_message_size = bcm63xx_spi_max_length;
566 host->auto_runtime_pm = true;
567 bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
568 bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
569 bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
570 bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
571
572 /* Initialize hardware */
573 ret = clk_prepare_enable(bs->clk);
574 if (ret)
575 goto out_err;
576
577 ret = reset_control_reset(reset);
578 if (ret) {
579 dev_err(dev, "unable to reset device: %d\n", ret);
580 goto out_clk_disable;
581 }
582
583 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
584
585 pm_runtime_enable(&pdev->dev);
586
587 /* register and we are done */
588 ret = devm_spi_register_controller(dev, host);
589 if (ret) {
590 dev_err(dev, "spi register failed\n");
591 goto out_pm_disable;
592 }
593
594 dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
595 r, irq, bs->fifo_size);
596
597 return 0;
598
599out_pm_disable:
600 pm_runtime_disable(&pdev->dev);
601out_clk_disable:
602 clk_disable_unprepare(clk);
603out_err:
604 spi_controller_put(host);
605 return ret;
606}
607
608static void bcm63xx_spi_remove(struct platform_device *pdev)
609{
610 struct spi_controller *host = platform_get_drvdata(pdev);
611 struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
612
613 /* reset spi block */
614 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
615
616 /* HW shutdown */
617 clk_disable_unprepare(bs->clk);
618}
619
620static int bcm63xx_spi_suspend(struct device *dev)
621{
622 struct spi_controller *host = dev_get_drvdata(dev);
623 struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
624
625 spi_controller_suspend(host);
626
627 clk_disable_unprepare(bs->clk);
628
629 return 0;
630}
631
632static int bcm63xx_spi_resume(struct device *dev)
633{
634 struct spi_controller *host = dev_get_drvdata(dev);
635 struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
636 int ret;
637
638 ret = clk_prepare_enable(bs->clk);
639 if (ret)
640 return ret;
641
642 spi_controller_resume(host);
643
644 return 0;
645}
646
647static DEFINE_SIMPLE_DEV_PM_OPS(bcm63xx_spi_pm_ops, bcm63xx_spi_suspend, bcm63xx_spi_resume);
648
649static struct platform_driver bcm63xx_spi_driver = {
650 .driver = {
651 .name = "bcm63xx-spi",
652 .pm = &bcm63xx_spi_pm_ops,
653 .of_match_table = bcm63xx_spi_of_match,
654 },
655 .id_table = bcm63xx_spi_dev_match,
656 .probe = bcm63xx_spi_probe,
657 .remove_new = bcm63xx_spi_remove,
658};
659
660module_platform_driver(bcm63xx_spi_driver);
661
662MODULE_ALIAS("platform:bcm63xx_spi");
663MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
664MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
665MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
666MODULE_LICENSE("GPL");
1/*
2 * Broadcom BCM63xx SPI controller support
3 *
4 * Copyright (C) 2009-2012 Florian Fainelli <florian@openwrt.org>
5 * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the
19 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 */
21
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/delay.h>
29#include <linux/interrupt.h>
30#include <linux/spi/spi.h>
31#include <linux/completion.h>
32#include <linux/err.h>
33#include <linux/workqueue.h>
34#include <linux/pm_runtime.h>
35
36#include <bcm63xx_dev_spi.h>
37
38#define PFX KBUILD_MODNAME
39#define DRV_VER "0.1.2"
40
41struct bcm63xx_spi {
42 struct completion done;
43
44 void __iomem *regs;
45 int irq;
46
47 /* Platform data */
48 u32 speed_hz;
49 unsigned fifo_size;
50
51 /* Data buffers */
52 const unsigned char *tx_ptr;
53 unsigned char *rx_ptr;
54
55 /* data iomem */
56 u8 __iomem *tx_io;
57 const u8 __iomem *rx_io;
58
59 int remaining_bytes;
60
61 struct clk *clk;
62 struct platform_device *pdev;
63};
64
65static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
66 unsigned int offset)
67{
68 return bcm_readb(bs->regs + bcm63xx_spireg(offset));
69}
70
71static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
72 unsigned int offset)
73{
74 return bcm_readw(bs->regs + bcm63xx_spireg(offset));
75}
76
77static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
78 u8 value, unsigned int offset)
79{
80 bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
81}
82
83static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
84 u16 value, unsigned int offset)
85{
86 bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
87}
88
89static const unsigned bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
90 { 20000000, SPI_CLK_20MHZ },
91 { 12500000, SPI_CLK_12_50MHZ },
92 { 6250000, SPI_CLK_6_250MHZ },
93 { 3125000, SPI_CLK_3_125MHZ },
94 { 1563000, SPI_CLK_1_563MHZ },
95 { 781000, SPI_CLK_0_781MHZ },
96 { 391000, SPI_CLK_0_391MHZ }
97};
98
99static int bcm63xx_spi_check_transfer(struct spi_device *spi,
100 struct spi_transfer *t)
101{
102 u8 bits_per_word;
103
104 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
105 if (bits_per_word != 8) {
106 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
107 __func__, bits_per_word);
108 return -EINVAL;
109 }
110
111 if (spi->chip_select > spi->master->num_chipselect) {
112 dev_err(&spi->dev, "%s, unsupported slave %d\n",
113 __func__, spi->chip_select);
114 return -EINVAL;
115 }
116
117 return 0;
118}
119
120static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
121 struct spi_transfer *t)
122{
123 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
124 u32 hz;
125 u8 clk_cfg, reg;
126 int i;
127
128 hz = (t) ? t->speed_hz : spi->max_speed_hz;
129
130 /* Find the closest clock configuration */
131 for (i = 0; i < SPI_CLK_MASK; i++) {
132 if (hz <= bcm63xx_spi_freq_table[i][0]) {
133 clk_cfg = bcm63xx_spi_freq_table[i][1];
134 break;
135 }
136 }
137
138 /* No matching configuration found, default to lowest */
139 if (i == SPI_CLK_MASK)
140 clk_cfg = SPI_CLK_0_391MHZ;
141
142 /* clear existing clock configuration bits of the register */
143 reg = bcm_spi_readb(bs, SPI_CLK_CFG);
144 reg &= ~SPI_CLK_MASK;
145 reg |= clk_cfg;
146
147 bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
148 dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
149 clk_cfg, hz);
150}
151
152/* the spi->mode bits understood by this driver: */
153#define MODEBITS (SPI_CPOL | SPI_CPHA)
154
155static int bcm63xx_spi_setup(struct spi_device *spi)
156{
157 struct bcm63xx_spi *bs;
158 int ret;
159
160 bs = spi_master_get_devdata(spi->master);
161
162 if (!spi->bits_per_word)
163 spi->bits_per_word = 8;
164
165 if (spi->mode & ~MODEBITS) {
166 dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
167 __func__, spi->mode & ~MODEBITS);
168 return -EINVAL;
169 }
170
171 ret = bcm63xx_spi_check_transfer(spi, NULL);
172 if (ret < 0) {
173 dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
174 spi->mode & ~MODEBITS);
175 return ret;
176 }
177
178 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
179 __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
180
181 return 0;
182}
183
184/* Fill the TX FIFO with as many bytes as possible */
185static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
186{
187 u8 size;
188
189 /* Fill the Tx FIFO with as many bytes as possible */
190 size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
191 bs->fifo_size;
192 memcpy_toio(bs->tx_io, bs->tx_ptr, size);
193 bs->remaining_bytes -= size;
194}
195
196static unsigned int bcm63xx_txrx_bufs(struct spi_device *spi,
197 struct spi_transfer *t)
198{
199 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
200 u16 msg_ctl;
201 u16 cmd;
202
203 /* Disable the CMD_DONE interrupt */
204 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
205
206 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
207 t->tx_buf, t->rx_buf, t->len);
208
209 /* Transmitter is inhibited */
210 bs->tx_ptr = t->tx_buf;
211 bs->rx_ptr = t->rx_buf;
212
213 if (t->tx_buf) {
214 bs->remaining_bytes = t->len;
215 bcm63xx_spi_fill_tx_fifo(bs);
216 }
217
218 init_completion(&bs->done);
219
220 /* Fill in the Message control register */
221 msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
222
223 if (t->rx_buf && t->tx_buf)
224 msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
225 else if (t->rx_buf)
226 msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
227 else if (t->tx_buf)
228 msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
229
230 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
231
232 /* Issue the transfer */
233 cmd = SPI_CMD_START_IMMEDIATE;
234 cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
235 cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
236 bcm_spi_writew(bs, cmd, SPI_CMD);
237
238 /* Enable the CMD_DONE interrupt */
239 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
240
241 return t->len - bs->remaining_bytes;
242}
243
244static int bcm63xx_spi_prepare_transfer(struct spi_master *master)
245{
246 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
247
248 pm_runtime_get_sync(&bs->pdev->dev);
249
250 return 0;
251}
252
253static int bcm63xx_spi_unprepare_transfer(struct spi_master *master)
254{
255 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
256
257 pm_runtime_put(&bs->pdev->dev);
258
259 return 0;
260}
261
262static int bcm63xx_spi_transfer_one(struct spi_master *master,
263 struct spi_message *m)
264{
265 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
266 struct spi_transfer *t;
267 struct spi_device *spi = m->spi;
268 int status = 0;
269 unsigned int timeout = 0;
270
271 list_for_each_entry(t, &m->transfers, transfer_list) {
272 unsigned int len = t->len;
273 u8 rx_tail;
274
275 status = bcm63xx_spi_check_transfer(spi, t);
276 if (status < 0)
277 goto exit;
278
279 /* configure adapter for a new transfer */
280 bcm63xx_spi_setup_transfer(spi, t);
281
282 while (len) {
283 /* send the data */
284 len -= bcm63xx_txrx_bufs(spi, t);
285
286 timeout = wait_for_completion_timeout(&bs->done, HZ);
287 if (!timeout) {
288 status = -ETIMEDOUT;
289 goto exit;
290 }
291
292 /* read out all data */
293 rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
294
295 /* Read out all the data */
296 if (rx_tail)
297 memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
298 }
299
300 m->actual_length += t->len;
301 }
302exit:
303 m->status = status;
304 spi_finalize_current_message(master);
305
306 return 0;
307}
308
309/* This driver supports single master mode only. Hence
310 * CMD_DONE is the only interrupt we care about
311 */
312static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
313{
314 struct spi_master *master = (struct spi_master *)dev_id;
315 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
316 u8 intr;
317
318 /* Read interupts and clear them immediately */
319 intr = bcm_spi_readb(bs, SPI_INT_STATUS);
320 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
321 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
322
323 /* A transfer completed */
324 if (intr & SPI_INTR_CMD_DONE)
325 complete(&bs->done);
326
327 return IRQ_HANDLED;
328}
329
330
331static int __devinit bcm63xx_spi_probe(struct platform_device *pdev)
332{
333 struct resource *r;
334 struct device *dev = &pdev->dev;
335 struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
336 int irq;
337 struct spi_master *master;
338 struct clk *clk;
339 struct bcm63xx_spi *bs;
340 int ret;
341
342 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343 if (!r) {
344 dev_err(dev, "no iomem\n");
345 ret = -ENXIO;
346 goto out;
347 }
348
349 irq = platform_get_irq(pdev, 0);
350 if (irq < 0) {
351 dev_err(dev, "no irq\n");
352 ret = -ENXIO;
353 goto out;
354 }
355
356 clk = clk_get(dev, "spi");
357 if (IS_ERR(clk)) {
358 dev_err(dev, "no clock for device\n");
359 ret = PTR_ERR(clk);
360 goto out;
361 }
362
363 master = spi_alloc_master(dev, sizeof(*bs));
364 if (!master) {
365 dev_err(dev, "out of memory\n");
366 ret = -ENOMEM;
367 goto out_clk;
368 }
369
370 bs = spi_master_get_devdata(master);
371
372 platform_set_drvdata(pdev, master);
373 bs->pdev = pdev;
374
375 if (!devm_request_mem_region(&pdev->dev, r->start,
376 resource_size(r), PFX)) {
377 dev_err(dev, "iomem request failed\n");
378 ret = -ENXIO;
379 goto out_err;
380 }
381
382 bs->regs = devm_ioremap_nocache(&pdev->dev, r->start,
383 resource_size(r));
384 if (!bs->regs) {
385 dev_err(dev, "unable to ioremap regs\n");
386 ret = -ENOMEM;
387 goto out_err;
388 }
389
390 bs->irq = irq;
391 bs->clk = clk;
392 bs->fifo_size = pdata->fifo_size;
393
394 ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
395 pdev->name, master);
396 if (ret) {
397 dev_err(dev, "unable to request irq\n");
398 goto out_err;
399 }
400
401 master->bus_num = pdata->bus_num;
402 master->num_chipselect = pdata->num_chipselect;
403 master->setup = bcm63xx_spi_setup;
404 master->prepare_transfer_hardware = bcm63xx_spi_prepare_transfer;
405 master->unprepare_transfer_hardware = bcm63xx_spi_unprepare_transfer;
406 master->transfer_one_message = bcm63xx_spi_transfer_one;
407 master->mode_bits = MODEBITS;
408 bs->speed_hz = pdata->speed_hz;
409 bs->tx_io = (u8 *)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
410 bs->rx_io = (const u8 *)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
411
412 /* Initialize hardware */
413 clk_enable(bs->clk);
414 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
415
416 /* register and we are done */
417 ret = spi_register_master(master);
418 if (ret) {
419 dev_err(dev, "spi register failed\n");
420 goto out_clk_disable;
421 }
422
423 dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
424 r->start, irq, bs->fifo_size, DRV_VER);
425
426 return 0;
427
428out_clk_disable:
429 clk_disable(clk);
430out_err:
431 platform_set_drvdata(pdev, NULL);
432 spi_master_put(master);
433out_clk:
434 clk_put(clk);
435out:
436 return ret;
437}
438
439static int __devexit bcm63xx_spi_remove(struct platform_device *pdev)
440{
441 struct spi_master *master = platform_get_drvdata(pdev);
442 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
443
444 spi_unregister_master(master);
445
446 /* reset spi block */
447 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
448
449 /* HW shutdown */
450 clk_disable(bs->clk);
451 clk_put(bs->clk);
452
453 platform_set_drvdata(pdev, 0);
454
455 return 0;
456}
457
458#ifdef CONFIG_PM
459static int bcm63xx_spi_suspend(struct device *dev)
460{
461 struct spi_master *master =
462 platform_get_drvdata(to_platform_device(dev));
463 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
464
465 clk_disable(bs->clk);
466
467 return 0;
468}
469
470static int bcm63xx_spi_resume(struct device *dev)
471{
472 struct spi_master *master =
473 platform_get_drvdata(to_platform_device(dev));
474 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
475
476 clk_enable(bs->clk);
477
478 return 0;
479}
480
481static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
482 .suspend = bcm63xx_spi_suspend,
483 .resume = bcm63xx_spi_resume,
484};
485
486#define BCM63XX_SPI_PM_OPS (&bcm63xx_spi_pm_ops)
487#else
488#define BCM63XX_SPI_PM_OPS NULL
489#endif
490
491static struct platform_driver bcm63xx_spi_driver = {
492 .driver = {
493 .name = "bcm63xx-spi",
494 .owner = THIS_MODULE,
495 .pm = BCM63XX_SPI_PM_OPS,
496 },
497 .probe = bcm63xx_spi_probe,
498 .remove = __devexit_p(bcm63xx_spi_remove),
499};
500
501module_platform_driver(bcm63xx_spi_driver);
502
503MODULE_ALIAS("platform:bcm63xx_spi");
504MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
505MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
506MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
507MODULE_LICENSE("GPL");