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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
4 *
5 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
6 *
7 * VME support added by Sam Creasey
8 *
9 * TODO: modify this driver to support multiple Sun3 SCSI VME boards
10 *
11 * Adapted from mac_scsinew.c:
12 */
13/*
14 * Generic Macintosh NCR5380 driver
15 *
16 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
17 *
18 * derived in part from:
19 */
20/*
21 * Generic Generic NCR5380 driver
22 *
23 * Copyright 1995, Russell King
24 */
25
26#include <linux/types.h>
27#include <linux/delay.h>
28#include <linux/module.h>
29#include <linux/ioport.h>
30#include <linux/init.h>
31#include <linux/blkdev.h>
32#include <linux/platform_device.h>
33
34#include <asm/io.h>
35#include <asm/dvma.h>
36
37#include <scsi/scsi_host.h>
38
39/* minimum number of bytes to do dma on */
40#define DMA_MIN_SIZE 129
41
42/* Definitions for the core NCR5380 driver. */
43
44#define NCR5380_implementation_fields /* none */
45
46#define NCR5380_read(reg) in_8(hostdata->io + (reg))
47#define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value)
48
49#define NCR5380_queue_command sun3scsi_queue_command
50#define NCR5380_host_reset sun3scsi_host_reset
51#define NCR5380_abort sun3scsi_abort
52#define NCR5380_info sun3scsi_info
53
54#define NCR5380_dma_xfer_len sun3scsi_dma_xfer_len
55#define NCR5380_dma_recv_setup sun3scsi_dma_count
56#define NCR5380_dma_send_setup sun3scsi_dma_count
57#define NCR5380_dma_residual sun3scsi_dma_residual
58
59#include "NCR5380.h"
60
61/* dma regs start at regbase + 8, directly after the NCR regs */
62struct sun3_dma_regs {
63 unsigned short dma_addr_hi; /* vme only */
64 unsigned short dma_addr_lo; /* vme only */
65 unsigned short dma_count_hi; /* vme only */
66 unsigned short dma_count_lo; /* vme only */
67 unsigned short udc_data; /* udc dma data reg (obio only) */
68 unsigned short udc_addr; /* uda dma addr reg (obio only) */
69 unsigned short fifo_data; /* fifo data reg,
70 * holds extra byte on odd dma reads
71 */
72 unsigned short fifo_count;
73 unsigned short csr; /* control/status reg */
74 unsigned short bpack_hi; /* vme only */
75 unsigned short bpack_lo; /* vme only */
76 unsigned short ivect; /* vme only */
77 unsigned short fifo_count_hi; /* vme only */
78};
79
80/* ucd chip specific regs - live in dvma space */
81struct sun3_udc_regs {
82 unsigned short rsel; /* select regs to load */
83 unsigned short addr_hi; /* high word of addr */
84 unsigned short addr_lo; /* low word */
85 unsigned short count; /* words to be xfer'd */
86 unsigned short mode_hi; /* high word of channel mode */
87 unsigned short mode_lo; /* low word of channel mode */
88};
89
90/* addresses of the udc registers */
91#define UDC_MODE 0x38
92#define UDC_CSR 0x2e /* command/status */
93#define UDC_CHN_HI 0x26 /* chain high word */
94#define UDC_CHN_LO 0x22 /* chain lo word */
95#define UDC_CURA_HI 0x1a /* cur reg A high */
96#define UDC_CURA_LO 0x0a /* cur reg A low */
97#define UDC_CURB_HI 0x12 /* cur reg B high */
98#define UDC_CURB_LO 0x02 /* cur reg B low */
99#define UDC_MODE_HI 0x56 /* mode reg high */
100#define UDC_MODE_LO 0x52 /* mode reg low */
101#define UDC_COUNT 0x32 /* words to xfer */
102
103/* some udc commands */
104#define UDC_RESET 0
105#define UDC_CHN_START 0xa0 /* start chain */
106#define UDC_INT_ENABLE 0x32 /* channel 1 int on */
107
108/* udc mode words */
109#define UDC_MODE_HIWORD 0x40
110#define UDC_MODE_LSEND 0xc2
111#define UDC_MODE_LRECV 0xd2
112
113/* udc reg selections */
114#define UDC_RSEL_SEND 0x282
115#define UDC_RSEL_RECV 0x182
116
117/* bits in csr reg */
118#define CSR_DMA_ACTIVE 0x8000
119#define CSR_DMA_CONFLICT 0x4000
120#define CSR_DMA_BUSERR 0x2000
121
122#define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
123#define CSR_SDB_INT 0x200 /* sbc interrupt pending */
124#define CSR_DMA_INT 0x100 /* dma interrupt pending */
125
126#define CSR_LEFT 0xc0
127#define CSR_LEFT_3 0xc0
128#define CSR_LEFT_2 0x80
129#define CSR_LEFT_1 0x40
130#define CSR_PACK_ENABLE 0x20
131
132#define CSR_DMA_ENABLE 0x10
133
134#define CSR_SEND 0x8 /* 1 = send 0 = recv */
135#define CSR_FIFO 0x2 /* reset fifo */
136#define CSR_INTR 0x4 /* interrupt enable */
137#define CSR_SCSI 0x1
138
139#define VME_DATA24 0x3d00
140
141extern int sun3_map_test(unsigned long, char *);
142
143static int setup_can_queue = -1;
144module_param(setup_can_queue, int, 0);
145static int setup_cmd_per_lun = -1;
146module_param(setup_cmd_per_lun, int, 0);
147static int setup_sg_tablesize = -1;
148module_param(setup_sg_tablesize, int, 0);
149static int setup_hostid = -1;
150module_param(setup_hostid, int, 0);
151
152/* ms to wait after hitting dma regs */
153#define SUN3_DMA_DELAY 10
154
155/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
156#define SUN3_DVMA_BUFSIZE 0xe000
157
158static struct scsi_cmnd *sun3_dma_setup_done;
159static volatile struct sun3_dma_regs *dregs;
160static struct sun3_udc_regs *udc_regs;
161static unsigned char *sun3_dma_orig_addr;
162static unsigned long sun3_dma_orig_count;
163static int sun3_dma_active;
164static unsigned long last_residual;
165
166#ifndef SUN3_SCSI_VME
167/* dma controller register access functions */
168
169static inline unsigned short sun3_udc_read(unsigned char reg)
170{
171 unsigned short ret;
172
173 dregs->udc_addr = UDC_CSR;
174 udelay(SUN3_DMA_DELAY);
175 ret = dregs->udc_data;
176 udelay(SUN3_DMA_DELAY);
177
178 return ret;
179}
180
181static inline void sun3_udc_write(unsigned short val, unsigned char reg)
182{
183 dregs->udc_addr = reg;
184 udelay(SUN3_DMA_DELAY);
185 dregs->udc_data = val;
186 udelay(SUN3_DMA_DELAY);
187}
188#endif
189
190// safe bits for the CSR
191#define CSR_GOOD 0x060f
192
193static irqreturn_t scsi_sun3_intr(int irq, void *dev)
194{
195 struct Scsi_Host *instance = dev;
196 unsigned short csr = dregs->csr;
197 int handled = 0;
198
199#ifdef SUN3_SCSI_VME
200 dregs->csr &= ~CSR_DMA_ENABLE;
201#endif
202
203 if(csr & ~CSR_GOOD) {
204 if (csr & CSR_DMA_BUSERR)
205 shost_printk(KERN_ERR, instance, "bus error in DMA\n");
206 if (csr & CSR_DMA_CONFLICT)
207 shost_printk(KERN_ERR, instance, "DMA conflict\n");
208 handled = 1;
209 }
210
211 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
212 NCR5380_intr(irq, dev);
213 handled = 1;
214 }
215
216 return IRQ_RETVAL(handled);
217}
218
219/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
220static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata,
221 unsigned char *data, int count, int write_flag)
222{
223 void *addr;
224
225 if(sun3_dma_orig_addr != NULL)
226 dvma_unmap(sun3_dma_orig_addr);
227
228#ifdef SUN3_SCSI_VME
229 addr = (void *)dvma_map_vme((unsigned long) data, count);
230#else
231 addr = (void *)dvma_map((unsigned long) data, count);
232#endif
233
234 sun3_dma_orig_addr = addr;
235 sun3_dma_orig_count = count;
236
237#ifndef SUN3_SCSI_VME
238 dregs->fifo_count = 0;
239 sun3_udc_write(UDC_RESET, UDC_CSR);
240
241 /* reset fifo */
242 dregs->csr &= ~CSR_FIFO;
243 dregs->csr |= CSR_FIFO;
244#endif
245
246 /* set direction */
247 if(write_flag)
248 dregs->csr |= CSR_SEND;
249 else
250 dregs->csr &= ~CSR_SEND;
251
252#ifdef SUN3_SCSI_VME
253 dregs->csr |= CSR_PACK_ENABLE;
254
255 dregs->dma_addr_hi = ((unsigned long)addr >> 16);
256 dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
257
258 dregs->dma_count_hi = 0;
259 dregs->dma_count_lo = 0;
260 dregs->fifo_count_hi = 0;
261 dregs->fifo_count = 0;
262#else
263 /* byte count for fifo */
264 dregs->fifo_count = count;
265
266 sun3_udc_write(UDC_RESET, UDC_CSR);
267
268 /* reset fifo */
269 dregs->csr &= ~CSR_FIFO;
270 dregs->csr |= CSR_FIFO;
271
272 if(dregs->fifo_count != count) {
273 shost_printk(KERN_ERR, hostdata->host,
274 "FIFO mismatch %04x not %04x\n",
275 dregs->fifo_count, (unsigned int) count);
276 NCR5380_dprint(NDEBUG_DMA, hostdata->host);
277 }
278
279 /* setup udc */
280 udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
281 udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
282 udc_regs->count = count/2; /* count in words */
283 udc_regs->mode_hi = UDC_MODE_HIWORD;
284 if(write_flag) {
285 if(count & 1)
286 udc_regs->count++;
287 udc_regs->mode_lo = UDC_MODE_LSEND;
288 udc_regs->rsel = UDC_RSEL_SEND;
289 } else {
290 udc_regs->mode_lo = UDC_MODE_LRECV;
291 udc_regs->rsel = UDC_RSEL_RECV;
292 }
293
294 /* announce location of regs block */
295 sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
296 UDC_CHN_HI);
297
298 sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
299
300 /* set dma master on */
301 sun3_udc_write(0xd, UDC_MODE);
302
303 /* interrupt enable */
304 sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
305#endif
306
307 return count;
308
309}
310
311static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata,
312 unsigned char *data, int count)
313{
314 return count;
315}
316
317static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata,
318 unsigned char *data, int count)
319{
320 return sun3scsi_dma_setup(hostdata, data, count, 0);
321}
322
323static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata,
324 unsigned char *data, int count)
325{
326 return sun3scsi_dma_setup(hostdata, data, count, 1);
327}
328
329static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata)
330{
331 return last_residual;
332}
333
334static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
335 struct scsi_cmnd *cmd)
336{
337 int wanted_len = NCR5380_to_ncmd(cmd)->this_residual;
338
339 if (wanted_len < DMA_MIN_SIZE || blk_rq_is_passthrough(scsi_cmd_to_rq(cmd)))
340 return 0;
341
342 return wanted_len;
343}
344
345static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
346{
347#ifdef SUN3_SCSI_VME
348 unsigned short csr;
349
350 csr = dregs->csr;
351
352 dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
353 dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
354
355 dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
356 dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
357
358/* if(!(csr & CSR_DMA_ENABLE))
359 * dregs->csr |= CSR_DMA_ENABLE;
360 */
361#else
362 sun3_udc_write(UDC_CHN_START, UDC_CSR);
363#endif
364
365 return 0;
366}
367
368/* clean up after our dma is done */
369static int sun3scsi_dma_finish(enum dma_data_direction data_dir)
370{
371 const bool write_flag = data_dir == DMA_TO_DEVICE;
372 unsigned short __maybe_unused count;
373 unsigned short fifo;
374 int ret = 0;
375
376 sun3_dma_active = 0;
377
378#ifdef SUN3_SCSI_VME
379 dregs->csr &= ~CSR_DMA_ENABLE;
380
381 fifo = dregs->fifo_count;
382 if (write_flag) {
383 if ((fifo > 0) && (fifo < sun3_dma_orig_count))
384 fifo++;
385 }
386
387 last_residual = fifo;
388 /* empty bytes from the fifo which didn't make it */
389 if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
390 unsigned char *vaddr;
391
392 vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);
393
394 vaddr += (sun3_dma_orig_count - fifo);
395 vaddr--;
396
397 switch (dregs->csr & CSR_LEFT) {
398 case CSR_LEFT_3:
399 *vaddr = (dregs->bpack_lo & 0xff00) >> 8;
400 vaddr--;
401 fallthrough;
402
403 case CSR_LEFT_2:
404 *vaddr = (dregs->bpack_hi & 0x00ff);
405 vaddr--;
406 fallthrough;
407
408 case CSR_LEFT_1:
409 *vaddr = (dregs->bpack_hi & 0xff00) >> 8;
410 break;
411 }
412 }
413#else
414 // check to empty the fifo on a read
415 if(!write_flag) {
416 int tmo = 20000; /* .2 sec */
417
418 while(1) {
419 if(dregs->csr & CSR_FIFO_EMPTY)
420 break;
421
422 if(--tmo <= 0) {
423 printk("sun3scsi: fifo failed to empty!\n");
424 return 1;
425 }
426 udelay(10);
427 }
428 }
429
430 dregs->udc_addr = 0x32;
431 udelay(SUN3_DMA_DELAY);
432 count = 2 * dregs->udc_data;
433 udelay(SUN3_DMA_DELAY);
434
435 fifo = dregs->fifo_count;
436 last_residual = fifo;
437
438 /* empty bytes from the fifo which didn't make it */
439 if((!write_flag) && (count - fifo) == 2) {
440 unsigned short data;
441 unsigned char *vaddr;
442
443 data = dregs->fifo_data;
444 vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
445
446 vaddr += (sun3_dma_orig_count - fifo);
447
448 vaddr[-2] = (data & 0xff00) >> 8;
449 vaddr[-1] = (data & 0xff);
450 }
451#endif
452
453 dvma_unmap(sun3_dma_orig_addr);
454 sun3_dma_orig_addr = NULL;
455
456#ifdef SUN3_SCSI_VME
457 dregs->dma_addr_hi = 0;
458 dregs->dma_addr_lo = 0;
459 dregs->dma_count_hi = 0;
460 dregs->dma_count_lo = 0;
461
462 dregs->fifo_count = 0;
463 dregs->fifo_count_hi = 0;
464
465 dregs->csr &= ~CSR_SEND;
466/* dregs->csr |= CSR_DMA_ENABLE; */
467#else
468 sun3_udc_write(UDC_RESET, UDC_CSR);
469 dregs->fifo_count = 0;
470 dregs->csr &= ~CSR_SEND;
471
472 /* reset fifo */
473 dregs->csr &= ~CSR_FIFO;
474 dregs->csr |= CSR_FIFO;
475#endif
476
477 sun3_dma_setup_done = NULL;
478
479 return ret;
480
481}
482
483#include "NCR5380.c"
484
485#ifdef SUN3_SCSI_VME
486#define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
487#define DRV_MODULE_NAME "sun3_scsi_vme"
488#else
489#define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
490#define DRV_MODULE_NAME "sun3_scsi"
491#endif
492
493#define PFX DRV_MODULE_NAME ": "
494
495static struct scsi_host_template sun3_scsi_template = {
496 .module = THIS_MODULE,
497 .proc_name = DRV_MODULE_NAME,
498 .name = SUN3_SCSI_NAME,
499 .info = sun3scsi_info,
500 .queuecommand = sun3scsi_queue_command,
501 .eh_abort_handler = sun3scsi_abort,
502 .eh_host_reset_handler = sun3scsi_host_reset,
503 .can_queue = 16,
504 .this_id = 7,
505 .sg_tablesize = 1,
506 .cmd_per_lun = 2,
507 .dma_boundary = PAGE_SIZE - 1,
508 .cmd_size = sizeof(struct NCR5380_cmd),
509};
510
511static int __init sun3_scsi_probe(struct platform_device *pdev)
512{
513 struct Scsi_Host *instance;
514 struct NCR5380_hostdata *hostdata;
515 int error;
516 struct resource *irq, *mem;
517 void __iomem *ioaddr;
518 int host_flags = 0;
519#ifdef SUN3_SCSI_VME
520 int i;
521#endif
522
523 if (setup_can_queue > 0)
524 sun3_scsi_template.can_queue = setup_can_queue;
525 if (setup_cmd_per_lun > 0)
526 sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
527 if (setup_sg_tablesize > 0)
528 sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
529 if (setup_hostid >= 0)
530 sun3_scsi_template.this_id = setup_hostid & 7;
531
532#ifdef SUN3_SCSI_VME
533 ioaddr = NULL;
534 for (i = 0; i < 2; i++) {
535 unsigned char x;
536
537 irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
538 mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
539 if (!irq || !mem)
540 break;
541
542 ioaddr = sun3_ioremap(mem->start, resource_size(mem),
543 SUN3_PAGE_TYPE_VME16);
544 dregs = (struct sun3_dma_regs *)(ioaddr + 8);
545
546 if (sun3_map_test((unsigned long)dregs, &x)) {
547 unsigned short oldcsr;
548
549 oldcsr = dregs->csr;
550 dregs->csr = 0;
551 udelay(SUN3_DMA_DELAY);
552 if (dregs->csr == 0x1400)
553 break;
554
555 dregs->csr = oldcsr;
556 }
557
558 iounmap(ioaddr);
559 ioaddr = NULL;
560 }
561 if (!ioaddr)
562 return -ENODEV;
563#else
564 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
565 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
566 if (!irq || !mem)
567 return -ENODEV;
568
569 ioaddr = ioremap(mem->start, resource_size(mem));
570 dregs = (struct sun3_dma_regs *)(ioaddr + 8);
571
572 udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
573 if (!udc_regs) {
574 pr_err(PFX "couldn't allocate DVMA memory!\n");
575 iounmap(ioaddr);
576 return -ENOMEM;
577 }
578#endif
579
580 instance = scsi_host_alloc(&sun3_scsi_template,
581 sizeof(struct NCR5380_hostdata));
582 if (!instance) {
583 error = -ENOMEM;
584 goto fail_alloc;
585 }
586
587 instance->irq = irq->start;
588
589 hostdata = shost_priv(instance);
590 hostdata->base = mem->start;
591 hostdata->io = ioaddr;
592
593 error = NCR5380_init(instance, host_flags);
594 if (error)
595 goto fail_init;
596
597 error = request_irq(instance->irq, scsi_sun3_intr, 0,
598 "NCR5380", instance);
599 if (error) {
600 pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
601 instance->host_no, instance->irq);
602 goto fail_irq;
603 }
604
605 dregs->csr = 0;
606 udelay(SUN3_DMA_DELAY);
607 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
608 udelay(SUN3_DMA_DELAY);
609 dregs->fifo_count = 0;
610#ifdef SUN3_SCSI_VME
611 dregs->fifo_count_hi = 0;
612 dregs->dma_addr_hi = 0;
613 dregs->dma_addr_lo = 0;
614 dregs->dma_count_hi = 0;
615 dregs->dma_count_lo = 0;
616
617 dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
618#endif
619
620 NCR5380_maybe_reset_bus(instance);
621
622 error = scsi_add_host(instance, NULL);
623 if (error)
624 goto fail_host;
625
626 platform_set_drvdata(pdev, instance);
627
628 scsi_scan_host(instance);
629 return 0;
630
631fail_host:
632 free_irq(instance->irq, instance);
633fail_irq:
634 NCR5380_exit(instance);
635fail_init:
636 scsi_host_put(instance);
637fail_alloc:
638 if (udc_regs)
639 dvma_free(udc_regs);
640 iounmap(ioaddr);
641 return error;
642}
643
644static void __exit sun3_scsi_remove(struct platform_device *pdev)
645{
646 struct Scsi_Host *instance = platform_get_drvdata(pdev);
647 struct NCR5380_hostdata *hostdata = shost_priv(instance);
648 void __iomem *ioaddr = hostdata->io;
649
650 scsi_remove_host(instance);
651 free_irq(instance->irq, instance);
652 NCR5380_exit(instance);
653 scsi_host_put(instance);
654 if (udc_regs)
655 dvma_free(udc_regs);
656 iounmap(ioaddr);
657}
658
659static struct platform_driver sun3_scsi_driver = {
660 .remove_new = __exit_p(sun3_scsi_remove),
661 .driver = {
662 .name = DRV_MODULE_NAME,
663 },
664};
665
666module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);
667
668MODULE_ALIAS("platform:" DRV_MODULE_NAME);
669MODULE_LICENSE("GPL");
1/*
2 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
3 *
4 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
5 *
6 * Adapted from mac_scsinew.c:
7 */
8/*
9 * Generic Macintosh NCR5380 driver
10 *
11 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
12 *
13 * derived in part from:
14 */
15/*
16 * Generic Generic NCR5380 driver
17 *
18 * Copyright 1995, Russell King
19 *
20 * ALPHA RELEASE 1.
21 *
22 * For more information, please consult
23 *
24 * NCR 5380 Family
25 * SCSI Protocol Controller
26 * Databook
27 *
28 * NCR Microelectronics
29 * 1635 Aeroplaza Drive
30 * Colorado Springs, CO 80916
31 * 1+ (719) 578-3400
32 * 1+ (800) 334-5454
33 */
34
35
36/*
37 * This is from mac_scsi.h, but hey, maybe this is useful for Sun3 too! :)
38 *
39 * Options :
40 *
41 * PARITY - enable parity checking. Not supported.
42 *
43 * SCSI2 - enable support for SCSI-II tagged queueing. Untested.
44 *
45 * USLEEP - enable support for devices that don't disconnect. Untested.
46 */
47
48/*
49 * $Log: sun3_NCR5380.c,v $
50 */
51
52#define AUTOSENSE
53
54#include <linux/types.h>
55#include <linux/stddef.h>
56#include <linux/ctype.h>
57#include <linux/delay.h>
58
59#include <linux/module.h>
60#include <linux/signal.h>
61#include <linux/ioport.h>
62#include <linux/init.h>
63#include <linux/blkdev.h>
64
65#include <asm/io.h>
66
67#include <asm/sun3ints.h>
68#include <asm/dvma.h>
69#include <asm/idprom.h>
70#include <asm/machines.h>
71
72#define NDEBUG 0
73
74#define NDEBUG_ABORT 0x00100000
75#define NDEBUG_TAGS 0x00200000
76#define NDEBUG_MERGING 0x00400000
77
78/* dma on! */
79#define REAL_DMA
80
81#include "scsi.h"
82#include "initio.h"
83#include <scsi/scsi_host.h>
84#include "sun3_scsi.h"
85
86static void NCR5380_print(struct Scsi_Host *instance);
87
88/* #define OLDDMA */
89
90#define USE_WRAPPER
91/*#define RESET_BOOT */
92#define DRIVER_SETUP
93
94/*
95 * BUG can be used to trigger a strange code-size related hang on 2.1 kernels
96 */
97#ifdef BUG
98#undef RESET_BOOT
99#undef DRIVER_SETUP
100#endif
101
102/* #define SUPPORT_TAGS */
103
104#define ENABLE_IRQ() enable_irq( IRQ_SUN3_SCSI );
105
106
107static irqreturn_t scsi_sun3_intr(int irq, void *dummy);
108static inline unsigned char sun3scsi_read(int reg);
109static inline void sun3scsi_write(int reg, int value);
110
111static int setup_can_queue = -1;
112module_param(setup_can_queue, int, 0);
113static int setup_cmd_per_lun = -1;
114module_param(setup_cmd_per_lun, int, 0);
115static int setup_sg_tablesize = -1;
116module_param(setup_sg_tablesize, int, 0);
117#ifdef SUPPORT_TAGS
118static int setup_use_tagged_queuing = -1;
119module_param(setup_use_tagged_queuing, int, 0);
120#endif
121static int setup_hostid = -1;
122module_param(setup_hostid, int, 0);
123
124static struct scsi_cmnd *sun3_dma_setup_done = NULL;
125
126#define AFTER_RESET_DELAY (HZ/2)
127
128/* ms to wait after hitting dma regs */
129#define SUN3_DMA_DELAY 10
130
131/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
132#define SUN3_DVMA_BUFSIZE 0xe000
133
134/* minimum number of bytes to do dma on */
135#define SUN3_DMA_MINSIZE 128
136
137static volatile unsigned char *sun3_scsi_regp;
138static volatile struct sun3_dma_regs *dregs;
139#ifdef OLDDMA
140static unsigned char *dmabuf = NULL; /* dma memory buffer */
141#endif
142static struct sun3_udc_regs *udc_regs = NULL;
143static unsigned char *sun3_dma_orig_addr = NULL;
144static unsigned long sun3_dma_orig_count = 0;
145static int sun3_dma_active = 0;
146static unsigned long last_residual = 0;
147
148/*
149 * NCR 5380 register access functions
150 */
151
152static inline unsigned char sun3scsi_read(int reg)
153{
154 return( sun3_scsi_regp[reg] );
155}
156
157static inline void sun3scsi_write(int reg, int value)
158{
159 sun3_scsi_regp[reg] = value;
160}
161
162/* dma controller register access functions */
163
164static inline unsigned short sun3_udc_read(unsigned char reg)
165{
166 unsigned short ret;
167
168 dregs->udc_addr = UDC_CSR;
169 udelay(SUN3_DMA_DELAY);
170 ret = dregs->udc_data;
171 udelay(SUN3_DMA_DELAY);
172
173 return ret;
174}
175
176static inline void sun3_udc_write(unsigned short val, unsigned char reg)
177{
178 dregs->udc_addr = reg;
179 udelay(SUN3_DMA_DELAY);
180 dregs->udc_data = val;
181 udelay(SUN3_DMA_DELAY);
182}
183
184/*
185 * XXX: status debug
186 */
187static struct Scsi_Host *default_instance;
188
189/*
190 * Function : int sun3scsi_detect(struct scsi_host_template * tpnt)
191 *
192 * Purpose : initializes mac NCR5380 driver based on the
193 * command line / compile time port and irq definitions.
194 *
195 * Inputs : tpnt - template for this SCSI adapter.
196 *
197 * Returns : 1 if a host adapter was found, 0 if not.
198 *
199 */
200
201int __init sun3scsi_detect(struct scsi_host_template * tpnt)
202{
203 unsigned long ioaddr;
204 static int called = 0;
205 struct Scsi_Host *instance;
206
207 /* check that this machine has an onboard 5380 */
208 switch(idprom->id_machtype) {
209 case SM_SUN3|SM_3_50:
210 case SM_SUN3|SM_3_60:
211 break;
212
213 default:
214 return 0;
215 }
216
217 if(called)
218 return 0;
219
220 tpnt->proc_name = "Sun3 5380 SCSI";
221
222 /* setup variables */
223 tpnt->can_queue =
224 (setup_can_queue > 0) ? setup_can_queue : CAN_QUEUE;
225 tpnt->cmd_per_lun =
226 (setup_cmd_per_lun > 0) ? setup_cmd_per_lun : CMD_PER_LUN;
227 tpnt->sg_tablesize =
228 (setup_sg_tablesize >= 0) ? setup_sg_tablesize : SG_TABLESIZE;
229
230 if (setup_hostid >= 0)
231 tpnt->this_id = setup_hostid;
232 else {
233 /* use 7 as default */
234 tpnt->this_id = 7;
235 }
236
237 ioaddr = (unsigned long)ioremap(IOBASE_SUN3_SCSI, PAGE_SIZE);
238 sun3_scsi_regp = (unsigned char *)ioaddr;
239
240 dregs = (struct sun3_dma_regs *)(((unsigned char *)ioaddr) + 8);
241
242 if((udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs)))
243 == NULL) {
244 printk("SUN3 Scsi couldn't allocate DVMA memory!\n");
245 return 0;
246 }
247#ifdef OLDDMA
248 if((dmabuf = dvma_malloc_align(SUN3_DVMA_BUFSIZE, 0x10000)) == NULL) {
249 printk("SUN3 Scsi couldn't allocate DVMA memory!\n");
250 return 0;
251 }
252#endif
253#ifdef SUPPORT_TAGS
254 if (setup_use_tagged_queuing < 0)
255 setup_use_tagged_queuing = USE_TAGGED_QUEUING;
256#endif
257
258 instance = scsi_register (tpnt, sizeof(struct NCR5380_hostdata));
259 if(instance == NULL)
260 return 0;
261
262 default_instance = instance;
263
264 instance->io_port = (unsigned long) ioaddr;
265 instance->irq = IRQ_SUN3_SCSI;
266
267 NCR5380_init(instance, 0);
268
269 instance->n_io_port = 32;
270
271 ((struct NCR5380_hostdata *)instance->hostdata)->ctrl = 0;
272
273 if (request_irq(instance->irq, scsi_sun3_intr,
274 0, "Sun3SCSI-5380", instance)) {
275#ifndef REAL_DMA
276 printk("scsi%d: IRQ%d not free, interrupts disabled\n",
277 instance->host_no, instance->irq);
278 instance->irq = SCSI_IRQ_NONE;
279#else
280 printk("scsi%d: IRQ%d not free, bailing out\n",
281 instance->host_no, instance->irq);
282 return 0;
283#endif
284 }
285
286 printk("scsi%d: Sun3 5380 at port %lX irq", instance->host_no, instance->io_port);
287 if (instance->irq == SCSI_IRQ_NONE)
288 printk ("s disabled");
289 else
290 printk (" %d", instance->irq);
291 printk(" options CAN_QUEUE=%d CMD_PER_LUN=%d release=%d",
292 instance->can_queue, instance->cmd_per_lun,
293 SUN3SCSI_PUBLIC_RELEASE);
294 printk("\nscsi%d:", instance->host_no);
295 NCR5380_print_options(instance);
296 printk("\n");
297
298 dregs->csr = 0;
299 udelay(SUN3_DMA_DELAY);
300 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
301 udelay(SUN3_DMA_DELAY);
302 dregs->fifo_count = 0;
303
304 called = 1;
305
306#ifdef RESET_BOOT
307 sun3_scsi_reset_boot(instance);
308#endif
309
310 return 1;
311}
312
313int sun3scsi_release (struct Scsi_Host *shpnt)
314{
315 if (shpnt->irq != SCSI_IRQ_NONE)
316 free_irq(shpnt->irq, shpnt);
317
318 iounmap((void *)sun3_scsi_regp);
319
320 NCR5380_exit(shpnt);
321 return 0;
322}
323
324#ifdef RESET_BOOT
325/*
326 * Our 'bus reset on boot' function
327 */
328
329static void sun3_scsi_reset_boot(struct Scsi_Host *instance)
330{
331 unsigned long end;
332
333 NCR5380_local_declare();
334 NCR5380_setup(instance);
335
336 /*
337 * Do a SCSI reset to clean up the bus during initialization. No
338 * messing with the queues, interrupts, or locks necessary here.
339 */
340
341 printk( "Sun3 SCSI: resetting the SCSI bus..." );
342
343 /* switch off SCSI IRQ - catch an interrupt without IRQ bit set else */
344// sun3_disable_irq( IRQ_SUN3_SCSI );
345
346 /* get in phase */
347 NCR5380_write( TARGET_COMMAND_REG,
348 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
349
350 /* assert RST */
351 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST );
352
353 /* The min. reset hold time is 25us, so 40us should be enough */
354 udelay( 50 );
355
356 /* reset RST and interrupt */
357 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE );
358 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
359
360 for( end = jiffies + AFTER_RESET_DELAY; time_before(jiffies, end); )
361 barrier();
362
363 /* switch on SCSI IRQ again */
364// sun3_enable_irq( IRQ_SUN3_SCSI );
365
366 printk( " done\n" );
367}
368#endif
369
370const char * sun3scsi_info (struct Scsi_Host *spnt) {
371 return "";
372}
373
374// safe bits for the CSR
375#define CSR_GOOD 0x060f
376
377static irqreturn_t scsi_sun3_intr(int irq, void *dummy)
378{
379 unsigned short csr = dregs->csr;
380 int handled = 0;
381
382 if(csr & ~CSR_GOOD) {
383 if(csr & CSR_DMA_BUSERR) {
384 printk("scsi%d: bus error in dma\n", default_instance->host_no);
385 }
386
387 if(csr & CSR_DMA_CONFLICT) {
388 printk("scsi%d: dma conflict\n", default_instance->host_no);
389 }
390 handled = 1;
391 }
392
393 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
394 NCR5380_intr(irq, dummy);
395 handled = 1;
396 }
397
398 return IRQ_RETVAL(handled);
399}
400
401/*
402 * Debug stuff - to be called on NMI, or sysrq key. Use at your own risk;
403 * reentering NCR5380_print_status seems to have ugly side effects
404 */
405
406/* this doesn't seem to get used at all -- sam */
407#if 0
408void sun3_sun3_debug (void)
409{
410 unsigned long flags;
411 NCR5380_local_declare();
412
413 if (default_instance) {
414 local_irq_save(flags);
415 NCR5380_print_status(default_instance);
416 local_irq_restore(flags);
417 }
418}
419#endif
420
421
422/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
423static unsigned long sun3scsi_dma_setup(void *data, unsigned long count, int write_flag)
424{
425#ifdef OLDDMA
426 if(write_flag)
427 memcpy(dmabuf, data, count);
428 else {
429 sun3_dma_orig_addr = data;
430 sun3_dma_orig_count = count;
431 }
432#else
433 void *addr;
434
435 if(sun3_dma_orig_addr != NULL)
436 dvma_unmap(sun3_dma_orig_addr);
437
438// addr = sun3_dvma_page((unsigned long)data, (unsigned long)dmabuf);
439 addr = (void *)dvma_map((unsigned long) data, count);
440
441 sun3_dma_orig_addr = addr;
442 sun3_dma_orig_count = count;
443#endif
444 dregs->fifo_count = 0;
445 sun3_udc_write(UDC_RESET, UDC_CSR);
446
447 /* reset fifo */
448 dregs->csr &= ~CSR_FIFO;
449 dregs->csr |= CSR_FIFO;
450
451 /* set direction */
452 if(write_flag)
453 dregs->csr |= CSR_SEND;
454 else
455 dregs->csr &= ~CSR_SEND;
456
457 /* byte count for fifo */
458 dregs->fifo_count = count;
459
460 sun3_udc_write(UDC_RESET, UDC_CSR);
461
462 /* reset fifo */
463 dregs->csr &= ~CSR_FIFO;
464 dregs->csr |= CSR_FIFO;
465
466 if(dregs->fifo_count != count) {
467 printk("scsi%d: fifo_mismatch %04x not %04x\n",
468 default_instance->host_no, dregs->fifo_count,
469 (unsigned int) count);
470 NCR5380_print(default_instance);
471 }
472
473 /* setup udc */
474#ifdef OLDDMA
475 udc_regs->addr_hi = ((dvma_vtob(dmabuf) & 0xff0000) >> 8);
476 udc_regs->addr_lo = (dvma_vtob(dmabuf) & 0xffff);
477#else
478 udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
479 udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
480#endif
481 udc_regs->count = count/2; /* count in words */
482 udc_regs->mode_hi = UDC_MODE_HIWORD;
483 if(write_flag) {
484 if(count & 1)
485 udc_regs->count++;
486 udc_regs->mode_lo = UDC_MODE_LSEND;
487 udc_regs->rsel = UDC_RSEL_SEND;
488 } else {
489 udc_regs->mode_lo = UDC_MODE_LRECV;
490 udc_regs->rsel = UDC_RSEL_RECV;
491 }
492
493 /* announce location of regs block */
494 sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
495 UDC_CHN_HI);
496
497 sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
498
499 /* set dma master on */
500 sun3_udc_write(0xd, UDC_MODE);
501
502 /* interrupt enable */
503 sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
504
505 return count;
506
507}
508
509static inline unsigned long sun3scsi_dma_count(struct Scsi_Host *instance)
510{
511 unsigned short resid;
512
513 dregs->udc_addr = 0x32;
514 udelay(SUN3_DMA_DELAY);
515 resid = dregs->udc_data;
516 udelay(SUN3_DMA_DELAY);
517 resid *= 2;
518
519 return (unsigned long) resid;
520}
521
522static inline unsigned long sun3scsi_dma_residual(struct Scsi_Host *instance)
523{
524 return last_residual;
525}
526
527static inline unsigned long sun3scsi_dma_xfer_len(unsigned long wanted,
528 struct scsi_cmnd *cmd,
529 int write_flag)
530{
531 if (cmd->request->cmd_type == REQ_TYPE_FS)
532 return wanted;
533 else
534 return 0;
535}
536
537static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
538{
539
540 sun3_udc_write(UDC_CHN_START, UDC_CSR);
541
542 return 0;
543}
544
545/* clean up after our dma is done */
546static int sun3scsi_dma_finish(int write_flag)
547{
548 unsigned short count;
549 unsigned short fifo;
550 int ret = 0;
551
552 sun3_dma_active = 0;
553#if 1
554 // check to empty the fifo on a read
555 if(!write_flag) {
556 int tmo = 20000; /* .2 sec */
557
558 while(1) {
559 if(dregs->csr & CSR_FIFO_EMPTY)
560 break;
561
562 if(--tmo <= 0) {
563 printk("sun3scsi: fifo failed to empty!\n");
564 return 1;
565 }
566 udelay(10);
567 }
568 }
569
570#endif
571
572 count = sun3scsi_dma_count(default_instance);
573#ifdef OLDDMA
574
575 /* if we've finished a read, copy out the data we read */
576 if(sun3_dma_orig_addr) {
577 /* check for residual bytes after dma end */
578 if(count && (NCR5380_read(BUS_AND_STATUS_REG) &
579 (BASR_PHASE_MATCH | BASR_ACK))) {
580 printk("scsi%d: sun3_scsi_finish: read overrun baby... ", default_instance->host_no);
581 printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG));
582 ret = count;
583 }
584
585 /* copy in what we dma'd no matter what */
586 memcpy(sun3_dma_orig_addr, dmabuf, sun3_dma_orig_count);
587 sun3_dma_orig_addr = NULL;
588
589 }
590#else
591
592 fifo = dregs->fifo_count;
593 last_residual = fifo;
594
595 /* empty bytes from the fifo which didn't make it */
596 if((!write_flag) && (count - fifo) == 2) {
597 unsigned short data;
598 unsigned char *vaddr;
599
600 data = dregs->fifo_data;
601 vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
602
603 vaddr += (sun3_dma_orig_count - fifo);
604
605 vaddr[-2] = (data & 0xff00) >> 8;
606 vaddr[-1] = (data & 0xff);
607 }
608
609 dvma_unmap(sun3_dma_orig_addr);
610 sun3_dma_orig_addr = NULL;
611#endif
612 sun3_udc_write(UDC_RESET, UDC_CSR);
613 dregs->fifo_count = 0;
614 dregs->csr &= ~CSR_SEND;
615
616 /* reset fifo */
617 dregs->csr &= ~CSR_FIFO;
618 dregs->csr |= CSR_FIFO;
619
620 sun3_dma_setup_done = NULL;
621
622 return ret;
623
624}
625
626#include "sun3_NCR5380.c"
627
628static struct scsi_host_template driver_template = {
629 .name = SUN3_SCSI_NAME,
630 .detect = sun3scsi_detect,
631 .release = sun3scsi_release,
632 .info = sun3scsi_info,
633 .queuecommand = sun3scsi_queue_command,
634 .eh_abort_handler = sun3scsi_abort,
635 .eh_bus_reset_handler = sun3scsi_bus_reset,
636 .can_queue = CAN_QUEUE,
637 .this_id = 7,
638 .sg_tablesize = SG_TABLESIZE,
639 .cmd_per_lun = CMD_PER_LUN,
640 .use_clustering = DISABLE_CLUSTERING
641};
642
643
644#include "scsi_module.c"
645
646MODULE_LICENSE("GPL");