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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * QLogic QLA3xxx NIC HBA Driver
4 * Copyright (c) 2003-2006 QLogic Corporation
5 */
6
7#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
9#include <linux/kernel.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/list.h>
13#include <linux/pci.h>
14#include <linux/dma-mapping.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <linux/dmapool.h>
18#include <linux/mempool.h>
19#include <linux/spinlock.h>
20#include <linux/kthread.h>
21#include <linux/interrupt.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/ip.h>
25#include <linux/in.h>
26#include <linux/if_arp.h>
27#include <linux/if_ether.h>
28#include <linux/netdevice.h>
29#include <linux/etherdevice.h>
30#include <linux/ethtool.h>
31#include <linux/skbuff.h>
32#include <linux/rtnetlink.h>
33#include <linux/if_vlan.h>
34#include <linux/delay.h>
35#include <linux/mm.h>
36#include <linux/prefetch.h>
37
38#include "qla3xxx.h"
39
40#define DRV_NAME "qla3xxx"
41#define DRV_STRING "QLogic ISP3XXX Network Driver"
42#define DRV_VERSION "v2.03.00-k5"
43
44static const char ql3xxx_driver_name[] = DRV_NAME;
45static const char ql3xxx_driver_version[] = DRV_VERSION;
46
47#define TIMED_OUT_MSG \
48"Timed out waiting for management port to get free before issuing command\n"
49
50MODULE_AUTHOR("QLogic Corporation");
51MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
52MODULE_LICENSE("GPL");
53MODULE_VERSION(DRV_VERSION);
54
55static const u32 default_msg
56 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
57 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
58
59static int debug = -1; /* defaults above */
60module_param(debug, int, 0);
61MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
62
63static int msi;
64module_param(msi, int, 0);
65MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
66
67static const struct pci_device_id ql3xxx_pci_tbl[] = {
68 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
69 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
70 /* required last entry */
71 {0,}
72};
73
74MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
75
76/*
77 * These are the known PHY's which are used
78 */
79enum PHY_DEVICE_TYPE {
80 PHY_TYPE_UNKNOWN = 0,
81 PHY_VITESSE_VSC8211,
82 PHY_AGERE_ET1011C,
83 MAX_PHY_DEV_TYPES
84};
85
86struct PHY_DEVICE_INFO {
87 const enum PHY_DEVICE_TYPE phyDevice;
88 const u32 phyIdOUI;
89 const u16 phyIdModel;
90 const char *name;
91};
92
93static const struct PHY_DEVICE_INFO PHY_DEVICES[] = {
94 {PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
95 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
96 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
97};
98
99
100/*
101 * Caller must take hw_lock.
102 */
103static int ql_sem_spinlock(struct ql3_adapter *qdev,
104 u32 sem_mask, u32 sem_bits)
105{
106 struct ql3xxx_port_registers __iomem *port_regs =
107 qdev->mem_map_registers;
108 u32 value;
109 unsigned int seconds = 3;
110
111 do {
112 writel((sem_mask | sem_bits),
113 &port_regs->CommonRegs.semaphoreReg);
114 value = readl(&port_regs->CommonRegs.semaphoreReg);
115 if ((value & (sem_mask >> 16)) == sem_bits)
116 return 0;
117 mdelay(1000);
118 } while (--seconds);
119 return -1;
120}
121
122static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
123{
124 struct ql3xxx_port_registers __iomem *port_regs =
125 qdev->mem_map_registers;
126 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
127 readl(&port_regs->CommonRegs.semaphoreReg);
128}
129
130static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
131{
132 struct ql3xxx_port_registers __iomem *port_regs =
133 qdev->mem_map_registers;
134 u32 value;
135
136 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
137 value = readl(&port_regs->CommonRegs.semaphoreReg);
138 return ((value & (sem_mask >> 16)) == sem_bits);
139}
140
141/*
142 * Caller holds hw_lock.
143 */
144static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
145{
146 int i = 0;
147
148 do {
149 if (ql_sem_lock(qdev,
150 QL_DRVR_SEM_MASK,
151 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
152 * 2) << 1)) {
153 netdev_printk(KERN_DEBUG, qdev->ndev,
154 "driver lock acquired\n");
155 return 1;
156 }
157 mdelay(1000);
158 } while (++i < 10);
159
160 netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n");
161 return 0;
162}
163
164static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
165{
166 struct ql3xxx_port_registers __iomem *port_regs =
167 qdev->mem_map_registers;
168
169 writel(((ISP_CONTROL_NP_MASK << 16) | page),
170 &port_regs->CommonRegs.ispControlStatus);
171 readl(&port_regs->CommonRegs.ispControlStatus);
172 qdev->current_page = page;
173}
174
175static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
176{
177 u32 value;
178 unsigned long hw_flags;
179
180 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
181 value = readl(reg);
182 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
183
184 return value;
185}
186
187static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
188{
189 return readl(reg);
190}
191
192static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
193{
194 u32 value;
195 unsigned long hw_flags;
196
197 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
198
199 if (qdev->current_page != 0)
200 ql_set_register_page(qdev, 0);
201 value = readl(reg);
202
203 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
204 return value;
205}
206
207static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
208{
209 if (qdev->current_page != 0)
210 ql_set_register_page(qdev, 0);
211 return readl(reg);
212}
213
214static void ql_write_common_reg_l(struct ql3_adapter *qdev,
215 u32 __iomem *reg, u32 value)
216{
217 unsigned long hw_flags;
218
219 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
220 writel(value, reg);
221 readl(reg);
222 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
223}
224
225static void ql_write_common_reg(struct ql3_adapter *qdev,
226 u32 __iomem *reg, u32 value)
227{
228 writel(value, reg);
229 readl(reg);
230}
231
232static void ql_write_nvram_reg(struct ql3_adapter *qdev,
233 u32 __iomem *reg, u32 value)
234{
235 writel(value, reg);
236 readl(reg);
237 udelay(1);
238}
239
240static void ql_write_page0_reg(struct ql3_adapter *qdev,
241 u32 __iomem *reg, u32 value)
242{
243 if (qdev->current_page != 0)
244 ql_set_register_page(qdev, 0);
245 writel(value, reg);
246 readl(reg);
247}
248
249/*
250 * Caller holds hw_lock. Only called during init.
251 */
252static void ql_write_page1_reg(struct ql3_adapter *qdev,
253 u32 __iomem *reg, u32 value)
254{
255 if (qdev->current_page != 1)
256 ql_set_register_page(qdev, 1);
257 writel(value, reg);
258 readl(reg);
259}
260
261/*
262 * Caller holds hw_lock. Only called during init.
263 */
264static void ql_write_page2_reg(struct ql3_adapter *qdev,
265 u32 __iomem *reg, u32 value)
266{
267 if (qdev->current_page != 2)
268 ql_set_register_page(qdev, 2);
269 writel(value, reg);
270 readl(reg);
271}
272
273static void ql_disable_interrupts(struct ql3_adapter *qdev)
274{
275 struct ql3xxx_port_registers __iomem *port_regs =
276 qdev->mem_map_registers;
277
278 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
279 (ISP_IMR_ENABLE_INT << 16));
280
281}
282
283static void ql_enable_interrupts(struct ql3_adapter *qdev)
284{
285 struct ql3xxx_port_registers __iomem *port_regs =
286 qdev->mem_map_registers;
287
288 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
289 ((0xff << 16) | ISP_IMR_ENABLE_INT));
290
291}
292
293static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
294 struct ql_rcv_buf_cb *lrg_buf_cb)
295{
296 dma_addr_t map;
297 int err;
298 lrg_buf_cb->next = NULL;
299
300 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
301 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
302 } else {
303 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
304 qdev->lrg_buf_free_tail = lrg_buf_cb;
305 }
306
307 if (!lrg_buf_cb->skb) {
308 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
309 qdev->lrg_buffer_len);
310 if (unlikely(!lrg_buf_cb->skb)) {
311 qdev->lrg_buf_skb_check++;
312 } else {
313 /*
314 * We save some space to copy the ethhdr from first
315 * buffer
316 */
317 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
318 map = dma_map_single(&qdev->pdev->dev,
319 lrg_buf_cb->skb->data,
320 qdev->lrg_buffer_len - QL_HEADER_SPACE,
321 DMA_FROM_DEVICE);
322 err = dma_mapping_error(&qdev->pdev->dev, map);
323 if (err) {
324 netdev_err(qdev->ndev,
325 "PCI mapping failed with error: %d\n",
326 err);
327 dev_kfree_skb(lrg_buf_cb->skb);
328 lrg_buf_cb->skb = NULL;
329
330 qdev->lrg_buf_skb_check++;
331 return;
332 }
333
334 lrg_buf_cb->buf_phy_addr_low =
335 cpu_to_le32(LS_64BITS(map));
336 lrg_buf_cb->buf_phy_addr_high =
337 cpu_to_le32(MS_64BITS(map));
338 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
339 dma_unmap_len_set(lrg_buf_cb, maplen,
340 qdev->lrg_buffer_len -
341 QL_HEADER_SPACE);
342 }
343 }
344
345 qdev->lrg_buf_free_count++;
346}
347
348static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
349 *qdev)
350{
351 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
352
353 if (lrg_buf_cb != NULL) {
354 qdev->lrg_buf_free_head = lrg_buf_cb->next;
355 if (qdev->lrg_buf_free_head == NULL)
356 qdev->lrg_buf_free_tail = NULL;
357 qdev->lrg_buf_free_count--;
358 }
359
360 return lrg_buf_cb;
361}
362
363static u32 addrBits = EEPROM_NO_ADDR_BITS;
364static u32 dataBits = EEPROM_NO_DATA_BITS;
365
366static void fm93c56a_deselect(struct ql3_adapter *qdev);
367static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
368 unsigned short *value);
369
370/*
371 * Caller holds hw_lock.
372 */
373static void fm93c56a_select(struct ql3_adapter *qdev)
374{
375 struct ql3xxx_port_registers __iomem *port_regs =
376 qdev->mem_map_registers;
377 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
378
379 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
380 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
381}
382
383/*
384 * Caller holds hw_lock.
385 */
386static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
387{
388 int i;
389 u32 mask;
390 u32 dataBit;
391 u32 previousBit;
392 struct ql3xxx_port_registers __iomem *port_regs =
393 qdev->mem_map_registers;
394 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
395
396 /* Clock in a zero, then do the start bit */
397 ql_write_nvram_reg(qdev, spir,
398 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
399 AUBURN_EEPROM_DO_1));
400 ql_write_nvram_reg(qdev, spir,
401 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
402 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE));
403 ql_write_nvram_reg(qdev, spir,
404 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
405 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL));
406
407 mask = 1 << (FM93C56A_CMD_BITS - 1);
408 /* Force the previous data bit to be different */
409 previousBit = 0xffff;
410 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
411 dataBit = (cmd & mask)
412 ? AUBURN_EEPROM_DO_1
413 : AUBURN_EEPROM_DO_0;
414 if (previousBit != dataBit) {
415 /* If the bit changed, change the DO state to match */
416 ql_write_nvram_reg(qdev, spir,
417 (ISP_NVRAM_MASK |
418 qdev->eeprom_cmd_data | dataBit));
419 previousBit = dataBit;
420 }
421 ql_write_nvram_reg(qdev, spir,
422 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
423 dataBit | AUBURN_EEPROM_CLK_RISE));
424 ql_write_nvram_reg(qdev, spir,
425 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
426 dataBit | AUBURN_EEPROM_CLK_FALL));
427 cmd = cmd << 1;
428 }
429
430 mask = 1 << (addrBits - 1);
431 /* Force the previous data bit to be different */
432 previousBit = 0xffff;
433 for (i = 0; i < addrBits; i++) {
434 dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1
435 : AUBURN_EEPROM_DO_0;
436 if (previousBit != dataBit) {
437 /*
438 * If the bit changed, then change the DO state to
439 * match
440 */
441 ql_write_nvram_reg(qdev, spir,
442 (ISP_NVRAM_MASK |
443 qdev->eeprom_cmd_data | dataBit));
444 previousBit = dataBit;
445 }
446 ql_write_nvram_reg(qdev, spir,
447 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
448 dataBit | AUBURN_EEPROM_CLK_RISE));
449 ql_write_nvram_reg(qdev, spir,
450 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
451 dataBit | AUBURN_EEPROM_CLK_FALL));
452 eepromAddr = eepromAddr << 1;
453 }
454}
455
456/*
457 * Caller holds hw_lock.
458 */
459static void fm93c56a_deselect(struct ql3_adapter *qdev)
460{
461 struct ql3xxx_port_registers __iomem *port_regs =
462 qdev->mem_map_registers;
463 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
464
465 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
466 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
467}
468
469/*
470 * Caller holds hw_lock.
471 */
472static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
473{
474 int i;
475 u32 data = 0;
476 u32 dataBit;
477 struct ql3xxx_port_registers __iomem *port_regs =
478 qdev->mem_map_registers;
479 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
480
481 /* Read the data bits */
482 /* The first bit is a dummy. Clock right over it. */
483 for (i = 0; i < dataBits; i++) {
484 ql_write_nvram_reg(qdev, spir,
485 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
486 AUBURN_EEPROM_CLK_RISE);
487 ql_write_nvram_reg(qdev, spir,
488 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
489 AUBURN_EEPROM_CLK_FALL);
490 dataBit = (ql_read_common_reg(qdev, spir) &
491 AUBURN_EEPROM_DI_1) ? 1 : 0;
492 data = (data << 1) | dataBit;
493 }
494 *value = (u16)data;
495}
496
497/*
498 * Caller holds hw_lock.
499 */
500static void eeprom_readword(struct ql3_adapter *qdev,
501 u32 eepromAddr, unsigned short *value)
502{
503 fm93c56a_select(qdev);
504 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
505 fm93c56a_datain(qdev, value);
506 fm93c56a_deselect(qdev);
507}
508
509static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
510{
511 __le16 buf[ETH_ALEN / 2];
512
513 buf[0] = cpu_to_le16(addr[0]);
514 buf[1] = cpu_to_le16(addr[1]);
515 buf[2] = cpu_to_le16(addr[2]);
516 eth_hw_addr_set(ndev, (u8 *)buf);
517}
518
519static int ql_get_nvram_params(struct ql3_adapter *qdev)
520{
521 u16 *pEEPROMData;
522 u16 checksum = 0;
523 u32 index;
524 unsigned long hw_flags;
525
526 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
527
528 pEEPROMData = (u16 *)&qdev->nvram_data;
529 qdev->eeprom_cmd_data = 0;
530 if (ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
531 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
532 2) << 10)) {
533 pr_err("%s: Failed ql_sem_spinlock()\n", __func__);
534 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
535 return -1;
536 }
537
538 for (index = 0; index < EEPROM_SIZE; index++) {
539 eeprom_readword(qdev, index, pEEPROMData);
540 checksum += *pEEPROMData;
541 pEEPROMData++;
542 }
543 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
544
545 if (checksum != 0) {
546 netdev_err(qdev->ndev, "checksum should be zero, is %x!!\n",
547 checksum);
548 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
549 return -1;
550 }
551
552 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
553 return checksum;
554}
555
556static const u32 PHYAddr[2] = {
557 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
558};
559
560static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
561{
562 struct ql3xxx_port_registers __iomem *port_regs =
563 qdev->mem_map_registers;
564 u32 temp;
565 int count = 1000;
566
567 while (count) {
568 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
569 if (!(temp & MAC_MII_STATUS_BSY))
570 return 0;
571 udelay(10);
572 count--;
573 }
574 return -1;
575}
576
577static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
578{
579 struct ql3xxx_port_registers __iomem *port_regs =
580 qdev->mem_map_registers;
581 u32 scanControl;
582
583 if (qdev->numPorts > 1) {
584 /* Auto scan will cycle through multiple ports */
585 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
586 } else {
587 scanControl = MAC_MII_CONTROL_SC;
588 }
589
590 /*
591 * Scan register 1 of PHY/PETBI,
592 * Set up to scan both devices
593 * The autoscan starts from the first register, completes
594 * the last one before rolling over to the first
595 */
596 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
597 PHYAddr[0] | MII_SCAN_REGISTER);
598
599 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
600 (scanControl) |
601 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
602}
603
604static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
605{
606 u8 ret;
607 struct ql3xxx_port_registers __iomem *port_regs =
608 qdev->mem_map_registers;
609
610 /* See if scan mode is enabled before we turn it off */
611 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
612 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
613 /* Scan is enabled */
614 ret = 1;
615 } else {
616 /* Scan is disabled */
617 ret = 0;
618 }
619
620 /*
621 * When disabling scan mode you must first change the MII register
622 * address
623 */
624 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
625 PHYAddr[0] | MII_SCAN_REGISTER);
626
627 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
628 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
629 MAC_MII_CONTROL_RC) << 16));
630
631 return ret;
632}
633
634static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
635 u16 regAddr, u16 value, u32 phyAddr)
636{
637 struct ql3xxx_port_registers __iomem *port_regs =
638 qdev->mem_map_registers;
639 u8 scanWasEnabled;
640
641 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
642
643 if (ql_wait_for_mii_ready(qdev)) {
644 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
645 return -1;
646 }
647
648 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
649 phyAddr | regAddr);
650
651 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
652
653 /* Wait for write to complete 9/10/04 SJP */
654 if (ql_wait_for_mii_ready(qdev)) {
655 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
656 return -1;
657 }
658
659 if (scanWasEnabled)
660 ql_mii_enable_scan_mode(qdev);
661
662 return 0;
663}
664
665static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
666 u16 *value, u32 phyAddr)
667{
668 struct ql3xxx_port_registers __iomem *port_regs =
669 qdev->mem_map_registers;
670 u8 scanWasEnabled;
671 u32 temp;
672
673 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
674
675 if (ql_wait_for_mii_ready(qdev)) {
676 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
677 return -1;
678 }
679
680 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
681 phyAddr | regAddr);
682
683 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
684 (MAC_MII_CONTROL_RC << 16));
685
686 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
687 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
688
689 /* Wait for the read to complete */
690 if (ql_wait_for_mii_ready(qdev)) {
691 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
692 return -1;
693 }
694
695 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
696 *value = (u16) temp;
697
698 if (scanWasEnabled)
699 ql_mii_enable_scan_mode(qdev);
700
701 return 0;
702}
703
704static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
705{
706 struct ql3xxx_port_registers __iomem *port_regs =
707 qdev->mem_map_registers;
708
709 ql_mii_disable_scan_mode(qdev);
710
711 if (ql_wait_for_mii_ready(qdev)) {
712 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
713 return -1;
714 }
715
716 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
717 qdev->PHYAddr | regAddr);
718
719 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
720
721 /* Wait for write to complete. */
722 if (ql_wait_for_mii_ready(qdev)) {
723 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
724 return -1;
725 }
726
727 ql_mii_enable_scan_mode(qdev);
728
729 return 0;
730}
731
732static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
733{
734 u32 temp;
735 struct ql3xxx_port_registers __iomem *port_regs =
736 qdev->mem_map_registers;
737
738 ql_mii_disable_scan_mode(qdev);
739
740 if (ql_wait_for_mii_ready(qdev)) {
741 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
742 return -1;
743 }
744
745 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
746 qdev->PHYAddr | regAddr);
747
748 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
749 (MAC_MII_CONTROL_RC << 16));
750
751 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
752 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
753
754 /* Wait for the read to complete */
755 if (ql_wait_for_mii_ready(qdev)) {
756 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
757 return -1;
758 }
759
760 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
761 *value = (u16) temp;
762
763 ql_mii_enable_scan_mode(qdev);
764
765 return 0;
766}
767
768static void ql_petbi_reset(struct ql3_adapter *qdev)
769{
770 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
771}
772
773static void ql_petbi_start_neg(struct ql3_adapter *qdev)
774{
775 u16 reg;
776
777 /* Enable Auto-negotiation sense */
778 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, ®);
779 reg |= PETBI_TBI_AUTO_SENSE;
780 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
781
782 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
783 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
784
785 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
786 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
787 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
788
789}
790
791static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
792{
793 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
794 PHYAddr[qdev->mac_index]);
795}
796
797static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
798{
799 u16 reg;
800
801 /* Enable Auto-negotiation sense */
802 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®,
803 PHYAddr[qdev->mac_index]);
804 reg |= PETBI_TBI_AUTO_SENSE;
805 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
806 PHYAddr[qdev->mac_index]);
807
808 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
809 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
810 PHYAddr[qdev->mac_index]);
811
812 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
813 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
814 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
815 PHYAddr[qdev->mac_index]);
816}
817
818static void ql_petbi_init(struct ql3_adapter *qdev)
819{
820 ql_petbi_reset(qdev);
821 ql_petbi_start_neg(qdev);
822}
823
824static void ql_petbi_init_ex(struct ql3_adapter *qdev)
825{
826 ql_petbi_reset_ex(qdev);
827 ql_petbi_start_neg_ex(qdev);
828}
829
830static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
831{
832 u16 reg;
833
834 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, ®) < 0)
835 return 0;
836
837 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
838}
839
840static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
841{
842 netdev_info(qdev->ndev, "enabling Agere specific PHY\n");
843 /* power down device bit 11 = 1 */
844 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
845 /* enable diagnostic mode bit 2 = 1 */
846 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
847 /* 1000MB amplitude adjust (see Agere errata) */
848 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
849 /* 1000MB amplitude adjust (see Agere errata) */
850 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
851 /* 100MB amplitude adjust (see Agere errata) */
852 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
853 /* 100MB amplitude adjust (see Agere errata) */
854 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
855 /* 10MB amplitude adjust (see Agere errata) */
856 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
857 /* 10MB amplitude adjust (see Agere errata) */
858 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
859 /* point to hidden reg 0x2806 */
860 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
861 /* Write new PHYAD w/bit 5 set */
862 ql_mii_write_reg_ex(qdev, 0x11,
863 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
864 /*
865 * Disable diagnostic mode bit 2 = 0
866 * Power up device bit 11 = 0
867 * Link up (on) and activity (blink)
868 */
869 ql_mii_write_reg(qdev, 0x12, 0x840a);
870 ql_mii_write_reg(qdev, 0x00, 0x1140);
871 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
872}
873
874static enum PHY_DEVICE_TYPE getPhyType(struct ql3_adapter *qdev,
875 u16 phyIdReg0, u16 phyIdReg1)
876{
877 enum PHY_DEVICE_TYPE result = PHY_TYPE_UNKNOWN;
878 u32 oui;
879 u16 model;
880 int i;
881
882 if (phyIdReg0 == 0xffff)
883 return result;
884
885 if (phyIdReg1 == 0xffff)
886 return result;
887
888 /* oui is split between two registers */
889 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
890
891 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
892
893 /* Scan table for this PHY */
894 for (i = 0; i < MAX_PHY_DEV_TYPES; i++) {
895 if ((oui == PHY_DEVICES[i].phyIdOUI) &&
896 (model == PHY_DEVICES[i].phyIdModel)) {
897 netdev_info(qdev->ndev, "Phy: %s\n",
898 PHY_DEVICES[i].name);
899 result = PHY_DEVICES[i].phyDevice;
900 break;
901 }
902 }
903
904 return result;
905}
906
907static int ql_phy_get_speed(struct ql3_adapter *qdev)
908{
909 u16 reg;
910
911 switch (qdev->phyType) {
912 case PHY_AGERE_ET1011C: {
913 if (ql_mii_read_reg(qdev, 0x1A, ®) < 0)
914 return 0;
915
916 reg = (reg >> 8) & 3;
917 break;
918 }
919 default:
920 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
921 return 0;
922
923 reg = (((reg & 0x18) >> 3) & 3);
924 }
925
926 switch (reg) {
927 case 2:
928 return SPEED_1000;
929 case 1:
930 return SPEED_100;
931 case 0:
932 return SPEED_10;
933 default:
934 return -1;
935 }
936}
937
938static int ql_is_full_dup(struct ql3_adapter *qdev)
939{
940 u16 reg;
941
942 switch (qdev->phyType) {
943 case PHY_AGERE_ET1011C: {
944 if (ql_mii_read_reg(qdev, 0x1A, ®))
945 return 0;
946
947 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
948 }
949 case PHY_VITESSE_VSC8211:
950 default: {
951 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
952 return 0;
953 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
954 }
955 }
956}
957
958static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
959{
960 u16 reg;
961
962 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, ®) < 0)
963 return 0;
964
965 return (reg & PHY_NEG_PAUSE) != 0;
966}
967
968static int PHY_Setup(struct ql3_adapter *qdev)
969{
970 u16 reg1;
971 u16 reg2;
972 bool agereAddrChangeNeeded = false;
973 u32 miiAddr = 0;
974 int err;
975
976 /* Determine the PHY we are using by reading the ID's */
977 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, ®1);
978 if (err != 0) {
979 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_0_REG\n");
980 return err;
981 }
982
983 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, ®2);
984 if (err != 0) {
985 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG\n");
986 return err;
987 }
988
989 /* Check if we have a Agere PHY */
990 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
991
992 /* Determine which MII address we should be using
993 determined by the index of the card */
994 if (qdev->mac_index == 0)
995 miiAddr = MII_AGERE_ADDR_1;
996 else
997 miiAddr = MII_AGERE_ADDR_2;
998
999 err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, ®1, miiAddr);
1000 if (err != 0) {
1001 netdev_err(qdev->ndev,
1002 "Could not read from reg PHY_ID_0_REG after Agere detected\n");
1003 return err;
1004 }
1005
1006 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, ®2, miiAddr);
1007 if (err != 0) {
1008 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG after Agere detected\n");
1009 return err;
1010 }
1011
1012 /* We need to remember to initialize the Agere PHY */
1013 agereAddrChangeNeeded = true;
1014 }
1015
1016 /* Determine the particular PHY we have on board to apply
1017 PHY specific initializations */
1018 qdev->phyType = getPhyType(qdev, reg1, reg2);
1019
1020 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1021 /* need this here so address gets changed */
1022 phyAgereSpecificInit(qdev, miiAddr);
1023 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1024 netdev_err(qdev->ndev, "PHY is unknown\n");
1025 return -EIO;
1026 }
1027
1028 return 0;
1029}
1030
1031/*
1032 * Caller holds hw_lock.
1033 */
1034static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1035{
1036 struct ql3xxx_port_registers __iomem *port_regs =
1037 qdev->mem_map_registers;
1038 u32 value;
1039
1040 if (enable)
1041 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1042 else
1043 value = (MAC_CONFIG_REG_PE << 16);
1044
1045 if (qdev->mac_index)
1046 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1047 else
1048 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1049}
1050
1051/*
1052 * Caller holds hw_lock.
1053 */
1054static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1055{
1056 struct ql3xxx_port_registers __iomem *port_regs =
1057 qdev->mem_map_registers;
1058 u32 value;
1059
1060 if (enable)
1061 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1062 else
1063 value = (MAC_CONFIG_REG_SR << 16);
1064
1065 if (qdev->mac_index)
1066 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1067 else
1068 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1069}
1070
1071/*
1072 * Caller holds hw_lock.
1073 */
1074static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1075{
1076 struct ql3xxx_port_registers __iomem *port_regs =
1077 qdev->mem_map_registers;
1078 u32 value;
1079
1080 if (enable)
1081 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1082 else
1083 value = (MAC_CONFIG_REG_GM << 16);
1084
1085 if (qdev->mac_index)
1086 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1087 else
1088 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1089}
1090
1091/*
1092 * Caller holds hw_lock.
1093 */
1094static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1095{
1096 struct ql3xxx_port_registers __iomem *port_regs =
1097 qdev->mem_map_registers;
1098 u32 value;
1099
1100 if (enable)
1101 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1102 else
1103 value = (MAC_CONFIG_REG_FD << 16);
1104
1105 if (qdev->mac_index)
1106 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1107 else
1108 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1109}
1110
1111/*
1112 * Caller holds hw_lock.
1113 */
1114static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1115{
1116 struct ql3xxx_port_registers __iomem *port_regs =
1117 qdev->mem_map_registers;
1118 u32 value;
1119
1120 if (enable)
1121 value =
1122 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1123 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1124 else
1125 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1126
1127 if (qdev->mac_index)
1128 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1129 else
1130 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1131}
1132
1133/*
1134 * Caller holds hw_lock.
1135 */
1136static int ql_is_fiber(struct ql3_adapter *qdev)
1137{
1138 struct ql3xxx_port_registers __iomem *port_regs =
1139 qdev->mem_map_registers;
1140 u32 bitToCheck = 0;
1141 u32 temp;
1142
1143 switch (qdev->mac_index) {
1144 case 0:
1145 bitToCheck = PORT_STATUS_SM0;
1146 break;
1147 case 1:
1148 bitToCheck = PORT_STATUS_SM1;
1149 break;
1150 }
1151
1152 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1153 return (temp & bitToCheck) != 0;
1154}
1155
1156static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1157{
1158 u16 reg;
1159 ql_mii_read_reg(qdev, 0x00, ®);
1160 return (reg & 0x1000) != 0;
1161}
1162
1163/*
1164 * Caller holds hw_lock.
1165 */
1166static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1167{
1168 struct ql3xxx_port_registers __iomem *port_regs =
1169 qdev->mem_map_registers;
1170 u32 bitToCheck = 0;
1171 u32 temp;
1172
1173 switch (qdev->mac_index) {
1174 case 0:
1175 bitToCheck = PORT_STATUS_AC0;
1176 break;
1177 case 1:
1178 bitToCheck = PORT_STATUS_AC1;
1179 break;
1180 }
1181
1182 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1183 if (temp & bitToCheck) {
1184 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate complete\n");
1185 return 1;
1186 }
1187 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate incomplete\n");
1188 return 0;
1189}
1190
1191/*
1192 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1193 */
1194static int ql_is_neg_pause(struct ql3_adapter *qdev)
1195{
1196 if (ql_is_fiber(qdev))
1197 return ql_is_petbi_neg_pause(qdev);
1198 else
1199 return ql_is_phy_neg_pause(qdev);
1200}
1201
1202static int ql_auto_neg_error(struct ql3_adapter *qdev)
1203{
1204 struct ql3xxx_port_registers __iomem *port_regs =
1205 qdev->mem_map_registers;
1206 u32 bitToCheck = 0;
1207 u32 temp;
1208
1209 switch (qdev->mac_index) {
1210 case 0:
1211 bitToCheck = PORT_STATUS_AE0;
1212 break;
1213 case 1:
1214 bitToCheck = PORT_STATUS_AE1;
1215 break;
1216 }
1217 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1218 return (temp & bitToCheck) != 0;
1219}
1220
1221static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1222{
1223 if (ql_is_fiber(qdev))
1224 return SPEED_1000;
1225 else
1226 return ql_phy_get_speed(qdev);
1227}
1228
1229static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1230{
1231 if (ql_is_fiber(qdev))
1232 return 1;
1233 else
1234 return ql_is_full_dup(qdev);
1235}
1236
1237/*
1238 * Caller holds hw_lock.
1239 */
1240static int ql_link_down_detect(struct ql3_adapter *qdev)
1241{
1242 struct ql3xxx_port_registers __iomem *port_regs =
1243 qdev->mem_map_registers;
1244 u32 bitToCheck = 0;
1245 u32 temp;
1246
1247 switch (qdev->mac_index) {
1248 case 0:
1249 bitToCheck = ISP_CONTROL_LINK_DN_0;
1250 break;
1251 case 1:
1252 bitToCheck = ISP_CONTROL_LINK_DN_1;
1253 break;
1254 }
1255
1256 temp =
1257 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1258 return (temp & bitToCheck) != 0;
1259}
1260
1261/*
1262 * Caller holds hw_lock.
1263 */
1264static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1265{
1266 struct ql3xxx_port_registers __iomem *port_regs =
1267 qdev->mem_map_registers;
1268
1269 switch (qdev->mac_index) {
1270 case 0:
1271 ql_write_common_reg(qdev,
1272 &port_regs->CommonRegs.ispControlStatus,
1273 (ISP_CONTROL_LINK_DN_0) |
1274 (ISP_CONTROL_LINK_DN_0 << 16));
1275 break;
1276
1277 case 1:
1278 ql_write_common_reg(qdev,
1279 &port_regs->CommonRegs.ispControlStatus,
1280 (ISP_CONTROL_LINK_DN_1) |
1281 (ISP_CONTROL_LINK_DN_1 << 16));
1282 break;
1283
1284 default:
1285 return 1;
1286 }
1287
1288 return 0;
1289}
1290
1291/*
1292 * Caller holds hw_lock.
1293 */
1294static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1295{
1296 struct ql3xxx_port_registers __iomem *port_regs =
1297 qdev->mem_map_registers;
1298 u32 bitToCheck = 0;
1299 u32 temp;
1300
1301 switch (qdev->mac_index) {
1302 case 0:
1303 bitToCheck = PORT_STATUS_F1_ENABLED;
1304 break;
1305 case 1:
1306 bitToCheck = PORT_STATUS_F3_ENABLED;
1307 break;
1308 default:
1309 break;
1310 }
1311
1312 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1313 if (temp & bitToCheck) {
1314 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1315 "not link master\n");
1316 return 0;
1317 }
1318
1319 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, "link master\n");
1320 return 1;
1321}
1322
1323static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1324{
1325 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1326 PHYAddr[qdev->mac_index]);
1327}
1328
1329static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1330{
1331 u16 reg;
1332 u16 portConfiguration;
1333
1334 if (qdev->phyType == PHY_AGERE_ET1011C)
1335 ql_mii_write_reg(qdev, 0x13, 0x0000);
1336 /* turn off external loopback */
1337
1338 if (qdev->mac_index == 0)
1339 portConfiguration =
1340 qdev->nvram_data.macCfg_port0.portConfiguration;
1341 else
1342 portConfiguration =
1343 qdev->nvram_data.macCfg_port1.portConfiguration;
1344
1345 /* Some HBA's in the field are set to 0 and they need to
1346 be reinterpreted with a default value */
1347 if (portConfiguration == 0)
1348 portConfiguration = PORT_CONFIG_DEFAULT;
1349
1350 /* Set the 1000 advertisements */
1351 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, ®,
1352 PHYAddr[qdev->mac_index]);
1353 reg &= ~PHY_GIG_ALL_PARAMS;
1354
1355 if (portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1356 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1357 reg |= PHY_GIG_ADV_1000F;
1358 else
1359 reg |= PHY_GIG_ADV_1000H;
1360 }
1361
1362 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1363 PHYAddr[qdev->mac_index]);
1364
1365 /* Set the 10/100 & pause negotiation advertisements */
1366 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, ®,
1367 PHYAddr[qdev->mac_index]);
1368 reg &= ~PHY_NEG_ALL_PARAMS;
1369
1370 if (portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1371 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1372
1373 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1374 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1375 reg |= PHY_NEG_ADV_100F;
1376
1377 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1378 reg |= PHY_NEG_ADV_10F;
1379 }
1380
1381 if (portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1382 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1383 reg |= PHY_NEG_ADV_100H;
1384
1385 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1386 reg |= PHY_NEG_ADV_10H;
1387 }
1388
1389 if (portConfiguration & PORT_CONFIG_1000MB_SPEED)
1390 reg |= 1;
1391
1392 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1393 PHYAddr[qdev->mac_index]);
1394
1395 ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]);
1396
1397 ql_mii_write_reg_ex(qdev, CONTROL_REG,
1398 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1399 PHYAddr[qdev->mac_index]);
1400}
1401
1402static void ql_phy_init_ex(struct ql3_adapter *qdev)
1403{
1404 ql_phy_reset_ex(qdev);
1405 PHY_Setup(qdev);
1406 ql_phy_start_neg_ex(qdev);
1407}
1408
1409/*
1410 * Caller holds hw_lock.
1411 */
1412static u32 ql_get_link_state(struct ql3_adapter *qdev)
1413{
1414 struct ql3xxx_port_registers __iomem *port_regs =
1415 qdev->mem_map_registers;
1416 u32 bitToCheck = 0;
1417 u32 temp, linkState;
1418
1419 switch (qdev->mac_index) {
1420 case 0:
1421 bitToCheck = PORT_STATUS_UP0;
1422 break;
1423 case 1:
1424 bitToCheck = PORT_STATUS_UP1;
1425 break;
1426 }
1427
1428 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1429 if (temp & bitToCheck)
1430 linkState = LS_UP;
1431 else
1432 linkState = LS_DOWN;
1433
1434 return linkState;
1435}
1436
1437static int ql_port_start(struct ql3_adapter *qdev)
1438{
1439 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1440 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1441 2) << 7)) {
1442 netdev_err(qdev->ndev, "Could not get hw lock for GIO\n");
1443 return -1;
1444 }
1445
1446 if (ql_is_fiber(qdev)) {
1447 ql_petbi_init(qdev);
1448 } else {
1449 /* Copper port */
1450 ql_phy_init_ex(qdev);
1451 }
1452
1453 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1454 return 0;
1455}
1456
1457static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1458{
1459
1460 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1461 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1462 2) << 7))
1463 return -1;
1464
1465 if (!ql_auto_neg_error(qdev)) {
1466 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1467 /* configure the MAC */
1468 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1469 "Configuring link\n");
1470 ql_mac_cfg_soft_reset(qdev, 1);
1471 ql_mac_cfg_gig(qdev,
1472 (ql_get_link_speed
1473 (qdev) ==
1474 SPEED_1000));
1475 ql_mac_cfg_full_dup(qdev,
1476 ql_is_link_full_dup
1477 (qdev));
1478 ql_mac_cfg_pause(qdev,
1479 ql_is_neg_pause
1480 (qdev));
1481 ql_mac_cfg_soft_reset(qdev, 0);
1482
1483 /* enable the MAC */
1484 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1485 "Enabling mac\n");
1486 ql_mac_enable(qdev, 1);
1487 }
1488
1489 qdev->port_link_state = LS_UP;
1490 netif_start_queue(qdev->ndev);
1491 netif_carrier_on(qdev->ndev);
1492 netif_info(qdev, link, qdev->ndev,
1493 "Link is up at %d Mbps, %s duplex\n",
1494 ql_get_link_speed(qdev),
1495 ql_is_link_full_dup(qdev) ? "full" : "half");
1496
1497 } else { /* Remote error detected */
1498
1499 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1500 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1501 "Remote error detected. Calling ql_port_start()\n");
1502 /*
1503 * ql_port_start() is shared code and needs
1504 * to lock the PHY on it's own.
1505 */
1506 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1507 if (ql_port_start(qdev)) /* Restart port */
1508 return -1;
1509 return 0;
1510 }
1511 }
1512 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1513 return 0;
1514}
1515
1516static void ql_link_state_machine_work(struct work_struct *work)
1517{
1518 struct ql3_adapter *qdev =
1519 container_of(work, struct ql3_adapter, link_state_work.work);
1520
1521 u32 curr_link_state;
1522 unsigned long hw_flags;
1523
1524 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1525
1526 curr_link_state = ql_get_link_state(qdev);
1527
1528 if (test_bit(QL_RESET_ACTIVE, &qdev->flags)) {
1529 netif_info(qdev, link, qdev->ndev,
1530 "Reset in progress, skip processing link state\n");
1531
1532 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1533
1534 /* Restart timer on 2 second interval. */
1535 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1536
1537 return;
1538 }
1539
1540 switch (qdev->port_link_state) {
1541 default:
1542 if (test_bit(QL_LINK_MASTER, &qdev->flags))
1543 ql_port_start(qdev);
1544 qdev->port_link_state = LS_DOWN;
1545 fallthrough;
1546
1547 case LS_DOWN:
1548 if (curr_link_state == LS_UP) {
1549 netif_info(qdev, link, qdev->ndev, "Link is up\n");
1550 if (ql_is_auto_neg_complete(qdev))
1551 ql_finish_auto_neg(qdev);
1552
1553 if (qdev->port_link_state == LS_UP)
1554 ql_link_down_detect_clear(qdev);
1555
1556 qdev->port_link_state = LS_UP;
1557 }
1558 break;
1559
1560 case LS_UP:
1561 /*
1562 * See if the link is currently down or went down and came
1563 * back up
1564 */
1565 if (curr_link_state == LS_DOWN) {
1566 netif_info(qdev, link, qdev->ndev, "Link is down\n");
1567 qdev->port_link_state = LS_DOWN;
1568 }
1569 if (ql_link_down_detect(qdev))
1570 qdev->port_link_state = LS_DOWN;
1571 break;
1572 }
1573 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1574
1575 /* Restart timer on 2 second interval. */
1576 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1577}
1578
1579/*
1580 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1581 */
1582static void ql_get_phy_owner(struct ql3_adapter *qdev)
1583{
1584 if (ql_this_adapter_controls_port(qdev))
1585 set_bit(QL_LINK_MASTER, &qdev->flags);
1586 else
1587 clear_bit(QL_LINK_MASTER, &qdev->flags);
1588}
1589
1590/*
1591 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1592 */
1593static void ql_init_scan_mode(struct ql3_adapter *qdev)
1594{
1595 ql_mii_enable_scan_mode(qdev);
1596
1597 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1598 if (ql_this_adapter_controls_port(qdev))
1599 ql_petbi_init_ex(qdev);
1600 } else {
1601 if (ql_this_adapter_controls_port(qdev))
1602 ql_phy_init_ex(qdev);
1603 }
1604}
1605
1606/*
1607 * MII_Setup needs to be called before taking the PHY out of reset
1608 * so that the management interface clock speed can be set properly.
1609 * It would be better if we had a way to disable MDC until after the
1610 * PHY is out of reset, but we don't have that capability.
1611 */
1612static int ql_mii_setup(struct ql3_adapter *qdev)
1613{
1614 u32 reg;
1615 struct ql3xxx_port_registers __iomem *port_regs =
1616 qdev->mem_map_registers;
1617
1618 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1619 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1620 2) << 7))
1621 return -1;
1622
1623 if (qdev->device_id == QL3032_DEVICE_ID)
1624 ql_write_page0_reg(qdev,
1625 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1626
1627 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1628 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1629
1630 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1631 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1632
1633 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1634 return 0;
1635}
1636
1637#define SUPPORTED_OPTICAL_MODES (SUPPORTED_1000baseT_Full | \
1638 SUPPORTED_FIBRE | \
1639 SUPPORTED_Autoneg)
1640#define SUPPORTED_TP_MODES (SUPPORTED_10baseT_Half | \
1641 SUPPORTED_10baseT_Full | \
1642 SUPPORTED_100baseT_Half | \
1643 SUPPORTED_100baseT_Full | \
1644 SUPPORTED_1000baseT_Half | \
1645 SUPPORTED_1000baseT_Full | \
1646 SUPPORTED_Autoneg | \
1647 SUPPORTED_TP) \
1648
1649static u32 ql_supported_modes(struct ql3_adapter *qdev)
1650{
1651 if (test_bit(QL_LINK_OPTICAL, &qdev->flags))
1652 return SUPPORTED_OPTICAL_MODES;
1653
1654 return SUPPORTED_TP_MODES;
1655}
1656
1657static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1658{
1659 int status;
1660 unsigned long hw_flags;
1661 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1662 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1663 (QL_RESOURCE_BITS_BASE_CODE |
1664 (qdev->mac_index) * 2) << 7)) {
1665 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1666 return 0;
1667 }
1668 status = ql_is_auto_cfg(qdev);
1669 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1670 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1671 return status;
1672}
1673
1674static u32 ql_get_speed(struct ql3_adapter *qdev)
1675{
1676 u32 status;
1677 unsigned long hw_flags;
1678 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1679 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1680 (QL_RESOURCE_BITS_BASE_CODE |
1681 (qdev->mac_index) * 2) << 7)) {
1682 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1683 return 0;
1684 }
1685 status = ql_get_link_speed(qdev);
1686 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1687 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1688 return status;
1689}
1690
1691static int ql_get_full_dup(struct ql3_adapter *qdev)
1692{
1693 int status;
1694 unsigned long hw_flags;
1695 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1696 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1697 (QL_RESOURCE_BITS_BASE_CODE |
1698 (qdev->mac_index) * 2) << 7)) {
1699 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1700 return 0;
1701 }
1702 status = ql_is_link_full_dup(qdev);
1703 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1704 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1705 return status;
1706}
1707
1708static int ql_get_link_ksettings(struct net_device *ndev,
1709 struct ethtool_link_ksettings *cmd)
1710{
1711 struct ql3_adapter *qdev = netdev_priv(ndev);
1712 u32 supported, advertising;
1713
1714 supported = ql_supported_modes(qdev);
1715
1716 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1717 cmd->base.port = PORT_FIBRE;
1718 } else {
1719 cmd->base.port = PORT_TP;
1720 cmd->base.phy_address = qdev->PHYAddr;
1721 }
1722 advertising = ql_supported_modes(qdev);
1723 cmd->base.autoneg = ql_get_auto_cfg_status(qdev);
1724 cmd->base.speed = ql_get_speed(qdev);
1725 cmd->base.duplex = ql_get_full_dup(qdev);
1726
1727 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1728 supported);
1729 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1730 advertising);
1731
1732 return 0;
1733}
1734
1735static void ql_get_drvinfo(struct net_device *ndev,
1736 struct ethtool_drvinfo *drvinfo)
1737{
1738 struct ql3_adapter *qdev = netdev_priv(ndev);
1739 strscpy(drvinfo->driver, ql3xxx_driver_name, sizeof(drvinfo->driver));
1740 strscpy(drvinfo->version, ql3xxx_driver_version,
1741 sizeof(drvinfo->version));
1742 strscpy(drvinfo->bus_info, pci_name(qdev->pdev),
1743 sizeof(drvinfo->bus_info));
1744}
1745
1746static u32 ql_get_msglevel(struct net_device *ndev)
1747{
1748 struct ql3_adapter *qdev = netdev_priv(ndev);
1749 return qdev->msg_enable;
1750}
1751
1752static void ql_set_msglevel(struct net_device *ndev, u32 value)
1753{
1754 struct ql3_adapter *qdev = netdev_priv(ndev);
1755 qdev->msg_enable = value;
1756}
1757
1758static void ql_get_pauseparam(struct net_device *ndev,
1759 struct ethtool_pauseparam *pause)
1760{
1761 struct ql3_adapter *qdev = netdev_priv(ndev);
1762 struct ql3xxx_port_registers __iomem *port_regs =
1763 qdev->mem_map_registers;
1764
1765 u32 reg;
1766 if (qdev->mac_index == 0)
1767 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1768 else
1769 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1770
1771 pause->autoneg = ql_get_auto_cfg_status(qdev);
1772 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1773 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1774}
1775
1776static const struct ethtool_ops ql3xxx_ethtool_ops = {
1777 .get_drvinfo = ql_get_drvinfo,
1778 .get_link = ethtool_op_get_link,
1779 .get_msglevel = ql_get_msglevel,
1780 .set_msglevel = ql_set_msglevel,
1781 .get_pauseparam = ql_get_pauseparam,
1782 .get_link_ksettings = ql_get_link_ksettings,
1783};
1784
1785static int ql_populate_free_queue(struct ql3_adapter *qdev)
1786{
1787 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1788 dma_addr_t map;
1789 int err;
1790
1791 while (lrg_buf_cb) {
1792 if (!lrg_buf_cb->skb) {
1793 lrg_buf_cb->skb =
1794 netdev_alloc_skb(qdev->ndev,
1795 qdev->lrg_buffer_len);
1796 if (unlikely(!lrg_buf_cb->skb)) {
1797 netdev_printk(KERN_DEBUG, qdev->ndev,
1798 "Failed netdev_alloc_skb()\n");
1799 break;
1800 } else {
1801 /*
1802 * We save some space to copy the ethhdr from
1803 * first buffer
1804 */
1805 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1806 map = dma_map_single(&qdev->pdev->dev,
1807 lrg_buf_cb->skb->data,
1808 qdev->lrg_buffer_len - QL_HEADER_SPACE,
1809 DMA_FROM_DEVICE);
1810
1811 err = dma_mapping_error(&qdev->pdev->dev, map);
1812 if (err) {
1813 netdev_err(qdev->ndev,
1814 "PCI mapping failed with error: %d\n",
1815 err);
1816 dev_kfree_skb(lrg_buf_cb->skb);
1817 lrg_buf_cb->skb = NULL;
1818 break;
1819 }
1820
1821
1822 lrg_buf_cb->buf_phy_addr_low =
1823 cpu_to_le32(LS_64BITS(map));
1824 lrg_buf_cb->buf_phy_addr_high =
1825 cpu_to_le32(MS_64BITS(map));
1826 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1827 dma_unmap_len_set(lrg_buf_cb, maplen,
1828 qdev->lrg_buffer_len -
1829 QL_HEADER_SPACE);
1830 --qdev->lrg_buf_skb_check;
1831 if (!qdev->lrg_buf_skb_check)
1832 return 1;
1833 }
1834 }
1835 lrg_buf_cb = lrg_buf_cb->next;
1836 }
1837 return 0;
1838}
1839
1840/*
1841 * Caller holds hw_lock.
1842 */
1843static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1844{
1845 struct ql3xxx_port_registers __iomem *port_regs =
1846 qdev->mem_map_registers;
1847
1848 if (qdev->small_buf_release_cnt >= 16) {
1849 while (qdev->small_buf_release_cnt >= 16) {
1850 qdev->small_buf_q_producer_index++;
1851
1852 if (qdev->small_buf_q_producer_index ==
1853 NUM_SBUFQ_ENTRIES)
1854 qdev->small_buf_q_producer_index = 0;
1855 qdev->small_buf_release_cnt -= 8;
1856 }
1857 wmb();
1858 writel_relaxed(qdev->small_buf_q_producer_index,
1859 &port_regs->CommonRegs.rxSmallQProducerIndex);
1860 }
1861}
1862
1863/*
1864 * Caller holds hw_lock.
1865 */
1866static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1867{
1868 struct bufq_addr_element *lrg_buf_q_ele;
1869 int i;
1870 struct ql_rcv_buf_cb *lrg_buf_cb;
1871 struct ql3xxx_port_registers __iomem *port_regs =
1872 qdev->mem_map_registers;
1873
1874 if ((qdev->lrg_buf_free_count >= 8) &&
1875 (qdev->lrg_buf_release_cnt >= 16)) {
1876
1877 if (qdev->lrg_buf_skb_check)
1878 if (!ql_populate_free_queue(qdev))
1879 return;
1880
1881 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1882
1883 while ((qdev->lrg_buf_release_cnt >= 16) &&
1884 (qdev->lrg_buf_free_count >= 8)) {
1885
1886 for (i = 0; i < 8; i++) {
1887 lrg_buf_cb =
1888 ql_get_from_lrg_buf_free_list(qdev);
1889 lrg_buf_q_ele->addr_high =
1890 lrg_buf_cb->buf_phy_addr_high;
1891 lrg_buf_q_ele->addr_low =
1892 lrg_buf_cb->buf_phy_addr_low;
1893 lrg_buf_q_ele++;
1894
1895 qdev->lrg_buf_release_cnt--;
1896 }
1897
1898 qdev->lrg_buf_q_producer_index++;
1899
1900 if (qdev->lrg_buf_q_producer_index ==
1901 qdev->num_lbufq_entries)
1902 qdev->lrg_buf_q_producer_index = 0;
1903
1904 if (qdev->lrg_buf_q_producer_index ==
1905 (qdev->num_lbufq_entries - 1)) {
1906 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1907 }
1908 }
1909 wmb();
1910 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1911 writel(qdev->lrg_buf_q_producer_index,
1912 &port_regs->CommonRegs.rxLargeQProducerIndex);
1913 }
1914}
1915
1916static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1917 struct ob_mac_iocb_rsp *mac_rsp)
1918{
1919 struct ql_tx_buf_cb *tx_cb;
1920 int i;
1921
1922 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1923 netdev_warn(qdev->ndev,
1924 "Frame too short but it was padded and sent\n");
1925 }
1926
1927 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1928
1929 /* Check the transmit response flags for any errors */
1930 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1931 netdev_err(qdev->ndev,
1932 "Frame too short to be legal, frame not sent\n");
1933
1934 qdev->ndev->stats.tx_errors++;
1935 goto frame_not_sent;
1936 }
1937
1938 if (tx_cb->seg_count == 0) {
1939 netdev_err(qdev->ndev, "tx_cb->seg_count == 0: %d\n",
1940 mac_rsp->transaction_id);
1941
1942 qdev->ndev->stats.tx_errors++;
1943 goto invalid_seg_count;
1944 }
1945
1946 dma_unmap_single(&qdev->pdev->dev,
1947 dma_unmap_addr(&tx_cb->map[0], mapaddr),
1948 dma_unmap_len(&tx_cb->map[0], maplen), DMA_TO_DEVICE);
1949 tx_cb->seg_count--;
1950 if (tx_cb->seg_count) {
1951 for (i = 1; i < tx_cb->seg_count; i++) {
1952 dma_unmap_page(&qdev->pdev->dev,
1953 dma_unmap_addr(&tx_cb->map[i], mapaddr),
1954 dma_unmap_len(&tx_cb->map[i], maplen),
1955 DMA_TO_DEVICE);
1956 }
1957 }
1958 qdev->ndev->stats.tx_packets++;
1959 qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
1960
1961frame_not_sent:
1962 dev_kfree_skb_irq(tx_cb->skb);
1963 tx_cb->skb = NULL;
1964
1965invalid_seg_count:
1966 atomic_inc(&qdev->tx_count);
1967}
1968
1969static void ql_get_sbuf(struct ql3_adapter *qdev)
1970{
1971 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1972 qdev->small_buf_index = 0;
1973 qdev->small_buf_release_cnt++;
1974}
1975
1976static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1977{
1978 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1979 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1980 qdev->lrg_buf_release_cnt++;
1981 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1982 qdev->lrg_buf_index = 0;
1983 return lrg_buf_cb;
1984}
1985
1986/*
1987 * The difference between 3022 and 3032 for inbound completions:
1988 * 3022 uses two buffers per completion. The first buffer contains
1989 * (some) header info, the second the remainder of the headers plus
1990 * the data. For this chip we reserve some space at the top of the
1991 * receive buffer so that the header info in buffer one can be
1992 * prepended to the buffer two. Buffer two is the sent up while
1993 * buffer one is returned to the hardware to be reused.
1994 * 3032 receives all of it's data and headers in one buffer for a
1995 * simpler process. 3032 also supports checksum verification as
1996 * can be seen in ql_process_macip_rx_intr().
1997 */
1998static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1999 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2000{
2001 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2002 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2003 struct sk_buff *skb;
2004 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2005
2006 /*
2007 * Get the inbound address list (small buffer).
2008 */
2009 ql_get_sbuf(qdev);
2010
2011 if (qdev->device_id == QL3022_DEVICE_ID)
2012 lrg_buf_cb1 = ql_get_lbuf(qdev);
2013
2014 /* start of second buffer */
2015 lrg_buf_cb2 = ql_get_lbuf(qdev);
2016 skb = lrg_buf_cb2->skb;
2017
2018 qdev->ndev->stats.rx_packets++;
2019 qdev->ndev->stats.rx_bytes += length;
2020
2021 skb_put(skb, length);
2022 dma_unmap_single(&qdev->pdev->dev,
2023 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2024 dma_unmap_len(lrg_buf_cb2, maplen), DMA_FROM_DEVICE);
2025 prefetch(skb->data);
2026 skb_checksum_none_assert(skb);
2027 skb->protocol = eth_type_trans(skb, qdev->ndev);
2028
2029 napi_gro_receive(&qdev->napi, skb);
2030 lrg_buf_cb2->skb = NULL;
2031
2032 if (qdev->device_id == QL3022_DEVICE_ID)
2033 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2034 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2035}
2036
2037static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2038 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2039{
2040 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2041 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2042 struct sk_buff *skb1 = NULL, *skb2;
2043 struct net_device *ndev = qdev->ndev;
2044 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2045 u16 size = 0;
2046
2047 /*
2048 * Get the inbound address list (small buffer).
2049 */
2050
2051 ql_get_sbuf(qdev);
2052
2053 if (qdev->device_id == QL3022_DEVICE_ID) {
2054 /* start of first buffer on 3022 */
2055 lrg_buf_cb1 = ql_get_lbuf(qdev);
2056 skb1 = lrg_buf_cb1->skb;
2057 size = ETH_HLEN;
2058 if (*((u16 *) skb1->data) != 0xFFFF)
2059 size += VLAN_ETH_HLEN - ETH_HLEN;
2060 }
2061
2062 /* start of second buffer */
2063 lrg_buf_cb2 = ql_get_lbuf(qdev);
2064 skb2 = lrg_buf_cb2->skb;
2065
2066 skb_put(skb2, length); /* Just the second buffer length here. */
2067 dma_unmap_single(&qdev->pdev->dev,
2068 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2069 dma_unmap_len(lrg_buf_cb2, maplen), DMA_FROM_DEVICE);
2070 prefetch(skb2->data);
2071
2072 skb_checksum_none_assert(skb2);
2073 if (qdev->device_id == QL3022_DEVICE_ID) {
2074 /*
2075 * Copy the ethhdr from first buffer to second. This
2076 * is necessary for 3022 IP completions.
2077 */
2078 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2079 skb_push(skb2, size), size);
2080 } else {
2081 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2082 if (checksum &
2083 (IB_IP_IOCB_RSP_3032_ICE |
2084 IB_IP_IOCB_RSP_3032_CE)) {
2085 netdev_err(ndev,
2086 "%s: Bad checksum for this %s packet, checksum = %x\n",
2087 __func__,
2088 ((checksum & IB_IP_IOCB_RSP_3032_TCP) ?
2089 "TCP" : "UDP"), checksum);
2090 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2091 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2092 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2093 skb2->ip_summed = CHECKSUM_UNNECESSARY;
2094 }
2095 }
2096 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2097
2098 napi_gro_receive(&qdev->napi, skb2);
2099 ndev->stats.rx_packets++;
2100 ndev->stats.rx_bytes += length;
2101 lrg_buf_cb2->skb = NULL;
2102
2103 if (qdev->device_id == QL3022_DEVICE_ID)
2104 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2105 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2106}
2107
2108static int ql_tx_rx_clean(struct ql3_adapter *qdev, int budget)
2109{
2110 struct net_rsp_iocb *net_rsp;
2111 struct net_device *ndev = qdev->ndev;
2112 int work_done = 0;
2113
2114 /* While there are entries in the completion queue. */
2115 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2116 qdev->rsp_consumer_index) && (work_done < budget)) {
2117
2118 net_rsp = qdev->rsp_current;
2119 rmb();
2120 /*
2121 * Fix 4032 chip's undocumented "feature" where bit-8 is set
2122 * if the inbound completion is for a VLAN.
2123 */
2124 if (qdev->device_id == QL3032_DEVICE_ID)
2125 net_rsp->opcode &= 0x7f;
2126 switch (net_rsp->opcode) {
2127
2128 case OPCODE_OB_MAC_IOCB_FN0:
2129 case OPCODE_OB_MAC_IOCB_FN2:
2130 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2131 net_rsp);
2132 break;
2133
2134 case OPCODE_IB_MAC_IOCB:
2135 case OPCODE_IB_3032_MAC_IOCB:
2136 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2137 net_rsp);
2138 work_done++;
2139 break;
2140
2141 case OPCODE_IB_IP_IOCB:
2142 case OPCODE_IB_3032_IP_IOCB:
2143 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2144 net_rsp);
2145 work_done++;
2146 break;
2147 default: {
2148 u32 *tmp = (u32 *)net_rsp;
2149 netdev_err(ndev,
2150 "Hit default case, not handled!\n"
2151 " dropping the packet, opcode = %x\n"
2152 "0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
2153 net_rsp->opcode,
2154 (unsigned long int)tmp[0],
2155 (unsigned long int)tmp[1],
2156 (unsigned long int)tmp[2],
2157 (unsigned long int)tmp[3]);
2158 }
2159 }
2160
2161 qdev->rsp_consumer_index++;
2162
2163 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2164 qdev->rsp_consumer_index = 0;
2165 qdev->rsp_current = qdev->rsp_q_virt_addr;
2166 } else {
2167 qdev->rsp_current++;
2168 }
2169
2170 }
2171
2172 return work_done;
2173}
2174
2175static int ql_poll(struct napi_struct *napi, int budget)
2176{
2177 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2178 struct ql3xxx_port_registers __iomem *port_regs =
2179 qdev->mem_map_registers;
2180 int work_done;
2181
2182 work_done = ql_tx_rx_clean(qdev, budget);
2183
2184 if (work_done < budget && napi_complete_done(napi, work_done)) {
2185 unsigned long flags;
2186
2187 spin_lock_irqsave(&qdev->hw_lock, flags);
2188 ql_update_small_bufq_prod_index(qdev);
2189 ql_update_lrg_bufq_prod_index(qdev);
2190 writel(qdev->rsp_consumer_index,
2191 &port_regs->CommonRegs.rspQConsumerIndex);
2192 spin_unlock_irqrestore(&qdev->hw_lock, flags);
2193
2194 ql_enable_interrupts(qdev);
2195 }
2196 return work_done;
2197}
2198
2199static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2200{
2201
2202 struct net_device *ndev = dev_id;
2203 struct ql3_adapter *qdev = netdev_priv(ndev);
2204 struct ql3xxx_port_registers __iomem *port_regs =
2205 qdev->mem_map_registers;
2206 u32 value;
2207 int handled = 1;
2208 u32 var;
2209
2210 value = ql_read_common_reg_l(qdev,
2211 &port_regs->CommonRegs.ispControlStatus);
2212
2213 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2214 spin_lock(&qdev->adapter_lock);
2215 netif_stop_queue(qdev->ndev);
2216 netif_carrier_off(qdev->ndev);
2217 ql_disable_interrupts(qdev);
2218 qdev->port_link_state = LS_DOWN;
2219 set_bit(QL_RESET_ACTIVE, &qdev->flags) ;
2220
2221 if (value & ISP_CONTROL_FE) {
2222 /*
2223 * Chip Fatal Error.
2224 */
2225 var =
2226 ql_read_page0_reg_l(qdev,
2227 &port_regs->PortFatalErrStatus);
2228 netdev_warn(ndev,
2229 "Resetting chip. PortFatalErrStatus register = 0x%x\n",
2230 var);
2231 set_bit(QL_RESET_START, &qdev->flags) ;
2232 } else {
2233 /*
2234 * Soft Reset Requested.
2235 */
2236 set_bit(QL_RESET_PER_SCSI, &qdev->flags) ;
2237 netdev_err(ndev,
2238 "Another function issued a reset to the chip. ISR value = %x\n",
2239 value);
2240 }
2241 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2242 spin_unlock(&qdev->adapter_lock);
2243 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2244 ql_disable_interrupts(qdev);
2245 if (likely(napi_schedule_prep(&qdev->napi)))
2246 __napi_schedule(&qdev->napi);
2247 } else
2248 return IRQ_NONE;
2249
2250 return IRQ_RETVAL(handled);
2251}
2252
2253/*
2254 * Get the total number of segments needed for the given number of fragments.
2255 * This is necessary because outbound address lists (OAL) will be used when
2256 * more than two frags are given. Each address list has 5 addr/len pairs.
2257 * The 5th pair in each OAL is used to point to the next OAL if more frags
2258 * are coming. That is why the frags:segment count ratio is not linear.
2259 */
2260static int ql_get_seg_count(struct ql3_adapter *qdev, unsigned short frags)
2261{
2262 if (qdev->device_id == QL3022_DEVICE_ID)
2263 return 1;
2264
2265 if (frags <= 2)
2266 return frags + 1;
2267 else if (frags <= 6)
2268 return frags + 2;
2269 else if (frags <= 10)
2270 return frags + 3;
2271 else if (frags <= 14)
2272 return frags + 4;
2273 else if (frags <= 18)
2274 return frags + 5;
2275 return -1;
2276}
2277
2278static void ql_hw_csum_setup(const struct sk_buff *skb,
2279 struct ob_mac_iocb_req *mac_iocb_ptr)
2280{
2281 const struct iphdr *ip = ip_hdr(skb);
2282
2283 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2284 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2285
2286 if (ip->protocol == IPPROTO_TCP) {
2287 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2288 OB_3032MAC_IOCB_REQ_IC;
2289 } else {
2290 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2291 OB_3032MAC_IOCB_REQ_IC;
2292 }
2293
2294}
2295
2296/*
2297 * Map the buffers for this transmit.
2298 * This will return NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2299 */
2300static int ql_send_map(struct ql3_adapter *qdev,
2301 struct ob_mac_iocb_req *mac_iocb_ptr,
2302 struct ql_tx_buf_cb *tx_cb,
2303 struct sk_buff *skb)
2304{
2305 struct oal *oal;
2306 struct oal_entry *oal_entry;
2307 int len = skb_headlen(skb);
2308 dma_addr_t map;
2309 int err;
2310 int completed_segs, i;
2311 int seg_cnt, seg = 0;
2312 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2313
2314 seg_cnt = tx_cb->seg_count;
2315 /*
2316 * Map the skb buffer first.
2317 */
2318 map = dma_map_single(&qdev->pdev->dev, skb->data, len, DMA_TO_DEVICE);
2319
2320 err = dma_mapping_error(&qdev->pdev->dev, map);
2321 if (err) {
2322 netdev_err(qdev->ndev, "PCI mapping failed with error: %d\n",
2323 err);
2324
2325 return NETDEV_TX_BUSY;
2326 }
2327
2328 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2329 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2330 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2331 oal_entry->len = cpu_to_le32(len);
2332 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2333 dma_unmap_len_set(&tx_cb->map[seg], maplen, len);
2334 seg++;
2335
2336 if (seg_cnt == 1) {
2337 /* Terminate the last segment. */
2338 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2339 return NETDEV_TX_OK;
2340 }
2341 oal = tx_cb->oal;
2342 for (completed_segs = 0;
2343 completed_segs < frag_cnt;
2344 completed_segs++, seg++) {
2345 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2346 oal_entry++;
2347 /*
2348 * Check for continuation requirements.
2349 * It's strange but necessary.
2350 * Continuation entry points to outbound address list.
2351 */
2352 if ((seg == 2 && seg_cnt > 3) ||
2353 (seg == 7 && seg_cnt > 8) ||
2354 (seg == 12 && seg_cnt > 13) ||
2355 (seg == 17 && seg_cnt > 18)) {
2356 map = dma_map_single(&qdev->pdev->dev, oal,
2357 sizeof(struct oal),
2358 DMA_TO_DEVICE);
2359
2360 err = dma_mapping_error(&qdev->pdev->dev, map);
2361 if (err) {
2362 netdev_err(qdev->ndev,
2363 "PCI mapping outbound address list with error: %d\n",
2364 err);
2365 goto map_error;
2366 }
2367
2368 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2369 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2370 oal_entry->len = cpu_to_le32(sizeof(struct oal) |
2371 OAL_CONT_ENTRY);
2372 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2373 dma_unmap_len_set(&tx_cb->map[seg], maplen,
2374 sizeof(struct oal));
2375 oal_entry = (struct oal_entry *)oal;
2376 oal++;
2377 seg++;
2378 }
2379
2380 map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
2381 DMA_TO_DEVICE);
2382
2383 err = dma_mapping_error(&qdev->pdev->dev, map);
2384 if (err) {
2385 netdev_err(qdev->ndev,
2386 "PCI mapping frags failed with error: %d\n",
2387 err);
2388 goto map_error;
2389 }
2390
2391 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2392 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2393 oal_entry->len = cpu_to_le32(skb_frag_size(frag));
2394 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2395 dma_unmap_len_set(&tx_cb->map[seg], maplen, skb_frag_size(frag));
2396 }
2397 /* Terminate the last segment. */
2398 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2399 return NETDEV_TX_OK;
2400
2401map_error:
2402 /* A PCI mapping failed and now we will need to back out
2403 * We need to traverse through the oal's and associated pages which
2404 * have been mapped and now we must unmap them to clean up properly
2405 */
2406
2407 seg = 1;
2408 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2409 oal = tx_cb->oal;
2410 for (i = 0; i < completed_segs; i++, seg++) {
2411 oal_entry++;
2412
2413 /*
2414 * Check for continuation requirements.
2415 * It's strange but necessary.
2416 */
2417
2418 if ((seg == 2 && seg_cnt > 3) ||
2419 (seg == 7 && seg_cnt > 8) ||
2420 (seg == 12 && seg_cnt > 13) ||
2421 (seg == 17 && seg_cnt > 18)) {
2422 dma_unmap_single(&qdev->pdev->dev,
2423 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2424 dma_unmap_len(&tx_cb->map[seg], maplen),
2425 DMA_TO_DEVICE);
2426 oal++;
2427 seg++;
2428 }
2429
2430 dma_unmap_page(&qdev->pdev->dev,
2431 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2432 dma_unmap_len(&tx_cb->map[seg], maplen),
2433 DMA_TO_DEVICE);
2434 }
2435
2436 dma_unmap_single(&qdev->pdev->dev,
2437 dma_unmap_addr(&tx_cb->map[0], mapaddr),
2438 dma_unmap_addr(&tx_cb->map[0], maplen),
2439 DMA_TO_DEVICE);
2440
2441 return NETDEV_TX_BUSY;
2442
2443}
2444
2445/*
2446 * The difference between 3022 and 3032 sends:
2447 * 3022 only supports a simple single segment transmission.
2448 * 3032 supports checksumming and scatter/gather lists (fragments).
2449 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2450 * in the IOCB plus a chain of outbound address lists (OAL) that
2451 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2452 * will be used to point to an OAL when more ALP entries are required.
2453 * The IOCB is always the top of the chain followed by one or more
2454 * OALs (when necessary).
2455 */
2456static netdev_tx_t ql3xxx_send(struct sk_buff *skb,
2457 struct net_device *ndev)
2458{
2459 struct ql3_adapter *qdev = netdev_priv(ndev);
2460 struct ql3xxx_port_registers __iomem *port_regs =
2461 qdev->mem_map_registers;
2462 struct ql_tx_buf_cb *tx_cb;
2463 u32 tot_len = skb->len;
2464 struct ob_mac_iocb_req *mac_iocb_ptr;
2465
2466 if (unlikely(atomic_read(&qdev->tx_count) < 2))
2467 return NETDEV_TX_BUSY;
2468
2469 tx_cb = &qdev->tx_buf[qdev->req_producer_index];
2470 tx_cb->seg_count = ql_get_seg_count(qdev,
2471 skb_shinfo(skb)->nr_frags);
2472 if (tx_cb->seg_count == -1) {
2473 netdev_err(ndev, "%s: invalid segment count!\n", __func__);
2474 dev_kfree_skb_any(skb);
2475 return NETDEV_TX_OK;
2476 }
2477
2478 mac_iocb_ptr = tx_cb->queue_entry;
2479 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2480 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2481 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2482 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2483 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2484 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2485 tx_cb->skb = skb;
2486 if (qdev->device_id == QL3032_DEVICE_ID &&
2487 skb->ip_summed == CHECKSUM_PARTIAL)
2488 ql_hw_csum_setup(skb, mac_iocb_ptr);
2489
2490 if (ql_send_map(qdev, mac_iocb_ptr, tx_cb, skb) != NETDEV_TX_OK) {
2491 netdev_err(ndev, "%s: Could not map the segments!\n", __func__);
2492 return NETDEV_TX_BUSY;
2493 }
2494
2495 wmb();
2496 qdev->req_producer_index++;
2497 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2498 qdev->req_producer_index = 0;
2499 wmb();
2500 ql_write_common_reg_l(qdev,
2501 &port_regs->CommonRegs.reqQProducerIndex,
2502 qdev->req_producer_index);
2503
2504 netif_printk(qdev, tx_queued, KERN_DEBUG, ndev,
2505 "tx queued, slot %d, len %d\n",
2506 qdev->req_producer_index, skb->len);
2507
2508 atomic_dec(&qdev->tx_count);
2509 return NETDEV_TX_OK;
2510}
2511
2512static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2513{
2514 qdev->req_q_size =
2515 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2516
2517 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2518
2519 /* The barrier is required to ensure request and response queue
2520 * addr writes to the registers.
2521 */
2522 wmb();
2523
2524 qdev->req_q_virt_addr =
2525 dma_alloc_coherent(&qdev->pdev->dev, (size_t)qdev->req_q_size,
2526 &qdev->req_q_phy_addr, GFP_KERNEL);
2527
2528 if ((qdev->req_q_virt_addr == NULL) ||
2529 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2530 netdev_err(qdev->ndev, "reqQ failed\n");
2531 return -ENOMEM;
2532 }
2533
2534 qdev->rsp_q_virt_addr =
2535 dma_alloc_coherent(&qdev->pdev->dev, (size_t)qdev->rsp_q_size,
2536 &qdev->rsp_q_phy_addr, GFP_KERNEL);
2537
2538 if ((qdev->rsp_q_virt_addr == NULL) ||
2539 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2540 netdev_err(qdev->ndev, "rspQ allocation failed\n");
2541 dma_free_coherent(&qdev->pdev->dev, (size_t)qdev->req_q_size,
2542 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2543 return -ENOMEM;
2544 }
2545
2546 set_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2547
2548 return 0;
2549}
2550
2551static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2552{
2553 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags)) {
2554 netdev_info(qdev->ndev, "Already done\n");
2555 return;
2556 }
2557
2558 dma_free_coherent(&qdev->pdev->dev, qdev->req_q_size,
2559 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2560
2561 qdev->req_q_virt_addr = NULL;
2562
2563 dma_free_coherent(&qdev->pdev->dev, qdev->rsp_q_size,
2564 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2565
2566 qdev->rsp_q_virt_addr = NULL;
2567
2568 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2569}
2570
2571static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2572{
2573 /* Create Large Buffer Queue */
2574 qdev->lrg_buf_q_size =
2575 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2576 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2577 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2578 else
2579 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2580
2581 qdev->lrg_buf = kmalloc_array(qdev->num_large_buffers,
2582 sizeof(struct ql_rcv_buf_cb),
2583 GFP_KERNEL);
2584 if (qdev->lrg_buf == NULL)
2585 return -ENOMEM;
2586
2587 qdev->lrg_buf_q_alloc_virt_addr =
2588 dma_alloc_coherent(&qdev->pdev->dev,
2589 qdev->lrg_buf_q_alloc_size,
2590 &qdev->lrg_buf_q_alloc_phy_addr, GFP_KERNEL);
2591
2592 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2593 netdev_err(qdev->ndev, "lBufQ failed\n");
2594 kfree(qdev->lrg_buf);
2595 return -ENOMEM;
2596 }
2597 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2598 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2599
2600 /* Create Small Buffer Queue */
2601 qdev->small_buf_q_size =
2602 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2603 if (qdev->small_buf_q_size < PAGE_SIZE)
2604 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2605 else
2606 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2607
2608 qdev->small_buf_q_alloc_virt_addr =
2609 dma_alloc_coherent(&qdev->pdev->dev,
2610 qdev->small_buf_q_alloc_size,
2611 &qdev->small_buf_q_alloc_phy_addr, GFP_KERNEL);
2612
2613 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2614 netdev_err(qdev->ndev, "Small Buffer Queue allocation failed\n");
2615 dma_free_coherent(&qdev->pdev->dev,
2616 qdev->lrg_buf_q_alloc_size,
2617 qdev->lrg_buf_q_alloc_virt_addr,
2618 qdev->lrg_buf_q_alloc_phy_addr);
2619 kfree(qdev->lrg_buf);
2620 return -ENOMEM;
2621 }
2622
2623 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2624 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2625 set_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2626 return 0;
2627}
2628
2629static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2630{
2631 if (!test_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags)) {
2632 netdev_info(qdev->ndev, "Already done\n");
2633 return;
2634 }
2635 kfree(qdev->lrg_buf);
2636 dma_free_coherent(&qdev->pdev->dev, qdev->lrg_buf_q_alloc_size,
2637 qdev->lrg_buf_q_alloc_virt_addr,
2638 qdev->lrg_buf_q_alloc_phy_addr);
2639
2640 qdev->lrg_buf_q_virt_addr = NULL;
2641
2642 dma_free_coherent(&qdev->pdev->dev, qdev->small_buf_q_alloc_size,
2643 qdev->small_buf_q_alloc_virt_addr,
2644 qdev->small_buf_q_alloc_phy_addr);
2645
2646 qdev->small_buf_q_virt_addr = NULL;
2647
2648 clear_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2649}
2650
2651static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2652{
2653 int i;
2654 struct bufq_addr_element *small_buf_q_entry;
2655
2656 /* Currently we allocate on one of memory and use it for smallbuffers */
2657 qdev->small_buf_total_size =
2658 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2659 QL_SMALL_BUFFER_SIZE);
2660
2661 qdev->small_buf_virt_addr =
2662 dma_alloc_coherent(&qdev->pdev->dev,
2663 qdev->small_buf_total_size,
2664 &qdev->small_buf_phy_addr, GFP_KERNEL);
2665
2666 if (qdev->small_buf_virt_addr == NULL) {
2667 netdev_err(qdev->ndev, "Failed to get small buffer memory\n");
2668 return -ENOMEM;
2669 }
2670
2671 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2672 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2673
2674 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2675
2676 /* Initialize the small buffer queue. */
2677 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2678 small_buf_q_entry->addr_high =
2679 cpu_to_le32(qdev->small_buf_phy_addr_high);
2680 small_buf_q_entry->addr_low =
2681 cpu_to_le32(qdev->small_buf_phy_addr_low +
2682 (i * QL_SMALL_BUFFER_SIZE));
2683 small_buf_q_entry++;
2684 }
2685 qdev->small_buf_index = 0;
2686 set_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags);
2687 return 0;
2688}
2689
2690static void ql_free_small_buffers(struct ql3_adapter *qdev)
2691{
2692 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags)) {
2693 netdev_info(qdev->ndev, "Already done\n");
2694 return;
2695 }
2696 if (qdev->small_buf_virt_addr != NULL) {
2697 dma_free_coherent(&qdev->pdev->dev,
2698 qdev->small_buf_total_size,
2699 qdev->small_buf_virt_addr,
2700 qdev->small_buf_phy_addr);
2701
2702 qdev->small_buf_virt_addr = NULL;
2703 }
2704}
2705
2706static void ql_free_large_buffers(struct ql3_adapter *qdev)
2707{
2708 int i = 0;
2709 struct ql_rcv_buf_cb *lrg_buf_cb;
2710
2711 for (i = 0; i < qdev->num_large_buffers; i++) {
2712 lrg_buf_cb = &qdev->lrg_buf[i];
2713 if (lrg_buf_cb->skb) {
2714 dev_kfree_skb(lrg_buf_cb->skb);
2715 dma_unmap_single(&qdev->pdev->dev,
2716 dma_unmap_addr(lrg_buf_cb, mapaddr),
2717 dma_unmap_len(lrg_buf_cb, maplen),
2718 DMA_FROM_DEVICE);
2719 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2720 } else {
2721 break;
2722 }
2723 }
2724}
2725
2726static void ql_init_large_buffers(struct ql3_adapter *qdev)
2727{
2728 int i;
2729 struct ql_rcv_buf_cb *lrg_buf_cb;
2730 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2731
2732 for (i = 0; i < qdev->num_large_buffers; i++) {
2733 lrg_buf_cb = &qdev->lrg_buf[i];
2734 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2735 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2736 buf_addr_ele++;
2737 }
2738 qdev->lrg_buf_index = 0;
2739 qdev->lrg_buf_skb_check = 0;
2740}
2741
2742static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2743{
2744 int i;
2745 struct ql_rcv_buf_cb *lrg_buf_cb;
2746 struct sk_buff *skb;
2747 dma_addr_t map;
2748 int err;
2749
2750 for (i = 0; i < qdev->num_large_buffers; i++) {
2751 lrg_buf_cb = &qdev->lrg_buf[i];
2752 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2753
2754 skb = netdev_alloc_skb(qdev->ndev,
2755 qdev->lrg_buffer_len);
2756 if (unlikely(!skb)) {
2757 /* Better luck next round */
2758 netdev_err(qdev->ndev,
2759 "large buff alloc failed for %d bytes at index %d\n",
2760 qdev->lrg_buffer_len * 2, i);
2761 ql_free_large_buffers(qdev);
2762 return -ENOMEM;
2763 } else {
2764 lrg_buf_cb->index = i;
2765 /*
2766 * We save some space to copy the ethhdr from first
2767 * buffer
2768 */
2769 skb_reserve(skb, QL_HEADER_SPACE);
2770 map = dma_map_single(&qdev->pdev->dev, skb->data,
2771 qdev->lrg_buffer_len - QL_HEADER_SPACE,
2772 DMA_FROM_DEVICE);
2773
2774 err = dma_mapping_error(&qdev->pdev->dev, map);
2775 if (err) {
2776 netdev_err(qdev->ndev,
2777 "PCI mapping failed with error: %d\n",
2778 err);
2779 dev_kfree_skb_irq(skb);
2780 ql_free_large_buffers(qdev);
2781 return -ENOMEM;
2782 }
2783
2784 lrg_buf_cb->skb = skb;
2785 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2786 dma_unmap_len_set(lrg_buf_cb, maplen,
2787 qdev->lrg_buffer_len -
2788 QL_HEADER_SPACE);
2789 lrg_buf_cb->buf_phy_addr_low =
2790 cpu_to_le32(LS_64BITS(map));
2791 lrg_buf_cb->buf_phy_addr_high =
2792 cpu_to_le32(MS_64BITS(map));
2793 }
2794 }
2795 return 0;
2796}
2797
2798static void ql_free_send_free_list(struct ql3_adapter *qdev)
2799{
2800 struct ql_tx_buf_cb *tx_cb;
2801 int i;
2802
2803 tx_cb = &qdev->tx_buf[0];
2804 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2805 kfree(tx_cb->oal);
2806 tx_cb->oal = NULL;
2807 tx_cb++;
2808 }
2809}
2810
2811static int ql_create_send_free_list(struct ql3_adapter *qdev)
2812{
2813 struct ql_tx_buf_cb *tx_cb;
2814 int i;
2815 struct ob_mac_iocb_req *req_q_curr = qdev->req_q_virt_addr;
2816
2817 /* Create free list of transmit buffers */
2818 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2819
2820 tx_cb = &qdev->tx_buf[i];
2821 tx_cb->skb = NULL;
2822 tx_cb->queue_entry = req_q_curr;
2823 req_q_curr++;
2824 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2825 if (tx_cb->oal == NULL)
2826 return -ENOMEM;
2827 }
2828 return 0;
2829}
2830
2831static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2832{
2833 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2834 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2835 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2836 } else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2837 /*
2838 * Bigger buffers, so less of them.
2839 */
2840 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2841 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2842 } else {
2843 netdev_err(qdev->ndev, "Invalid mtu size: %d. Only %d and %d are accepted.\n",
2844 qdev->ndev->mtu, NORMAL_MTU_SIZE, JUMBO_MTU_SIZE);
2845 return -ENOMEM;
2846 }
2847 qdev->num_large_buffers =
2848 qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2849 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2850 qdev->max_frame_size =
2851 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2852
2853 /*
2854 * First allocate a page of shared memory and use it for shadow
2855 * locations of Network Request Queue Consumer Address Register and
2856 * Network Completion Queue Producer Index Register
2857 */
2858 qdev->shadow_reg_virt_addr =
2859 dma_alloc_coherent(&qdev->pdev->dev, PAGE_SIZE,
2860 &qdev->shadow_reg_phy_addr, GFP_KERNEL);
2861
2862 if (qdev->shadow_reg_virt_addr != NULL) {
2863 qdev->preq_consumer_index = qdev->shadow_reg_virt_addr;
2864 qdev->req_consumer_index_phy_addr_high =
2865 MS_64BITS(qdev->shadow_reg_phy_addr);
2866 qdev->req_consumer_index_phy_addr_low =
2867 LS_64BITS(qdev->shadow_reg_phy_addr);
2868
2869 qdev->prsp_producer_index =
2870 (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2871 qdev->rsp_producer_index_phy_addr_high =
2872 qdev->req_consumer_index_phy_addr_high;
2873 qdev->rsp_producer_index_phy_addr_low =
2874 qdev->req_consumer_index_phy_addr_low + 8;
2875 } else {
2876 netdev_err(qdev->ndev, "shadowReg Alloc failed\n");
2877 return -ENOMEM;
2878 }
2879
2880 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2881 netdev_err(qdev->ndev, "ql_alloc_net_req_rsp_queues failed\n");
2882 goto err_req_rsp;
2883 }
2884
2885 if (ql_alloc_buffer_queues(qdev) != 0) {
2886 netdev_err(qdev->ndev, "ql_alloc_buffer_queues failed\n");
2887 goto err_buffer_queues;
2888 }
2889
2890 if (ql_alloc_small_buffers(qdev) != 0) {
2891 netdev_err(qdev->ndev, "ql_alloc_small_buffers failed\n");
2892 goto err_small_buffers;
2893 }
2894
2895 if (ql_alloc_large_buffers(qdev) != 0) {
2896 netdev_err(qdev->ndev, "ql_alloc_large_buffers failed\n");
2897 goto err_small_buffers;
2898 }
2899
2900 /* Initialize the large buffer queue. */
2901 ql_init_large_buffers(qdev);
2902 if (ql_create_send_free_list(qdev))
2903 goto err_free_list;
2904
2905 qdev->rsp_current = qdev->rsp_q_virt_addr;
2906
2907 return 0;
2908err_free_list:
2909 ql_free_send_free_list(qdev);
2910err_small_buffers:
2911 ql_free_buffer_queues(qdev);
2912err_buffer_queues:
2913 ql_free_net_req_rsp_queues(qdev);
2914err_req_rsp:
2915 dma_free_coherent(&qdev->pdev->dev, PAGE_SIZE,
2916 qdev->shadow_reg_virt_addr,
2917 qdev->shadow_reg_phy_addr);
2918
2919 return -ENOMEM;
2920}
2921
2922static void ql_free_mem_resources(struct ql3_adapter *qdev)
2923{
2924 ql_free_send_free_list(qdev);
2925 ql_free_large_buffers(qdev);
2926 ql_free_small_buffers(qdev);
2927 ql_free_buffer_queues(qdev);
2928 ql_free_net_req_rsp_queues(qdev);
2929 if (qdev->shadow_reg_virt_addr != NULL) {
2930 dma_free_coherent(&qdev->pdev->dev, PAGE_SIZE,
2931 qdev->shadow_reg_virt_addr,
2932 qdev->shadow_reg_phy_addr);
2933 qdev->shadow_reg_virt_addr = NULL;
2934 }
2935}
2936
2937static int ql_init_misc_registers(struct ql3_adapter *qdev)
2938{
2939 struct ql3xxx_local_ram_registers __iomem *local_ram =
2940 (void __iomem *)qdev->mem_map_registers;
2941
2942 if (ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2943 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2944 2) << 4))
2945 return -1;
2946
2947 ql_write_page2_reg(qdev,
2948 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2949
2950 ql_write_page2_reg(qdev,
2951 &local_ram->maxBufletCount,
2952 qdev->nvram_data.bufletCount);
2953
2954 ql_write_page2_reg(qdev,
2955 &local_ram->freeBufletThresholdLow,
2956 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2957 (qdev->nvram_data.tcpWindowThreshold0));
2958
2959 ql_write_page2_reg(qdev,
2960 &local_ram->freeBufletThresholdHigh,
2961 qdev->nvram_data.tcpWindowThreshold50);
2962
2963 ql_write_page2_reg(qdev,
2964 &local_ram->ipHashTableBase,
2965 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2966 qdev->nvram_data.ipHashTableBaseLo);
2967 ql_write_page2_reg(qdev,
2968 &local_ram->ipHashTableCount,
2969 qdev->nvram_data.ipHashTableSize);
2970 ql_write_page2_reg(qdev,
2971 &local_ram->tcpHashTableBase,
2972 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2973 qdev->nvram_data.tcpHashTableBaseLo);
2974 ql_write_page2_reg(qdev,
2975 &local_ram->tcpHashTableCount,
2976 qdev->nvram_data.tcpHashTableSize);
2977 ql_write_page2_reg(qdev,
2978 &local_ram->ncbBase,
2979 (qdev->nvram_data.ncbTableBaseHi << 16) |
2980 qdev->nvram_data.ncbTableBaseLo);
2981 ql_write_page2_reg(qdev,
2982 &local_ram->maxNcbCount,
2983 qdev->nvram_data.ncbTableSize);
2984 ql_write_page2_reg(qdev,
2985 &local_ram->drbBase,
2986 (qdev->nvram_data.drbTableBaseHi << 16) |
2987 qdev->nvram_data.drbTableBaseLo);
2988 ql_write_page2_reg(qdev,
2989 &local_ram->maxDrbCount,
2990 qdev->nvram_data.drbTableSize);
2991 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2992 return 0;
2993}
2994
2995static int ql_adapter_initialize(struct ql3_adapter *qdev)
2996{
2997 u32 value;
2998 struct ql3xxx_port_registers __iomem *port_regs =
2999 qdev->mem_map_registers;
3000 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
3001 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3002 (void __iomem *)port_regs;
3003 u32 delay = 10;
3004 int status = 0;
3005
3006 if (ql_mii_setup(qdev))
3007 return -1;
3008
3009 /* Bring out PHY out of reset */
3010 ql_write_common_reg(qdev, spir,
3011 (ISP_SERIAL_PORT_IF_WE |
3012 (ISP_SERIAL_PORT_IF_WE << 16)));
3013 /* Give the PHY time to come out of reset. */
3014 mdelay(100);
3015 qdev->port_link_state = LS_DOWN;
3016 netif_carrier_off(qdev->ndev);
3017
3018 /* V2 chip fix for ARS-39168. */
3019 ql_write_common_reg(qdev, spir,
3020 (ISP_SERIAL_PORT_IF_SDE |
3021 (ISP_SERIAL_PORT_IF_SDE << 16)));
3022
3023 /* Request Queue Registers */
3024 *((u32 *)(qdev->preq_consumer_index)) = 0;
3025 atomic_set(&qdev->tx_count, NUM_REQ_Q_ENTRIES);
3026 qdev->req_producer_index = 0;
3027
3028 ql_write_page1_reg(qdev,
3029 &hmem_regs->reqConsumerIndexAddrHigh,
3030 qdev->req_consumer_index_phy_addr_high);
3031 ql_write_page1_reg(qdev,
3032 &hmem_regs->reqConsumerIndexAddrLow,
3033 qdev->req_consumer_index_phy_addr_low);
3034
3035 ql_write_page1_reg(qdev,
3036 &hmem_regs->reqBaseAddrHigh,
3037 MS_64BITS(qdev->req_q_phy_addr));
3038 ql_write_page1_reg(qdev,
3039 &hmem_regs->reqBaseAddrLow,
3040 LS_64BITS(qdev->req_q_phy_addr));
3041 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3042
3043 /* Response Queue Registers */
3044 *((__le16 *) (qdev->prsp_producer_index)) = 0;
3045 qdev->rsp_consumer_index = 0;
3046 qdev->rsp_current = qdev->rsp_q_virt_addr;
3047
3048 ql_write_page1_reg(qdev,
3049 &hmem_regs->rspProducerIndexAddrHigh,
3050 qdev->rsp_producer_index_phy_addr_high);
3051
3052 ql_write_page1_reg(qdev,
3053 &hmem_regs->rspProducerIndexAddrLow,
3054 qdev->rsp_producer_index_phy_addr_low);
3055
3056 ql_write_page1_reg(qdev,
3057 &hmem_regs->rspBaseAddrHigh,
3058 MS_64BITS(qdev->rsp_q_phy_addr));
3059
3060 ql_write_page1_reg(qdev,
3061 &hmem_regs->rspBaseAddrLow,
3062 LS_64BITS(qdev->rsp_q_phy_addr));
3063
3064 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3065
3066 /* Large Buffer Queue */
3067 ql_write_page1_reg(qdev,
3068 &hmem_regs->rxLargeQBaseAddrHigh,
3069 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3070
3071 ql_write_page1_reg(qdev,
3072 &hmem_regs->rxLargeQBaseAddrLow,
3073 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3074
3075 ql_write_page1_reg(qdev,
3076 &hmem_regs->rxLargeQLength,
3077 qdev->num_lbufq_entries);
3078
3079 ql_write_page1_reg(qdev,
3080 &hmem_regs->rxLargeBufferLength,
3081 qdev->lrg_buffer_len);
3082
3083 /* Small Buffer Queue */
3084 ql_write_page1_reg(qdev,
3085 &hmem_regs->rxSmallQBaseAddrHigh,
3086 MS_64BITS(qdev->small_buf_q_phy_addr));
3087
3088 ql_write_page1_reg(qdev,
3089 &hmem_regs->rxSmallQBaseAddrLow,
3090 LS_64BITS(qdev->small_buf_q_phy_addr));
3091
3092 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3093 ql_write_page1_reg(qdev,
3094 &hmem_regs->rxSmallBufferLength,
3095 QL_SMALL_BUFFER_SIZE);
3096
3097 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3098 qdev->small_buf_release_cnt = 8;
3099 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3100 qdev->lrg_buf_release_cnt = 8;
3101 qdev->lrg_buf_next_free = qdev->lrg_buf_q_virt_addr;
3102 qdev->small_buf_index = 0;
3103 qdev->lrg_buf_index = 0;
3104 qdev->lrg_buf_free_count = 0;
3105 qdev->lrg_buf_free_head = NULL;
3106 qdev->lrg_buf_free_tail = NULL;
3107
3108 ql_write_common_reg(qdev,
3109 &port_regs->CommonRegs.
3110 rxSmallQProducerIndex,
3111 qdev->small_buf_q_producer_index);
3112 ql_write_common_reg(qdev,
3113 &port_regs->CommonRegs.
3114 rxLargeQProducerIndex,
3115 qdev->lrg_buf_q_producer_index);
3116
3117 /*
3118 * Find out if the chip has already been initialized. If it has, then
3119 * we skip some of the initialization.
3120 */
3121 clear_bit(QL_LINK_MASTER, &qdev->flags);
3122 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3123 if ((value & PORT_STATUS_IC) == 0) {
3124
3125 /* Chip has not been configured yet, so let it rip. */
3126 if (ql_init_misc_registers(qdev)) {
3127 status = -1;
3128 goto out;
3129 }
3130
3131 value = qdev->nvram_data.tcpMaxWindowSize;
3132 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3133
3134 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3135
3136 if (ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3137 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3138 * 2) << 13)) {
3139 status = -1;
3140 goto out;
3141 }
3142 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3143 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3144 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3145 16) | (INTERNAL_CHIP_SD |
3146 INTERNAL_CHIP_WE)));
3147 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3148 }
3149
3150 if (qdev->mac_index)
3151 ql_write_page0_reg(qdev,
3152 &port_regs->mac1MaxFrameLengthReg,
3153 qdev->max_frame_size);
3154 else
3155 ql_write_page0_reg(qdev,
3156 &port_regs->mac0MaxFrameLengthReg,
3157 qdev->max_frame_size);
3158
3159 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3160 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3161 2) << 7)) {
3162 status = -1;
3163 goto out;
3164 }
3165
3166 PHY_Setup(qdev);
3167 ql_init_scan_mode(qdev);
3168 ql_get_phy_owner(qdev);
3169
3170 /* Load the MAC Configuration */
3171
3172 /* Program lower 32 bits of the MAC address */
3173 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3174 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3175 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3176 ((qdev->ndev->dev_addr[2] << 24)
3177 | (qdev->ndev->dev_addr[3] << 16)
3178 | (qdev->ndev->dev_addr[4] << 8)
3179 | qdev->ndev->dev_addr[5]));
3180
3181 /* Program top 16 bits of the MAC address */
3182 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3183 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3184 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3185 ((qdev->ndev->dev_addr[0] << 8)
3186 | qdev->ndev->dev_addr[1]));
3187
3188 /* Enable Primary MAC */
3189 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3190 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3191 MAC_ADDR_INDIRECT_PTR_REG_PE));
3192
3193 /* Clear Primary and Secondary IP addresses */
3194 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3195 ((IP_ADDR_INDEX_REG_MASK << 16) |
3196 (qdev->mac_index << 2)));
3197 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3198
3199 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3200 ((IP_ADDR_INDEX_REG_MASK << 16) |
3201 ((qdev->mac_index << 2) + 1)));
3202 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3203
3204 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3205
3206 /* Indicate Configuration Complete */
3207 ql_write_page0_reg(qdev,
3208 &port_regs->portControl,
3209 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3210
3211 do {
3212 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3213 if (value & PORT_STATUS_IC)
3214 break;
3215 spin_unlock_irq(&qdev->hw_lock);
3216 msleep(500);
3217 spin_lock_irq(&qdev->hw_lock);
3218 } while (--delay);
3219
3220 if (delay == 0) {
3221 netdev_err(qdev->ndev, "Hw Initialization timeout\n");
3222 status = -1;
3223 goto out;
3224 }
3225
3226 /* Enable Ethernet Function */
3227 if (qdev->device_id == QL3032_DEVICE_ID) {
3228 value =
3229 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3230 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3231 QL3032_PORT_CONTROL_ET);
3232 ql_write_page0_reg(qdev, &port_regs->functionControl,
3233 ((value << 16) | value));
3234 } else {
3235 value =
3236 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3237 PORT_CONTROL_HH);
3238 ql_write_page0_reg(qdev, &port_regs->portControl,
3239 ((value << 16) | value));
3240 }
3241
3242
3243out:
3244 return status;
3245}
3246
3247/*
3248 * Caller holds hw_lock.
3249 */
3250static int ql_adapter_reset(struct ql3_adapter *qdev)
3251{
3252 struct ql3xxx_port_registers __iomem *port_regs =
3253 qdev->mem_map_registers;
3254 int status = 0;
3255 u16 value;
3256 int max_wait_time;
3257
3258 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3259 clear_bit(QL_RESET_DONE, &qdev->flags);
3260
3261 /*
3262 * Issue soft reset to chip.
3263 */
3264 netdev_printk(KERN_DEBUG, qdev->ndev, "Issue soft reset to chip\n");
3265 ql_write_common_reg(qdev,
3266 &port_regs->CommonRegs.ispControlStatus,
3267 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3268
3269 /* Wait 3 seconds for reset to complete. */
3270 netdev_printk(KERN_DEBUG, qdev->ndev,
3271 "Wait 10 milliseconds for reset to complete\n");
3272
3273 /* Wait until the firmware tells us the Soft Reset is done */
3274 max_wait_time = 5;
3275 do {
3276 value =
3277 ql_read_common_reg(qdev,
3278 &port_regs->CommonRegs.ispControlStatus);
3279 if ((value & ISP_CONTROL_SR) == 0)
3280 break;
3281
3282 mdelay(1000);
3283 } while ((--max_wait_time));
3284
3285 /*
3286 * Also, make sure that the Network Reset Interrupt bit has been
3287 * cleared after the soft reset has taken place.
3288 */
3289 value =
3290 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3291 if (value & ISP_CONTROL_RI) {
3292 netdev_printk(KERN_DEBUG, qdev->ndev,
3293 "clearing RI after reset\n");
3294 ql_write_common_reg(qdev,
3295 &port_regs->CommonRegs.
3296 ispControlStatus,
3297 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3298 }
3299
3300 if (max_wait_time == 0) {
3301 /* Issue Force Soft Reset */
3302 ql_write_common_reg(qdev,
3303 &port_regs->CommonRegs.
3304 ispControlStatus,
3305 ((ISP_CONTROL_FSR << 16) |
3306 ISP_CONTROL_FSR));
3307 /*
3308 * Wait until the firmware tells us the Force Soft Reset is
3309 * done
3310 */
3311 max_wait_time = 5;
3312 do {
3313 value = ql_read_common_reg(qdev,
3314 &port_regs->CommonRegs.
3315 ispControlStatus);
3316 if ((value & ISP_CONTROL_FSR) == 0)
3317 break;
3318 mdelay(1000);
3319 } while ((--max_wait_time));
3320 }
3321 if (max_wait_time == 0)
3322 status = 1;
3323
3324 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3325 set_bit(QL_RESET_DONE, &qdev->flags);
3326 return status;
3327}
3328
3329static void ql_set_mac_info(struct ql3_adapter *qdev)
3330{
3331 struct ql3xxx_port_registers __iomem *port_regs =
3332 qdev->mem_map_registers;
3333 u32 value, port_status;
3334 u8 func_number;
3335
3336 /* Get the function number */
3337 value =
3338 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3339 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3340 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3341 switch (value & ISP_CONTROL_FN_MASK) {
3342 case ISP_CONTROL_FN0_NET:
3343 qdev->mac_index = 0;
3344 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3345 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3346 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3347 if (port_status & PORT_STATUS_SM0)
3348 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3349 else
3350 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3351 break;
3352
3353 case ISP_CONTROL_FN1_NET:
3354 qdev->mac_index = 1;
3355 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3356 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3357 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3358 if (port_status & PORT_STATUS_SM1)
3359 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3360 else
3361 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3362 break;
3363
3364 case ISP_CONTROL_FN0_SCSI:
3365 case ISP_CONTROL_FN1_SCSI:
3366 default:
3367 netdev_printk(KERN_DEBUG, qdev->ndev,
3368 "Invalid function number, ispControlStatus = 0x%x\n",
3369 value);
3370 break;
3371 }
3372 qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
3373}
3374
3375static void ql_display_dev_info(struct net_device *ndev)
3376{
3377 struct ql3_adapter *qdev = netdev_priv(ndev);
3378 struct pci_dev *pdev = qdev->pdev;
3379
3380 netdev_info(ndev,
3381 "%s Adapter %d RevisionID %d found %s on PCI slot %d\n",
3382 DRV_NAME, qdev->index, qdev->chip_rev_id,
3383 qdev->device_id == QL3032_DEVICE_ID ? "QLA3032" : "QLA3022",
3384 qdev->pci_slot);
3385 netdev_info(ndev, "%s Interface\n",
3386 test_bit(QL_LINK_OPTICAL, &qdev->flags) ? "OPTICAL" : "COPPER");
3387
3388 /*
3389 * Print PCI bus width/type.
3390 */
3391 netdev_info(ndev, "Bus interface is %s %s\n",
3392 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3393 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3394
3395 netdev_info(ndev, "mem IO base address adjusted = 0x%p\n",
3396 qdev->mem_map_registers);
3397 netdev_info(ndev, "Interrupt number = %d\n", pdev->irq);
3398
3399 netif_info(qdev, probe, ndev, "MAC address %pM\n", ndev->dev_addr);
3400}
3401
3402static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3403{
3404 struct net_device *ndev = qdev->ndev;
3405 int retval = 0;
3406
3407 netif_stop_queue(ndev);
3408 netif_carrier_off(ndev);
3409
3410 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3411 clear_bit(QL_LINK_MASTER, &qdev->flags);
3412
3413 ql_disable_interrupts(qdev);
3414
3415 free_irq(qdev->pdev->irq, ndev);
3416
3417 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3418 netdev_info(qdev->ndev, "calling pci_disable_msi()\n");
3419 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3420 pci_disable_msi(qdev->pdev);
3421 }
3422
3423 del_timer_sync(&qdev->adapter_timer);
3424
3425 napi_disable(&qdev->napi);
3426
3427 if (do_reset) {
3428 int soft_reset;
3429 unsigned long hw_flags;
3430
3431 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3432 if (ql_wait_for_drvr_lock(qdev)) {
3433 soft_reset = ql_adapter_reset(qdev);
3434 if (soft_reset) {
3435 netdev_err(ndev, "ql_adapter_reset(%d) FAILED!\n",
3436 qdev->index);
3437 }
3438 netdev_err(ndev,
3439 "Releasing driver lock via chip reset\n");
3440 } else {
3441 netdev_err(ndev,
3442 "Could not acquire driver lock to do reset!\n");
3443 retval = -1;
3444 }
3445 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3446 }
3447 ql_free_mem_resources(qdev);
3448 return retval;
3449}
3450
3451static int ql_adapter_up(struct ql3_adapter *qdev)
3452{
3453 struct net_device *ndev = qdev->ndev;
3454 int err;
3455 unsigned long irq_flags = IRQF_SHARED;
3456 unsigned long hw_flags;
3457
3458 if (ql_alloc_mem_resources(qdev)) {
3459 netdev_err(ndev, "Unable to allocate buffers\n");
3460 return -ENOMEM;
3461 }
3462
3463 if (qdev->msi) {
3464 if (pci_enable_msi(qdev->pdev)) {
3465 netdev_err(ndev,
3466 "User requested MSI, but MSI failed to initialize. Continuing without MSI.\n");
3467 qdev->msi = 0;
3468 } else {
3469 netdev_info(ndev, "MSI Enabled...\n");
3470 set_bit(QL_MSI_ENABLED, &qdev->flags);
3471 irq_flags &= ~IRQF_SHARED;
3472 }
3473 }
3474
3475 err = request_irq(qdev->pdev->irq, ql3xxx_isr,
3476 irq_flags, ndev->name, ndev);
3477 if (err) {
3478 netdev_err(ndev,
3479 "Failed to reserve interrupt %d - already in use\n",
3480 qdev->pdev->irq);
3481 goto err_irq;
3482 }
3483
3484 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3485
3486 if (!ql_wait_for_drvr_lock(qdev)) {
3487 netdev_err(ndev, "Could not acquire driver lock\n");
3488 err = -ENODEV;
3489 goto err_lock;
3490 }
3491
3492 err = ql_adapter_initialize(qdev);
3493 if (err) {
3494 netdev_err(ndev, "Unable to initialize adapter\n");
3495 goto err_init;
3496 }
3497 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3498
3499 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3500
3501 set_bit(QL_ADAPTER_UP, &qdev->flags);
3502
3503 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3504
3505 napi_enable(&qdev->napi);
3506 ql_enable_interrupts(qdev);
3507 return 0;
3508
3509err_init:
3510 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3511err_lock:
3512 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3513 free_irq(qdev->pdev->irq, ndev);
3514err_irq:
3515 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3516 netdev_info(ndev, "calling pci_disable_msi()\n");
3517 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3518 pci_disable_msi(qdev->pdev);
3519 }
3520 return err;
3521}
3522
3523static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3524{
3525 if (ql_adapter_down(qdev, reset) || ql_adapter_up(qdev)) {
3526 netdev_err(qdev->ndev,
3527 "Driver up/down cycle failed, closing device\n");
3528 rtnl_lock();
3529 dev_close(qdev->ndev);
3530 rtnl_unlock();
3531 return -1;
3532 }
3533 return 0;
3534}
3535
3536static int ql3xxx_close(struct net_device *ndev)
3537{
3538 struct ql3_adapter *qdev = netdev_priv(ndev);
3539
3540 /*
3541 * Wait for device to recover from a reset.
3542 * (Rarely happens, but possible.)
3543 */
3544 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3545 msleep(50);
3546
3547 ql_adapter_down(qdev, QL_DO_RESET);
3548 return 0;
3549}
3550
3551static int ql3xxx_open(struct net_device *ndev)
3552{
3553 struct ql3_adapter *qdev = netdev_priv(ndev);
3554 return ql_adapter_up(qdev);
3555}
3556
3557static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3558{
3559 struct ql3_adapter *qdev = netdev_priv(ndev);
3560 struct ql3xxx_port_registers __iomem *port_regs =
3561 qdev->mem_map_registers;
3562 struct sockaddr *addr = p;
3563 unsigned long hw_flags;
3564
3565 if (netif_running(ndev))
3566 return -EBUSY;
3567
3568 if (!is_valid_ether_addr(addr->sa_data))
3569 return -EADDRNOTAVAIL;
3570
3571 eth_hw_addr_set(ndev, addr->sa_data);
3572
3573 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3574 /* Program lower 32 bits of the MAC address */
3575 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3576 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3577 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3578 ((ndev->dev_addr[2] << 24) | (ndev->
3579 dev_addr[3] << 16) |
3580 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3581
3582 /* Program top 16 bits of the MAC address */
3583 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3584 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3585 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3586 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3587 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3588
3589 return 0;
3590}
3591
3592static void ql3xxx_tx_timeout(struct net_device *ndev, unsigned int txqueue)
3593{
3594 struct ql3_adapter *qdev = netdev_priv(ndev);
3595
3596 netdev_err(ndev, "Resetting...\n");
3597 /*
3598 * Stop the queues, we've got a problem.
3599 */
3600 netif_stop_queue(ndev);
3601
3602 /*
3603 * Wake up the worker to process this event.
3604 */
3605 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3606}
3607
3608static void ql_reset_work(struct work_struct *work)
3609{
3610 struct ql3_adapter *qdev =
3611 container_of(work, struct ql3_adapter, reset_work.work);
3612 struct net_device *ndev = qdev->ndev;
3613 u32 value;
3614 struct ql_tx_buf_cb *tx_cb;
3615 int max_wait_time, i;
3616 struct ql3xxx_port_registers __iomem *port_regs =
3617 qdev->mem_map_registers;
3618 unsigned long hw_flags;
3619
3620 if (test_bit(QL_RESET_PER_SCSI, &qdev->flags) ||
3621 test_bit(QL_RESET_START, &qdev->flags)) {
3622 clear_bit(QL_LINK_MASTER, &qdev->flags);
3623
3624 /*
3625 * Loop through the active list and return the skb.
3626 */
3627 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3628 int j;
3629 tx_cb = &qdev->tx_buf[i];
3630 if (tx_cb->skb) {
3631 netdev_printk(KERN_DEBUG, ndev,
3632 "Freeing lost SKB\n");
3633 dma_unmap_single(&qdev->pdev->dev,
3634 dma_unmap_addr(&tx_cb->map[0], mapaddr),
3635 dma_unmap_len(&tx_cb->map[0], maplen),
3636 DMA_TO_DEVICE);
3637 for (j = 1; j < tx_cb->seg_count; j++) {
3638 dma_unmap_page(&qdev->pdev->dev,
3639 dma_unmap_addr(&tx_cb->map[j], mapaddr),
3640 dma_unmap_len(&tx_cb->map[j], maplen),
3641 DMA_TO_DEVICE);
3642 }
3643 dev_kfree_skb(tx_cb->skb);
3644 tx_cb->skb = NULL;
3645 }
3646 }
3647
3648 netdev_err(ndev, "Clearing NRI after reset\n");
3649 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3650 ql_write_common_reg(qdev,
3651 &port_regs->CommonRegs.
3652 ispControlStatus,
3653 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3654 /*
3655 * Wait the for Soft Reset to Complete.
3656 */
3657 max_wait_time = 10;
3658 do {
3659 value = ql_read_common_reg(qdev,
3660 &port_regs->CommonRegs.
3661
3662 ispControlStatus);
3663 if ((value & ISP_CONTROL_SR) == 0) {
3664 netdev_printk(KERN_DEBUG, ndev,
3665 "reset completed\n");
3666 break;
3667 }
3668
3669 if (value & ISP_CONTROL_RI) {
3670 netdev_printk(KERN_DEBUG, ndev,
3671 "clearing NRI after reset\n");
3672 ql_write_common_reg(qdev,
3673 &port_regs->
3674 CommonRegs.
3675 ispControlStatus,
3676 ((ISP_CONTROL_RI <<
3677 16) | ISP_CONTROL_RI));
3678 }
3679
3680 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3681 ssleep(1);
3682 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3683 } while (--max_wait_time);
3684 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3685
3686 if (value & ISP_CONTROL_SR) {
3687
3688 /*
3689 * Set the reset flags and clear the board again.
3690 * Nothing else to do...
3691 */
3692 netdev_err(ndev,
3693 "Timed out waiting for reset to complete\n");
3694 netdev_err(ndev, "Do a reset\n");
3695 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3696 clear_bit(QL_RESET_START, &qdev->flags);
3697 ql_cycle_adapter(qdev, QL_DO_RESET);
3698 return;
3699 }
3700
3701 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3702 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3703 clear_bit(QL_RESET_START, &qdev->flags);
3704 ql_cycle_adapter(qdev, QL_NO_RESET);
3705 }
3706}
3707
3708static void ql_tx_timeout_work(struct work_struct *work)
3709{
3710 struct ql3_adapter *qdev =
3711 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3712
3713 ql_cycle_adapter(qdev, QL_DO_RESET);
3714}
3715
3716static void ql_get_board_info(struct ql3_adapter *qdev)
3717{
3718 struct ql3xxx_port_registers __iomem *port_regs =
3719 qdev->mem_map_registers;
3720 u32 value;
3721
3722 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3723
3724 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3725 if (value & PORT_STATUS_64)
3726 qdev->pci_width = 64;
3727 else
3728 qdev->pci_width = 32;
3729 if (value & PORT_STATUS_X)
3730 qdev->pci_x = 1;
3731 else
3732 qdev->pci_x = 0;
3733 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3734}
3735
3736static void ql3xxx_timer(struct timer_list *t)
3737{
3738 struct ql3_adapter *qdev = from_timer(qdev, t, adapter_timer);
3739 queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
3740}
3741
3742static const struct net_device_ops ql3xxx_netdev_ops = {
3743 .ndo_open = ql3xxx_open,
3744 .ndo_start_xmit = ql3xxx_send,
3745 .ndo_stop = ql3xxx_close,
3746 .ndo_validate_addr = eth_validate_addr,
3747 .ndo_set_mac_address = ql3xxx_set_mac_address,
3748 .ndo_tx_timeout = ql3xxx_tx_timeout,
3749};
3750
3751static int ql3xxx_probe(struct pci_dev *pdev,
3752 const struct pci_device_id *pci_entry)
3753{
3754 struct net_device *ndev = NULL;
3755 struct ql3_adapter *qdev = NULL;
3756 static int cards_found;
3757 int err;
3758
3759 err = pci_enable_device(pdev);
3760 if (err) {
3761 pr_err("%s cannot enable PCI device\n", pci_name(pdev));
3762 goto err_out;
3763 }
3764
3765 err = pci_request_regions(pdev, DRV_NAME);
3766 if (err) {
3767 pr_err("%s cannot obtain PCI resources\n", pci_name(pdev));
3768 goto err_out_disable_pdev;
3769 }
3770
3771 pci_set_master(pdev);
3772
3773 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3774 if (err) {
3775 pr_err("%s no usable DMA configuration\n", pci_name(pdev));
3776 goto err_out_free_regions;
3777 }
3778
3779 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3780 if (!ndev) {
3781 err = -ENOMEM;
3782 goto err_out_free_regions;
3783 }
3784
3785 SET_NETDEV_DEV(ndev, &pdev->dev);
3786
3787 pci_set_drvdata(pdev, ndev);
3788
3789 qdev = netdev_priv(ndev);
3790 qdev->index = cards_found;
3791 qdev->ndev = ndev;
3792 qdev->pdev = pdev;
3793 qdev->device_id = pci_entry->device;
3794 qdev->port_link_state = LS_DOWN;
3795 if (msi)
3796 qdev->msi = 1;
3797
3798 qdev->msg_enable = netif_msg_init(debug, default_msg);
3799
3800 ndev->features |= NETIF_F_HIGHDMA;
3801 if (qdev->device_id == QL3032_DEVICE_ID)
3802 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3803
3804 qdev->mem_map_registers = pci_ioremap_bar(pdev, 1);
3805 if (!qdev->mem_map_registers) {
3806 pr_err("%s: cannot map device registers\n", pci_name(pdev));
3807 err = -EIO;
3808 goto err_out_free_ndev;
3809 }
3810
3811 spin_lock_init(&qdev->adapter_lock);
3812 spin_lock_init(&qdev->hw_lock);
3813
3814 /* Set driver entry points */
3815 ndev->netdev_ops = &ql3xxx_netdev_ops;
3816 ndev->ethtool_ops = &ql3xxx_ethtool_ops;
3817 ndev->watchdog_timeo = 5 * HZ;
3818
3819 netif_napi_add(ndev, &qdev->napi, ql_poll);
3820
3821 ndev->irq = pdev->irq;
3822
3823 /* make sure the EEPROM is good */
3824 if (ql_get_nvram_params(qdev)) {
3825 pr_alert("%s: Adapter #%d, Invalid NVRAM parameters\n",
3826 __func__, qdev->index);
3827 err = -EIO;
3828 goto err_out_iounmap;
3829 }
3830
3831 ql_set_mac_info(qdev);
3832
3833 /* Validate and set parameters */
3834 if (qdev->mac_index) {
3835 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3836 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
3837 } else {
3838 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3839 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
3840 }
3841
3842 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3843
3844 /* Record PCI bus information. */
3845 ql_get_board_info(qdev);
3846
3847 /*
3848 * Set the Maximum Memory Read Byte Count value. We do this to handle
3849 * jumbo frames.
3850 */
3851 if (qdev->pci_x)
3852 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3853
3854 err = register_netdev(ndev);
3855 if (err) {
3856 pr_err("%s: cannot register net device\n", pci_name(pdev));
3857 goto err_out_iounmap;
3858 }
3859
3860 /* we're going to reset, so assume we have no link for now */
3861
3862 netif_carrier_off(ndev);
3863 netif_stop_queue(ndev);
3864
3865 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3866 if (!qdev->workqueue) {
3867 unregister_netdev(ndev);
3868 err = -ENOMEM;
3869 goto err_out_iounmap;
3870 }
3871
3872 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3873 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3874 INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
3875
3876 timer_setup(&qdev->adapter_timer, ql3xxx_timer, 0);
3877 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3878
3879 if (!cards_found) {
3880 pr_alert("%s\n", DRV_STRING);
3881 pr_alert("Driver name: %s, Version: %s\n",
3882 DRV_NAME, DRV_VERSION);
3883 }
3884 ql_display_dev_info(ndev);
3885
3886 cards_found++;
3887 return 0;
3888
3889err_out_iounmap:
3890 iounmap(qdev->mem_map_registers);
3891err_out_free_ndev:
3892 free_netdev(ndev);
3893err_out_free_regions:
3894 pci_release_regions(pdev);
3895err_out_disable_pdev:
3896 pci_disable_device(pdev);
3897err_out:
3898 return err;
3899}
3900
3901static void ql3xxx_remove(struct pci_dev *pdev)
3902{
3903 struct net_device *ndev = pci_get_drvdata(pdev);
3904 struct ql3_adapter *qdev = netdev_priv(ndev);
3905
3906 unregister_netdev(ndev);
3907
3908 ql_disable_interrupts(qdev);
3909
3910 if (qdev->workqueue) {
3911 cancel_delayed_work(&qdev->reset_work);
3912 cancel_delayed_work(&qdev->tx_timeout_work);
3913 destroy_workqueue(qdev->workqueue);
3914 qdev->workqueue = NULL;
3915 }
3916
3917 iounmap(qdev->mem_map_registers);
3918 pci_release_regions(pdev);
3919 free_netdev(ndev);
3920}
3921
3922static struct pci_driver ql3xxx_driver = {
3923
3924 .name = DRV_NAME,
3925 .id_table = ql3xxx_pci_tbl,
3926 .probe = ql3xxx_probe,
3927 .remove = ql3xxx_remove,
3928};
3929
3930module_pci_driver(ql3xxx_driver);
1/*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/kthread.h>
23#include <linux/interrupt.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/ip.h>
27#include <linux/in.h>
28#include <linux/if_arp.h>
29#include <linux/if_ether.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/skbuff.h>
34#include <linux/rtnetlink.h>
35#include <linux/if_vlan.h>
36#include <linux/delay.h>
37#include <linux/mm.h>
38#include <linux/prefetch.h>
39
40#include "qla3xxx.h"
41
42#define DRV_NAME "qla3xxx"
43#define DRV_STRING "QLogic ISP3XXX Network Driver"
44#define DRV_VERSION "v2.03.00-k5"
45
46static const char ql3xxx_driver_name[] = DRV_NAME;
47static const char ql3xxx_driver_version[] = DRV_VERSION;
48
49#define TIMED_OUT_MSG \
50"Timed out waiting for management port to get free before issuing command\n"
51
52MODULE_AUTHOR("QLogic Corporation");
53MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
54MODULE_LICENSE("GPL");
55MODULE_VERSION(DRV_VERSION);
56
57static const u32 default_msg
58 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
59 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
60
61static int debug = -1; /* defaults above */
62module_param(debug, int, 0);
63MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
64
65static int msi;
66module_param(msi, int, 0);
67MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
68
69static DEFINE_PCI_DEVICE_TABLE(ql3xxx_pci_tbl) = {
70 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
71 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
72 /* required last entry */
73 {0,}
74};
75
76MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
77
78/*
79 * These are the known PHY's which are used
80 */
81enum PHY_DEVICE_TYPE {
82 PHY_TYPE_UNKNOWN = 0,
83 PHY_VITESSE_VSC8211,
84 PHY_AGERE_ET1011C,
85 MAX_PHY_DEV_TYPES
86};
87
88struct PHY_DEVICE_INFO {
89 const enum PHY_DEVICE_TYPE phyDevice;
90 const u32 phyIdOUI;
91 const u16 phyIdModel;
92 const char *name;
93};
94
95static const struct PHY_DEVICE_INFO PHY_DEVICES[] = {
96 {PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
97 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
98 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
99};
100
101
102/*
103 * Caller must take hw_lock.
104 */
105static int ql_sem_spinlock(struct ql3_adapter *qdev,
106 u32 sem_mask, u32 sem_bits)
107{
108 struct ql3xxx_port_registers __iomem *port_regs =
109 qdev->mem_map_registers;
110 u32 value;
111 unsigned int seconds = 3;
112
113 do {
114 writel((sem_mask | sem_bits),
115 &port_regs->CommonRegs.semaphoreReg);
116 value = readl(&port_regs->CommonRegs.semaphoreReg);
117 if ((value & (sem_mask >> 16)) == sem_bits)
118 return 0;
119 ssleep(1);
120 } while (--seconds);
121 return -1;
122}
123
124static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
125{
126 struct ql3xxx_port_registers __iomem *port_regs =
127 qdev->mem_map_registers;
128 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
129 readl(&port_regs->CommonRegs.semaphoreReg);
130}
131
132static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
133{
134 struct ql3xxx_port_registers __iomem *port_regs =
135 qdev->mem_map_registers;
136 u32 value;
137
138 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
139 value = readl(&port_regs->CommonRegs.semaphoreReg);
140 return ((value & (sem_mask >> 16)) == sem_bits);
141}
142
143/*
144 * Caller holds hw_lock.
145 */
146static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
147{
148 int i = 0;
149
150 while (i < 10) {
151 if (i)
152 ssleep(1);
153
154 if (ql_sem_lock(qdev,
155 QL_DRVR_SEM_MASK,
156 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
157 * 2) << 1)) {
158 netdev_printk(KERN_DEBUG, qdev->ndev,
159 "driver lock acquired\n");
160 return 1;
161 }
162 }
163
164 netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n");
165 return 0;
166}
167
168static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
169{
170 struct ql3xxx_port_registers __iomem *port_regs =
171 qdev->mem_map_registers;
172
173 writel(((ISP_CONTROL_NP_MASK << 16) | page),
174 &port_regs->CommonRegs.ispControlStatus);
175 readl(&port_regs->CommonRegs.ispControlStatus);
176 qdev->current_page = page;
177}
178
179static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
180{
181 u32 value;
182 unsigned long hw_flags;
183
184 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
185 value = readl(reg);
186 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
187
188 return value;
189}
190
191static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
192{
193 return readl(reg);
194}
195
196static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
197{
198 u32 value;
199 unsigned long hw_flags;
200
201 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
202
203 if (qdev->current_page != 0)
204 ql_set_register_page(qdev, 0);
205 value = readl(reg);
206
207 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
208 return value;
209}
210
211static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
212{
213 if (qdev->current_page != 0)
214 ql_set_register_page(qdev, 0);
215 return readl(reg);
216}
217
218static void ql_write_common_reg_l(struct ql3_adapter *qdev,
219 u32 __iomem *reg, u32 value)
220{
221 unsigned long hw_flags;
222
223 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
224 writel(value, reg);
225 readl(reg);
226 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
227}
228
229static void ql_write_common_reg(struct ql3_adapter *qdev,
230 u32 __iomem *reg, u32 value)
231{
232 writel(value, reg);
233 readl(reg);
234}
235
236static void ql_write_nvram_reg(struct ql3_adapter *qdev,
237 u32 __iomem *reg, u32 value)
238{
239 writel(value, reg);
240 readl(reg);
241 udelay(1);
242}
243
244static void ql_write_page0_reg(struct ql3_adapter *qdev,
245 u32 __iomem *reg, u32 value)
246{
247 if (qdev->current_page != 0)
248 ql_set_register_page(qdev, 0);
249 writel(value, reg);
250 readl(reg);
251}
252
253/*
254 * Caller holds hw_lock. Only called during init.
255 */
256static void ql_write_page1_reg(struct ql3_adapter *qdev,
257 u32 __iomem *reg, u32 value)
258{
259 if (qdev->current_page != 1)
260 ql_set_register_page(qdev, 1);
261 writel(value, reg);
262 readl(reg);
263}
264
265/*
266 * Caller holds hw_lock. Only called during init.
267 */
268static void ql_write_page2_reg(struct ql3_adapter *qdev,
269 u32 __iomem *reg, u32 value)
270{
271 if (qdev->current_page != 2)
272 ql_set_register_page(qdev, 2);
273 writel(value, reg);
274 readl(reg);
275}
276
277static void ql_disable_interrupts(struct ql3_adapter *qdev)
278{
279 struct ql3xxx_port_registers __iomem *port_regs =
280 qdev->mem_map_registers;
281
282 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
283 (ISP_IMR_ENABLE_INT << 16));
284
285}
286
287static void ql_enable_interrupts(struct ql3_adapter *qdev)
288{
289 struct ql3xxx_port_registers __iomem *port_regs =
290 qdev->mem_map_registers;
291
292 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
293 ((0xff << 16) | ISP_IMR_ENABLE_INT));
294
295}
296
297static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
298 struct ql_rcv_buf_cb *lrg_buf_cb)
299{
300 dma_addr_t map;
301 int err;
302 lrg_buf_cb->next = NULL;
303
304 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
305 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
306 } else {
307 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
308 qdev->lrg_buf_free_tail = lrg_buf_cb;
309 }
310
311 if (!lrg_buf_cb->skb) {
312 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
313 qdev->lrg_buffer_len);
314 if (unlikely(!lrg_buf_cb->skb)) {
315 netdev_err(qdev->ndev, "failed netdev_alloc_skb()\n");
316 qdev->lrg_buf_skb_check++;
317 } else {
318 /*
319 * We save some space to copy the ethhdr from first
320 * buffer
321 */
322 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
323 map = pci_map_single(qdev->pdev,
324 lrg_buf_cb->skb->data,
325 qdev->lrg_buffer_len -
326 QL_HEADER_SPACE,
327 PCI_DMA_FROMDEVICE);
328 err = pci_dma_mapping_error(qdev->pdev, map);
329 if (err) {
330 netdev_err(qdev->ndev,
331 "PCI mapping failed with error: %d\n",
332 err);
333 dev_kfree_skb(lrg_buf_cb->skb);
334 lrg_buf_cb->skb = NULL;
335
336 qdev->lrg_buf_skb_check++;
337 return;
338 }
339
340 lrg_buf_cb->buf_phy_addr_low =
341 cpu_to_le32(LS_64BITS(map));
342 lrg_buf_cb->buf_phy_addr_high =
343 cpu_to_le32(MS_64BITS(map));
344 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
345 dma_unmap_len_set(lrg_buf_cb, maplen,
346 qdev->lrg_buffer_len -
347 QL_HEADER_SPACE);
348 }
349 }
350
351 qdev->lrg_buf_free_count++;
352}
353
354static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
355 *qdev)
356{
357 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
358
359 if (lrg_buf_cb != NULL) {
360 qdev->lrg_buf_free_head = lrg_buf_cb->next;
361 if (qdev->lrg_buf_free_head == NULL)
362 qdev->lrg_buf_free_tail = NULL;
363 qdev->lrg_buf_free_count--;
364 }
365
366 return lrg_buf_cb;
367}
368
369static u32 addrBits = EEPROM_NO_ADDR_BITS;
370static u32 dataBits = EEPROM_NO_DATA_BITS;
371
372static void fm93c56a_deselect(struct ql3_adapter *qdev);
373static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
374 unsigned short *value);
375
376/*
377 * Caller holds hw_lock.
378 */
379static void fm93c56a_select(struct ql3_adapter *qdev)
380{
381 struct ql3xxx_port_registers __iomem *port_regs =
382 qdev->mem_map_registers;
383 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
384
385 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
386 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
387 ql_write_nvram_reg(qdev, spir,
388 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
389}
390
391/*
392 * Caller holds hw_lock.
393 */
394static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
395{
396 int i;
397 u32 mask;
398 u32 dataBit;
399 u32 previousBit;
400 struct ql3xxx_port_registers __iomem *port_regs =
401 qdev->mem_map_registers;
402 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
403
404 /* Clock in a zero, then do the start bit */
405 ql_write_nvram_reg(qdev, spir,
406 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
407 AUBURN_EEPROM_DO_1));
408 ql_write_nvram_reg(qdev, spir,
409 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
410 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE));
411 ql_write_nvram_reg(qdev, spir,
412 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
413 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL));
414
415 mask = 1 << (FM93C56A_CMD_BITS - 1);
416 /* Force the previous data bit to be different */
417 previousBit = 0xffff;
418 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
419 dataBit = (cmd & mask)
420 ? AUBURN_EEPROM_DO_1
421 : AUBURN_EEPROM_DO_0;
422 if (previousBit != dataBit) {
423 /* If the bit changed, change the DO state to match */
424 ql_write_nvram_reg(qdev, spir,
425 (ISP_NVRAM_MASK |
426 qdev->eeprom_cmd_data | dataBit));
427 previousBit = dataBit;
428 }
429 ql_write_nvram_reg(qdev, spir,
430 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
431 dataBit | AUBURN_EEPROM_CLK_RISE));
432 ql_write_nvram_reg(qdev, spir,
433 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
434 dataBit | AUBURN_EEPROM_CLK_FALL));
435 cmd = cmd << 1;
436 }
437
438 mask = 1 << (addrBits - 1);
439 /* Force the previous data bit to be different */
440 previousBit = 0xffff;
441 for (i = 0; i < addrBits; i++) {
442 dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1
443 : AUBURN_EEPROM_DO_0;
444 if (previousBit != dataBit) {
445 /*
446 * If the bit changed, then change the DO state to
447 * match
448 */
449 ql_write_nvram_reg(qdev, spir,
450 (ISP_NVRAM_MASK |
451 qdev->eeprom_cmd_data | dataBit));
452 previousBit = dataBit;
453 }
454 ql_write_nvram_reg(qdev, spir,
455 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
456 dataBit | AUBURN_EEPROM_CLK_RISE));
457 ql_write_nvram_reg(qdev, spir,
458 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
459 dataBit | AUBURN_EEPROM_CLK_FALL));
460 eepromAddr = eepromAddr << 1;
461 }
462}
463
464/*
465 * Caller holds hw_lock.
466 */
467static void fm93c56a_deselect(struct ql3_adapter *qdev)
468{
469 struct ql3xxx_port_registers __iomem *port_regs =
470 qdev->mem_map_registers;
471 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
472
473 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
474 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
475}
476
477/*
478 * Caller holds hw_lock.
479 */
480static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
481{
482 int i;
483 u32 data = 0;
484 u32 dataBit;
485 struct ql3xxx_port_registers __iomem *port_regs =
486 qdev->mem_map_registers;
487 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
488
489 /* Read the data bits */
490 /* The first bit is a dummy. Clock right over it. */
491 for (i = 0; i < dataBits; i++) {
492 ql_write_nvram_reg(qdev, spir,
493 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
494 AUBURN_EEPROM_CLK_RISE);
495 ql_write_nvram_reg(qdev, spir,
496 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
497 AUBURN_EEPROM_CLK_FALL);
498 dataBit = (ql_read_common_reg(qdev, spir) &
499 AUBURN_EEPROM_DI_1) ? 1 : 0;
500 data = (data << 1) | dataBit;
501 }
502 *value = (u16)data;
503}
504
505/*
506 * Caller holds hw_lock.
507 */
508static void eeprom_readword(struct ql3_adapter *qdev,
509 u32 eepromAddr, unsigned short *value)
510{
511 fm93c56a_select(qdev);
512 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
513 fm93c56a_datain(qdev, value);
514 fm93c56a_deselect(qdev);
515}
516
517static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
518{
519 __le16 *p = (__le16 *)ndev->dev_addr;
520 p[0] = cpu_to_le16(addr[0]);
521 p[1] = cpu_to_le16(addr[1]);
522 p[2] = cpu_to_le16(addr[2]);
523}
524
525static int ql_get_nvram_params(struct ql3_adapter *qdev)
526{
527 u16 *pEEPROMData;
528 u16 checksum = 0;
529 u32 index;
530 unsigned long hw_flags;
531
532 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
533
534 pEEPROMData = (u16 *)&qdev->nvram_data;
535 qdev->eeprom_cmd_data = 0;
536 if (ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
537 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
538 2) << 10)) {
539 pr_err("%s: Failed ql_sem_spinlock()\n", __func__);
540 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
541 return -1;
542 }
543
544 for (index = 0; index < EEPROM_SIZE; index++) {
545 eeprom_readword(qdev, index, pEEPROMData);
546 checksum += *pEEPROMData;
547 pEEPROMData++;
548 }
549 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
550
551 if (checksum != 0) {
552 netdev_err(qdev->ndev, "checksum should be zero, is %x!!\n",
553 checksum);
554 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
555 return -1;
556 }
557
558 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
559 return checksum;
560}
561
562static const u32 PHYAddr[2] = {
563 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
564};
565
566static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
567{
568 struct ql3xxx_port_registers __iomem *port_regs =
569 qdev->mem_map_registers;
570 u32 temp;
571 int count = 1000;
572
573 while (count) {
574 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
575 if (!(temp & MAC_MII_STATUS_BSY))
576 return 0;
577 udelay(10);
578 count--;
579 }
580 return -1;
581}
582
583static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
584{
585 struct ql3xxx_port_registers __iomem *port_regs =
586 qdev->mem_map_registers;
587 u32 scanControl;
588
589 if (qdev->numPorts > 1) {
590 /* Auto scan will cycle through multiple ports */
591 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
592 } else {
593 scanControl = MAC_MII_CONTROL_SC;
594 }
595
596 /*
597 * Scan register 1 of PHY/PETBI,
598 * Set up to scan both devices
599 * The autoscan starts from the first register, completes
600 * the last one before rolling over to the first
601 */
602 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
603 PHYAddr[0] | MII_SCAN_REGISTER);
604
605 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
606 (scanControl) |
607 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
608}
609
610static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
611{
612 u8 ret;
613 struct ql3xxx_port_registers __iomem *port_regs =
614 qdev->mem_map_registers;
615
616 /* See if scan mode is enabled before we turn it off */
617 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
618 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
619 /* Scan is enabled */
620 ret = 1;
621 } else {
622 /* Scan is disabled */
623 ret = 0;
624 }
625
626 /*
627 * When disabling scan mode you must first change the MII register
628 * address
629 */
630 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
631 PHYAddr[0] | MII_SCAN_REGISTER);
632
633 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
634 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
635 MAC_MII_CONTROL_RC) << 16));
636
637 return ret;
638}
639
640static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
641 u16 regAddr, u16 value, u32 phyAddr)
642{
643 struct ql3xxx_port_registers __iomem *port_regs =
644 qdev->mem_map_registers;
645 u8 scanWasEnabled;
646
647 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
648
649 if (ql_wait_for_mii_ready(qdev)) {
650 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
651 return -1;
652 }
653
654 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
655 phyAddr | regAddr);
656
657 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
658
659 /* Wait for write to complete 9/10/04 SJP */
660 if (ql_wait_for_mii_ready(qdev)) {
661 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
662 return -1;
663 }
664
665 if (scanWasEnabled)
666 ql_mii_enable_scan_mode(qdev);
667
668 return 0;
669}
670
671static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
672 u16 *value, u32 phyAddr)
673{
674 struct ql3xxx_port_registers __iomem *port_regs =
675 qdev->mem_map_registers;
676 u8 scanWasEnabled;
677 u32 temp;
678
679 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
680
681 if (ql_wait_for_mii_ready(qdev)) {
682 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
683 return -1;
684 }
685
686 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
687 phyAddr | regAddr);
688
689 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
690 (MAC_MII_CONTROL_RC << 16));
691
692 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
693 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
694
695 /* Wait for the read to complete */
696 if (ql_wait_for_mii_ready(qdev)) {
697 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
698 return -1;
699 }
700
701 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
702 *value = (u16) temp;
703
704 if (scanWasEnabled)
705 ql_mii_enable_scan_mode(qdev);
706
707 return 0;
708}
709
710static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
711{
712 struct ql3xxx_port_registers __iomem *port_regs =
713 qdev->mem_map_registers;
714
715 ql_mii_disable_scan_mode(qdev);
716
717 if (ql_wait_for_mii_ready(qdev)) {
718 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
719 return -1;
720 }
721
722 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
723 qdev->PHYAddr | regAddr);
724
725 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
726
727 /* Wait for write to complete. */
728 if (ql_wait_for_mii_ready(qdev)) {
729 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
730 return -1;
731 }
732
733 ql_mii_enable_scan_mode(qdev);
734
735 return 0;
736}
737
738static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
739{
740 u32 temp;
741 struct ql3xxx_port_registers __iomem *port_regs =
742 qdev->mem_map_registers;
743
744 ql_mii_disable_scan_mode(qdev);
745
746 if (ql_wait_for_mii_ready(qdev)) {
747 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
748 return -1;
749 }
750
751 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
752 qdev->PHYAddr | regAddr);
753
754 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
755 (MAC_MII_CONTROL_RC << 16));
756
757 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
758 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
759
760 /* Wait for the read to complete */
761 if (ql_wait_for_mii_ready(qdev)) {
762 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
763 return -1;
764 }
765
766 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
767 *value = (u16) temp;
768
769 ql_mii_enable_scan_mode(qdev);
770
771 return 0;
772}
773
774static void ql_petbi_reset(struct ql3_adapter *qdev)
775{
776 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
777}
778
779static void ql_petbi_start_neg(struct ql3_adapter *qdev)
780{
781 u16 reg;
782
783 /* Enable Auto-negotiation sense */
784 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, ®);
785 reg |= PETBI_TBI_AUTO_SENSE;
786 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
787
788 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
789 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
790
791 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
792 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
793 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
794
795}
796
797static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
798{
799 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
800 PHYAddr[qdev->mac_index]);
801}
802
803static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
804{
805 u16 reg;
806
807 /* Enable Auto-negotiation sense */
808 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®,
809 PHYAddr[qdev->mac_index]);
810 reg |= PETBI_TBI_AUTO_SENSE;
811 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
812 PHYAddr[qdev->mac_index]);
813
814 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
815 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
816 PHYAddr[qdev->mac_index]);
817
818 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
819 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
820 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
821 PHYAddr[qdev->mac_index]);
822}
823
824static void ql_petbi_init(struct ql3_adapter *qdev)
825{
826 ql_petbi_reset(qdev);
827 ql_petbi_start_neg(qdev);
828}
829
830static void ql_petbi_init_ex(struct ql3_adapter *qdev)
831{
832 ql_petbi_reset_ex(qdev);
833 ql_petbi_start_neg_ex(qdev);
834}
835
836static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
837{
838 u16 reg;
839
840 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, ®) < 0)
841 return 0;
842
843 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
844}
845
846static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
847{
848 netdev_info(qdev->ndev, "enabling Agere specific PHY\n");
849 /* power down device bit 11 = 1 */
850 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
851 /* enable diagnostic mode bit 2 = 1 */
852 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
853 /* 1000MB amplitude adjust (see Agere errata) */
854 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
855 /* 1000MB amplitude adjust (see Agere errata) */
856 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
857 /* 100MB amplitude adjust (see Agere errata) */
858 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
859 /* 100MB amplitude adjust (see Agere errata) */
860 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
861 /* 10MB amplitude adjust (see Agere errata) */
862 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
863 /* 10MB amplitude adjust (see Agere errata) */
864 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
865 /* point to hidden reg 0x2806 */
866 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
867 /* Write new PHYAD w/bit 5 set */
868 ql_mii_write_reg_ex(qdev, 0x11,
869 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
870 /*
871 * Disable diagnostic mode bit 2 = 0
872 * Power up device bit 11 = 0
873 * Link up (on) and activity (blink)
874 */
875 ql_mii_write_reg(qdev, 0x12, 0x840a);
876 ql_mii_write_reg(qdev, 0x00, 0x1140);
877 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
878}
879
880static enum PHY_DEVICE_TYPE getPhyType(struct ql3_adapter *qdev,
881 u16 phyIdReg0, u16 phyIdReg1)
882{
883 enum PHY_DEVICE_TYPE result = PHY_TYPE_UNKNOWN;
884 u32 oui;
885 u16 model;
886 int i;
887
888 if (phyIdReg0 == 0xffff)
889 return result;
890
891 if (phyIdReg1 == 0xffff)
892 return result;
893
894 /* oui is split between two registers */
895 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
896
897 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
898
899 /* Scan table for this PHY */
900 for (i = 0; i < MAX_PHY_DEV_TYPES; i++) {
901 if ((oui == PHY_DEVICES[i].phyIdOUI) &&
902 (model == PHY_DEVICES[i].phyIdModel)) {
903 netdev_info(qdev->ndev, "Phy: %s\n",
904 PHY_DEVICES[i].name);
905 result = PHY_DEVICES[i].phyDevice;
906 break;
907 }
908 }
909
910 return result;
911}
912
913static int ql_phy_get_speed(struct ql3_adapter *qdev)
914{
915 u16 reg;
916
917 switch (qdev->phyType) {
918 case PHY_AGERE_ET1011C: {
919 if (ql_mii_read_reg(qdev, 0x1A, ®) < 0)
920 return 0;
921
922 reg = (reg >> 8) & 3;
923 break;
924 }
925 default:
926 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
927 return 0;
928
929 reg = (((reg & 0x18) >> 3) & 3);
930 }
931
932 switch (reg) {
933 case 2:
934 return SPEED_1000;
935 case 1:
936 return SPEED_100;
937 case 0:
938 return SPEED_10;
939 default:
940 return -1;
941 }
942}
943
944static int ql_is_full_dup(struct ql3_adapter *qdev)
945{
946 u16 reg;
947
948 switch (qdev->phyType) {
949 case PHY_AGERE_ET1011C: {
950 if (ql_mii_read_reg(qdev, 0x1A, ®))
951 return 0;
952
953 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
954 }
955 case PHY_VITESSE_VSC8211:
956 default: {
957 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0)
958 return 0;
959 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
960 }
961 }
962}
963
964static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
965{
966 u16 reg;
967
968 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, ®) < 0)
969 return 0;
970
971 return (reg & PHY_NEG_PAUSE) != 0;
972}
973
974static int PHY_Setup(struct ql3_adapter *qdev)
975{
976 u16 reg1;
977 u16 reg2;
978 bool agereAddrChangeNeeded = false;
979 u32 miiAddr = 0;
980 int err;
981
982 /* Determine the PHY we are using by reading the ID's */
983 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, ®1);
984 if (err != 0) {
985 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_0_REG\n");
986 return err;
987 }
988
989 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, ®2);
990 if (err != 0) {
991 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG\n");
992 return err;
993 }
994
995 /* Check if we have a Agere PHY */
996 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
997
998 /* Determine which MII address we should be using
999 determined by the index of the card */
1000 if (qdev->mac_index == 0)
1001 miiAddr = MII_AGERE_ADDR_1;
1002 else
1003 miiAddr = MII_AGERE_ADDR_2;
1004
1005 err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, ®1, miiAddr);
1006 if (err != 0) {
1007 netdev_err(qdev->ndev,
1008 "Could not read from reg PHY_ID_0_REG after Agere detected\n");
1009 return err;
1010 }
1011
1012 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, ®2, miiAddr);
1013 if (err != 0) {
1014 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG after Agere detected\n");
1015 return err;
1016 }
1017
1018 /* We need to remember to initialize the Agere PHY */
1019 agereAddrChangeNeeded = true;
1020 }
1021
1022 /* Determine the particular PHY we have on board to apply
1023 PHY specific initializations */
1024 qdev->phyType = getPhyType(qdev, reg1, reg2);
1025
1026 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1027 /* need this here so address gets changed */
1028 phyAgereSpecificInit(qdev, miiAddr);
1029 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
1030 netdev_err(qdev->ndev, "PHY is unknown\n");
1031 return -EIO;
1032 }
1033
1034 return 0;
1035}
1036
1037/*
1038 * Caller holds hw_lock.
1039 */
1040static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1041{
1042 struct ql3xxx_port_registers __iomem *port_regs =
1043 qdev->mem_map_registers;
1044 u32 value;
1045
1046 if (enable)
1047 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1048 else
1049 value = (MAC_CONFIG_REG_PE << 16);
1050
1051 if (qdev->mac_index)
1052 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1053 else
1054 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1055}
1056
1057/*
1058 * Caller holds hw_lock.
1059 */
1060static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1061{
1062 struct ql3xxx_port_registers __iomem *port_regs =
1063 qdev->mem_map_registers;
1064 u32 value;
1065
1066 if (enable)
1067 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1068 else
1069 value = (MAC_CONFIG_REG_SR << 16);
1070
1071 if (qdev->mac_index)
1072 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1073 else
1074 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1075}
1076
1077/*
1078 * Caller holds hw_lock.
1079 */
1080static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1081{
1082 struct ql3xxx_port_registers __iomem *port_regs =
1083 qdev->mem_map_registers;
1084 u32 value;
1085
1086 if (enable)
1087 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1088 else
1089 value = (MAC_CONFIG_REG_GM << 16);
1090
1091 if (qdev->mac_index)
1092 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1093 else
1094 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1095}
1096
1097/*
1098 * Caller holds hw_lock.
1099 */
1100static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1101{
1102 struct ql3xxx_port_registers __iomem *port_regs =
1103 qdev->mem_map_registers;
1104 u32 value;
1105
1106 if (enable)
1107 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1108 else
1109 value = (MAC_CONFIG_REG_FD << 16);
1110
1111 if (qdev->mac_index)
1112 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1113 else
1114 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1115}
1116
1117/*
1118 * Caller holds hw_lock.
1119 */
1120static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1121{
1122 struct ql3xxx_port_registers __iomem *port_regs =
1123 qdev->mem_map_registers;
1124 u32 value;
1125
1126 if (enable)
1127 value =
1128 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1129 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1130 else
1131 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1132
1133 if (qdev->mac_index)
1134 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1135 else
1136 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1137}
1138
1139/*
1140 * Caller holds hw_lock.
1141 */
1142static int ql_is_fiber(struct ql3_adapter *qdev)
1143{
1144 struct ql3xxx_port_registers __iomem *port_regs =
1145 qdev->mem_map_registers;
1146 u32 bitToCheck = 0;
1147 u32 temp;
1148
1149 switch (qdev->mac_index) {
1150 case 0:
1151 bitToCheck = PORT_STATUS_SM0;
1152 break;
1153 case 1:
1154 bitToCheck = PORT_STATUS_SM1;
1155 break;
1156 }
1157
1158 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1159 return (temp & bitToCheck) != 0;
1160}
1161
1162static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1163{
1164 u16 reg;
1165 ql_mii_read_reg(qdev, 0x00, ®);
1166 return (reg & 0x1000) != 0;
1167}
1168
1169/*
1170 * Caller holds hw_lock.
1171 */
1172static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1173{
1174 struct ql3xxx_port_registers __iomem *port_regs =
1175 qdev->mem_map_registers;
1176 u32 bitToCheck = 0;
1177 u32 temp;
1178
1179 switch (qdev->mac_index) {
1180 case 0:
1181 bitToCheck = PORT_STATUS_AC0;
1182 break;
1183 case 1:
1184 bitToCheck = PORT_STATUS_AC1;
1185 break;
1186 }
1187
1188 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1189 if (temp & bitToCheck) {
1190 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate complete\n");
1191 return 1;
1192 }
1193 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate incomplete\n");
1194 return 0;
1195}
1196
1197/*
1198 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1199 */
1200static int ql_is_neg_pause(struct ql3_adapter *qdev)
1201{
1202 if (ql_is_fiber(qdev))
1203 return ql_is_petbi_neg_pause(qdev);
1204 else
1205 return ql_is_phy_neg_pause(qdev);
1206}
1207
1208static int ql_auto_neg_error(struct ql3_adapter *qdev)
1209{
1210 struct ql3xxx_port_registers __iomem *port_regs =
1211 qdev->mem_map_registers;
1212 u32 bitToCheck = 0;
1213 u32 temp;
1214
1215 switch (qdev->mac_index) {
1216 case 0:
1217 bitToCheck = PORT_STATUS_AE0;
1218 break;
1219 case 1:
1220 bitToCheck = PORT_STATUS_AE1;
1221 break;
1222 }
1223 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1224 return (temp & bitToCheck) != 0;
1225}
1226
1227static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1228{
1229 if (ql_is_fiber(qdev))
1230 return SPEED_1000;
1231 else
1232 return ql_phy_get_speed(qdev);
1233}
1234
1235static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1236{
1237 if (ql_is_fiber(qdev))
1238 return 1;
1239 else
1240 return ql_is_full_dup(qdev);
1241}
1242
1243/*
1244 * Caller holds hw_lock.
1245 */
1246static int ql_link_down_detect(struct ql3_adapter *qdev)
1247{
1248 struct ql3xxx_port_registers __iomem *port_regs =
1249 qdev->mem_map_registers;
1250 u32 bitToCheck = 0;
1251 u32 temp;
1252
1253 switch (qdev->mac_index) {
1254 case 0:
1255 bitToCheck = ISP_CONTROL_LINK_DN_0;
1256 break;
1257 case 1:
1258 bitToCheck = ISP_CONTROL_LINK_DN_1;
1259 break;
1260 }
1261
1262 temp =
1263 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1264 return (temp & bitToCheck) != 0;
1265}
1266
1267/*
1268 * Caller holds hw_lock.
1269 */
1270static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1271{
1272 struct ql3xxx_port_registers __iomem *port_regs =
1273 qdev->mem_map_registers;
1274
1275 switch (qdev->mac_index) {
1276 case 0:
1277 ql_write_common_reg(qdev,
1278 &port_regs->CommonRegs.ispControlStatus,
1279 (ISP_CONTROL_LINK_DN_0) |
1280 (ISP_CONTROL_LINK_DN_0 << 16));
1281 break;
1282
1283 case 1:
1284 ql_write_common_reg(qdev,
1285 &port_regs->CommonRegs.ispControlStatus,
1286 (ISP_CONTROL_LINK_DN_1) |
1287 (ISP_CONTROL_LINK_DN_1 << 16));
1288 break;
1289
1290 default:
1291 return 1;
1292 }
1293
1294 return 0;
1295}
1296
1297/*
1298 * Caller holds hw_lock.
1299 */
1300static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
1301{
1302 struct ql3xxx_port_registers __iomem *port_regs =
1303 qdev->mem_map_registers;
1304 u32 bitToCheck = 0;
1305 u32 temp;
1306
1307 switch (qdev->mac_index) {
1308 case 0:
1309 bitToCheck = PORT_STATUS_F1_ENABLED;
1310 break;
1311 case 1:
1312 bitToCheck = PORT_STATUS_F3_ENABLED;
1313 break;
1314 default:
1315 break;
1316 }
1317
1318 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1319 if (temp & bitToCheck) {
1320 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1321 "not link master\n");
1322 return 0;
1323 }
1324
1325 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, "link master\n");
1326 return 1;
1327}
1328
1329static void ql_phy_reset_ex(struct ql3_adapter *qdev)
1330{
1331 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
1332 PHYAddr[qdev->mac_index]);
1333}
1334
1335static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
1336{
1337 u16 reg;
1338 u16 portConfiguration;
1339
1340 if (qdev->phyType == PHY_AGERE_ET1011C)
1341 ql_mii_write_reg(qdev, 0x13, 0x0000);
1342 /* turn off external loopback */
1343
1344 if (qdev->mac_index == 0)
1345 portConfiguration =
1346 qdev->nvram_data.macCfg_port0.portConfiguration;
1347 else
1348 portConfiguration =
1349 qdev->nvram_data.macCfg_port1.portConfiguration;
1350
1351 /* Some HBA's in the field are set to 0 and they need to
1352 be reinterpreted with a default value */
1353 if (portConfiguration == 0)
1354 portConfiguration = PORT_CONFIG_DEFAULT;
1355
1356 /* Set the 1000 advertisements */
1357 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, ®,
1358 PHYAddr[qdev->mac_index]);
1359 reg &= ~PHY_GIG_ALL_PARAMS;
1360
1361 if (portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1362 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
1363 reg |= PHY_GIG_ADV_1000F;
1364 else
1365 reg |= PHY_GIG_ADV_1000H;
1366 }
1367
1368 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
1369 PHYAddr[qdev->mac_index]);
1370
1371 /* Set the 10/100 & pause negotiation advertisements */
1372 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, ®,
1373 PHYAddr[qdev->mac_index]);
1374 reg &= ~PHY_NEG_ALL_PARAMS;
1375
1376 if (portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
1377 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1378
1379 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1380 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1381 reg |= PHY_NEG_ADV_100F;
1382
1383 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1384 reg |= PHY_NEG_ADV_10F;
1385 }
1386
1387 if (portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1388 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
1389 reg |= PHY_NEG_ADV_100H;
1390
1391 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
1392 reg |= PHY_NEG_ADV_10H;
1393 }
1394
1395 if (portConfiguration & PORT_CONFIG_1000MB_SPEED)
1396 reg |= 1;
1397
1398 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
1399 PHYAddr[qdev->mac_index]);
1400
1401 ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]);
1402
1403 ql_mii_write_reg_ex(qdev, CONTROL_REG,
1404 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1405 PHYAddr[qdev->mac_index]);
1406}
1407
1408static void ql_phy_init_ex(struct ql3_adapter *qdev)
1409{
1410 ql_phy_reset_ex(qdev);
1411 PHY_Setup(qdev);
1412 ql_phy_start_neg_ex(qdev);
1413}
1414
1415/*
1416 * Caller holds hw_lock.
1417 */
1418static u32 ql_get_link_state(struct ql3_adapter *qdev)
1419{
1420 struct ql3xxx_port_registers __iomem *port_regs =
1421 qdev->mem_map_registers;
1422 u32 bitToCheck = 0;
1423 u32 temp, linkState;
1424
1425 switch (qdev->mac_index) {
1426 case 0:
1427 bitToCheck = PORT_STATUS_UP0;
1428 break;
1429 case 1:
1430 bitToCheck = PORT_STATUS_UP1;
1431 break;
1432 }
1433
1434 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1435 if (temp & bitToCheck)
1436 linkState = LS_UP;
1437 else
1438 linkState = LS_DOWN;
1439
1440 return linkState;
1441}
1442
1443static int ql_port_start(struct ql3_adapter *qdev)
1444{
1445 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1446 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1447 2) << 7)) {
1448 netdev_err(qdev->ndev, "Could not get hw lock for GIO\n");
1449 return -1;
1450 }
1451
1452 if (ql_is_fiber(qdev)) {
1453 ql_petbi_init(qdev);
1454 } else {
1455 /* Copper port */
1456 ql_phy_init_ex(qdev);
1457 }
1458
1459 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1460 return 0;
1461}
1462
1463static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1464{
1465
1466 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1467 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1468 2) << 7))
1469 return -1;
1470
1471 if (!ql_auto_neg_error(qdev)) {
1472 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1473 /* configure the MAC */
1474 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1475 "Configuring link\n");
1476 ql_mac_cfg_soft_reset(qdev, 1);
1477 ql_mac_cfg_gig(qdev,
1478 (ql_get_link_speed
1479 (qdev) ==
1480 SPEED_1000));
1481 ql_mac_cfg_full_dup(qdev,
1482 ql_is_link_full_dup
1483 (qdev));
1484 ql_mac_cfg_pause(qdev,
1485 ql_is_neg_pause
1486 (qdev));
1487 ql_mac_cfg_soft_reset(qdev, 0);
1488
1489 /* enable the MAC */
1490 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1491 "Enabling mac\n");
1492 ql_mac_enable(qdev, 1);
1493 }
1494
1495 qdev->port_link_state = LS_UP;
1496 netif_start_queue(qdev->ndev);
1497 netif_carrier_on(qdev->ndev);
1498 netif_info(qdev, link, qdev->ndev,
1499 "Link is up at %d Mbps, %s duplex\n",
1500 ql_get_link_speed(qdev),
1501 ql_is_link_full_dup(qdev) ? "full" : "half");
1502
1503 } else { /* Remote error detected */
1504
1505 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
1506 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1507 "Remote error detected. Calling ql_port_start()\n");
1508 /*
1509 * ql_port_start() is shared code and needs
1510 * to lock the PHY on it's own.
1511 */
1512 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1513 if (ql_port_start(qdev)) /* Restart port */
1514 return -1;
1515 return 0;
1516 }
1517 }
1518 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1519 return 0;
1520}
1521
1522static void ql_link_state_machine_work(struct work_struct *work)
1523{
1524 struct ql3_adapter *qdev =
1525 container_of(work, struct ql3_adapter, link_state_work.work);
1526
1527 u32 curr_link_state;
1528 unsigned long hw_flags;
1529
1530 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1531
1532 curr_link_state = ql_get_link_state(qdev);
1533
1534 if (test_bit(QL_RESET_ACTIVE, &qdev->flags)) {
1535 netif_info(qdev, link, qdev->ndev,
1536 "Reset in progress, skip processing link state\n");
1537
1538 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1539
1540 /* Restart timer on 2 second interval. */
1541 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1542
1543 return;
1544 }
1545
1546 switch (qdev->port_link_state) {
1547 default:
1548 if (test_bit(QL_LINK_MASTER, &qdev->flags))
1549 ql_port_start(qdev);
1550 qdev->port_link_state = LS_DOWN;
1551 /* Fall Through */
1552
1553 case LS_DOWN:
1554 if (curr_link_state == LS_UP) {
1555 netif_info(qdev, link, qdev->ndev, "Link is up\n");
1556 if (ql_is_auto_neg_complete(qdev))
1557 ql_finish_auto_neg(qdev);
1558
1559 if (qdev->port_link_state == LS_UP)
1560 ql_link_down_detect_clear(qdev);
1561
1562 qdev->port_link_state = LS_UP;
1563 }
1564 break;
1565
1566 case LS_UP:
1567 /*
1568 * See if the link is currently down or went down and came
1569 * back up
1570 */
1571 if (curr_link_state == LS_DOWN) {
1572 netif_info(qdev, link, qdev->ndev, "Link is down\n");
1573 qdev->port_link_state = LS_DOWN;
1574 }
1575 if (ql_link_down_detect(qdev))
1576 qdev->port_link_state = LS_DOWN;
1577 break;
1578 }
1579 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1580
1581 /* Restart timer on 2 second interval. */
1582 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
1583}
1584
1585/*
1586 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1587 */
1588static void ql_get_phy_owner(struct ql3_adapter *qdev)
1589{
1590 if (ql_this_adapter_controls_port(qdev))
1591 set_bit(QL_LINK_MASTER, &qdev->flags);
1592 else
1593 clear_bit(QL_LINK_MASTER, &qdev->flags);
1594}
1595
1596/*
1597 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1598 */
1599static void ql_init_scan_mode(struct ql3_adapter *qdev)
1600{
1601 ql_mii_enable_scan_mode(qdev);
1602
1603 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1604 if (ql_this_adapter_controls_port(qdev))
1605 ql_petbi_init_ex(qdev);
1606 } else {
1607 if (ql_this_adapter_controls_port(qdev))
1608 ql_phy_init_ex(qdev);
1609 }
1610}
1611
1612/*
1613 * MII_Setup needs to be called before taking the PHY out of reset
1614 * so that the management interface clock speed can be set properly.
1615 * It would be better if we had a way to disable MDC until after the
1616 * PHY is out of reset, but we don't have that capability.
1617 */
1618static int ql_mii_setup(struct ql3_adapter *qdev)
1619{
1620 u32 reg;
1621 struct ql3xxx_port_registers __iomem *port_regs =
1622 qdev->mem_map_registers;
1623
1624 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1625 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1626 2) << 7))
1627 return -1;
1628
1629 if (qdev->device_id == QL3032_DEVICE_ID)
1630 ql_write_page0_reg(qdev,
1631 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1632
1633 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1634 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1635
1636 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1637 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1638
1639 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1640 return 0;
1641}
1642
1643#define SUPPORTED_OPTICAL_MODES (SUPPORTED_1000baseT_Full | \
1644 SUPPORTED_FIBRE | \
1645 SUPPORTED_Autoneg)
1646#define SUPPORTED_TP_MODES (SUPPORTED_10baseT_Half | \
1647 SUPPORTED_10baseT_Full | \
1648 SUPPORTED_100baseT_Half | \
1649 SUPPORTED_100baseT_Full | \
1650 SUPPORTED_1000baseT_Half | \
1651 SUPPORTED_1000baseT_Full | \
1652 SUPPORTED_Autoneg | \
1653 SUPPORTED_TP) \
1654
1655static u32 ql_supported_modes(struct ql3_adapter *qdev)
1656{
1657 if (test_bit(QL_LINK_OPTICAL, &qdev->flags))
1658 return SUPPORTED_OPTICAL_MODES;
1659
1660 return SUPPORTED_TP_MODES;
1661}
1662
1663static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1664{
1665 int status;
1666 unsigned long hw_flags;
1667 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1668 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1669 (QL_RESOURCE_BITS_BASE_CODE |
1670 (qdev->mac_index) * 2) << 7)) {
1671 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1672 return 0;
1673 }
1674 status = ql_is_auto_cfg(qdev);
1675 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1676 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1677 return status;
1678}
1679
1680static u32 ql_get_speed(struct ql3_adapter *qdev)
1681{
1682 u32 status;
1683 unsigned long hw_flags;
1684 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1685 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1686 (QL_RESOURCE_BITS_BASE_CODE |
1687 (qdev->mac_index) * 2) << 7)) {
1688 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1689 return 0;
1690 }
1691 status = ql_get_link_speed(qdev);
1692 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1693 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1694 return status;
1695}
1696
1697static int ql_get_full_dup(struct ql3_adapter *qdev)
1698{
1699 int status;
1700 unsigned long hw_flags;
1701 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1702 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1703 (QL_RESOURCE_BITS_BASE_CODE |
1704 (qdev->mac_index) * 2) << 7)) {
1705 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1706 return 0;
1707 }
1708 status = ql_is_link_full_dup(qdev);
1709 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1710 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1711 return status;
1712}
1713
1714static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1715{
1716 struct ql3_adapter *qdev = netdev_priv(ndev);
1717
1718 ecmd->transceiver = XCVR_INTERNAL;
1719 ecmd->supported = ql_supported_modes(qdev);
1720
1721 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
1722 ecmd->port = PORT_FIBRE;
1723 } else {
1724 ecmd->port = PORT_TP;
1725 ecmd->phy_address = qdev->PHYAddr;
1726 }
1727 ecmd->advertising = ql_supported_modes(qdev);
1728 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1729 ethtool_cmd_speed_set(ecmd, ql_get_speed(qdev));
1730 ecmd->duplex = ql_get_full_dup(qdev);
1731 return 0;
1732}
1733
1734static void ql_get_drvinfo(struct net_device *ndev,
1735 struct ethtool_drvinfo *drvinfo)
1736{
1737 struct ql3_adapter *qdev = netdev_priv(ndev);
1738 strlcpy(drvinfo->driver, ql3xxx_driver_name, sizeof(drvinfo->driver));
1739 strlcpy(drvinfo->version, ql3xxx_driver_version,
1740 sizeof(drvinfo->version));
1741 strlcpy(drvinfo->bus_info, pci_name(qdev->pdev),
1742 sizeof(drvinfo->bus_info));
1743 drvinfo->regdump_len = 0;
1744 drvinfo->eedump_len = 0;
1745}
1746
1747static u32 ql_get_msglevel(struct net_device *ndev)
1748{
1749 struct ql3_adapter *qdev = netdev_priv(ndev);
1750 return qdev->msg_enable;
1751}
1752
1753static void ql_set_msglevel(struct net_device *ndev, u32 value)
1754{
1755 struct ql3_adapter *qdev = netdev_priv(ndev);
1756 qdev->msg_enable = value;
1757}
1758
1759static void ql_get_pauseparam(struct net_device *ndev,
1760 struct ethtool_pauseparam *pause)
1761{
1762 struct ql3_adapter *qdev = netdev_priv(ndev);
1763 struct ql3xxx_port_registers __iomem *port_regs =
1764 qdev->mem_map_registers;
1765
1766 u32 reg;
1767 if (qdev->mac_index == 0)
1768 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1769 else
1770 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1771
1772 pause->autoneg = ql_get_auto_cfg_status(qdev);
1773 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1774 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1775}
1776
1777static const struct ethtool_ops ql3xxx_ethtool_ops = {
1778 .get_settings = ql_get_settings,
1779 .get_drvinfo = ql_get_drvinfo,
1780 .get_link = ethtool_op_get_link,
1781 .get_msglevel = ql_get_msglevel,
1782 .set_msglevel = ql_set_msglevel,
1783 .get_pauseparam = ql_get_pauseparam,
1784};
1785
1786static int ql_populate_free_queue(struct ql3_adapter *qdev)
1787{
1788 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1789 dma_addr_t map;
1790 int err;
1791
1792 while (lrg_buf_cb) {
1793 if (!lrg_buf_cb->skb) {
1794 lrg_buf_cb->skb =
1795 netdev_alloc_skb(qdev->ndev,
1796 qdev->lrg_buffer_len);
1797 if (unlikely(!lrg_buf_cb->skb)) {
1798 netdev_printk(KERN_DEBUG, qdev->ndev,
1799 "Failed netdev_alloc_skb()\n");
1800 break;
1801 } else {
1802 /*
1803 * We save some space to copy the ethhdr from
1804 * first buffer
1805 */
1806 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1807 map = pci_map_single(qdev->pdev,
1808 lrg_buf_cb->skb->data,
1809 qdev->lrg_buffer_len -
1810 QL_HEADER_SPACE,
1811 PCI_DMA_FROMDEVICE);
1812
1813 err = pci_dma_mapping_error(qdev->pdev, map);
1814 if (err) {
1815 netdev_err(qdev->ndev,
1816 "PCI mapping failed with error: %d\n",
1817 err);
1818 dev_kfree_skb(lrg_buf_cb->skb);
1819 lrg_buf_cb->skb = NULL;
1820 break;
1821 }
1822
1823
1824 lrg_buf_cb->buf_phy_addr_low =
1825 cpu_to_le32(LS_64BITS(map));
1826 lrg_buf_cb->buf_phy_addr_high =
1827 cpu_to_le32(MS_64BITS(map));
1828 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1829 dma_unmap_len_set(lrg_buf_cb, maplen,
1830 qdev->lrg_buffer_len -
1831 QL_HEADER_SPACE);
1832 --qdev->lrg_buf_skb_check;
1833 if (!qdev->lrg_buf_skb_check)
1834 return 1;
1835 }
1836 }
1837 lrg_buf_cb = lrg_buf_cb->next;
1838 }
1839 return 0;
1840}
1841
1842/*
1843 * Caller holds hw_lock.
1844 */
1845static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1846{
1847 struct ql3xxx_port_registers __iomem *port_regs =
1848 qdev->mem_map_registers;
1849
1850 if (qdev->small_buf_release_cnt >= 16) {
1851 while (qdev->small_buf_release_cnt >= 16) {
1852 qdev->small_buf_q_producer_index++;
1853
1854 if (qdev->small_buf_q_producer_index ==
1855 NUM_SBUFQ_ENTRIES)
1856 qdev->small_buf_q_producer_index = 0;
1857 qdev->small_buf_release_cnt -= 8;
1858 }
1859 wmb();
1860 writel(qdev->small_buf_q_producer_index,
1861 &port_regs->CommonRegs.rxSmallQProducerIndex);
1862 }
1863}
1864
1865/*
1866 * Caller holds hw_lock.
1867 */
1868static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1869{
1870 struct bufq_addr_element *lrg_buf_q_ele;
1871 int i;
1872 struct ql_rcv_buf_cb *lrg_buf_cb;
1873 struct ql3xxx_port_registers __iomem *port_regs =
1874 qdev->mem_map_registers;
1875
1876 if ((qdev->lrg_buf_free_count >= 8) &&
1877 (qdev->lrg_buf_release_cnt >= 16)) {
1878
1879 if (qdev->lrg_buf_skb_check)
1880 if (!ql_populate_free_queue(qdev))
1881 return;
1882
1883 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1884
1885 while ((qdev->lrg_buf_release_cnt >= 16) &&
1886 (qdev->lrg_buf_free_count >= 8)) {
1887
1888 for (i = 0; i < 8; i++) {
1889 lrg_buf_cb =
1890 ql_get_from_lrg_buf_free_list(qdev);
1891 lrg_buf_q_ele->addr_high =
1892 lrg_buf_cb->buf_phy_addr_high;
1893 lrg_buf_q_ele->addr_low =
1894 lrg_buf_cb->buf_phy_addr_low;
1895 lrg_buf_q_ele++;
1896
1897 qdev->lrg_buf_release_cnt--;
1898 }
1899
1900 qdev->lrg_buf_q_producer_index++;
1901
1902 if (qdev->lrg_buf_q_producer_index ==
1903 qdev->num_lbufq_entries)
1904 qdev->lrg_buf_q_producer_index = 0;
1905
1906 if (qdev->lrg_buf_q_producer_index ==
1907 (qdev->num_lbufq_entries - 1)) {
1908 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1909 }
1910 }
1911 wmb();
1912 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1913 writel(qdev->lrg_buf_q_producer_index,
1914 &port_regs->CommonRegs.rxLargeQProducerIndex);
1915 }
1916}
1917
1918static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1919 struct ob_mac_iocb_rsp *mac_rsp)
1920{
1921 struct ql_tx_buf_cb *tx_cb;
1922 int i;
1923 int retval = 0;
1924
1925 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1926 netdev_warn(qdev->ndev,
1927 "Frame too short but it was padded and sent\n");
1928 }
1929
1930 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1931
1932 /* Check the transmit response flags for any errors */
1933 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1934 netdev_err(qdev->ndev,
1935 "Frame too short to be legal, frame not sent\n");
1936
1937 qdev->ndev->stats.tx_errors++;
1938 retval = -EIO;
1939 goto frame_not_sent;
1940 }
1941
1942 if (tx_cb->seg_count == 0) {
1943 netdev_err(qdev->ndev, "tx_cb->seg_count == 0: %d\n",
1944 mac_rsp->transaction_id);
1945
1946 qdev->ndev->stats.tx_errors++;
1947 retval = -EIO;
1948 goto invalid_seg_count;
1949 }
1950
1951 pci_unmap_single(qdev->pdev,
1952 dma_unmap_addr(&tx_cb->map[0], mapaddr),
1953 dma_unmap_len(&tx_cb->map[0], maplen),
1954 PCI_DMA_TODEVICE);
1955 tx_cb->seg_count--;
1956 if (tx_cb->seg_count) {
1957 for (i = 1; i < tx_cb->seg_count; i++) {
1958 pci_unmap_page(qdev->pdev,
1959 dma_unmap_addr(&tx_cb->map[i],
1960 mapaddr),
1961 dma_unmap_len(&tx_cb->map[i], maplen),
1962 PCI_DMA_TODEVICE);
1963 }
1964 }
1965 qdev->ndev->stats.tx_packets++;
1966 qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
1967
1968frame_not_sent:
1969 dev_kfree_skb_irq(tx_cb->skb);
1970 tx_cb->skb = NULL;
1971
1972invalid_seg_count:
1973 atomic_inc(&qdev->tx_count);
1974}
1975
1976static void ql_get_sbuf(struct ql3_adapter *qdev)
1977{
1978 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1979 qdev->small_buf_index = 0;
1980 qdev->small_buf_release_cnt++;
1981}
1982
1983static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1984{
1985 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1986 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1987 qdev->lrg_buf_release_cnt++;
1988 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1989 qdev->lrg_buf_index = 0;
1990 return lrg_buf_cb;
1991}
1992
1993/*
1994 * The difference between 3022 and 3032 for inbound completions:
1995 * 3022 uses two buffers per completion. The first buffer contains
1996 * (some) header info, the second the remainder of the headers plus
1997 * the data. For this chip we reserve some space at the top of the
1998 * receive buffer so that the header info in buffer one can be
1999 * prepended to the buffer two. Buffer two is the sent up while
2000 * buffer one is returned to the hardware to be reused.
2001 * 3032 receives all of it's data and headers in one buffer for a
2002 * simpler process. 3032 also supports checksum verification as
2003 * can be seen in ql_process_macip_rx_intr().
2004 */
2005static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2006 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2007{
2008 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2009 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2010 struct sk_buff *skb;
2011 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2012
2013 /*
2014 * Get the inbound address list (small buffer).
2015 */
2016 ql_get_sbuf(qdev);
2017
2018 if (qdev->device_id == QL3022_DEVICE_ID)
2019 lrg_buf_cb1 = ql_get_lbuf(qdev);
2020
2021 /* start of second buffer */
2022 lrg_buf_cb2 = ql_get_lbuf(qdev);
2023 skb = lrg_buf_cb2->skb;
2024
2025 qdev->ndev->stats.rx_packets++;
2026 qdev->ndev->stats.rx_bytes += length;
2027
2028 skb_put(skb, length);
2029 pci_unmap_single(qdev->pdev,
2030 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2031 dma_unmap_len(lrg_buf_cb2, maplen),
2032 PCI_DMA_FROMDEVICE);
2033 prefetch(skb->data);
2034 skb_checksum_none_assert(skb);
2035 skb->protocol = eth_type_trans(skb, qdev->ndev);
2036
2037 netif_receive_skb(skb);
2038 lrg_buf_cb2->skb = NULL;
2039
2040 if (qdev->device_id == QL3022_DEVICE_ID)
2041 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2042 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2043}
2044
2045static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2046 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2047{
2048 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2049 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
2050 struct sk_buff *skb1 = NULL, *skb2;
2051 struct net_device *ndev = qdev->ndev;
2052 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2053 u16 size = 0;
2054
2055 /*
2056 * Get the inbound address list (small buffer).
2057 */
2058
2059 ql_get_sbuf(qdev);
2060
2061 if (qdev->device_id == QL3022_DEVICE_ID) {
2062 /* start of first buffer on 3022 */
2063 lrg_buf_cb1 = ql_get_lbuf(qdev);
2064 skb1 = lrg_buf_cb1->skb;
2065 size = ETH_HLEN;
2066 if (*((u16 *) skb1->data) != 0xFFFF)
2067 size += VLAN_ETH_HLEN - ETH_HLEN;
2068 }
2069
2070 /* start of second buffer */
2071 lrg_buf_cb2 = ql_get_lbuf(qdev);
2072 skb2 = lrg_buf_cb2->skb;
2073
2074 skb_put(skb2, length); /* Just the second buffer length here. */
2075 pci_unmap_single(qdev->pdev,
2076 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2077 dma_unmap_len(lrg_buf_cb2, maplen),
2078 PCI_DMA_FROMDEVICE);
2079 prefetch(skb2->data);
2080
2081 skb_checksum_none_assert(skb2);
2082 if (qdev->device_id == QL3022_DEVICE_ID) {
2083 /*
2084 * Copy the ethhdr from first buffer to second. This
2085 * is necessary for 3022 IP completions.
2086 */
2087 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2088 skb_push(skb2, size), size);
2089 } else {
2090 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
2091 if (checksum &
2092 (IB_IP_IOCB_RSP_3032_ICE |
2093 IB_IP_IOCB_RSP_3032_CE)) {
2094 netdev_err(ndev,
2095 "%s: Bad checksum for this %s packet, checksum = %x\n",
2096 __func__,
2097 ((checksum & IB_IP_IOCB_RSP_3032_TCP) ?
2098 "TCP" : "UDP"), checksum);
2099 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2100 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2101 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
2102 skb2->ip_summed = CHECKSUM_UNNECESSARY;
2103 }
2104 }
2105 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2106
2107 netif_receive_skb(skb2);
2108 ndev->stats.rx_packets++;
2109 ndev->stats.rx_bytes += length;
2110 lrg_buf_cb2->skb = NULL;
2111
2112 if (qdev->device_id == QL3022_DEVICE_ID)
2113 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
2114 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2115}
2116
2117static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2118 int *tx_cleaned, int *rx_cleaned, int work_to_do)
2119{
2120 struct net_rsp_iocb *net_rsp;
2121 struct net_device *ndev = qdev->ndev;
2122 int work_done = 0;
2123
2124 /* While there are entries in the completion queue. */
2125 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
2126 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
2127
2128 net_rsp = qdev->rsp_current;
2129 rmb();
2130 /*
2131 * Fix 4032 chip's undocumented "feature" where bit-8 is set
2132 * if the inbound completion is for a VLAN.
2133 */
2134 if (qdev->device_id == QL3032_DEVICE_ID)
2135 net_rsp->opcode &= 0x7f;
2136 switch (net_rsp->opcode) {
2137
2138 case OPCODE_OB_MAC_IOCB_FN0:
2139 case OPCODE_OB_MAC_IOCB_FN2:
2140 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2141 net_rsp);
2142 (*tx_cleaned)++;
2143 break;
2144
2145 case OPCODE_IB_MAC_IOCB:
2146 case OPCODE_IB_3032_MAC_IOCB:
2147 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2148 net_rsp);
2149 (*rx_cleaned)++;
2150 break;
2151
2152 case OPCODE_IB_IP_IOCB:
2153 case OPCODE_IB_3032_IP_IOCB:
2154 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2155 net_rsp);
2156 (*rx_cleaned)++;
2157 break;
2158 default: {
2159 u32 *tmp = (u32 *)net_rsp;
2160 netdev_err(ndev,
2161 "Hit default case, not handled!\n"
2162 " dropping the packet, opcode = %x\n"
2163 "0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
2164 net_rsp->opcode,
2165 (unsigned long int)tmp[0],
2166 (unsigned long int)tmp[1],
2167 (unsigned long int)tmp[2],
2168 (unsigned long int)tmp[3]);
2169 }
2170 }
2171
2172 qdev->rsp_consumer_index++;
2173
2174 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2175 qdev->rsp_consumer_index = 0;
2176 qdev->rsp_current = qdev->rsp_q_virt_addr;
2177 } else {
2178 qdev->rsp_current++;
2179 }
2180
2181 work_done = *tx_cleaned + *rx_cleaned;
2182 }
2183
2184 return work_done;
2185}
2186
2187static int ql_poll(struct napi_struct *napi, int budget)
2188{
2189 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
2190 int rx_cleaned = 0, tx_cleaned = 0;
2191 unsigned long hw_flags;
2192 struct ql3xxx_port_registers __iomem *port_regs =
2193 qdev->mem_map_registers;
2194
2195 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget);
2196
2197 if (tx_cleaned + rx_cleaned != budget) {
2198 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2199 __napi_complete(napi);
2200 ql_update_small_bufq_prod_index(qdev);
2201 ql_update_lrg_bufq_prod_index(qdev);
2202 writel(qdev->rsp_consumer_index,
2203 &port_regs->CommonRegs.rspQConsumerIndex);
2204 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2205
2206 ql_enable_interrupts(qdev);
2207 }
2208 return tx_cleaned + rx_cleaned;
2209}
2210
2211static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2212{
2213
2214 struct net_device *ndev = dev_id;
2215 struct ql3_adapter *qdev = netdev_priv(ndev);
2216 struct ql3xxx_port_registers __iomem *port_regs =
2217 qdev->mem_map_registers;
2218 u32 value;
2219 int handled = 1;
2220 u32 var;
2221
2222 value = ql_read_common_reg_l(qdev,
2223 &port_regs->CommonRegs.ispControlStatus);
2224
2225 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2226 spin_lock(&qdev->adapter_lock);
2227 netif_stop_queue(qdev->ndev);
2228 netif_carrier_off(qdev->ndev);
2229 ql_disable_interrupts(qdev);
2230 qdev->port_link_state = LS_DOWN;
2231 set_bit(QL_RESET_ACTIVE, &qdev->flags) ;
2232
2233 if (value & ISP_CONTROL_FE) {
2234 /*
2235 * Chip Fatal Error.
2236 */
2237 var =
2238 ql_read_page0_reg_l(qdev,
2239 &port_regs->PortFatalErrStatus);
2240 netdev_warn(ndev,
2241 "Resetting chip. PortFatalErrStatus register = 0x%x\n",
2242 var);
2243 set_bit(QL_RESET_START, &qdev->flags) ;
2244 } else {
2245 /*
2246 * Soft Reset Requested.
2247 */
2248 set_bit(QL_RESET_PER_SCSI, &qdev->flags) ;
2249 netdev_err(ndev,
2250 "Another function issued a reset to the chip. ISR value = %x\n",
2251 value);
2252 }
2253 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2254 spin_unlock(&qdev->adapter_lock);
2255 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2256 ql_disable_interrupts(qdev);
2257 if (likely(napi_schedule_prep(&qdev->napi)))
2258 __napi_schedule(&qdev->napi);
2259 } else
2260 return IRQ_NONE;
2261
2262 return IRQ_RETVAL(handled);
2263}
2264
2265/*
2266 * Get the total number of segments needed for the given number of fragments.
2267 * This is necessary because outbound address lists (OAL) will be used when
2268 * more than two frags are given. Each address list has 5 addr/len pairs.
2269 * The 5th pair in each OAL is used to point to the next OAL if more frags
2270 * are coming. That is why the frags:segment count ratio is not linear.
2271 */
2272static int ql_get_seg_count(struct ql3_adapter *qdev, unsigned short frags)
2273{
2274 if (qdev->device_id == QL3022_DEVICE_ID)
2275 return 1;
2276
2277 if (frags <= 2)
2278 return frags + 1;
2279 else if (frags <= 6)
2280 return frags + 2;
2281 else if (frags <= 10)
2282 return frags + 3;
2283 else if (frags <= 14)
2284 return frags + 4;
2285 else if (frags <= 18)
2286 return frags + 5;
2287 return -1;
2288}
2289
2290static void ql_hw_csum_setup(const struct sk_buff *skb,
2291 struct ob_mac_iocb_req *mac_iocb_ptr)
2292{
2293 const struct iphdr *ip = ip_hdr(skb);
2294
2295 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2296 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2297
2298 if (ip->protocol == IPPROTO_TCP) {
2299 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2300 OB_3032MAC_IOCB_REQ_IC;
2301 } else {
2302 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2303 OB_3032MAC_IOCB_REQ_IC;
2304 }
2305
2306}
2307
2308/*
2309 * Map the buffers for this transmit.
2310 * This will return NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2311 */
2312static int ql_send_map(struct ql3_adapter *qdev,
2313 struct ob_mac_iocb_req *mac_iocb_ptr,
2314 struct ql_tx_buf_cb *tx_cb,
2315 struct sk_buff *skb)
2316{
2317 struct oal *oal;
2318 struct oal_entry *oal_entry;
2319 int len = skb_headlen(skb);
2320 dma_addr_t map;
2321 int err;
2322 int completed_segs, i;
2323 int seg_cnt, seg = 0;
2324 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2325
2326 seg_cnt = tx_cb->seg_count;
2327 /*
2328 * Map the skb buffer first.
2329 */
2330 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2331
2332 err = pci_dma_mapping_error(qdev->pdev, map);
2333 if (err) {
2334 netdev_err(qdev->ndev, "PCI mapping failed with error: %d\n",
2335 err);
2336
2337 return NETDEV_TX_BUSY;
2338 }
2339
2340 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2341 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2342 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2343 oal_entry->len = cpu_to_le32(len);
2344 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2345 dma_unmap_len_set(&tx_cb->map[seg], maplen, len);
2346 seg++;
2347
2348 if (seg_cnt == 1) {
2349 /* Terminate the last segment. */
2350 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2351 return NETDEV_TX_OK;
2352 }
2353 oal = tx_cb->oal;
2354 for (completed_segs = 0;
2355 completed_segs < frag_cnt;
2356 completed_segs++, seg++) {
2357 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2358 oal_entry++;
2359 /*
2360 * Check for continuation requirements.
2361 * It's strange but necessary.
2362 * Continuation entry points to outbound address list.
2363 */
2364 if ((seg == 2 && seg_cnt > 3) ||
2365 (seg == 7 && seg_cnt > 8) ||
2366 (seg == 12 && seg_cnt > 13) ||
2367 (seg == 17 && seg_cnt > 18)) {
2368 map = pci_map_single(qdev->pdev, oal,
2369 sizeof(struct oal),
2370 PCI_DMA_TODEVICE);
2371
2372 err = pci_dma_mapping_error(qdev->pdev, map);
2373 if (err) {
2374 netdev_err(qdev->ndev,
2375 "PCI mapping outbound address list with error: %d\n",
2376 err);
2377 goto map_error;
2378 }
2379
2380 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2381 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2382 oal_entry->len = cpu_to_le32(sizeof(struct oal) |
2383 OAL_CONT_ENTRY);
2384 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2385 dma_unmap_len_set(&tx_cb->map[seg], maplen,
2386 sizeof(struct oal));
2387 oal_entry = (struct oal_entry *)oal;
2388 oal++;
2389 seg++;
2390 }
2391
2392 map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
2393 DMA_TO_DEVICE);
2394
2395 err = dma_mapping_error(&qdev->pdev->dev, map);
2396 if (err) {
2397 netdev_err(qdev->ndev,
2398 "PCI mapping frags failed with error: %d\n",
2399 err);
2400 goto map_error;
2401 }
2402
2403 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2404 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2405 oal_entry->len = cpu_to_le32(skb_frag_size(frag));
2406 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2407 dma_unmap_len_set(&tx_cb->map[seg], maplen, skb_frag_size(frag));
2408 }
2409 /* Terminate the last segment. */
2410 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
2411 return NETDEV_TX_OK;
2412
2413map_error:
2414 /* A PCI mapping failed and now we will need to back out
2415 * We need to traverse through the oal's and associated pages which
2416 * have been mapped and now we must unmap them to clean up properly
2417 */
2418
2419 seg = 1;
2420 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2421 oal = tx_cb->oal;
2422 for (i = 0; i < completed_segs; i++, seg++) {
2423 oal_entry++;
2424
2425 /*
2426 * Check for continuation requirements.
2427 * It's strange but necessary.
2428 */
2429
2430 if ((seg == 2 && seg_cnt > 3) ||
2431 (seg == 7 && seg_cnt > 8) ||
2432 (seg == 12 && seg_cnt > 13) ||
2433 (seg == 17 && seg_cnt > 18)) {
2434 pci_unmap_single(qdev->pdev,
2435 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2436 dma_unmap_len(&tx_cb->map[seg], maplen),
2437 PCI_DMA_TODEVICE);
2438 oal++;
2439 seg++;
2440 }
2441
2442 pci_unmap_page(qdev->pdev,
2443 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2444 dma_unmap_len(&tx_cb->map[seg], maplen),
2445 PCI_DMA_TODEVICE);
2446 }
2447
2448 pci_unmap_single(qdev->pdev,
2449 dma_unmap_addr(&tx_cb->map[0], mapaddr),
2450 dma_unmap_addr(&tx_cb->map[0], maplen),
2451 PCI_DMA_TODEVICE);
2452
2453 return NETDEV_TX_BUSY;
2454
2455}
2456
2457/*
2458 * The difference between 3022 and 3032 sends:
2459 * 3022 only supports a simple single segment transmission.
2460 * 3032 supports checksumming and scatter/gather lists (fragments).
2461 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2462 * in the IOCB plus a chain of outbound address lists (OAL) that
2463 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2464 * will be used to point to an OAL when more ALP entries are required.
2465 * The IOCB is always the top of the chain followed by one or more
2466 * OALs (when necessary).
2467 */
2468static netdev_tx_t ql3xxx_send(struct sk_buff *skb,
2469 struct net_device *ndev)
2470{
2471 struct ql3_adapter *qdev = netdev_priv(ndev);
2472 struct ql3xxx_port_registers __iomem *port_regs =
2473 qdev->mem_map_registers;
2474 struct ql_tx_buf_cb *tx_cb;
2475 u32 tot_len = skb->len;
2476 struct ob_mac_iocb_req *mac_iocb_ptr;
2477
2478 if (unlikely(atomic_read(&qdev->tx_count) < 2))
2479 return NETDEV_TX_BUSY;
2480
2481 tx_cb = &qdev->tx_buf[qdev->req_producer_index];
2482 tx_cb->seg_count = ql_get_seg_count(qdev,
2483 skb_shinfo(skb)->nr_frags);
2484 if (tx_cb->seg_count == -1) {
2485 netdev_err(ndev, "%s: invalid segment count!\n", __func__);
2486 return NETDEV_TX_OK;
2487 }
2488
2489 mac_iocb_ptr = tx_cb->queue_entry;
2490 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2491 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2492 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2493 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2494 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2495 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2496 tx_cb->skb = skb;
2497 if (qdev->device_id == QL3032_DEVICE_ID &&
2498 skb->ip_summed == CHECKSUM_PARTIAL)
2499 ql_hw_csum_setup(skb, mac_iocb_ptr);
2500
2501 if (ql_send_map(qdev, mac_iocb_ptr, tx_cb, skb) != NETDEV_TX_OK) {
2502 netdev_err(ndev, "%s: Could not map the segments!\n", __func__);
2503 return NETDEV_TX_BUSY;
2504 }
2505
2506 wmb();
2507 qdev->req_producer_index++;
2508 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2509 qdev->req_producer_index = 0;
2510 wmb();
2511 ql_write_common_reg_l(qdev,
2512 &port_regs->CommonRegs.reqQProducerIndex,
2513 qdev->req_producer_index);
2514
2515 netif_printk(qdev, tx_queued, KERN_DEBUG, ndev,
2516 "tx queued, slot %d, len %d\n",
2517 qdev->req_producer_index, skb->len);
2518
2519 atomic_dec(&qdev->tx_count);
2520 return NETDEV_TX_OK;
2521}
2522
2523static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2524{
2525 qdev->req_q_size =
2526 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2527
2528 qdev->req_q_virt_addr =
2529 pci_alloc_consistent(qdev->pdev,
2530 (size_t) qdev->req_q_size,
2531 &qdev->req_q_phy_addr);
2532
2533 if ((qdev->req_q_virt_addr == NULL) ||
2534 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2535 netdev_err(qdev->ndev, "reqQ failed\n");
2536 return -ENOMEM;
2537 }
2538
2539 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2540
2541 qdev->rsp_q_virt_addr =
2542 pci_alloc_consistent(qdev->pdev,
2543 (size_t) qdev->rsp_q_size,
2544 &qdev->rsp_q_phy_addr);
2545
2546 if ((qdev->rsp_q_virt_addr == NULL) ||
2547 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2548 netdev_err(qdev->ndev, "rspQ allocation failed\n");
2549 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2550 qdev->req_q_virt_addr,
2551 qdev->req_q_phy_addr);
2552 return -ENOMEM;
2553 }
2554
2555 set_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2556
2557 return 0;
2558}
2559
2560static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2561{
2562 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags)) {
2563 netdev_info(qdev->ndev, "Already done\n");
2564 return;
2565 }
2566
2567 pci_free_consistent(qdev->pdev,
2568 qdev->req_q_size,
2569 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2570
2571 qdev->req_q_virt_addr = NULL;
2572
2573 pci_free_consistent(qdev->pdev,
2574 qdev->rsp_q_size,
2575 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2576
2577 qdev->rsp_q_virt_addr = NULL;
2578
2579 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
2580}
2581
2582static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2583{
2584 /* Create Large Buffer Queue */
2585 qdev->lrg_buf_q_size =
2586 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2587 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2588 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2589 else
2590 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2591
2592 qdev->lrg_buf =
2593 kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),
2594 GFP_KERNEL);
2595 if (qdev->lrg_buf == NULL) {
2596 netdev_err(qdev->ndev, "qdev->lrg_buf alloc failed\n");
2597 return -ENOMEM;
2598 }
2599
2600 qdev->lrg_buf_q_alloc_virt_addr =
2601 pci_alloc_consistent(qdev->pdev,
2602 qdev->lrg_buf_q_alloc_size,
2603 &qdev->lrg_buf_q_alloc_phy_addr);
2604
2605 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2606 netdev_err(qdev->ndev, "lBufQ failed\n");
2607 return -ENOMEM;
2608 }
2609 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2610 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2611
2612 /* Create Small Buffer Queue */
2613 qdev->small_buf_q_size =
2614 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2615 if (qdev->small_buf_q_size < PAGE_SIZE)
2616 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2617 else
2618 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2619
2620 qdev->small_buf_q_alloc_virt_addr =
2621 pci_alloc_consistent(qdev->pdev,
2622 qdev->small_buf_q_alloc_size,
2623 &qdev->small_buf_q_alloc_phy_addr);
2624
2625 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2626 netdev_err(qdev->ndev, "Small Buffer Queue allocation failed\n");
2627 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2628 qdev->lrg_buf_q_alloc_virt_addr,
2629 qdev->lrg_buf_q_alloc_phy_addr);
2630 return -ENOMEM;
2631 }
2632
2633 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2634 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2635 set_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2636 return 0;
2637}
2638
2639static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2640{
2641 if (!test_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags)) {
2642 netdev_info(qdev->ndev, "Already done\n");
2643 return;
2644 }
2645 kfree(qdev->lrg_buf);
2646 pci_free_consistent(qdev->pdev,
2647 qdev->lrg_buf_q_alloc_size,
2648 qdev->lrg_buf_q_alloc_virt_addr,
2649 qdev->lrg_buf_q_alloc_phy_addr);
2650
2651 qdev->lrg_buf_q_virt_addr = NULL;
2652
2653 pci_free_consistent(qdev->pdev,
2654 qdev->small_buf_q_alloc_size,
2655 qdev->small_buf_q_alloc_virt_addr,
2656 qdev->small_buf_q_alloc_phy_addr);
2657
2658 qdev->small_buf_q_virt_addr = NULL;
2659
2660 clear_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
2661}
2662
2663static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2664{
2665 int i;
2666 struct bufq_addr_element *small_buf_q_entry;
2667
2668 /* Currently we allocate on one of memory and use it for smallbuffers */
2669 qdev->small_buf_total_size =
2670 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2671 QL_SMALL_BUFFER_SIZE);
2672
2673 qdev->small_buf_virt_addr =
2674 pci_alloc_consistent(qdev->pdev,
2675 qdev->small_buf_total_size,
2676 &qdev->small_buf_phy_addr);
2677
2678 if (qdev->small_buf_virt_addr == NULL) {
2679 netdev_err(qdev->ndev, "Failed to get small buffer memory\n");
2680 return -ENOMEM;
2681 }
2682
2683 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2684 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2685
2686 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2687
2688 /* Initialize the small buffer queue. */
2689 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2690 small_buf_q_entry->addr_high =
2691 cpu_to_le32(qdev->small_buf_phy_addr_high);
2692 small_buf_q_entry->addr_low =
2693 cpu_to_le32(qdev->small_buf_phy_addr_low +
2694 (i * QL_SMALL_BUFFER_SIZE));
2695 small_buf_q_entry++;
2696 }
2697 qdev->small_buf_index = 0;
2698 set_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags);
2699 return 0;
2700}
2701
2702static void ql_free_small_buffers(struct ql3_adapter *qdev)
2703{
2704 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags)) {
2705 netdev_info(qdev->ndev, "Already done\n");
2706 return;
2707 }
2708 if (qdev->small_buf_virt_addr != NULL) {
2709 pci_free_consistent(qdev->pdev,
2710 qdev->small_buf_total_size,
2711 qdev->small_buf_virt_addr,
2712 qdev->small_buf_phy_addr);
2713
2714 qdev->small_buf_virt_addr = NULL;
2715 }
2716}
2717
2718static void ql_free_large_buffers(struct ql3_adapter *qdev)
2719{
2720 int i = 0;
2721 struct ql_rcv_buf_cb *lrg_buf_cb;
2722
2723 for (i = 0; i < qdev->num_large_buffers; i++) {
2724 lrg_buf_cb = &qdev->lrg_buf[i];
2725 if (lrg_buf_cb->skb) {
2726 dev_kfree_skb(lrg_buf_cb->skb);
2727 pci_unmap_single(qdev->pdev,
2728 dma_unmap_addr(lrg_buf_cb, mapaddr),
2729 dma_unmap_len(lrg_buf_cb, maplen),
2730 PCI_DMA_FROMDEVICE);
2731 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2732 } else {
2733 break;
2734 }
2735 }
2736}
2737
2738static void ql_init_large_buffers(struct ql3_adapter *qdev)
2739{
2740 int i;
2741 struct ql_rcv_buf_cb *lrg_buf_cb;
2742 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2743
2744 for (i = 0; i < qdev->num_large_buffers; i++) {
2745 lrg_buf_cb = &qdev->lrg_buf[i];
2746 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2747 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2748 buf_addr_ele++;
2749 }
2750 qdev->lrg_buf_index = 0;
2751 qdev->lrg_buf_skb_check = 0;
2752}
2753
2754static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2755{
2756 int i;
2757 struct ql_rcv_buf_cb *lrg_buf_cb;
2758 struct sk_buff *skb;
2759 dma_addr_t map;
2760 int err;
2761
2762 for (i = 0; i < qdev->num_large_buffers; i++) {
2763 skb = netdev_alloc_skb(qdev->ndev,
2764 qdev->lrg_buffer_len);
2765 if (unlikely(!skb)) {
2766 /* Better luck next round */
2767 netdev_err(qdev->ndev,
2768 "large buff alloc failed for %d bytes at index %d\n",
2769 qdev->lrg_buffer_len * 2, i);
2770 ql_free_large_buffers(qdev);
2771 return -ENOMEM;
2772 } else {
2773
2774 lrg_buf_cb = &qdev->lrg_buf[i];
2775 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2776 lrg_buf_cb->index = i;
2777 lrg_buf_cb->skb = skb;
2778 /*
2779 * We save some space to copy the ethhdr from first
2780 * buffer
2781 */
2782 skb_reserve(skb, QL_HEADER_SPACE);
2783 map = pci_map_single(qdev->pdev,
2784 skb->data,
2785 qdev->lrg_buffer_len -
2786 QL_HEADER_SPACE,
2787 PCI_DMA_FROMDEVICE);
2788
2789 err = pci_dma_mapping_error(qdev->pdev, map);
2790 if (err) {
2791 netdev_err(qdev->ndev,
2792 "PCI mapping failed with error: %d\n",
2793 err);
2794 ql_free_large_buffers(qdev);
2795 return -ENOMEM;
2796 }
2797
2798 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2799 dma_unmap_len_set(lrg_buf_cb, maplen,
2800 qdev->lrg_buffer_len -
2801 QL_HEADER_SPACE);
2802 lrg_buf_cb->buf_phy_addr_low =
2803 cpu_to_le32(LS_64BITS(map));
2804 lrg_buf_cb->buf_phy_addr_high =
2805 cpu_to_le32(MS_64BITS(map));
2806 }
2807 }
2808 return 0;
2809}
2810
2811static void ql_free_send_free_list(struct ql3_adapter *qdev)
2812{
2813 struct ql_tx_buf_cb *tx_cb;
2814 int i;
2815
2816 tx_cb = &qdev->tx_buf[0];
2817 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2818 kfree(tx_cb->oal);
2819 tx_cb->oal = NULL;
2820 tx_cb++;
2821 }
2822}
2823
2824static int ql_create_send_free_list(struct ql3_adapter *qdev)
2825{
2826 struct ql_tx_buf_cb *tx_cb;
2827 int i;
2828 struct ob_mac_iocb_req *req_q_curr = qdev->req_q_virt_addr;
2829
2830 /* Create free list of transmit buffers */
2831 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2832
2833 tx_cb = &qdev->tx_buf[i];
2834 tx_cb->skb = NULL;
2835 tx_cb->queue_entry = req_q_curr;
2836 req_q_curr++;
2837 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2838 if (tx_cb->oal == NULL)
2839 return -ENOMEM;
2840 }
2841 return 0;
2842}
2843
2844static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2845{
2846 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2847 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2848 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2849 } else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2850 /*
2851 * Bigger buffers, so less of them.
2852 */
2853 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2854 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2855 } else {
2856 netdev_err(qdev->ndev, "Invalid mtu size: %d. Only %d and %d are accepted.\n",
2857 qdev->ndev->mtu, NORMAL_MTU_SIZE, JUMBO_MTU_SIZE);
2858 return -ENOMEM;
2859 }
2860 qdev->num_large_buffers =
2861 qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2862 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2863 qdev->max_frame_size =
2864 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2865
2866 /*
2867 * First allocate a page of shared memory and use it for shadow
2868 * locations of Network Request Queue Consumer Address Register and
2869 * Network Completion Queue Producer Index Register
2870 */
2871 qdev->shadow_reg_virt_addr =
2872 pci_alloc_consistent(qdev->pdev,
2873 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2874
2875 if (qdev->shadow_reg_virt_addr != NULL) {
2876 qdev->preq_consumer_index = qdev->shadow_reg_virt_addr;
2877 qdev->req_consumer_index_phy_addr_high =
2878 MS_64BITS(qdev->shadow_reg_phy_addr);
2879 qdev->req_consumer_index_phy_addr_low =
2880 LS_64BITS(qdev->shadow_reg_phy_addr);
2881
2882 qdev->prsp_producer_index =
2883 (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2884 qdev->rsp_producer_index_phy_addr_high =
2885 qdev->req_consumer_index_phy_addr_high;
2886 qdev->rsp_producer_index_phy_addr_low =
2887 qdev->req_consumer_index_phy_addr_low + 8;
2888 } else {
2889 netdev_err(qdev->ndev, "shadowReg Alloc failed\n");
2890 return -ENOMEM;
2891 }
2892
2893 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2894 netdev_err(qdev->ndev, "ql_alloc_net_req_rsp_queues failed\n");
2895 goto err_req_rsp;
2896 }
2897
2898 if (ql_alloc_buffer_queues(qdev) != 0) {
2899 netdev_err(qdev->ndev, "ql_alloc_buffer_queues failed\n");
2900 goto err_buffer_queues;
2901 }
2902
2903 if (ql_alloc_small_buffers(qdev) != 0) {
2904 netdev_err(qdev->ndev, "ql_alloc_small_buffers failed\n");
2905 goto err_small_buffers;
2906 }
2907
2908 if (ql_alloc_large_buffers(qdev) != 0) {
2909 netdev_err(qdev->ndev, "ql_alloc_large_buffers failed\n");
2910 goto err_small_buffers;
2911 }
2912
2913 /* Initialize the large buffer queue. */
2914 ql_init_large_buffers(qdev);
2915 if (ql_create_send_free_list(qdev))
2916 goto err_free_list;
2917
2918 qdev->rsp_current = qdev->rsp_q_virt_addr;
2919
2920 return 0;
2921err_free_list:
2922 ql_free_send_free_list(qdev);
2923err_small_buffers:
2924 ql_free_buffer_queues(qdev);
2925err_buffer_queues:
2926 ql_free_net_req_rsp_queues(qdev);
2927err_req_rsp:
2928 pci_free_consistent(qdev->pdev,
2929 PAGE_SIZE,
2930 qdev->shadow_reg_virt_addr,
2931 qdev->shadow_reg_phy_addr);
2932
2933 return -ENOMEM;
2934}
2935
2936static void ql_free_mem_resources(struct ql3_adapter *qdev)
2937{
2938 ql_free_send_free_list(qdev);
2939 ql_free_large_buffers(qdev);
2940 ql_free_small_buffers(qdev);
2941 ql_free_buffer_queues(qdev);
2942 ql_free_net_req_rsp_queues(qdev);
2943 if (qdev->shadow_reg_virt_addr != NULL) {
2944 pci_free_consistent(qdev->pdev,
2945 PAGE_SIZE,
2946 qdev->shadow_reg_virt_addr,
2947 qdev->shadow_reg_phy_addr);
2948 qdev->shadow_reg_virt_addr = NULL;
2949 }
2950}
2951
2952static int ql_init_misc_registers(struct ql3_adapter *qdev)
2953{
2954 struct ql3xxx_local_ram_registers __iomem *local_ram =
2955 (void __iomem *)qdev->mem_map_registers;
2956
2957 if (ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2958 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2959 2) << 4))
2960 return -1;
2961
2962 ql_write_page2_reg(qdev,
2963 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2964
2965 ql_write_page2_reg(qdev,
2966 &local_ram->maxBufletCount,
2967 qdev->nvram_data.bufletCount);
2968
2969 ql_write_page2_reg(qdev,
2970 &local_ram->freeBufletThresholdLow,
2971 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2972 (qdev->nvram_data.tcpWindowThreshold0));
2973
2974 ql_write_page2_reg(qdev,
2975 &local_ram->freeBufletThresholdHigh,
2976 qdev->nvram_data.tcpWindowThreshold50);
2977
2978 ql_write_page2_reg(qdev,
2979 &local_ram->ipHashTableBase,
2980 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2981 qdev->nvram_data.ipHashTableBaseLo);
2982 ql_write_page2_reg(qdev,
2983 &local_ram->ipHashTableCount,
2984 qdev->nvram_data.ipHashTableSize);
2985 ql_write_page2_reg(qdev,
2986 &local_ram->tcpHashTableBase,
2987 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2988 qdev->nvram_data.tcpHashTableBaseLo);
2989 ql_write_page2_reg(qdev,
2990 &local_ram->tcpHashTableCount,
2991 qdev->nvram_data.tcpHashTableSize);
2992 ql_write_page2_reg(qdev,
2993 &local_ram->ncbBase,
2994 (qdev->nvram_data.ncbTableBaseHi << 16) |
2995 qdev->nvram_data.ncbTableBaseLo);
2996 ql_write_page2_reg(qdev,
2997 &local_ram->maxNcbCount,
2998 qdev->nvram_data.ncbTableSize);
2999 ql_write_page2_reg(qdev,
3000 &local_ram->drbBase,
3001 (qdev->nvram_data.drbTableBaseHi << 16) |
3002 qdev->nvram_data.drbTableBaseLo);
3003 ql_write_page2_reg(qdev,
3004 &local_ram->maxDrbCount,
3005 qdev->nvram_data.drbTableSize);
3006 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3007 return 0;
3008}
3009
3010static int ql_adapter_initialize(struct ql3_adapter *qdev)
3011{
3012 u32 value;
3013 struct ql3xxx_port_registers __iomem *port_regs =
3014 qdev->mem_map_registers;
3015 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
3016 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
3017 (void __iomem *)port_regs;
3018 u32 delay = 10;
3019 int status = 0;
3020
3021 if (ql_mii_setup(qdev))
3022 return -1;
3023
3024 /* Bring out PHY out of reset */
3025 ql_write_common_reg(qdev, spir,
3026 (ISP_SERIAL_PORT_IF_WE |
3027 (ISP_SERIAL_PORT_IF_WE << 16)));
3028 /* Give the PHY time to come out of reset. */
3029 mdelay(100);
3030 qdev->port_link_state = LS_DOWN;
3031 netif_carrier_off(qdev->ndev);
3032
3033 /* V2 chip fix for ARS-39168. */
3034 ql_write_common_reg(qdev, spir,
3035 (ISP_SERIAL_PORT_IF_SDE |
3036 (ISP_SERIAL_PORT_IF_SDE << 16)));
3037
3038 /* Request Queue Registers */
3039 *((u32 *)(qdev->preq_consumer_index)) = 0;
3040 atomic_set(&qdev->tx_count, NUM_REQ_Q_ENTRIES);
3041 qdev->req_producer_index = 0;
3042
3043 ql_write_page1_reg(qdev,
3044 &hmem_regs->reqConsumerIndexAddrHigh,
3045 qdev->req_consumer_index_phy_addr_high);
3046 ql_write_page1_reg(qdev,
3047 &hmem_regs->reqConsumerIndexAddrLow,
3048 qdev->req_consumer_index_phy_addr_low);
3049
3050 ql_write_page1_reg(qdev,
3051 &hmem_regs->reqBaseAddrHigh,
3052 MS_64BITS(qdev->req_q_phy_addr));
3053 ql_write_page1_reg(qdev,
3054 &hmem_regs->reqBaseAddrLow,
3055 LS_64BITS(qdev->req_q_phy_addr));
3056 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3057
3058 /* Response Queue Registers */
3059 *((__le16 *) (qdev->prsp_producer_index)) = 0;
3060 qdev->rsp_consumer_index = 0;
3061 qdev->rsp_current = qdev->rsp_q_virt_addr;
3062
3063 ql_write_page1_reg(qdev,
3064 &hmem_regs->rspProducerIndexAddrHigh,
3065 qdev->rsp_producer_index_phy_addr_high);
3066
3067 ql_write_page1_reg(qdev,
3068 &hmem_regs->rspProducerIndexAddrLow,
3069 qdev->rsp_producer_index_phy_addr_low);
3070
3071 ql_write_page1_reg(qdev,
3072 &hmem_regs->rspBaseAddrHigh,
3073 MS_64BITS(qdev->rsp_q_phy_addr));
3074
3075 ql_write_page1_reg(qdev,
3076 &hmem_regs->rspBaseAddrLow,
3077 LS_64BITS(qdev->rsp_q_phy_addr));
3078
3079 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3080
3081 /* Large Buffer Queue */
3082 ql_write_page1_reg(qdev,
3083 &hmem_regs->rxLargeQBaseAddrHigh,
3084 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3085
3086 ql_write_page1_reg(qdev,
3087 &hmem_regs->rxLargeQBaseAddrLow,
3088 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3089
3090 ql_write_page1_reg(qdev,
3091 &hmem_regs->rxLargeQLength,
3092 qdev->num_lbufq_entries);
3093
3094 ql_write_page1_reg(qdev,
3095 &hmem_regs->rxLargeBufferLength,
3096 qdev->lrg_buffer_len);
3097
3098 /* Small Buffer Queue */
3099 ql_write_page1_reg(qdev,
3100 &hmem_regs->rxSmallQBaseAddrHigh,
3101 MS_64BITS(qdev->small_buf_q_phy_addr));
3102
3103 ql_write_page1_reg(qdev,
3104 &hmem_regs->rxSmallQBaseAddrLow,
3105 LS_64BITS(qdev->small_buf_q_phy_addr));
3106
3107 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3108 ql_write_page1_reg(qdev,
3109 &hmem_regs->rxSmallBufferLength,
3110 QL_SMALL_BUFFER_SIZE);
3111
3112 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3113 qdev->small_buf_release_cnt = 8;
3114 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3115 qdev->lrg_buf_release_cnt = 8;
3116 qdev->lrg_buf_next_free = qdev->lrg_buf_q_virt_addr;
3117 qdev->small_buf_index = 0;
3118 qdev->lrg_buf_index = 0;
3119 qdev->lrg_buf_free_count = 0;
3120 qdev->lrg_buf_free_head = NULL;
3121 qdev->lrg_buf_free_tail = NULL;
3122
3123 ql_write_common_reg(qdev,
3124 &port_regs->CommonRegs.
3125 rxSmallQProducerIndex,
3126 qdev->small_buf_q_producer_index);
3127 ql_write_common_reg(qdev,
3128 &port_regs->CommonRegs.
3129 rxLargeQProducerIndex,
3130 qdev->lrg_buf_q_producer_index);
3131
3132 /*
3133 * Find out if the chip has already been initialized. If it has, then
3134 * we skip some of the initialization.
3135 */
3136 clear_bit(QL_LINK_MASTER, &qdev->flags);
3137 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3138 if ((value & PORT_STATUS_IC) == 0) {
3139
3140 /* Chip has not been configured yet, so let it rip. */
3141 if (ql_init_misc_registers(qdev)) {
3142 status = -1;
3143 goto out;
3144 }
3145
3146 value = qdev->nvram_data.tcpMaxWindowSize;
3147 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3148
3149 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3150
3151 if (ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3152 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3153 * 2) << 13)) {
3154 status = -1;
3155 goto out;
3156 }
3157 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3158 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3159 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3160 16) | (INTERNAL_CHIP_SD |
3161 INTERNAL_CHIP_WE)));
3162 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3163 }
3164
3165 if (qdev->mac_index)
3166 ql_write_page0_reg(qdev,
3167 &port_regs->mac1MaxFrameLengthReg,
3168 qdev->max_frame_size);
3169 else
3170 ql_write_page0_reg(qdev,
3171 &port_regs->mac0MaxFrameLengthReg,
3172 qdev->max_frame_size);
3173
3174 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3175 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3176 2) << 7)) {
3177 status = -1;
3178 goto out;
3179 }
3180
3181 PHY_Setup(qdev);
3182 ql_init_scan_mode(qdev);
3183 ql_get_phy_owner(qdev);
3184
3185 /* Load the MAC Configuration */
3186
3187 /* Program lower 32 bits of the MAC address */
3188 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3189 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3190 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3191 ((qdev->ndev->dev_addr[2] << 24)
3192 | (qdev->ndev->dev_addr[3] << 16)
3193 | (qdev->ndev->dev_addr[4] << 8)
3194 | qdev->ndev->dev_addr[5]));
3195
3196 /* Program top 16 bits of the MAC address */
3197 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3198 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3199 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3200 ((qdev->ndev->dev_addr[0] << 8)
3201 | qdev->ndev->dev_addr[1]));
3202
3203 /* Enable Primary MAC */
3204 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3205 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3206 MAC_ADDR_INDIRECT_PTR_REG_PE));
3207
3208 /* Clear Primary and Secondary IP addresses */
3209 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3210 ((IP_ADDR_INDEX_REG_MASK << 16) |
3211 (qdev->mac_index << 2)));
3212 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3213
3214 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3215 ((IP_ADDR_INDEX_REG_MASK << 16) |
3216 ((qdev->mac_index << 2) + 1)));
3217 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3218
3219 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3220
3221 /* Indicate Configuration Complete */
3222 ql_write_page0_reg(qdev,
3223 &port_regs->portControl,
3224 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3225
3226 do {
3227 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3228 if (value & PORT_STATUS_IC)
3229 break;
3230 spin_unlock_irq(&qdev->hw_lock);
3231 msleep(500);
3232 spin_lock_irq(&qdev->hw_lock);
3233 } while (--delay);
3234
3235 if (delay == 0) {
3236 netdev_err(qdev->ndev, "Hw Initialization timeout\n");
3237 status = -1;
3238 goto out;
3239 }
3240
3241 /* Enable Ethernet Function */
3242 if (qdev->device_id == QL3032_DEVICE_ID) {
3243 value =
3244 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3245 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3246 QL3032_PORT_CONTROL_ET);
3247 ql_write_page0_reg(qdev, &port_regs->functionControl,
3248 ((value << 16) | value));
3249 } else {
3250 value =
3251 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3252 PORT_CONTROL_HH);
3253 ql_write_page0_reg(qdev, &port_regs->portControl,
3254 ((value << 16) | value));
3255 }
3256
3257
3258out:
3259 return status;
3260}
3261
3262/*
3263 * Caller holds hw_lock.
3264 */
3265static int ql_adapter_reset(struct ql3_adapter *qdev)
3266{
3267 struct ql3xxx_port_registers __iomem *port_regs =
3268 qdev->mem_map_registers;
3269 int status = 0;
3270 u16 value;
3271 int max_wait_time;
3272
3273 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3274 clear_bit(QL_RESET_DONE, &qdev->flags);
3275
3276 /*
3277 * Issue soft reset to chip.
3278 */
3279 netdev_printk(KERN_DEBUG, qdev->ndev, "Issue soft reset to chip\n");
3280 ql_write_common_reg(qdev,
3281 &port_regs->CommonRegs.ispControlStatus,
3282 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3283
3284 /* Wait 3 seconds for reset to complete. */
3285 netdev_printk(KERN_DEBUG, qdev->ndev,
3286 "Wait 10 milliseconds for reset to complete\n");
3287
3288 /* Wait until the firmware tells us the Soft Reset is done */
3289 max_wait_time = 5;
3290 do {
3291 value =
3292 ql_read_common_reg(qdev,
3293 &port_regs->CommonRegs.ispControlStatus);
3294 if ((value & ISP_CONTROL_SR) == 0)
3295 break;
3296
3297 ssleep(1);
3298 } while ((--max_wait_time));
3299
3300 /*
3301 * Also, make sure that the Network Reset Interrupt bit has been
3302 * cleared after the soft reset has taken place.
3303 */
3304 value =
3305 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3306 if (value & ISP_CONTROL_RI) {
3307 netdev_printk(KERN_DEBUG, qdev->ndev,
3308 "clearing RI after reset\n");
3309 ql_write_common_reg(qdev,
3310 &port_regs->CommonRegs.
3311 ispControlStatus,
3312 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3313 }
3314
3315 if (max_wait_time == 0) {
3316 /* Issue Force Soft Reset */
3317 ql_write_common_reg(qdev,
3318 &port_regs->CommonRegs.
3319 ispControlStatus,
3320 ((ISP_CONTROL_FSR << 16) |
3321 ISP_CONTROL_FSR));
3322 /*
3323 * Wait until the firmware tells us the Force Soft Reset is
3324 * done
3325 */
3326 max_wait_time = 5;
3327 do {
3328 value = ql_read_common_reg(qdev,
3329 &port_regs->CommonRegs.
3330 ispControlStatus);
3331 if ((value & ISP_CONTROL_FSR) == 0)
3332 break;
3333 ssleep(1);
3334 } while ((--max_wait_time));
3335 }
3336 if (max_wait_time == 0)
3337 status = 1;
3338
3339 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3340 set_bit(QL_RESET_DONE, &qdev->flags);
3341 return status;
3342}
3343
3344static void ql_set_mac_info(struct ql3_adapter *qdev)
3345{
3346 struct ql3xxx_port_registers __iomem *port_regs =
3347 qdev->mem_map_registers;
3348 u32 value, port_status;
3349 u8 func_number;
3350
3351 /* Get the function number */
3352 value =
3353 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3354 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3355 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3356 switch (value & ISP_CONTROL_FN_MASK) {
3357 case ISP_CONTROL_FN0_NET:
3358 qdev->mac_index = 0;
3359 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3360 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3361 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3362 if (port_status & PORT_STATUS_SM0)
3363 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3364 else
3365 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3366 break;
3367
3368 case ISP_CONTROL_FN1_NET:
3369 qdev->mac_index = 1;
3370 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3371 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3372 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3373 if (port_status & PORT_STATUS_SM1)
3374 set_bit(QL_LINK_OPTICAL, &qdev->flags);
3375 else
3376 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
3377 break;
3378
3379 case ISP_CONTROL_FN0_SCSI:
3380 case ISP_CONTROL_FN1_SCSI:
3381 default:
3382 netdev_printk(KERN_DEBUG, qdev->ndev,
3383 "Invalid function number, ispControlStatus = 0x%x\n",
3384 value);
3385 break;
3386 }
3387 qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
3388}
3389
3390static void ql_display_dev_info(struct net_device *ndev)
3391{
3392 struct ql3_adapter *qdev = netdev_priv(ndev);
3393 struct pci_dev *pdev = qdev->pdev;
3394
3395 netdev_info(ndev,
3396 "%s Adapter %d RevisionID %d found %s on PCI slot %d\n",
3397 DRV_NAME, qdev->index, qdev->chip_rev_id,
3398 qdev->device_id == QL3032_DEVICE_ID ? "QLA3032" : "QLA3022",
3399 qdev->pci_slot);
3400 netdev_info(ndev, "%s Interface\n",
3401 test_bit(QL_LINK_OPTICAL, &qdev->flags) ? "OPTICAL" : "COPPER");
3402
3403 /*
3404 * Print PCI bus width/type.
3405 */
3406 netdev_info(ndev, "Bus interface is %s %s\n",
3407 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3408 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3409
3410 netdev_info(ndev, "mem IO base address adjusted = 0x%p\n",
3411 qdev->mem_map_registers);
3412 netdev_info(ndev, "Interrupt number = %d\n", pdev->irq);
3413
3414 netif_info(qdev, probe, ndev, "MAC address %pM\n", ndev->dev_addr);
3415}
3416
3417static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3418{
3419 struct net_device *ndev = qdev->ndev;
3420 int retval = 0;
3421
3422 netif_stop_queue(ndev);
3423 netif_carrier_off(ndev);
3424
3425 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3426 clear_bit(QL_LINK_MASTER, &qdev->flags);
3427
3428 ql_disable_interrupts(qdev);
3429
3430 free_irq(qdev->pdev->irq, ndev);
3431
3432 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3433 netdev_info(qdev->ndev, "calling pci_disable_msi()\n");
3434 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3435 pci_disable_msi(qdev->pdev);
3436 }
3437
3438 del_timer_sync(&qdev->adapter_timer);
3439
3440 napi_disable(&qdev->napi);
3441
3442 if (do_reset) {
3443 int soft_reset;
3444 unsigned long hw_flags;
3445
3446 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3447 if (ql_wait_for_drvr_lock(qdev)) {
3448 soft_reset = ql_adapter_reset(qdev);
3449 if (soft_reset) {
3450 netdev_err(ndev, "ql_adapter_reset(%d) FAILED!\n",
3451 qdev->index);
3452 }
3453 netdev_err(ndev,
3454 "Releasing driver lock via chip reset\n");
3455 } else {
3456 netdev_err(ndev,
3457 "Could not acquire driver lock to do reset!\n");
3458 retval = -1;
3459 }
3460 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3461 }
3462 ql_free_mem_resources(qdev);
3463 return retval;
3464}
3465
3466static int ql_adapter_up(struct ql3_adapter *qdev)
3467{
3468 struct net_device *ndev = qdev->ndev;
3469 int err;
3470 unsigned long irq_flags = IRQF_SHARED;
3471 unsigned long hw_flags;
3472
3473 if (ql_alloc_mem_resources(qdev)) {
3474 netdev_err(ndev, "Unable to allocate buffers\n");
3475 return -ENOMEM;
3476 }
3477
3478 if (qdev->msi) {
3479 if (pci_enable_msi(qdev->pdev)) {
3480 netdev_err(ndev,
3481 "User requested MSI, but MSI failed to initialize. Continuing without MSI.\n");
3482 qdev->msi = 0;
3483 } else {
3484 netdev_info(ndev, "MSI Enabled...\n");
3485 set_bit(QL_MSI_ENABLED, &qdev->flags);
3486 irq_flags &= ~IRQF_SHARED;
3487 }
3488 }
3489
3490 err = request_irq(qdev->pdev->irq, ql3xxx_isr,
3491 irq_flags, ndev->name, ndev);
3492 if (err) {
3493 netdev_err(ndev,
3494 "Failed to reserve interrupt %d - already in use\n",
3495 qdev->pdev->irq);
3496 goto err_irq;
3497 }
3498
3499 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3500
3501 err = ql_wait_for_drvr_lock(qdev);
3502 if (err) {
3503 err = ql_adapter_initialize(qdev);
3504 if (err) {
3505 netdev_err(ndev, "Unable to initialize adapter\n");
3506 goto err_init;
3507 }
3508 netdev_err(ndev, "Releasing driver lock\n");
3509 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3510 } else {
3511 netdev_err(ndev, "Could not acquire driver lock\n");
3512 goto err_lock;
3513 }
3514
3515 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3516
3517 set_bit(QL_ADAPTER_UP, &qdev->flags);
3518
3519 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3520
3521 napi_enable(&qdev->napi);
3522 ql_enable_interrupts(qdev);
3523 return 0;
3524
3525err_init:
3526 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3527err_lock:
3528 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3529 free_irq(qdev->pdev->irq, ndev);
3530err_irq:
3531 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
3532 netdev_info(ndev, "calling pci_disable_msi()\n");
3533 clear_bit(QL_MSI_ENABLED, &qdev->flags);
3534 pci_disable_msi(qdev->pdev);
3535 }
3536 return err;
3537}
3538
3539static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3540{
3541 if (ql_adapter_down(qdev, reset) || ql_adapter_up(qdev)) {
3542 netdev_err(qdev->ndev,
3543 "Driver up/down cycle failed, closing device\n");
3544 rtnl_lock();
3545 dev_close(qdev->ndev);
3546 rtnl_unlock();
3547 return -1;
3548 }
3549 return 0;
3550}
3551
3552static int ql3xxx_close(struct net_device *ndev)
3553{
3554 struct ql3_adapter *qdev = netdev_priv(ndev);
3555
3556 /*
3557 * Wait for device to recover from a reset.
3558 * (Rarely happens, but possible.)
3559 */
3560 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3561 msleep(50);
3562
3563 ql_adapter_down(qdev, QL_DO_RESET);
3564 return 0;
3565}
3566
3567static int ql3xxx_open(struct net_device *ndev)
3568{
3569 struct ql3_adapter *qdev = netdev_priv(ndev);
3570 return ql_adapter_up(qdev);
3571}
3572
3573static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3574{
3575 struct ql3_adapter *qdev = netdev_priv(ndev);
3576 struct ql3xxx_port_registers __iomem *port_regs =
3577 qdev->mem_map_registers;
3578 struct sockaddr *addr = p;
3579 unsigned long hw_flags;
3580
3581 if (netif_running(ndev))
3582 return -EBUSY;
3583
3584 if (!is_valid_ether_addr(addr->sa_data))
3585 return -EADDRNOTAVAIL;
3586
3587 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3588
3589 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3590 /* Program lower 32 bits of the MAC address */
3591 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3592 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3593 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3594 ((ndev->dev_addr[2] << 24) | (ndev->
3595 dev_addr[3] << 16) |
3596 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3597
3598 /* Program top 16 bits of the MAC address */
3599 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3600 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3601 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3602 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3603 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3604
3605 return 0;
3606}
3607
3608static void ql3xxx_tx_timeout(struct net_device *ndev)
3609{
3610 struct ql3_adapter *qdev = netdev_priv(ndev);
3611
3612 netdev_err(ndev, "Resetting...\n");
3613 /*
3614 * Stop the queues, we've got a problem.
3615 */
3616 netif_stop_queue(ndev);
3617
3618 /*
3619 * Wake up the worker to process this event.
3620 */
3621 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3622}
3623
3624static void ql_reset_work(struct work_struct *work)
3625{
3626 struct ql3_adapter *qdev =
3627 container_of(work, struct ql3_adapter, reset_work.work);
3628 struct net_device *ndev = qdev->ndev;
3629 u32 value;
3630 struct ql_tx_buf_cb *tx_cb;
3631 int max_wait_time, i;
3632 struct ql3xxx_port_registers __iomem *port_regs =
3633 qdev->mem_map_registers;
3634 unsigned long hw_flags;
3635
3636 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START), &qdev->flags)) {
3637 clear_bit(QL_LINK_MASTER, &qdev->flags);
3638
3639 /*
3640 * Loop through the active list and return the skb.
3641 */
3642 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3643 int j;
3644 tx_cb = &qdev->tx_buf[i];
3645 if (tx_cb->skb) {
3646 netdev_printk(KERN_DEBUG, ndev,
3647 "Freeing lost SKB\n");
3648 pci_unmap_single(qdev->pdev,
3649 dma_unmap_addr(&tx_cb->map[0],
3650 mapaddr),
3651 dma_unmap_len(&tx_cb->map[0], maplen),
3652 PCI_DMA_TODEVICE);
3653 for (j = 1; j < tx_cb->seg_count; j++) {
3654 pci_unmap_page(qdev->pdev,
3655 dma_unmap_addr(&tx_cb->map[j],
3656 mapaddr),
3657 dma_unmap_len(&tx_cb->map[j],
3658 maplen),
3659 PCI_DMA_TODEVICE);
3660 }
3661 dev_kfree_skb(tx_cb->skb);
3662 tx_cb->skb = NULL;
3663 }
3664 }
3665
3666 netdev_err(ndev, "Clearing NRI after reset\n");
3667 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3668 ql_write_common_reg(qdev,
3669 &port_regs->CommonRegs.
3670 ispControlStatus,
3671 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3672 /*
3673 * Wait the for Soft Reset to Complete.
3674 */
3675 max_wait_time = 10;
3676 do {
3677 value = ql_read_common_reg(qdev,
3678 &port_regs->CommonRegs.
3679
3680 ispControlStatus);
3681 if ((value & ISP_CONTROL_SR) == 0) {
3682 netdev_printk(KERN_DEBUG, ndev,
3683 "reset completed\n");
3684 break;
3685 }
3686
3687 if (value & ISP_CONTROL_RI) {
3688 netdev_printk(KERN_DEBUG, ndev,
3689 "clearing NRI after reset\n");
3690 ql_write_common_reg(qdev,
3691 &port_regs->
3692 CommonRegs.
3693 ispControlStatus,
3694 ((ISP_CONTROL_RI <<
3695 16) | ISP_CONTROL_RI));
3696 }
3697
3698 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3699 ssleep(1);
3700 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3701 } while (--max_wait_time);
3702 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3703
3704 if (value & ISP_CONTROL_SR) {
3705
3706 /*
3707 * Set the reset flags and clear the board again.
3708 * Nothing else to do...
3709 */
3710 netdev_err(ndev,
3711 "Timed out waiting for reset to complete\n");
3712 netdev_err(ndev, "Do a reset\n");
3713 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3714 clear_bit(QL_RESET_START, &qdev->flags);
3715 ql_cycle_adapter(qdev, QL_DO_RESET);
3716 return;
3717 }
3718
3719 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3720 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3721 clear_bit(QL_RESET_START, &qdev->flags);
3722 ql_cycle_adapter(qdev, QL_NO_RESET);
3723 }
3724}
3725
3726static void ql_tx_timeout_work(struct work_struct *work)
3727{
3728 struct ql3_adapter *qdev =
3729 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3730
3731 ql_cycle_adapter(qdev, QL_DO_RESET);
3732}
3733
3734static void ql_get_board_info(struct ql3_adapter *qdev)
3735{
3736 struct ql3xxx_port_registers __iomem *port_regs =
3737 qdev->mem_map_registers;
3738 u32 value;
3739
3740 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3741
3742 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3743 if (value & PORT_STATUS_64)
3744 qdev->pci_width = 64;
3745 else
3746 qdev->pci_width = 32;
3747 if (value & PORT_STATUS_X)
3748 qdev->pci_x = 1;
3749 else
3750 qdev->pci_x = 0;
3751 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3752}
3753
3754static void ql3xxx_timer(unsigned long ptr)
3755{
3756 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3757 queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
3758}
3759
3760static const struct net_device_ops ql3xxx_netdev_ops = {
3761 .ndo_open = ql3xxx_open,
3762 .ndo_start_xmit = ql3xxx_send,
3763 .ndo_stop = ql3xxx_close,
3764 .ndo_change_mtu = eth_change_mtu,
3765 .ndo_validate_addr = eth_validate_addr,
3766 .ndo_set_mac_address = ql3xxx_set_mac_address,
3767 .ndo_tx_timeout = ql3xxx_tx_timeout,
3768};
3769
3770static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3771 const struct pci_device_id *pci_entry)
3772{
3773 struct net_device *ndev = NULL;
3774 struct ql3_adapter *qdev = NULL;
3775 static int cards_found;
3776 int uninitialized_var(pci_using_dac), err;
3777
3778 err = pci_enable_device(pdev);
3779 if (err) {
3780 pr_err("%s cannot enable PCI device\n", pci_name(pdev));
3781 goto err_out;
3782 }
3783
3784 err = pci_request_regions(pdev, DRV_NAME);
3785 if (err) {
3786 pr_err("%s cannot obtain PCI resources\n", pci_name(pdev));
3787 goto err_out_disable_pdev;
3788 }
3789
3790 pci_set_master(pdev);
3791
3792 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3793 pci_using_dac = 1;
3794 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3795 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3796 pci_using_dac = 0;
3797 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3798 }
3799
3800 if (err) {
3801 pr_err("%s no usable DMA configuration\n", pci_name(pdev));
3802 goto err_out_free_regions;
3803 }
3804
3805 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3806 if (!ndev) {
3807 err = -ENOMEM;
3808 goto err_out_free_regions;
3809 }
3810
3811 SET_NETDEV_DEV(ndev, &pdev->dev);
3812
3813 pci_set_drvdata(pdev, ndev);
3814
3815 qdev = netdev_priv(ndev);
3816 qdev->index = cards_found;
3817 qdev->ndev = ndev;
3818 qdev->pdev = pdev;
3819 qdev->device_id = pci_entry->device;
3820 qdev->port_link_state = LS_DOWN;
3821 if (msi)
3822 qdev->msi = 1;
3823
3824 qdev->msg_enable = netif_msg_init(debug, default_msg);
3825
3826 if (pci_using_dac)
3827 ndev->features |= NETIF_F_HIGHDMA;
3828 if (qdev->device_id == QL3032_DEVICE_ID)
3829 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3830
3831 qdev->mem_map_registers = pci_ioremap_bar(pdev, 1);
3832 if (!qdev->mem_map_registers) {
3833 pr_err("%s: cannot map device registers\n", pci_name(pdev));
3834 err = -EIO;
3835 goto err_out_free_ndev;
3836 }
3837
3838 spin_lock_init(&qdev->adapter_lock);
3839 spin_lock_init(&qdev->hw_lock);
3840
3841 /* Set driver entry points */
3842 ndev->netdev_ops = &ql3xxx_netdev_ops;
3843 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3844 ndev->watchdog_timeo = 5 * HZ;
3845
3846 netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
3847
3848 ndev->irq = pdev->irq;
3849
3850 /* make sure the EEPROM is good */
3851 if (ql_get_nvram_params(qdev)) {
3852 pr_alert("%s: Adapter #%d, Invalid NVRAM parameters\n",
3853 __func__, qdev->index);
3854 err = -EIO;
3855 goto err_out_iounmap;
3856 }
3857
3858 ql_set_mac_info(qdev);
3859
3860 /* Validate and set parameters */
3861 if (qdev->mac_index) {
3862 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3863 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
3864 } else {
3865 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3866 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
3867 }
3868 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3869
3870 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3871
3872 /* Record PCI bus information. */
3873 ql_get_board_info(qdev);
3874
3875 /*
3876 * Set the Maximum Memory Read Byte Count value. We do this to handle
3877 * jumbo frames.
3878 */
3879 if (qdev->pci_x)
3880 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3881
3882 err = register_netdev(ndev);
3883 if (err) {
3884 pr_err("%s: cannot register net device\n", pci_name(pdev));
3885 goto err_out_iounmap;
3886 }
3887
3888 /* we're going to reset, so assume we have no link for now */
3889
3890 netif_carrier_off(ndev);
3891 netif_stop_queue(ndev);
3892
3893 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3894 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3895 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3896 INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
3897
3898 init_timer(&qdev->adapter_timer);
3899 qdev->adapter_timer.function = ql3xxx_timer;
3900 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3901 qdev->adapter_timer.data = (unsigned long)qdev;
3902
3903 if (!cards_found) {
3904 pr_alert("%s\n", DRV_STRING);
3905 pr_alert("Driver name: %s, Version: %s\n",
3906 DRV_NAME, DRV_VERSION);
3907 }
3908 ql_display_dev_info(ndev);
3909
3910 cards_found++;
3911 return 0;
3912
3913err_out_iounmap:
3914 iounmap(qdev->mem_map_registers);
3915err_out_free_ndev:
3916 free_netdev(ndev);
3917err_out_free_regions:
3918 pci_release_regions(pdev);
3919err_out_disable_pdev:
3920 pci_disable_device(pdev);
3921 pci_set_drvdata(pdev, NULL);
3922err_out:
3923 return err;
3924}
3925
3926static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3927{
3928 struct net_device *ndev = pci_get_drvdata(pdev);
3929 struct ql3_adapter *qdev = netdev_priv(ndev);
3930
3931 unregister_netdev(ndev);
3932
3933 ql_disable_interrupts(qdev);
3934
3935 if (qdev->workqueue) {
3936 cancel_delayed_work(&qdev->reset_work);
3937 cancel_delayed_work(&qdev->tx_timeout_work);
3938 destroy_workqueue(qdev->workqueue);
3939 qdev->workqueue = NULL;
3940 }
3941
3942 iounmap(qdev->mem_map_registers);
3943 pci_release_regions(pdev);
3944 pci_set_drvdata(pdev, NULL);
3945 free_netdev(ndev);
3946}
3947
3948static struct pci_driver ql3xxx_driver = {
3949
3950 .name = DRV_NAME,
3951 .id_table = ql3xxx_pci_tbl,
3952 .probe = ql3xxx_probe,
3953 .remove = __devexit_p(ql3xxx_remove),
3954};
3955
3956static int __init ql3xxx_init_module(void)
3957{
3958 return pci_register_driver(&ql3xxx_driver);
3959}
3960
3961static void __exit ql3xxx_exit(void)
3962{
3963 pci_unregister_driver(&ql3xxx_driver);
3964}
3965
3966module_init(ql3xxx_init_module);
3967module_exit(ql3xxx_exit);