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1/*
2 * Copyright (c) 2012, 2013 Intel Corporation. All rights reserved.
3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/vmalloc.h>
38#include <linux/delay.h>
39#include <linux/module.h>
40#include <linux/printk.h>
41#ifdef CONFIG_INFINIBAND_QIB_DCA
42#include <linux/dca.h>
43#endif
44#include <rdma/rdma_vt.h>
45
46#include "qib.h"
47#include "qib_common.h"
48#include "qib_mad.h"
49#ifdef CONFIG_DEBUG_FS
50#include "qib_debugfs.h"
51#include "qib_verbs.h"
52#endif
53
54#undef pr_fmt
55#define pr_fmt(fmt) QIB_DRV_NAME ": " fmt
56
57/*
58 * min buffers we want to have per context, after driver
59 */
60#define QIB_MIN_USER_CTXT_BUFCNT 7
61
62#define QLOGIC_IB_R_SOFTWARE_MASK 0xFF
63#define QLOGIC_IB_R_SOFTWARE_SHIFT 24
64#define QLOGIC_IB_R_EMULATOR_MASK (1ULL<<62)
65
66/*
67 * Number of ctxts we are configured to use (to allow for more pio
68 * buffers per ctxt, etc.) Zero means use chip value.
69 */
70ushort qib_cfgctxts;
71module_param_named(cfgctxts, qib_cfgctxts, ushort, S_IRUGO);
72MODULE_PARM_DESC(cfgctxts, "Set max number of contexts to use");
73
74unsigned qib_numa_aware;
75module_param_named(numa_aware, qib_numa_aware, uint, S_IRUGO);
76MODULE_PARM_DESC(numa_aware,
77 "0 -> PSM allocation close to HCA, 1 -> PSM allocation local to process");
78
79/*
80 * If set, do not write to any regs if avoidable, hack to allow
81 * check for deranged default register values.
82 */
83ushort qib_mini_init;
84module_param_named(mini_init, qib_mini_init, ushort, S_IRUGO);
85MODULE_PARM_DESC(mini_init, "If set, do minimal diag init");
86
87unsigned qib_n_krcv_queues;
88module_param_named(krcvqs, qib_n_krcv_queues, uint, S_IRUGO);
89MODULE_PARM_DESC(krcvqs, "number of kernel receive queues per IB port");
90
91unsigned qib_cc_table_size;
92module_param_named(cc_table_size, qib_cc_table_size, uint, S_IRUGO);
93MODULE_PARM_DESC(cc_table_size, "Congestion control table entries 0 (CCA disabled - default), min = 128, max = 1984");
94
95static void verify_interrupt(struct timer_list *);
96
97DEFINE_XARRAY_FLAGS(qib_dev_table, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);
98u32 qib_cpulist_count;
99unsigned long *qib_cpulist;
100
101/* set number of contexts we'll actually use */
102void qib_set_ctxtcnt(struct qib_devdata *dd)
103{
104 if (!qib_cfgctxts) {
105 dd->cfgctxts = dd->first_user_ctxt + num_online_cpus();
106 if (dd->cfgctxts > dd->ctxtcnt)
107 dd->cfgctxts = dd->ctxtcnt;
108 } else if (qib_cfgctxts < dd->num_pports)
109 dd->cfgctxts = dd->ctxtcnt;
110 else if (qib_cfgctxts <= dd->ctxtcnt)
111 dd->cfgctxts = qib_cfgctxts;
112 else
113 dd->cfgctxts = dd->ctxtcnt;
114 dd->freectxts = (dd->first_user_ctxt > dd->cfgctxts) ? 0 :
115 dd->cfgctxts - dd->first_user_ctxt;
116}
117
118/*
119 * Common code for creating the receive context array.
120 */
121int qib_create_ctxts(struct qib_devdata *dd)
122{
123 unsigned i;
124 int local_node_id = pcibus_to_node(dd->pcidev->bus);
125
126 if (local_node_id < 0)
127 local_node_id = numa_node_id();
128 dd->assigned_node_id = local_node_id;
129
130 /*
131 * Allocate full ctxtcnt array, rather than just cfgctxts, because
132 * cleanup iterates across all possible ctxts.
133 */
134 dd->rcd = kcalloc(dd->ctxtcnt, sizeof(*dd->rcd), GFP_KERNEL);
135 if (!dd->rcd)
136 return -ENOMEM;
137
138 /* create (one or more) kctxt */
139 for (i = 0; i < dd->first_user_ctxt; ++i) {
140 struct qib_pportdata *ppd;
141 struct qib_ctxtdata *rcd;
142
143 if (dd->skip_kctxt_mask & (1 << i))
144 continue;
145
146 ppd = dd->pport + (i % dd->num_pports);
147
148 rcd = qib_create_ctxtdata(ppd, i, dd->assigned_node_id);
149 if (!rcd) {
150 qib_dev_err(dd,
151 "Unable to allocate ctxtdata for Kernel ctxt, failing\n");
152 kfree(dd->rcd);
153 dd->rcd = NULL;
154 return -ENOMEM;
155 }
156 rcd->pkeys[0] = QIB_DEFAULT_P_KEY;
157 rcd->seq_cnt = 1;
158 }
159 return 0;
160}
161
162/*
163 * Common code for user and kernel context setup.
164 */
165struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *ppd, u32 ctxt,
166 int node_id)
167{
168 struct qib_devdata *dd = ppd->dd;
169 struct qib_ctxtdata *rcd;
170
171 rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, node_id);
172 if (rcd) {
173 INIT_LIST_HEAD(&rcd->qp_wait_list);
174 rcd->node_id = node_id;
175 rcd->ppd = ppd;
176 rcd->dd = dd;
177 rcd->cnt = 1;
178 rcd->ctxt = ctxt;
179 dd->rcd[ctxt] = rcd;
180#ifdef CONFIG_DEBUG_FS
181 if (ctxt < dd->first_user_ctxt) { /* N/A for PSM contexts */
182 rcd->opstats = kzalloc_node(sizeof(*rcd->opstats),
183 GFP_KERNEL, node_id);
184 if (!rcd->opstats) {
185 kfree(rcd);
186 qib_dev_err(dd,
187 "Unable to allocate per ctxt stats buffer\n");
188 return NULL;
189 }
190 }
191#endif
192 dd->f_init_ctxt(rcd);
193
194 /*
195 * To avoid wasting a lot of memory, we allocate 32KB chunks
196 * of physically contiguous memory, advance through it until
197 * used up and then allocate more. Of course, we need
198 * memory to store those extra pointers, now. 32KB seems to
199 * be the most that is "safe" under memory pressure
200 * (creating large files and then copying them over
201 * NFS while doing lots of MPI jobs). The OOM killer can
202 * get invoked, even though we say we can sleep and this can
203 * cause significant system problems....
204 */
205 rcd->rcvegrbuf_size = 0x8000;
206 rcd->rcvegrbufs_perchunk =
207 rcd->rcvegrbuf_size / dd->rcvegrbufsize;
208 rcd->rcvegrbuf_chunks = (rcd->rcvegrcnt +
209 rcd->rcvegrbufs_perchunk - 1) /
210 rcd->rcvegrbufs_perchunk;
211 rcd->rcvegrbufs_perchunk_shift =
212 ilog2(rcd->rcvegrbufs_perchunk);
213 }
214 return rcd;
215}
216
217/*
218 * Common code for initializing the physical port structure.
219 */
220int qib_init_pportdata(struct qib_pportdata *ppd, struct qib_devdata *dd,
221 u8 hw_pidx, u8 port)
222{
223 int size;
224
225 ppd->dd = dd;
226 ppd->hw_pidx = hw_pidx;
227 ppd->port = port; /* IB port number, not index */
228
229 spin_lock_init(&ppd->sdma_lock);
230 spin_lock_init(&ppd->lflags_lock);
231 spin_lock_init(&ppd->cc_shadow_lock);
232 init_waitqueue_head(&ppd->state_wait);
233
234 timer_setup(&ppd->symerr_clear_timer, qib_clear_symerror_on_linkup, 0);
235
236 ppd->qib_wq = NULL;
237 ppd->ibport_data.pmastats =
238 alloc_percpu(struct qib_pma_counters);
239 if (!ppd->ibport_data.pmastats)
240 return -ENOMEM;
241 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
242 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
243 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
244 if (!(ppd->ibport_data.rvp.rc_acks) ||
245 !(ppd->ibport_data.rvp.rc_qacks) ||
246 !(ppd->ibport_data.rvp.rc_delayed_comp))
247 return -ENOMEM;
248
249 if (qib_cc_table_size < IB_CCT_MIN_ENTRIES)
250 goto bail;
251
252 ppd->cc_supported_table_entries = min(max_t(int, qib_cc_table_size,
253 IB_CCT_MIN_ENTRIES), IB_CCT_ENTRIES*IB_CC_TABLE_CAP_DEFAULT);
254
255 ppd->cc_max_table_entries =
256 ppd->cc_supported_table_entries/IB_CCT_ENTRIES;
257
258 size = IB_CC_TABLE_CAP_DEFAULT * sizeof(struct ib_cc_table_entry)
259 * IB_CCT_ENTRIES;
260 ppd->ccti_entries = kzalloc(size, GFP_KERNEL);
261 if (!ppd->ccti_entries)
262 goto bail;
263
264 size = IB_CC_CCS_ENTRIES * sizeof(struct ib_cc_congestion_entry);
265 ppd->congestion_entries = kzalloc(size, GFP_KERNEL);
266 if (!ppd->congestion_entries)
267 goto bail_1;
268
269 size = sizeof(struct cc_table_shadow);
270 ppd->ccti_entries_shadow = kzalloc(size, GFP_KERNEL);
271 if (!ppd->ccti_entries_shadow)
272 goto bail_2;
273
274 size = sizeof(struct ib_cc_congestion_setting_attr);
275 ppd->congestion_entries_shadow = kzalloc(size, GFP_KERNEL);
276 if (!ppd->congestion_entries_shadow)
277 goto bail_3;
278
279 return 0;
280
281bail_3:
282 kfree(ppd->ccti_entries_shadow);
283 ppd->ccti_entries_shadow = NULL;
284bail_2:
285 kfree(ppd->congestion_entries);
286 ppd->congestion_entries = NULL;
287bail_1:
288 kfree(ppd->ccti_entries);
289 ppd->ccti_entries = NULL;
290bail:
291 /* User is intentionally disabling the congestion control agent */
292 if (!qib_cc_table_size)
293 return 0;
294
295 if (qib_cc_table_size < IB_CCT_MIN_ENTRIES) {
296 qib_cc_table_size = 0;
297 qib_dev_err(dd,
298 "Congestion Control table size %d less than minimum %d for port %d\n",
299 qib_cc_table_size, IB_CCT_MIN_ENTRIES, port);
300 }
301
302 qib_dev_err(dd, "Congestion Control Agent disabled for port %d\n",
303 port);
304 return 0;
305}
306
307static int init_pioavailregs(struct qib_devdata *dd)
308{
309 int ret, pidx;
310 u64 *status_page;
311
312 dd->pioavailregs_dma = dma_alloc_coherent(
313 &dd->pcidev->dev, PAGE_SIZE, &dd->pioavailregs_phys,
314 GFP_KERNEL);
315 if (!dd->pioavailregs_dma) {
316 qib_dev_err(dd,
317 "failed to allocate PIOavail reg area in memory\n");
318 ret = -ENOMEM;
319 goto done;
320 }
321
322 /*
323 * We really want L2 cache aligned, but for current CPUs of
324 * interest, they are the same.
325 */
326 status_page = (u64 *)
327 ((char *) dd->pioavailregs_dma +
328 ((2 * L1_CACHE_BYTES +
329 dd->pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
330 /* device status comes first, for backwards compatibility */
331 dd->devstatusp = status_page;
332 *status_page++ = 0;
333 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
334 dd->pport[pidx].statusp = status_page;
335 *status_page++ = 0;
336 }
337
338 /*
339 * Setup buffer to hold freeze and other messages, accessible to
340 * apps, following statusp. This is per-unit, not per port.
341 */
342 dd->freezemsg = (char *) status_page;
343 *dd->freezemsg = 0;
344 /* length of msg buffer is "whatever is left" */
345 ret = (char *) status_page - (char *) dd->pioavailregs_dma;
346 dd->freezelen = PAGE_SIZE - ret;
347
348 ret = 0;
349
350done:
351 return ret;
352}
353
354/**
355 * init_shadow_tids - allocate the shadow TID array
356 * @dd: the qlogic_ib device
357 *
358 * allocate the shadow TID array, so we can qib_munlock previous
359 * entries. It may make more sense to move the pageshadow to the
360 * ctxt data structure, so we only allocate memory for ctxts actually
361 * in use, since we at 8k per ctxt, now.
362 * We don't want failures here to prevent use of the driver/chip,
363 * so no return value.
364 */
365static void init_shadow_tids(struct qib_devdata *dd)
366{
367 struct page **pages;
368 dma_addr_t *addrs;
369
370 pages = vzalloc(array_size(sizeof(struct page *),
371 dd->cfgctxts * dd->rcvtidcnt));
372 if (!pages)
373 goto bail;
374
375 addrs = vzalloc(array_size(sizeof(dma_addr_t),
376 dd->cfgctxts * dd->rcvtidcnt));
377 if (!addrs)
378 goto bail_free;
379
380 dd->pageshadow = pages;
381 dd->physshadow = addrs;
382 return;
383
384bail_free:
385 vfree(pages);
386bail:
387 dd->pageshadow = NULL;
388}
389
390/*
391 * Do initialization for device that is only needed on
392 * first detect, not on resets.
393 */
394static int loadtime_init(struct qib_devdata *dd)
395{
396 int ret = 0;
397
398 if (((dd->revision >> QLOGIC_IB_R_SOFTWARE_SHIFT) &
399 QLOGIC_IB_R_SOFTWARE_MASK) != QIB_CHIP_SWVERSION) {
400 qib_dev_err(dd,
401 "Driver only handles version %d, chip swversion is %d (%llx), failing\n",
402 QIB_CHIP_SWVERSION,
403 (int)(dd->revision >>
404 QLOGIC_IB_R_SOFTWARE_SHIFT) &
405 QLOGIC_IB_R_SOFTWARE_MASK,
406 (unsigned long long) dd->revision);
407 ret = -ENOSYS;
408 goto done;
409 }
410
411 if (dd->revision & QLOGIC_IB_R_EMULATOR_MASK)
412 qib_devinfo(dd->pcidev, "%s", dd->boardversion);
413
414 spin_lock_init(&dd->pioavail_lock);
415 spin_lock_init(&dd->sendctrl_lock);
416 spin_lock_init(&dd->uctxt_lock);
417 spin_lock_init(&dd->qib_diag_trans_lock);
418 spin_lock_init(&dd->eep_st_lock);
419 mutex_init(&dd->eep_lock);
420
421 if (qib_mini_init)
422 goto done;
423
424 ret = init_pioavailregs(dd);
425 init_shadow_tids(dd);
426
427 qib_get_eeprom_info(dd);
428
429 /* setup time (don't start yet) to verify we got interrupt */
430 timer_setup(&dd->intrchk_timer, verify_interrupt, 0);
431done:
432 return ret;
433}
434
435/**
436 * init_after_reset - re-initialize after a reset
437 * @dd: the qlogic_ib device
438 *
439 * sanity check at least some of the values after reset, and
440 * ensure no receive or transmit (explicitly, in case reset
441 * failed
442 */
443static int init_after_reset(struct qib_devdata *dd)
444{
445 int i;
446
447 /*
448 * Ensure chip does no sends or receives, tail updates, or
449 * pioavail updates while we re-initialize. This is mostly
450 * for the driver data structures, not chip registers.
451 */
452 for (i = 0; i < dd->num_pports; ++i) {
453 /*
454 * ctxt == -1 means "all contexts". Only really safe for
455 * _dis_abling things, as here.
456 */
457 dd->f_rcvctrl(dd->pport + i, QIB_RCVCTRL_CTXT_DIS |
458 QIB_RCVCTRL_INTRAVAIL_DIS |
459 QIB_RCVCTRL_TAILUPD_DIS, -1);
460 /* Redundant across ports for some, but no big deal. */
461 dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_DIS |
462 QIB_SENDCTRL_AVAIL_DIS);
463 }
464
465 return 0;
466}
467
468static void enable_chip(struct qib_devdata *dd)
469{
470 u64 rcvmask;
471 int i;
472
473 /*
474 * Enable PIO send, and update of PIOavail regs to memory.
475 */
476 for (i = 0; i < dd->num_pports; ++i)
477 dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_ENB |
478 QIB_SENDCTRL_AVAIL_ENB);
479 /*
480 * Enable kernel ctxts' receive and receive interrupt.
481 * Other ctxts done as user opens and inits them.
482 */
483 rcvmask = QIB_RCVCTRL_CTXT_ENB | QIB_RCVCTRL_INTRAVAIL_ENB;
484 rcvmask |= (dd->flags & QIB_NODMA_RTAIL) ?
485 QIB_RCVCTRL_TAILUPD_DIS : QIB_RCVCTRL_TAILUPD_ENB;
486 for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
487 struct qib_ctxtdata *rcd = dd->rcd[i];
488
489 if (rcd)
490 dd->f_rcvctrl(rcd->ppd, rcvmask, i);
491 }
492}
493
494static void verify_interrupt(struct timer_list *t)
495{
496 struct qib_devdata *dd = from_timer(dd, t, intrchk_timer);
497 u64 int_counter;
498
499 if (!dd)
500 return; /* being torn down */
501
502 /*
503 * If we don't have a lid or any interrupts, let the user know and
504 * don't bother checking again.
505 */
506 int_counter = qib_int_counter(dd) - dd->z_int_counter;
507 if (int_counter == 0) {
508 if (!dd->f_intr_fallback(dd))
509 dev_err(&dd->pcidev->dev,
510 "No interrupts detected, not usable.\n");
511 else /* re-arm the timer to see if fallback works */
512 mod_timer(&dd->intrchk_timer, jiffies + HZ/2);
513 }
514}
515
516static void init_piobuf_state(struct qib_devdata *dd)
517{
518 int i, pidx;
519 u32 uctxts;
520
521 /*
522 * Ensure all buffers are free, and fifos empty. Buffers
523 * are common, so only do once for port 0.
524 *
525 * After enable and qib_chg_pioavailkernel so we can safely
526 * enable pioavail updates and PIOENABLE. After this, packets
527 * are ready and able to go out.
528 */
529 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_ALL);
530 for (pidx = 0; pidx < dd->num_pports; ++pidx)
531 dd->f_sendctrl(dd->pport + pidx, QIB_SENDCTRL_FLUSH);
532
533 /*
534 * If not all sendbufs are used, add the one to each of the lower
535 * numbered contexts. pbufsctxt and lastctxt_piobuf are
536 * calculated in chip-specific code because it may cause some
537 * chip-specific adjustments to be made.
538 */
539 uctxts = dd->cfgctxts - dd->first_user_ctxt;
540 dd->ctxts_extrabuf = dd->pbufsctxt ?
541 dd->lastctxt_piobuf - (dd->pbufsctxt * uctxts) : 0;
542
543 /*
544 * Set up the shadow copies of the piobufavail registers,
545 * which we compare against the chip registers for now, and
546 * the in memory DMA'ed copies of the registers.
547 * By now pioavail updates to memory should have occurred, so
548 * copy them into our working/shadow registers; this is in
549 * case something went wrong with abort, but mostly to get the
550 * initial values of the generation bit correct.
551 */
552 for (i = 0; i < dd->pioavregs; i++) {
553 __le64 tmp;
554
555 tmp = dd->pioavailregs_dma[i];
556 /*
557 * Don't need to worry about pioavailkernel here
558 * because we will call qib_chg_pioavailkernel() later
559 * in initialization, to busy out buffers as needed.
560 */
561 dd->pioavailshadow[i] = le64_to_cpu(tmp);
562 }
563 while (i < ARRAY_SIZE(dd->pioavailshadow))
564 dd->pioavailshadow[i++] = 0; /* for debugging sanity */
565
566 /* after pioavailshadow is setup */
567 qib_chg_pioavailkernel(dd, 0, dd->piobcnt2k + dd->piobcnt4k,
568 TXCHK_CHG_TYPE_KERN, NULL);
569 dd->f_initvl15_bufs(dd);
570}
571
572/**
573 * qib_create_workqueues - create per port workqueues
574 * @dd: the qlogic_ib device
575 */
576static int qib_create_workqueues(struct qib_devdata *dd)
577{
578 int pidx;
579 struct qib_pportdata *ppd;
580
581 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
582 ppd = dd->pport + pidx;
583 if (!ppd->qib_wq) {
584 char wq_name[8]; /* 3 + 2 + 1 + 1 + 1 */
585
586 snprintf(wq_name, sizeof(wq_name), "qib%d_%d",
587 dd->unit, pidx);
588 ppd->qib_wq = alloc_ordered_workqueue(wq_name,
589 WQ_MEM_RECLAIM);
590 if (!ppd->qib_wq)
591 goto wq_error;
592 }
593 }
594 return 0;
595wq_error:
596 pr_err("create_singlethread_workqueue failed for port %d\n",
597 pidx + 1);
598 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
599 ppd = dd->pport + pidx;
600 if (ppd->qib_wq) {
601 destroy_workqueue(ppd->qib_wq);
602 ppd->qib_wq = NULL;
603 }
604 }
605 return -ENOMEM;
606}
607
608static void qib_free_pportdata(struct qib_pportdata *ppd)
609{
610 free_percpu(ppd->ibport_data.pmastats);
611 free_percpu(ppd->ibport_data.rvp.rc_acks);
612 free_percpu(ppd->ibport_data.rvp.rc_qacks);
613 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
614 ppd->ibport_data.pmastats = NULL;
615}
616
617/**
618 * qib_init - do the actual initialization sequence on the chip
619 * @dd: the qlogic_ib device
620 * @reinit: reinitializing, so don't allocate new memory
621 *
622 * Do the actual initialization sequence on the chip. This is done
623 * both from the init routine called from the PCI infrastructure, and
624 * when we reset the chip, or detect that it was reset internally,
625 * or it's administratively re-enabled.
626 *
627 * Memory allocation here and in called routines is only done in
628 * the first case (reinit == 0). We have to be careful, because even
629 * without memory allocation, we need to re-write all the chip registers
630 * TIDs, etc. after the reset or enable has completed.
631 */
632int qib_init(struct qib_devdata *dd, int reinit)
633{
634 int ret = 0, pidx, lastfail = 0;
635 u32 portok = 0;
636 unsigned i;
637 struct qib_ctxtdata *rcd;
638 struct qib_pportdata *ppd;
639 unsigned long flags;
640
641 /* Set linkstate to unknown, so we can watch for a transition. */
642 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
643 ppd = dd->pport + pidx;
644 spin_lock_irqsave(&ppd->lflags_lock, flags);
645 ppd->lflags &= ~(QIBL_LINKACTIVE | QIBL_LINKARMED |
646 QIBL_LINKDOWN | QIBL_LINKINIT |
647 QIBL_LINKV);
648 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
649 }
650
651 if (reinit)
652 ret = init_after_reset(dd);
653 else
654 ret = loadtime_init(dd);
655 if (ret)
656 goto done;
657
658 /* Bypass most chip-init, to get to device creation */
659 if (qib_mini_init)
660 return 0;
661
662 ret = dd->f_late_initreg(dd);
663 if (ret)
664 goto done;
665
666 /* dd->rcd can be NULL if early init failed */
667 for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
668 /*
669 * Set up the (kernel) rcvhdr queue and egr TIDs. If doing
670 * re-init, the simplest way to handle this is to free
671 * existing, and re-allocate.
672 * Need to re-create rest of ctxt 0 ctxtdata as well.
673 */
674 rcd = dd->rcd[i];
675 if (!rcd)
676 continue;
677
678 lastfail = qib_create_rcvhdrq(dd, rcd);
679 if (!lastfail)
680 lastfail = qib_setup_eagerbufs(rcd);
681 if (lastfail)
682 qib_dev_err(dd,
683 "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
684 }
685
686 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
687 int mtu;
688
689 if (lastfail)
690 ret = lastfail;
691 ppd = dd->pport + pidx;
692 mtu = ib_mtu_enum_to_int(qib_ibmtu);
693 if (mtu == -1) {
694 mtu = QIB_DEFAULT_MTU;
695 qib_ibmtu = 0; /* don't leave invalid value */
696 }
697 /* set max we can ever have for this driver load */
698 ppd->init_ibmaxlen = min(mtu > 2048 ?
699 dd->piosize4k : dd->piosize2k,
700 dd->rcvegrbufsize +
701 (dd->rcvhdrentsize << 2));
702 /*
703 * Have to initialize ibmaxlen, but this will normally
704 * change immediately in qib_set_mtu().
705 */
706 ppd->ibmaxlen = ppd->init_ibmaxlen;
707 qib_set_mtu(ppd, mtu);
708
709 spin_lock_irqsave(&ppd->lflags_lock, flags);
710 ppd->lflags |= QIBL_IB_LINK_DISABLED;
711 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
712
713 lastfail = dd->f_bringup_serdes(ppd);
714 if (lastfail) {
715 qib_devinfo(dd->pcidev,
716 "Failed to bringup IB port %u\n", ppd->port);
717 lastfail = -ENETDOWN;
718 continue;
719 }
720
721 portok++;
722 }
723
724 if (!portok) {
725 /* none of the ports initialized */
726 if (!ret && lastfail)
727 ret = lastfail;
728 else if (!ret)
729 ret = -ENETDOWN;
730 /* but continue on, so we can debug cause */
731 }
732
733 enable_chip(dd);
734
735 init_piobuf_state(dd);
736
737done:
738 if (!ret) {
739 /* chip is OK for user apps; mark it as initialized */
740 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
741 ppd = dd->pport + pidx;
742 /*
743 * Set status even if port serdes is not initialized
744 * so that diags will work.
745 */
746 *ppd->statusp |= QIB_STATUS_CHIP_PRESENT |
747 QIB_STATUS_INITTED;
748 if (!ppd->link_speed_enabled)
749 continue;
750 if (dd->flags & QIB_HAS_SEND_DMA)
751 ret = qib_setup_sdma(ppd);
752 timer_setup(&ppd->hol_timer, qib_hol_event, 0);
753 ppd->hol_state = QIB_HOL_UP;
754 }
755
756 /* now we can enable all interrupts from the chip */
757 dd->f_set_intr_state(dd, 1);
758
759 /*
760 * Setup to verify we get an interrupt, and fallback
761 * to an alternate if necessary and possible.
762 */
763 mod_timer(&dd->intrchk_timer, jiffies + HZ/2);
764 /* start stats retrieval timer */
765 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
766 }
767
768 /* if ret is non-zero, we probably should do some cleanup here... */
769 return ret;
770}
771
772/*
773 * These next two routines are placeholders in case we don't have per-arch
774 * code for controlling write combining. If explicit control of write
775 * combining is not available, performance will probably be awful.
776 */
777
778int __attribute__((weak)) qib_enable_wc(struct qib_devdata *dd)
779{
780 return -EOPNOTSUPP;
781}
782
783void __attribute__((weak)) qib_disable_wc(struct qib_devdata *dd)
784{
785}
786
787struct qib_devdata *qib_lookup(int unit)
788{
789 return xa_load(&qib_dev_table, unit);
790}
791
792/*
793 * Stop the timers during unit shutdown, or after an error late
794 * in initialization.
795 */
796static void qib_stop_timers(struct qib_devdata *dd)
797{
798 struct qib_pportdata *ppd;
799 int pidx;
800
801 if (dd->stats_timer.function)
802 del_timer_sync(&dd->stats_timer);
803 if (dd->intrchk_timer.function)
804 del_timer_sync(&dd->intrchk_timer);
805 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
806 ppd = dd->pport + pidx;
807 if (ppd->hol_timer.function)
808 del_timer_sync(&ppd->hol_timer);
809 if (ppd->led_override_timer.function) {
810 del_timer_sync(&ppd->led_override_timer);
811 atomic_set(&ppd->led_override_timer_active, 0);
812 }
813 if (ppd->symerr_clear_timer.function)
814 del_timer_sync(&ppd->symerr_clear_timer);
815 }
816}
817
818/**
819 * qib_shutdown_device - shut down a device
820 * @dd: the qlogic_ib device
821 *
822 * This is called to make the device quiet when we are about to
823 * unload the driver, and also when the device is administratively
824 * disabled. It does not free any data structures.
825 * Everything it does has to be setup again by qib_init(dd, 1)
826 */
827static void qib_shutdown_device(struct qib_devdata *dd)
828{
829 struct qib_pportdata *ppd;
830 unsigned pidx;
831
832 if (dd->flags & QIB_SHUTDOWN)
833 return;
834 dd->flags |= QIB_SHUTDOWN;
835
836 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
837 ppd = dd->pport + pidx;
838
839 spin_lock_irq(&ppd->lflags_lock);
840 ppd->lflags &= ~(QIBL_LINKDOWN | QIBL_LINKINIT |
841 QIBL_LINKARMED | QIBL_LINKACTIVE |
842 QIBL_LINKV);
843 spin_unlock_irq(&ppd->lflags_lock);
844 *ppd->statusp &= ~(QIB_STATUS_IB_CONF | QIB_STATUS_IB_READY);
845 }
846 dd->flags &= ~QIB_INITTED;
847
848 /* mask interrupts, but not errors */
849 dd->f_set_intr_state(dd, 0);
850
851 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
852 ppd = dd->pport + pidx;
853 dd->f_rcvctrl(ppd, QIB_RCVCTRL_TAILUPD_DIS |
854 QIB_RCVCTRL_CTXT_DIS |
855 QIB_RCVCTRL_INTRAVAIL_DIS |
856 QIB_RCVCTRL_PKEY_ENB, -1);
857 /*
858 * Gracefully stop all sends allowing any in progress to
859 * trickle out first.
860 */
861 dd->f_sendctrl(ppd, QIB_SENDCTRL_CLEAR);
862 }
863
864 /*
865 * Enough for anything that's going to trickle out to have actually
866 * done so.
867 */
868 udelay(20);
869
870 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
871 ppd = dd->pport + pidx;
872 dd->f_setextled(ppd, 0); /* make sure LEDs are off */
873
874 if (dd->flags & QIB_HAS_SEND_DMA)
875 qib_teardown_sdma(ppd);
876
877 dd->f_sendctrl(ppd, QIB_SENDCTRL_AVAIL_DIS |
878 QIB_SENDCTRL_SEND_DIS);
879 /*
880 * Clear SerdesEnable.
881 * We can't count on interrupts since we are stopping.
882 */
883 dd->f_quiet_serdes(ppd);
884
885 if (ppd->qib_wq) {
886 destroy_workqueue(ppd->qib_wq);
887 ppd->qib_wq = NULL;
888 }
889 qib_free_pportdata(ppd);
890 }
891
892}
893
894/**
895 * qib_free_ctxtdata - free a context's allocated data
896 * @dd: the qlogic_ib device
897 * @rcd: the ctxtdata structure
898 *
899 * free up any allocated data for a context
900 * This should not touch anything that would affect a simultaneous
901 * re-allocation of context data, because it is called after qib_mutex
902 * is released (and can be called from reinit as well).
903 * It should never change any chip state, or global driver state.
904 */
905void qib_free_ctxtdata(struct qib_devdata *dd, struct qib_ctxtdata *rcd)
906{
907 if (!rcd)
908 return;
909
910 if (rcd->rcvhdrq) {
911 dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size,
912 rcd->rcvhdrq, rcd->rcvhdrq_phys);
913 rcd->rcvhdrq = NULL;
914 if (rcd->rcvhdrtail_kvaddr) {
915 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
916 rcd->rcvhdrtail_kvaddr,
917 rcd->rcvhdrqtailaddr_phys);
918 rcd->rcvhdrtail_kvaddr = NULL;
919 }
920 }
921 if (rcd->rcvegrbuf) {
922 unsigned e;
923
924 for (e = 0; e < rcd->rcvegrbuf_chunks; e++) {
925 void *base = rcd->rcvegrbuf[e];
926 size_t size = rcd->rcvegrbuf_size;
927
928 dma_free_coherent(&dd->pcidev->dev, size,
929 base, rcd->rcvegrbuf_phys[e]);
930 }
931 kfree(rcd->rcvegrbuf);
932 rcd->rcvegrbuf = NULL;
933 kfree(rcd->rcvegrbuf_phys);
934 rcd->rcvegrbuf_phys = NULL;
935 rcd->rcvegrbuf_chunks = 0;
936 }
937
938 kfree(rcd->tid_pg_list);
939 vfree(rcd->user_event_mask);
940 vfree(rcd->subctxt_uregbase);
941 vfree(rcd->subctxt_rcvegrbuf);
942 vfree(rcd->subctxt_rcvhdr_base);
943#ifdef CONFIG_DEBUG_FS
944 kfree(rcd->opstats);
945 rcd->opstats = NULL;
946#endif
947 kfree(rcd);
948}
949
950/*
951 * Perform a PIO buffer bandwidth write test, to verify proper system
952 * configuration. Even when all the setup calls work, occasionally
953 * BIOS or other issues can prevent write combining from working, or
954 * can cause other bandwidth problems to the chip.
955 *
956 * This test simply writes the same buffer over and over again, and
957 * measures close to the peak bandwidth to the chip (not testing
958 * data bandwidth to the wire). On chips that use an address-based
959 * trigger to send packets to the wire, this is easy. On chips that
960 * use a count to trigger, we want to make sure that the packet doesn't
961 * go out on the wire, or trigger flow control checks.
962 */
963static void qib_verify_pioperf(struct qib_devdata *dd)
964{
965 u32 pbnum, cnt, lcnt;
966 u32 __iomem *piobuf;
967 u32 *addr;
968 u64 msecs, emsecs;
969
970 piobuf = dd->f_getsendbuf(dd->pport, 0ULL, &pbnum);
971 if (!piobuf) {
972 qib_devinfo(dd->pcidev,
973 "No PIObufs for checking perf, skipping\n");
974 return;
975 }
976
977 /*
978 * Enough to give us a reasonable test, less than piobuf size, and
979 * likely multiple of store buffer length.
980 */
981 cnt = 1024;
982
983 addr = vmalloc(cnt);
984 if (!addr)
985 goto done;
986
987 preempt_disable(); /* we want reasonably accurate elapsed time */
988 msecs = 1 + jiffies_to_msecs(jiffies);
989 for (lcnt = 0; lcnt < 10000U; lcnt++) {
990 /* wait until we cross msec boundary */
991 if (jiffies_to_msecs(jiffies) >= msecs)
992 break;
993 udelay(1);
994 }
995
996 dd->f_set_armlaunch(dd, 0);
997
998 /*
999 * length 0, no dwords actually sent
1000 */
1001 writeq(0, piobuf);
1002 qib_flush_wc();
1003
1004 /*
1005 * This is only roughly accurate, since even with preempt we
1006 * still take interrupts that could take a while. Running for
1007 * >= 5 msec seems to get us "close enough" to accurate values.
1008 */
1009 msecs = jiffies_to_msecs(jiffies);
1010 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
1011 qib_pio_copy(piobuf + 64, addr, cnt >> 2);
1012 emsecs = jiffies_to_msecs(jiffies) - msecs;
1013 }
1014
1015 /* 1 GiB/sec, slightly over IB SDR line rate */
1016 if (lcnt < (emsecs * 1024U))
1017 qib_dev_err(dd,
1018 "Performance problem: bandwidth to PIO buffers is only %u MiB/sec\n",
1019 lcnt / (u32) emsecs);
1020
1021 preempt_enable();
1022
1023 vfree(addr);
1024
1025done:
1026 /* disarm piobuf, so it's available again */
1027 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(pbnum));
1028 qib_sendbuf_done(dd, pbnum);
1029 dd->f_set_armlaunch(dd, 1);
1030}
1031
1032void qib_free_devdata(struct qib_devdata *dd)
1033{
1034 unsigned long flags;
1035
1036 xa_lock_irqsave(&qib_dev_table, flags);
1037 __xa_erase(&qib_dev_table, dd->unit);
1038 xa_unlock_irqrestore(&qib_dev_table, flags);
1039
1040#ifdef CONFIG_DEBUG_FS
1041 qib_dbg_ibdev_exit(&dd->verbs_dev);
1042#endif
1043 free_percpu(dd->int_counter);
1044 rvt_dealloc_device(&dd->verbs_dev.rdi);
1045}
1046
1047u64 qib_int_counter(struct qib_devdata *dd)
1048{
1049 int cpu;
1050 u64 int_counter = 0;
1051
1052 for_each_possible_cpu(cpu)
1053 int_counter += *per_cpu_ptr(dd->int_counter, cpu);
1054 return int_counter;
1055}
1056
1057u64 qib_sps_ints(void)
1058{
1059 unsigned long index, flags;
1060 struct qib_devdata *dd;
1061 u64 sps_ints = 0;
1062
1063 xa_lock_irqsave(&qib_dev_table, flags);
1064 xa_for_each(&qib_dev_table, index, dd) {
1065 sps_ints += qib_int_counter(dd);
1066 }
1067 xa_unlock_irqrestore(&qib_dev_table, flags);
1068 return sps_ints;
1069}
1070
1071/*
1072 * Allocate our primary per-unit data structure. Must be done via verbs
1073 * allocator, because the verbs cleanup process both does cleanup and
1074 * free of the data structure.
1075 * "extra" is for chip-specific data.
1076 */
1077struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra)
1078{
1079 struct qib_devdata *dd;
1080 int ret, nports;
1081
1082 /* extra is * number of ports */
1083 nports = extra / sizeof(struct qib_pportdata);
1084 dd = (struct qib_devdata *)rvt_alloc_device(sizeof(*dd) + extra,
1085 nports);
1086 if (!dd)
1087 return ERR_PTR(-ENOMEM);
1088
1089 ret = xa_alloc_irq(&qib_dev_table, &dd->unit, dd, xa_limit_32b,
1090 GFP_KERNEL);
1091 if (ret < 0) {
1092 qib_early_err(&pdev->dev,
1093 "Could not allocate unit ID: error %d\n", -ret);
1094 goto bail;
1095 }
1096 rvt_set_ibdev_name(&dd->verbs_dev.rdi, "%s%d", "qib", dd->unit);
1097
1098 dd->int_counter = alloc_percpu(u64);
1099 if (!dd->int_counter) {
1100 ret = -ENOMEM;
1101 qib_early_err(&pdev->dev,
1102 "Could not allocate per-cpu int_counter\n");
1103 goto bail;
1104 }
1105
1106 if (!qib_cpulist_count) {
1107 u32 count = num_online_cpus();
1108
1109 qib_cpulist = bitmap_zalloc(count, GFP_KERNEL);
1110 if (qib_cpulist)
1111 qib_cpulist_count = count;
1112 }
1113#ifdef CONFIG_DEBUG_FS
1114 qib_dbg_ibdev_init(&dd->verbs_dev);
1115#endif
1116 return dd;
1117bail:
1118 if (!list_empty(&dd->list))
1119 list_del_init(&dd->list);
1120 rvt_dealloc_device(&dd->verbs_dev.rdi);
1121 return ERR_PTR(ret);
1122}
1123
1124/*
1125 * Called from freeze mode handlers, and from PCI error
1126 * reporting code. Should be paranoid about state of
1127 * system and data structures.
1128 */
1129void qib_disable_after_error(struct qib_devdata *dd)
1130{
1131 if (dd->flags & QIB_INITTED) {
1132 u32 pidx;
1133
1134 dd->flags &= ~QIB_INITTED;
1135 if (dd->pport)
1136 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1137 struct qib_pportdata *ppd;
1138
1139 ppd = dd->pport + pidx;
1140 if (dd->flags & QIB_PRESENT) {
1141 qib_set_linkstate(ppd,
1142 QIB_IB_LINKDOWN_DISABLE);
1143 dd->f_setextled(ppd, 0);
1144 }
1145 *ppd->statusp &= ~QIB_STATUS_IB_READY;
1146 }
1147 }
1148
1149 /*
1150 * Mark as having had an error for driver, and also
1151 * for /sys and status word mapped to user programs.
1152 * This marks unit as not usable, until reset.
1153 */
1154 if (dd->devstatusp)
1155 *dd->devstatusp |= QIB_STATUS_HWERROR;
1156}
1157
1158static void qib_remove_one(struct pci_dev *);
1159static int qib_init_one(struct pci_dev *, const struct pci_device_id *);
1160static void qib_shutdown_one(struct pci_dev *);
1161
1162#define DRIVER_LOAD_MSG "Intel " QIB_DRV_NAME " loaded: "
1163#define PFX QIB_DRV_NAME ": "
1164
1165static const struct pci_device_id qib_pci_tbl[] = {
1166 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_QLOGIC_IB_6120) },
1167 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7220) },
1168 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7322) },
1169 { 0, }
1170};
1171
1172MODULE_DEVICE_TABLE(pci, qib_pci_tbl);
1173
1174static struct pci_driver qib_driver = {
1175 .name = QIB_DRV_NAME,
1176 .probe = qib_init_one,
1177 .remove = qib_remove_one,
1178 .shutdown = qib_shutdown_one,
1179 .id_table = qib_pci_tbl,
1180 .err_handler = &qib_pci_err_handler,
1181};
1182
1183#ifdef CONFIG_INFINIBAND_QIB_DCA
1184
1185static int qib_notify_dca(struct notifier_block *, unsigned long, void *);
1186static struct notifier_block dca_notifier = {
1187 .notifier_call = qib_notify_dca,
1188 .next = NULL,
1189 .priority = 0
1190};
1191
1192static int qib_notify_dca_device(struct device *device, void *data)
1193{
1194 struct qib_devdata *dd = dev_get_drvdata(device);
1195 unsigned long event = *(unsigned long *)data;
1196
1197 return dd->f_notify_dca(dd, event);
1198}
1199
1200static int qib_notify_dca(struct notifier_block *nb, unsigned long event,
1201 void *p)
1202{
1203 int rval;
1204
1205 rval = driver_for_each_device(&qib_driver.driver, NULL,
1206 &event, qib_notify_dca_device);
1207 return rval ? NOTIFY_BAD : NOTIFY_DONE;
1208}
1209
1210#endif
1211
1212/*
1213 * Do all the generic driver unit- and chip-independent memory
1214 * allocation and initialization.
1215 */
1216static int __init qib_ib_init(void)
1217{
1218 int ret;
1219
1220 ret = qib_dev_init();
1221 if (ret)
1222 goto bail;
1223
1224 /*
1225 * These must be called before the driver is registered with
1226 * the PCI subsystem.
1227 */
1228#ifdef CONFIG_INFINIBAND_QIB_DCA
1229 dca_register_notify(&dca_notifier);
1230#endif
1231#ifdef CONFIG_DEBUG_FS
1232 qib_dbg_init();
1233#endif
1234 ret = pci_register_driver(&qib_driver);
1235 if (ret < 0) {
1236 pr_err("Unable to register driver: error %d\n", -ret);
1237 goto bail_dev;
1238 }
1239
1240 /* not fatal if it doesn't work */
1241 if (qib_init_qibfs())
1242 pr_err("Unable to register ipathfs\n");
1243 goto bail; /* all OK */
1244
1245bail_dev:
1246#ifdef CONFIG_INFINIBAND_QIB_DCA
1247 dca_unregister_notify(&dca_notifier);
1248#endif
1249#ifdef CONFIG_DEBUG_FS
1250 qib_dbg_exit();
1251#endif
1252 qib_dev_cleanup();
1253bail:
1254 return ret;
1255}
1256
1257module_init(qib_ib_init);
1258
1259/*
1260 * Do the non-unit driver cleanup, memory free, etc. at unload.
1261 */
1262static void __exit qib_ib_cleanup(void)
1263{
1264 int ret;
1265
1266 ret = qib_exit_qibfs();
1267 if (ret)
1268 pr_err(
1269 "Unable to cleanup counter filesystem: error %d\n",
1270 -ret);
1271
1272#ifdef CONFIG_INFINIBAND_QIB_DCA
1273 dca_unregister_notify(&dca_notifier);
1274#endif
1275 pci_unregister_driver(&qib_driver);
1276#ifdef CONFIG_DEBUG_FS
1277 qib_dbg_exit();
1278#endif
1279
1280 qib_cpulist_count = 0;
1281 bitmap_free(qib_cpulist);
1282
1283 WARN_ON(!xa_empty(&qib_dev_table));
1284 qib_dev_cleanup();
1285}
1286
1287module_exit(qib_ib_cleanup);
1288
1289/* this can only be called after a successful initialization */
1290static void cleanup_device_data(struct qib_devdata *dd)
1291{
1292 int ctxt;
1293 int pidx;
1294 struct qib_ctxtdata **tmp;
1295 unsigned long flags;
1296
1297 /* users can't do anything more with chip */
1298 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1299 if (dd->pport[pidx].statusp)
1300 *dd->pport[pidx].statusp &= ~QIB_STATUS_CHIP_PRESENT;
1301
1302 spin_lock(&dd->pport[pidx].cc_shadow_lock);
1303
1304 kfree(dd->pport[pidx].congestion_entries);
1305 dd->pport[pidx].congestion_entries = NULL;
1306 kfree(dd->pport[pidx].ccti_entries);
1307 dd->pport[pidx].ccti_entries = NULL;
1308 kfree(dd->pport[pidx].ccti_entries_shadow);
1309 dd->pport[pidx].ccti_entries_shadow = NULL;
1310 kfree(dd->pport[pidx].congestion_entries_shadow);
1311 dd->pport[pidx].congestion_entries_shadow = NULL;
1312
1313 spin_unlock(&dd->pport[pidx].cc_shadow_lock);
1314 }
1315
1316 qib_disable_wc(dd);
1317
1318 if (dd->pioavailregs_dma) {
1319 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1320 (void *) dd->pioavailregs_dma,
1321 dd->pioavailregs_phys);
1322 dd->pioavailregs_dma = NULL;
1323 }
1324
1325 if (dd->pageshadow) {
1326 struct page **tmpp = dd->pageshadow;
1327 dma_addr_t *tmpd = dd->physshadow;
1328 int i;
1329
1330 for (ctxt = 0; ctxt < dd->cfgctxts; ctxt++) {
1331 int ctxt_tidbase = ctxt * dd->rcvtidcnt;
1332 int maxtid = ctxt_tidbase + dd->rcvtidcnt;
1333
1334 for (i = ctxt_tidbase; i < maxtid; i++) {
1335 if (!tmpp[i])
1336 continue;
1337 dma_unmap_page(&dd->pcidev->dev, tmpd[i],
1338 PAGE_SIZE, DMA_FROM_DEVICE);
1339 qib_release_user_pages(&tmpp[i], 1);
1340 tmpp[i] = NULL;
1341 }
1342 }
1343
1344 dd->pageshadow = NULL;
1345 vfree(tmpp);
1346 dd->physshadow = NULL;
1347 vfree(tmpd);
1348 }
1349
1350 /*
1351 * Free any resources still in use (usually just kernel contexts)
1352 * at unload; we do for ctxtcnt, because that's what we allocate.
1353 * We acquire lock to be really paranoid that rcd isn't being
1354 * accessed from some interrupt-related code (that should not happen,
1355 * but best to be sure).
1356 */
1357 spin_lock_irqsave(&dd->uctxt_lock, flags);
1358 tmp = dd->rcd;
1359 dd->rcd = NULL;
1360 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
1361 for (ctxt = 0; tmp && ctxt < dd->ctxtcnt; ctxt++) {
1362 struct qib_ctxtdata *rcd = tmp[ctxt];
1363
1364 tmp[ctxt] = NULL; /* debugging paranoia */
1365 qib_free_ctxtdata(dd, rcd);
1366 }
1367 kfree(tmp);
1368}
1369
1370/*
1371 * Clean up on unit shutdown, or error during unit load after
1372 * successful initialization.
1373 */
1374static void qib_postinit_cleanup(struct qib_devdata *dd)
1375{
1376 /*
1377 * Clean up chip-specific stuff.
1378 * We check for NULL here, because it's outside
1379 * the kregbase check, and we need to call it
1380 * after the free_irq. Thus it's possible that
1381 * the function pointers were never initialized.
1382 */
1383 if (dd->f_cleanup)
1384 dd->f_cleanup(dd);
1385
1386 qib_pcie_ddcleanup(dd);
1387
1388 cleanup_device_data(dd);
1389
1390 qib_free_devdata(dd);
1391}
1392
1393static int qib_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1394{
1395 int ret, j, pidx, initfail;
1396 struct qib_devdata *dd = NULL;
1397
1398 ret = qib_pcie_init(pdev, ent);
1399 if (ret)
1400 goto bail;
1401
1402 /*
1403 * Do device-specific initialiation, function table setup, dd
1404 * allocation, etc.
1405 */
1406 switch (ent->device) {
1407 case PCI_DEVICE_ID_QLOGIC_IB_6120:
1408#ifdef CONFIG_PCI_MSI
1409 dd = qib_init_iba6120_funcs(pdev, ent);
1410#else
1411 qib_early_err(&pdev->dev,
1412 "Intel PCIE device 0x%x cannot work if CONFIG_PCI_MSI is not enabled\n",
1413 ent->device);
1414 dd = ERR_PTR(-ENODEV);
1415#endif
1416 break;
1417
1418 case PCI_DEVICE_ID_QLOGIC_IB_7220:
1419 dd = qib_init_iba7220_funcs(pdev, ent);
1420 break;
1421
1422 case PCI_DEVICE_ID_QLOGIC_IB_7322:
1423 dd = qib_init_iba7322_funcs(pdev, ent);
1424 break;
1425
1426 default:
1427 qib_early_err(&pdev->dev,
1428 "Failing on unknown Intel deviceid 0x%x\n",
1429 ent->device);
1430 ret = -ENODEV;
1431 }
1432
1433 if (IS_ERR(dd))
1434 ret = PTR_ERR(dd);
1435 if (ret)
1436 goto bail; /* error already printed */
1437
1438 ret = qib_create_workqueues(dd);
1439 if (ret)
1440 goto bail;
1441
1442 /* do the generic initialization */
1443 initfail = qib_init(dd, 0);
1444
1445 ret = qib_register_ib_device(dd);
1446
1447 /*
1448 * Now ready for use. this should be cleared whenever we
1449 * detect a reset, or initiate one. If earlier failure,
1450 * we still create devices, so diags, etc. can be used
1451 * to determine cause of problem.
1452 */
1453 if (!qib_mini_init && !initfail && !ret)
1454 dd->flags |= QIB_INITTED;
1455
1456 j = qib_device_create(dd);
1457 if (j)
1458 qib_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1459 j = qibfs_add(dd);
1460 if (j)
1461 qib_dev_err(dd, "Failed filesystem setup for counters: %d\n",
1462 -j);
1463
1464 if (qib_mini_init || initfail || ret) {
1465 qib_stop_timers(dd);
1466 flush_workqueue(ib_wq);
1467 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1468 dd->f_quiet_serdes(dd->pport + pidx);
1469 if (qib_mini_init)
1470 goto bail;
1471 if (!j) {
1472 (void) qibfs_remove(dd);
1473 qib_device_remove(dd);
1474 }
1475 if (!ret)
1476 qib_unregister_ib_device(dd);
1477 qib_postinit_cleanup(dd);
1478 if (initfail)
1479 ret = initfail;
1480 goto bail;
1481 }
1482
1483 ret = qib_enable_wc(dd);
1484 if (ret) {
1485 qib_dev_err(dd,
1486 "Write combining not enabled (err %d): performance may be poor\n",
1487 -ret);
1488 ret = 0;
1489 }
1490
1491 qib_verify_pioperf(dd);
1492bail:
1493 return ret;
1494}
1495
1496static void qib_remove_one(struct pci_dev *pdev)
1497{
1498 struct qib_devdata *dd = pci_get_drvdata(pdev);
1499 int ret;
1500
1501 /* unregister from IB core */
1502 qib_unregister_ib_device(dd);
1503
1504 /*
1505 * Disable the IB link, disable interrupts on the device,
1506 * clear dma engines, etc.
1507 */
1508 if (!qib_mini_init)
1509 qib_shutdown_device(dd);
1510
1511 qib_stop_timers(dd);
1512
1513 /* wait until all of our (qsfp) queue_work() calls complete */
1514 flush_workqueue(ib_wq);
1515
1516 ret = qibfs_remove(dd);
1517 if (ret)
1518 qib_dev_err(dd, "Failed counters filesystem cleanup: %d\n",
1519 -ret);
1520
1521 qib_device_remove(dd);
1522
1523 qib_postinit_cleanup(dd);
1524}
1525
1526static void qib_shutdown_one(struct pci_dev *pdev)
1527{
1528 struct qib_devdata *dd = pci_get_drvdata(pdev);
1529
1530 qib_shutdown_device(dd);
1531}
1532
1533/**
1534 * qib_create_rcvhdrq - create a receive header queue
1535 * @dd: the qlogic_ib device
1536 * @rcd: the context data
1537 *
1538 * This must be contiguous memory (from an i/o perspective), and must be
1539 * DMA'able (which means for some systems, it will go through an IOMMU,
1540 * or be forced into a low address range).
1541 */
1542int qib_create_rcvhdrq(struct qib_devdata *dd, struct qib_ctxtdata *rcd)
1543{
1544 unsigned amt;
1545 int old_node_id;
1546
1547 if (!rcd->rcvhdrq) {
1548 dma_addr_t phys_hdrqtail;
1549
1550 amt = ALIGN(dd->rcvhdrcnt * dd->rcvhdrentsize *
1551 sizeof(u32), PAGE_SIZE);
1552
1553 old_node_id = dev_to_node(&dd->pcidev->dev);
1554 set_dev_node(&dd->pcidev->dev, rcd->node_id);
1555 rcd->rcvhdrq = dma_alloc_coherent(&dd->pcidev->dev, amt,
1556 &rcd->rcvhdrq_phys, GFP_KERNEL);
1557 set_dev_node(&dd->pcidev->dev, old_node_id);
1558
1559 if (!rcd->rcvhdrq) {
1560 qib_dev_err(dd,
1561 "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1562 amt, rcd->ctxt);
1563 goto bail;
1564 }
1565
1566 if (rcd->ctxt >= dd->first_user_ctxt) {
1567 rcd->user_event_mask = vmalloc_user(PAGE_SIZE);
1568 if (!rcd->user_event_mask)
1569 goto bail_free_hdrq;
1570 }
1571
1572 if (!(dd->flags & QIB_NODMA_RTAIL)) {
1573 set_dev_node(&dd->pcidev->dev, rcd->node_id);
1574 rcd->rcvhdrtail_kvaddr = dma_alloc_coherent(
1575 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1576 GFP_KERNEL);
1577 set_dev_node(&dd->pcidev->dev, old_node_id);
1578 if (!rcd->rcvhdrtail_kvaddr)
1579 goto bail_free;
1580 rcd->rcvhdrqtailaddr_phys = phys_hdrqtail;
1581 }
1582
1583 rcd->rcvhdrq_size = amt;
1584 }
1585
1586 /* clear for security and sanity on each use */
1587 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
1588 if (rcd->rcvhdrtail_kvaddr)
1589 memset(rcd->rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1590 return 0;
1591
1592bail_free:
1593 qib_dev_err(dd,
1594 "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1595 rcd->ctxt);
1596 vfree(rcd->user_event_mask);
1597 rcd->user_event_mask = NULL;
1598bail_free_hdrq:
1599 dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1600 rcd->rcvhdrq_phys);
1601 rcd->rcvhdrq = NULL;
1602bail:
1603 return -ENOMEM;
1604}
1605
1606/**
1607 * qib_setup_eagerbufs - allocate eager buffers, both kernel and user contexts.
1608 * @rcd: the context we are setting up.
1609 *
1610 * Allocate the eager TID buffers and program them into hip.
1611 * They are no longer completely contiguous, we do multiple allocation
1612 * calls. Otherwise we get the OOM code involved, by asking for too
1613 * much per call, with disastrous results on some kernels.
1614 */
1615int qib_setup_eagerbufs(struct qib_ctxtdata *rcd)
1616{
1617 struct qib_devdata *dd = rcd->dd;
1618 unsigned e, egrcnt, egrperchunk, chunk, egrsize, egroff;
1619 size_t size;
1620 int old_node_id;
1621
1622 egrcnt = rcd->rcvegrcnt;
1623 egroff = rcd->rcvegr_tid_base;
1624 egrsize = dd->rcvegrbufsize;
1625
1626 chunk = rcd->rcvegrbuf_chunks;
1627 egrperchunk = rcd->rcvegrbufs_perchunk;
1628 size = rcd->rcvegrbuf_size;
1629 if (!rcd->rcvegrbuf) {
1630 rcd->rcvegrbuf =
1631 kcalloc_node(chunk, sizeof(rcd->rcvegrbuf[0]),
1632 GFP_KERNEL, rcd->node_id);
1633 if (!rcd->rcvegrbuf)
1634 goto bail;
1635 }
1636 if (!rcd->rcvegrbuf_phys) {
1637 rcd->rcvegrbuf_phys =
1638 kmalloc_array_node(chunk,
1639 sizeof(rcd->rcvegrbuf_phys[0]),
1640 GFP_KERNEL, rcd->node_id);
1641 if (!rcd->rcvegrbuf_phys)
1642 goto bail_rcvegrbuf;
1643 }
1644 for (e = 0; e < rcd->rcvegrbuf_chunks; e++) {
1645 if (rcd->rcvegrbuf[e])
1646 continue;
1647
1648 old_node_id = dev_to_node(&dd->pcidev->dev);
1649 set_dev_node(&dd->pcidev->dev, rcd->node_id);
1650 rcd->rcvegrbuf[e] =
1651 dma_alloc_coherent(&dd->pcidev->dev, size,
1652 &rcd->rcvegrbuf_phys[e],
1653 GFP_KERNEL);
1654 set_dev_node(&dd->pcidev->dev, old_node_id);
1655 if (!rcd->rcvegrbuf[e])
1656 goto bail_rcvegrbuf_phys;
1657 }
1658
1659 rcd->rcvegr_phys = rcd->rcvegrbuf_phys[0];
1660
1661 for (e = chunk = 0; chunk < rcd->rcvegrbuf_chunks; chunk++) {
1662 dma_addr_t pa = rcd->rcvegrbuf_phys[chunk];
1663 unsigned i;
1664
1665 /* clear for security and sanity on each use */
1666 memset(rcd->rcvegrbuf[chunk], 0, size);
1667
1668 for (i = 0; e < egrcnt && i < egrperchunk; e++, i++) {
1669 dd->f_put_tid(dd, e + egroff +
1670 (u64 __iomem *)
1671 ((char __iomem *)
1672 dd->kregbase +
1673 dd->rcvegrbase),
1674 RCVHQ_RCV_TYPE_EAGER, pa);
1675 pa += egrsize;
1676 }
1677 cond_resched(); /* don't hog the cpu */
1678 }
1679
1680 return 0;
1681
1682bail_rcvegrbuf_phys:
1683 for (e = 0; e < rcd->rcvegrbuf_chunks && rcd->rcvegrbuf[e]; e++)
1684 dma_free_coherent(&dd->pcidev->dev, size,
1685 rcd->rcvegrbuf[e], rcd->rcvegrbuf_phys[e]);
1686 kfree(rcd->rcvegrbuf_phys);
1687 rcd->rcvegrbuf_phys = NULL;
1688bail_rcvegrbuf:
1689 kfree(rcd->rcvegrbuf);
1690 rcd->rcvegrbuf = NULL;
1691bail:
1692 return -ENOMEM;
1693}
1694
1695/*
1696 * Note: Changes to this routine should be mirrored
1697 * for the diagnostics routine qib_remap_ioaddr32().
1698 * There is also related code for VL15 buffers in qib_init_7322_variables().
1699 * The teardown code that unmaps is in qib_pcie_ddcleanup()
1700 */
1701int init_chip_wc_pat(struct qib_devdata *dd, u32 vl15buflen)
1702{
1703 u64 __iomem *qib_kregbase = NULL;
1704 void __iomem *qib_piobase = NULL;
1705 u64 __iomem *qib_userbase = NULL;
1706 u64 qib_kreglen;
1707 u64 qib_pio2koffset = dd->piobufbase & 0xffffffff;
1708 u64 qib_pio4koffset = dd->piobufbase >> 32;
1709 u64 qib_pio2klen = dd->piobcnt2k * dd->palign;
1710 u64 qib_pio4klen = dd->piobcnt4k * dd->align4k;
1711 u64 qib_physaddr = dd->physaddr;
1712 u64 qib_piolen;
1713 u64 qib_userlen = 0;
1714
1715 /*
1716 * Free the old mapping because the kernel will try to reuse the
1717 * old mapping and not create a new mapping with the
1718 * write combining attribute.
1719 */
1720 iounmap(dd->kregbase);
1721 dd->kregbase = NULL;
1722
1723 /*
1724 * Assumes chip address space looks like:
1725 * - kregs + sregs + cregs + uregs (in any order)
1726 * - piobufs (2K and 4K bufs in either order)
1727 * or:
1728 * - kregs + sregs + cregs (in any order)
1729 * - piobufs (2K and 4K bufs in either order)
1730 * - uregs
1731 */
1732 if (dd->piobcnt4k == 0) {
1733 qib_kreglen = qib_pio2koffset;
1734 qib_piolen = qib_pio2klen;
1735 } else if (qib_pio2koffset < qib_pio4koffset) {
1736 qib_kreglen = qib_pio2koffset;
1737 qib_piolen = qib_pio4koffset + qib_pio4klen - qib_kreglen;
1738 } else {
1739 qib_kreglen = qib_pio4koffset;
1740 qib_piolen = qib_pio2koffset + qib_pio2klen - qib_kreglen;
1741 }
1742 qib_piolen += vl15buflen;
1743 /* Map just the configured ports (not all hw ports) */
1744 if (dd->uregbase > qib_kreglen)
1745 qib_userlen = dd->ureg_align * dd->cfgctxts;
1746
1747 /* Sanity checks passed, now create the new mappings */
1748 qib_kregbase = ioremap(qib_physaddr, qib_kreglen);
1749 if (!qib_kregbase)
1750 goto bail;
1751
1752 qib_piobase = ioremap_wc(qib_physaddr + qib_kreglen, qib_piolen);
1753 if (!qib_piobase)
1754 goto bail_kregbase;
1755
1756 if (qib_userlen) {
1757 qib_userbase = ioremap(qib_physaddr + dd->uregbase,
1758 qib_userlen);
1759 if (!qib_userbase)
1760 goto bail_piobase;
1761 }
1762
1763 dd->kregbase = qib_kregbase;
1764 dd->kregend = (u64 __iomem *)
1765 ((char __iomem *) qib_kregbase + qib_kreglen);
1766 dd->piobase = qib_piobase;
1767 dd->pio2kbase = (void __iomem *)
1768 (((char __iomem *) dd->piobase) +
1769 qib_pio2koffset - qib_kreglen);
1770 if (dd->piobcnt4k)
1771 dd->pio4kbase = (void __iomem *)
1772 (((char __iomem *) dd->piobase) +
1773 qib_pio4koffset - qib_kreglen);
1774 if (qib_userlen)
1775 /* ureg will now be accessed relative to dd->userbase */
1776 dd->userbase = qib_userbase;
1777 return 0;
1778
1779bail_piobase:
1780 iounmap(qib_piobase);
1781bail_kregbase:
1782 iounmap(qib_kregbase);
1783bail:
1784 return -ENOMEM;
1785}
1/*
2 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
3 * All rights reserved.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/vmalloc.h>
38#include <linux/delay.h>
39#include <linux/idr.h>
40#include <linux/module.h>
41
42#include "qib.h"
43#include "qib_common.h"
44
45/*
46 * min buffers we want to have per context, after driver
47 */
48#define QIB_MIN_USER_CTXT_BUFCNT 7
49
50#define QLOGIC_IB_R_SOFTWARE_MASK 0xFF
51#define QLOGIC_IB_R_SOFTWARE_SHIFT 24
52#define QLOGIC_IB_R_EMULATOR_MASK (1ULL<<62)
53
54/*
55 * Number of ctxts we are configured to use (to allow for more pio
56 * buffers per ctxt, etc.) Zero means use chip value.
57 */
58ushort qib_cfgctxts;
59module_param_named(cfgctxts, qib_cfgctxts, ushort, S_IRUGO);
60MODULE_PARM_DESC(cfgctxts, "Set max number of contexts to use");
61
62/*
63 * If set, do not write to any regs if avoidable, hack to allow
64 * check for deranged default register values.
65 */
66ushort qib_mini_init;
67module_param_named(mini_init, qib_mini_init, ushort, S_IRUGO);
68MODULE_PARM_DESC(mini_init, "If set, do minimal diag init");
69
70unsigned qib_n_krcv_queues;
71module_param_named(krcvqs, qib_n_krcv_queues, uint, S_IRUGO);
72MODULE_PARM_DESC(krcvqs, "number of kernel receive queues per IB port");
73
74/*
75 * qib_wc_pat parameter:
76 * 0 is WC via MTRR
77 * 1 is WC via PAT
78 * If PAT initialization fails, code reverts back to MTRR
79 */
80unsigned qib_wc_pat = 1; /* default (1) is to use PAT, not MTRR */
81module_param_named(wc_pat, qib_wc_pat, uint, S_IRUGO);
82MODULE_PARM_DESC(wc_pat, "enable write-combining via PAT mechanism");
83
84struct workqueue_struct *qib_cq_wq;
85
86static void verify_interrupt(unsigned long);
87
88static struct idr qib_unit_table;
89u32 qib_cpulist_count;
90unsigned long *qib_cpulist;
91
92/* set number of contexts we'll actually use */
93void qib_set_ctxtcnt(struct qib_devdata *dd)
94{
95 if (!qib_cfgctxts) {
96 dd->cfgctxts = dd->first_user_ctxt + num_online_cpus();
97 if (dd->cfgctxts > dd->ctxtcnt)
98 dd->cfgctxts = dd->ctxtcnt;
99 } else if (qib_cfgctxts < dd->num_pports)
100 dd->cfgctxts = dd->ctxtcnt;
101 else if (qib_cfgctxts <= dd->ctxtcnt)
102 dd->cfgctxts = qib_cfgctxts;
103 else
104 dd->cfgctxts = dd->ctxtcnt;
105 dd->freectxts = (dd->first_user_ctxt > dd->cfgctxts) ? 0 :
106 dd->cfgctxts - dd->first_user_ctxt;
107}
108
109/*
110 * Common code for creating the receive context array.
111 */
112int qib_create_ctxts(struct qib_devdata *dd)
113{
114 unsigned i;
115 int ret;
116
117 /*
118 * Allocate full ctxtcnt array, rather than just cfgctxts, because
119 * cleanup iterates across all possible ctxts.
120 */
121 dd->rcd = kzalloc(sizeof(*dd->rcd) * dd->ctxtcnt, GFP_KERNEL);
122 if (!dd->rcd) {
123 qib_dev_err(dd, "Unable to allocate ctxtdata array, "
124 "failing\n");
125 ret = -ENOMEM;
126 goto done;
127 }
128
129 /* create (one or more) kctxt */
130 for (i = 0; i < dd->first_user_ctxt; ++i) {
131 struct qib_pportdata *ppd;
132 struct qib_ctxtdata *rcd;
133
134 if (dd->skip_kctxt_mask & (1 << i))
135 continue;
136
137 ppd = dd->pport + (i % dd->num_pports);
138 rcd = qib_create_ctxtdata(ppd, i);
139 if (!rcd) {
140 qib_dev_err(dd, "Unable to allocate ctxtdata"
141 " for Kernel ctxt, failing\n");
142 ret = -ENOMEM;
143 goto done;
144 }
145 rcd->pkeys[0] = QIB_DEFAULT_P_KEY;
146 rcd->seq_cnt = 1;
147 }
148 ret = 0;
149done:
150 return ret;
151}
152
153/*
154 * Common code for user and kernel context setup.
155 */
156struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *ppd, u32 ctxt)
157{
158 struct qib_devdata *dd = ppd->dd;
159 struct qib_ctxtdata *rcd;
160
161 rcd = kzalloc(sizeof(*rcd), GFP_KERNEL);
162 if (rcd) {
163 INIT_LIST_HEAD(&rcd->qp_wait_list);
164 rcd->ppd = ppd;
165 rcd->dd = dd;
166 rcd->cnt = 1;
167 rcd->ctxt = ctxt;
168 dd->rcd[ctxt] = rcd;
169
170 dd->f_init_ctxt(rcd);
171
172 /*
173 * To avoid wasting a lot of memory, we allocate 32KB chunks
174 * of physically contiguous memory, advance through it until
175 * used up and then allocate more. Of course, we need
176 * memory to store those extra pointers, now. 32KB seems to
177 * be the most that is "safe" under memory pressure
178 * (creating large files and then copying them over
179 * NFS while doing lots of MPI jobs). The OOM killer can
180 * get invoked, even though we say we can sleep and this can
181 * cause significant system problems....
182 */
183 rcd->rcvegrbuf_size = 0x8000;
184 rcd->rcvegrbufs_perchunk =
185 rcd->rcvegrbuf_size / dd->rcvegrbufsize;
186 rcd->rcvegrbuf_chunks = (rcd->rcvegrcnt +
187 rcd->rcvegrbufs_perchunk - 1) /
188 rcd->rcvegrbufs_perchunk;
189 BUG_ON(!is_power_of_2(rcd->rcvegrbufs_perchunk));
190 rcd->rcvegrbufs_perchunk_shift =
191 ilog2(rcd->rcvegrbufs_perchunk);
192 }
193 return rcd;
194}
195
196/*
197 * Common code for initializing the physical port structure.
198 */
199void qib_init_pportdata(struct qib_pportdata *ppd, struct qib_devdata *dd,
200 u8 hw_pidx, u8 port)
201{
202 ppd->dd = dd;
203 ppd->hw_pidx = hw_pidx;
204 ppd->port = port; /* IB port number, not index */
205
206 spin_lock_init(&ppd->sdma_lock);
207 spin_lock_init(&ppd->lflags_lock);
208 init_waitqueue_head(&ppd->state_wait);
209
210 init_timer(&ppd->symerr_clear_timer);
211 ppd->symerr_clear_timer.function = qib_clear_symerror_on_linkup;
212 ppd->symerr_clear_timer.data = (unsigned long)ppd;
213}
214
215static int init_pioavailregs(struct qib_devdata *dd)
216{
217 int ret, pidx;
218 u64 *status_page;
219
220 dd->pioavailregs_dma = dma_alloc_coherent(
221 &dd->pcidev->dev, PAGE_SIZE, &dd->pioavailregs_phys,
222 GFP_KERNEL);
223 if (!dd->pioavailregs_dma) {
224 qib_dev_err(dd, "failed to allocate PIOavail reg area "
225 "in memory\n");
226 ret = -ENOMEM;
227 goto done;
228 }
229
230 /*
231 * We really want L2 cache aligned, but for current CPUs of
232 * interest, they are the same.
233 */
234 status_page = (u64 *)
235 ((char *) dd->pioavailregs_dma +
236 ((2 * L1_CACHE_BYTES +
237 dd->pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
238 /* device status comes first, for backwards compatibility */
239 dd->devstatusp = status_page;
240 *status_page++ = 0;
241 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
242 dd->pport[pidx].statusp = status_page;
243 *status_page++ = 0;
244 }
245
246 /*
247 * Setup buffer to hold freeze and other messages, accessible to
248 * apps, following statusp. This is per-unit, not per port.
249 */
250 dd->freezemsg = (char *) status_page;
251 *dd->freezemsg = 0;
252 /* length of msg buffer is "whatever is left" */
253 ret = (char *) status_page - (char *) dd->pioavailregs_dma;
254 dd->freezelen = PAGE_SIZE - ret;
255
256 ret = 0;
257
258done:
259 return ret;
260}
261
262/**
263 * init_shadow_tids - allocate the shadow TID array
264 * @dd: the qlogic_ib device
265 *
266 * allocate the shadow TID array, so we can qib_munlock previous
267 * entries. It may make more sense to move the pageshadow to the
268 * ctxt data structure, so we only allocate memory for ctxts actually
269 * in use, since we at 8k per ctxt, now.
270 * We don't want failures here to prevent use of the driver/chip,
271 * so no return value.
272 */
273static void init_shadow_tids(struct qib_devdata *dd)
274{
275 struct page **pages;
276 dma_addr_t *addrs;
277
278 pages = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(struct page *));
279 if (!pages) {
280 qib_dev_err(dd, "failed to allocate shadow page * "
281 "array, no expected sends!\n");
282 goto bail;
283 }
284
285 addrs = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(dma_addr_t));
286 if (!addrs) {
287 qib_dev_err(dd, "failed to allocate shadow dma handle "
288 "array, no expected sends!\n");
289 goto bail_free;
290 }
291
292 dd->pageshadow = pages;
293 dd->physshadow = addrs;
294 return;
295
296bail_free:
297 vfree(pages);
298bail:
299 dd->pageshadow = NULL;
300}
301
302/*
303 * Do initialization for device that is only needed on
304 * first detect, not on resets.
305 */
306static int loadtime_init(struct qib_devdata *dd)
307{
308 int ret = 0;
309
310 if (((dd->revision >> QLOGIC_IB_R_SOFTWARE_SHIFT) &
311 QLOGIC_IB_R_SOFTWARE_MASK) != QIB_CHIP_SWVERSION) {
312 qib_dev_err(dd, "Driver only handles version %d, "
313 "chip swversion is %d (%llx), failng\n",
314 QIB_CHIP_SWVERSION,
315 (int)(dd->revision >>
316 QLOGIC_IB_R_SOFTWARE_SHIFT) &
317 QLOGIC_IB_R_SOFTWARE_MASK,
318 (unsigned long long) dd->revision);
319 ret = -ENOSYS;
320 goto done;
321 }
322
323 if (dd->revision & QLOGIC_IB_R_EMULATOR_MASK)
324 qib_devinfo(dd->pcidev, "%s", dd->boardversion);
325
326 spin_lock_init(&dd->pioavail_lock);
327 spin_lock_init(&dd->sendctrl_lock);
328 spin_lock_init(&dd->uctxt_lock);
329 spin_lock_init(&dd->qib_diag_trans_lock);
330 spin_lock_init(&dd->eep_st_lock);
331 mutex_init(&dd->eep_lock);
332
333 if (qib_mini_init)
334 goto done;
335
336 ret = init_pioavailregs(dd);
337 init_shadow_tids(dd);
338
339 qib_get_eeprom_info(dd);
340
341 /* setup time (don't start yet) to verify we got interrupt */
342 init_timer(&dd->intrchk_timer);
343 dd->intrchk_timer.function = verify_interrupt;
344 dd->intrchk_timer.data = (unsigned long) dd;
345
346done:
347 return ret;
348}
349
350/**
351 * init_after_reset - re-initialize after a reset
352 * @dd: the qlogic_ib device
353 *
354 * sanity check at least some of the values after reset, and
355 * ensure no receive or transmit (explicitly, in case reset
356 * failed
357 */
358static int init_after_reset(struct qib_devdata *dd)
359{
360 int i;
361
362 /*
363 * Ensure chip does no sends or receives, tail updates, or
364 * pioavail updates while we re-initialize. This is mostly
365 * for the driver data structures, not chip registers.
366 */
367 for (i = 0; i < dd->num_pports; ++i) {
368 /*
369 * ctxt == -1 means "all contexts". Only really safe for
370 * _dis_abling things, as here.
371 */
372 dd->f_rcvctrl(dd->pport + i, QIB_RCVCTRL_CTXT_DIS |
373 QIB_RCVCTRL_INTRAVAIL_DIS |
374 QIB_RCVCTRL_TAILUPD_DIS, -1);
375 /* Redundant across ports for some, but no big deal. */
376 dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_DIS |
377 QIB_SENDCTRL_AVAIL_DIS);
378 }
379
380 return 0;
381}
382
383static void enable_chip(struct qib_devdata *dd)
384{
385 u64 rcvmask;
386 int i;
387
388 /*
389 * Enable PIO send, and update of PIOavail regs to memory.
390 */
391 for (i = 0; i < dd->num_pports; ++i)
392 dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_ENB |
393 QIB_SENDCTRL_AVAIL_ENB);
394 /*
395 * Enable kernel ctxts' receive and receive interrupt.
396 * Other ctxts done as user opens and inits them.
397 */
398 rcvmask = QIB_RCVCTRL_CTXT_ENB | QIB_RCVCTRL_INTRAVAIL_ENB;
399 rcvmask |= (dd->flags & QIB_NODMA_RTAIL) ?
400 QIB_RCVCTRL_TAILUPD_DIS : QIB_RCVCTRL_TAILUPD_ENB;
401 for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
402 struct qib_ctxtdata *rcd = dd->rcd[i];
403
404 if (rcd)
405 dd->f_rcvctrl(rcd->ppd, rcvmask, i);
406 }
407}
408
409static void verify_interrupt(unsigned long opaque)
410{
411 struct qib_devdata *dd = (struct qib_devdata *) opaque;
412
413 if (!dd)
414 return; /* being torn down */
415
416 /*
417 * If we don't have a lid or any interrupts, let the user know and
418 * don't bother checking again.
419 */
420 if (dd->int_counter == 0) {
421 if (!dd->f_intr_fallback(dd))
422 dev_err(&dd->pcidev->dev, "No interrupts detected, "
423 "not usable.\n");
424 else /* re-arm the timer to see if fallback works */
425 mod_timer(&dd->intrchk_timer, jiffies + HZ/2);
426 }
427}
428
429static void init_piobuf_state(struct qib_devdata *dd)
430{
431 int i, pidx;
432 u32 uctxts;
433
434 /*
435 * Ensure all buffers are free, and fifos empty. Buffers
436 * are common, so only do once for port 0.
437 *
438 * After enable and qib_chg_pioavailkernel so we can safely
439 * enable pioavail updates and PIOENABLE. After this, packets
440 * are ready and able to go out.
441 */
442 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_ALL);
443 for (pidx = 0; pidx < dd->num_pports; ++pidx)
444 dd->f_sendctrl(dd->pport + pidx, QIB_SENDCTRL_FLUSH);
445
446 /*
447 * If not all sendbufs are used, add the one to each of the lower
448 * numbered contexts. pbufsctxt and lastctxt_piobuf are
449 * calculated in chip-specific code because it may cause some
450 * chip-specific adjustments to be made.
451 */
452 uctxts = dd->cfgctxts - dd->first_user_ctxt;
453 dd->ctxts_extrabuf = dd->pbufsctxt ?
454 dd->lastctxt_piobuf - (dd->pbufsctxt * uctxts) : 0;
455
456 /*
457 * Set up the shadow copies of the piobufavail registers,
458 * which we compare against the chip registers for now, and
459 * the in memory DMA'ed copies of the registers.
460 * By now pioavail updates to memory should have occurred, so
461 * copy them into our working/shadow registers; this is in
462 * case something went wrong with abort, but mostly to get the
463 * initial values of the generation bit correct.
464 */
465 for (i = 0; i < dd->pioavregs; i++) {
466 __le64 tmp;
467
468 tmp = dd->pioavailregs_dma[i];
469 /*
470 * Don't need to worry about pioavailkernel here
471 * because we will call qib_chg_pioavailkernel() later
472 * in initialization, to busy out buffers as needed.
473 */
474 dd->pioavailshadow[i] = le64_to_cpu(tmp);
475 }
476 while (i < ARRAY_SIZE(dd->pioavailshadow))
477 dd->pioavailshadow[i++] = 0; /* for debugging sanity */
478
479 /* after pioavailshadow is setup */
480 qib_chg_pioavailkernel(dd, 0, dd->piobcnt2k + dd->piobcnt4k,
481 TXCHK_CHG_TYPE_KERN, NULL);
482 dd->f_initvl15_bufs(dd);
483}
484
485/**
486 * qib_init - do the actual initialization sequence on the chip
487 * @dd: the qlogic_ib device
488 * @reinit: reinitializing, so don't allocate new memory
489 *
490 * Do the actual initialization sequence on the chip. This is done
491 * both from the init routine called from the PCI infrastructure, and
492 * when we reset the chip, or detect that it was reset internally,
493 * or it's administratively re-enabled.
494 *
495 * Memory allocation here and in called routines is only done in
496 * the first case (reinit == 0). We have to be careful, because even
497 * without memory allocation, we need to re-write all the chip registers
498 * TIDs, etc. after the reset or enable has completed.
499 */
500int qib_init(struct qib_devdata *dd, int reinit)
501{
502 int ret = 0, pidx, lastfail = 0;
503 u32 portok = 0;
504 unsigned i;
505 struct qib_ctxtdata *rcd;
506 struct qib_pportdata *ppd;
507 unsigned long flags;
508
509 /* Set linkstate to unknown, so we can watch for a transition. */
510 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
511 ppd = dd->pport + pidx;
512 spin_lock_irqsave(&ppd->lflags_lock, flags);
513 ppd->lflags &= ~(QIBL_LINKACTIVE | QIBL_LINKARMED |
514 QIBL_LINKDOWN | QIBL_LINKINIT |
515 QIBL_LINKV);
516 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
517 }
518
519 if (reinit)
520 ret = init_after_reset(dd);
521 else
522 ret = loadtime_init(dd);
523 if (ret)
524 goto done;
525
526 /* Bypass most chip-init, to get to device creation */
527 if (qib_mini_init)
528 return 0;
529
530 ret = dd->f_late_initreg(dd);
531 if (ret)
532 goto done;
533
534 /* dd->rcd can be NULL if early init failed */
535 for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
536 /*
537 * Set up the (kernel) rcvhdr queue and egr TIDs. If doing
538 * re-init, the simplest way to handle this is to free
539 * existing, and re-allocate.
540 * Need to re-create rest of ctxt 0 ctxtdata as well.
541 */
542 rcd = dd->rcd[i];
543 if (!rcd)
544 continue;
545
546 lastfail = qib_create_rcvhdrq(dd, rcd);
547 if (!lastfail)
548 lastfail = qib_setup_eagerbufs(rcd);
549 if (lastfail) {
550 qib_dev_err(dd, "failed to allocate kernel ctxt's "
551 "rcvhdrq and/or egr bufs\n");
552 continue;
553 }
554 }
555
556 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
557 int mtu;
558 if (lastfail)
559 ret = lastfail;
560 ppd = dd->pport + pidx;
561 mtu = ib_mtu_enum_to_int(qib_ibmtu);
562 if (mtu == -1) {
563 mtu = QIB_DEFAULT_MTU;
564 qib_ibmtu = 0; /* don't leave invalid value */
565 }
566 /* set max we can ever have for this driver load */
567 ppd->init_ibmaxlen = min(mtu > 2048 ?
568 dd->piosize4k : dd->piosize2k,
569 dd->rcvegrbufsize +
570 (dd->rcvhdrentsize << 2));
571 /*
572 * Have to initialize ibmaxlen, but this will normally
573 * change immediately in qib_set_mtu().
574 */
575 ppd->ibmaxlen = ppd->init_ibmaxlen;
576 qib_set_mtu(ppd, mtu);
577
578 spin_lock_irqsave(&ppd->lflags_lock, flags);
579 ppd->lflags |= QIBL_IB_LINK_DISABLED;
580 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
581
582 lastfail = dd->f_bringup_serdes(ppd);
583 if (lastfail) {
584 qib_devinfo(dd->pcidev,
585 "Failed to bringup IB port %u\n", ppd->port);
586 lastfail = -ENETDOWN;
587 continue;
588 }
589
590 portok++;
591 }
592
593 if (!portok) {
594 /* none of the ports initialized */
595 if (!ret && lastfail)
596 ret = lastfail;
597 else if (!ret)
598 ret = -ENETDOWN;
599 /* but continue on, so we can debug cause */
600 }
601
602 enable_chip(dd);
603
604 init_piobuf_state(dd);
605
606done:
607 if (!ret) {
608 /* chip is OK for user apps; mark it as initialized */
609 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
610 ppd = dd->pport + pidx;
611 /*
612 * Set status even if port serdes is not initialized
613 * so that diags will work.
614 */
615 *ppd->statusp |= QIB_STATUS_CHIP_PRESENT |
616 QIB_STATUS_INITTED;
617 if (!ppd->link_speed_enabled)
618 continue;
619 if (dd->flags & QIB_HAS_SEND_DMA)
620 ret = qib_setup_sdma(ppd);
621 init_timer(&ppd->hol_timer);
622 ppd->hol_timer.function = qib_hol_event;
623 ppd->hol_timer.data = (unsigned long)ppd;
624 ppd->hol_state = QIB_HOL_UP;
625 }
626
627 /* now we can enable all interrupts from the chip */
628 dd->f_set_intr_state(dd, 1);
629
630 /*
631 * Setup to verify we get an interrupt, and fallback
632 * to an alternate if necessary and possible.
633 */
634 mod_timer(&dd->intrchk_timer, jiffies + HZ/2);
635 /* start stats retrieval timer */
636 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
637 }
638
639 /* if ret is non-zero, we probably should do some cleanup here... */
640 return ret;
641}
642
643/*
644 * These next two routines are placeholders in case we don't have per-arch
645 * code for controlling write combining. If explicit control of write
646 * combining is not available, performance will probably be awful.
647 */
648
649int __attribute__((weak)) qib_enable_wc(struct qib_devdata *dd)
650{
651 return -EOPNOTSUPP;
652}
653
654void __attribute__((weak)) qib_disable_wc(struct qib_devdata *dd)
655{
656}
657
658static inline struct qib_devdata *__qib_lookup(int unit)
659{
660 return idr_find(&qib_unit_table, unit);
661}
662
663struct qib_devdata *qib_lookup(int unit)
664{
665 struct qib_devdata *dd;
666 unsigned long flags;
667
668 spin_lock_irqsave(&qib_devs_lock, flags);
669 dd = __qib_lookup(unit);
670 spin_unlock_irqrestore(&qib_devs_lock, flags);
671
672 return dd;
673}
674
675/*
676 * Stop the timers during unit shutdown, or after an error late
677 * in initialization.
678 */
679static void qib_stop_timers(struct qib_devdata *dd)
680{
681 struct qib_pportdata *ppd;
682 int pidx;
683
684 if (dd->stats_timer.data) {
685 del_timer_sync(&dd->stats_timer);
686 dd->stats_timer.data = 0;
687 }
688 if (dd->intrchk_timer.data) {
689 del_timer_sync(&dd->intrchk_timer);
690 dd->intrchk_timer.data = 0;
691 }
692 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
693 ppd = dd->pport + pidx;
694 if (ppd->hol_timer.data)
695 del_timer_sync(&ppd->hol_timer);
696 if (ppd->led_override_timer.data) {
697 del_timer_sync(&ppd->led_override_timer);
698 atomic_set(&ppd->led_override_timer_active, 0);
699 }
700 if (ppd->symerr_clear_timer.data)
701 del_timer_sync(&ppd->symerr_clear_timer);
702 }
703}
704
705/**
706 * qib_shutdown_device - shut down a device
707 * @dd: the qlogic_ib device
708 *
709 * This is called to make the device quiet when we are about to
710 * unload the driver, and also when the device is administratively
711 * disabled. It does not free any data structures.
712 * Everything it does has to be setup again by qib_init(dd, 1)
713 */
714static void qib_shutdown_device(struct qib_devdata *dd)
715{
716 struct qib_pportdata *ppd;
717 unsigned pidx;
718
719 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
720 ppd = dd->pport + pidx;
721
722 spin_lock_irq(&ppd->lflags_lock);
723 ppd->lflags &= ~(QIBL_LINKDOWN | QIBL_LINKINIT |
724 QIBL_LINKARMED | QIBL_LINKACTIVE |
725 QIBL_LINKV);
726 spin_unlock_irq(&ppd->lflags_lock);
727 *ppd->statusp &= ~(QIB_STATUS_IB_CONF | QIB_STATUS_IB_READY);
728 }
729 dd->flags &= ~QIB_INITTED;
730
731 /* mask interrupts, but not errors */
732 dd->f_set_intr_state(dd, 0);
733
734 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
735 ppd = dd->pport + pidx;
736 dd->f_rcvctrl(ppd, QIB_RCVCTRL_TAILUPD_DIS |
737 QIB_RCVCTRL_CTXT_DIS |
738 QIB_RCVCTRL_INTRAVAIL_DIS |
739 QIB_RCVCTRL_PKEY_ENB, -1);
740 /*
741 * Gracefully stop all sends allowing any in progress to
742 * trickle out first.
743 */
744 dd->f_sendctrl(ppd, QIB_SENDCTRL_CLEAR);
745 }
746
747 /*
748 * Enough for anything that's going to trickle out to have actually
749 * done so.
750 */
751 udelay(20);
752
753 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
754 ppd = dd->pport + pidx;
755 dd->f_setextled(ppd, 0); /* make sure LEDs are off */
756
757 if (dd->flags & QIB_HAS_SEND_DMA)
758 qib_teardown_sdma(ppd);
759
760 dd->f_sendctrl(ppd, QIB_SENDCTRL_AVAIL_DIS |
761 QIB_SENDCTRL_SEND_DIS);
762 /*
763 * Clear SerdesEnable.
764 * We can't count on interrupts since we are stopping.
765 */
766 dd->f_quiet_serdes(ppd);
767 }
768
769 qib_update_eeprom_log(dd);
770}
771
772/**
773 * qib_free_ctxtdata - free a context's allocated data
774 * @dd: the qlogic_ib device
775 * @rcd: the ctxtdata structure
776 *
777 * free up any allocated data for a context
778 * This should not touch anything that would affect a simultaneous
779 * re-allocation of context data, because it is called after qib_mutex
780 * is released (and can be called from reinit as well).
781 * It should never change any chip state, or global driver state.
782 */
783void qib_free_ctxtdata(struct qib_devdata *dd, struct qib_ctxtdata *rcd)
784{
785 if (!rcd)
786 return;
787
788 if (rcd->rcvhdrq) {
789 dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size,
790 rcd->rcvhdrq, rcd->rcvhdrq_phys);
791 rcd->rcvhdrq = NULL;
792 if (rcd->rcvhdrtail_kvaddr) {
793 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
794 rcd->rcvhdrtail_kvaddr,
795 rcd->rcvhdrqtailaddr_phys);
796 rcd->rcvhdrtail_kvaddr = NULL;
797 }
798 }
799 if (rcd->rcvegrbuf) {
800 unsigned e;
801
802 for (e = 0; e < rcd->rcvegrbuf_chunks; e++) {
803 void *base = rcd->rcvegrbuf[e];
804 size_t size = rcd->rcvegrbuf_size;
805
806 dma_free_coherent(&dd->pcidev->dev, size,
807 base, rcd->rcvegrbuf_phys[e]);
808 }
809 kfree(rcd->rcvegrbuf);
810 rcd->rcvegrbuf = NULL;
811 kfree(rcd->rcvegrbuf_phys);
812 rcd->rcvegrbuf_phys = NULL;
813 rcd->rcvegrbuf_chunks = 0;
814 }
815
816 kfree(rcd->tid_pg_list);
817 vfree(rcd->user_event_mask);
818 vfree(rcd->subctxt_uregbase);
819 vfree(rcd->subctxt_rcvegrbuf);
820 vfree(rcd->subctxt_rcvhdr_base);
821 kfree(rcd);
822}
823
824/*
825 * Perform a PIO buffer bandwidth write test, to verify proper system
826 * configuration. Even when all the setup calls work, occasionally
827 * BIOS or other issues can prevent write combining from working, or
828 * can cause other bandwidth problems to the chip.
829 *
830 * This test simply writes the same buffer over and over again, and
831 * measures close to the peak bandwidth to the chip (not testing
832 * data bandwidth to the wire). On chips that use an address-based
833 * trigger to send packets to the wire, this is easy. On chips that
834 * use a count to trigger, we want to make sure that the packet doesn't
835 * go out on the wire, or trigger flow control checks.
836 */
837static void qib_verify_pioperf(struct qib_devdata *dd)
838{
839 u32 pbnum, cnt, lcnt;
840 u32 __iomem *piobuf;
841 u32 *addr;
842 u64 msecs, emsecs;
843
844 piobuf = dd->f_getsendbuf(dd->pport, 0ULL, &pbnum);
845 if (!piobuf) {
846 qib_devinfo(dd->pcidev,
847 "No PIObufs for checking perf, skipping\n");
848 return;
849 }
850
851 /*
852 * Enough to give us a reasonable test, less than piobuf size, and
853 * likely multiple of store buffer length.
854 */
855 cnt = 1024;
856
857 addr = vmalloc(cnt);
858 if (!addr) {
859 qib_devinfo(dd->pcidev,
860 "Couldn't get memory for checking PIO perf,"
861 " skipping\n");
862 goto done;
863 }
864
865 preempt_disable(); /* we want reasonably accurate elapsed time */
866 msecs = 1 + jiffies_to_msecs(jiffies);
867 for (lcnt = 0; lcnt < 10000U; lcnt++) {
868 /* wait until we cross msec boundary */
869 if (jiffies_to_msecs(jiffies) >= msecs)
870 break;
871 udelay(1);
872 }
873
874 dd->f_set_armlaunch(dd, 0);
875
876 /*
877 * length 0, no dwords actually sent
878 */
879 writeq(0, piobuf);
880 qib_flush_wc();
881
882 /*
883 * This is only roughly accurate, since even with preempt we
884 * still take interrupts that could take a while. Running for
885 * >= 5 msec seems to get us "close enough" to accurate values.
886 */
887 msecs = jiffies_to_msecs(jiffies);
888 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
889 qib_pio_copy(piobuf + 64, addr, cnt >> 2);
890 emsecs = jiffies_to_msecs(jiffies) - msecs;
891 }
892
893 /* 1 GiB/sec, slightly over IB SDR line rate */
894 if (lcnt < (emsecs * 1024U))
895 qib_dev_err(dd,
896 "Performance problem: bandwidth to PIO buffers is "
897 "only %u MiB/sec\n",
898 lcnt / (u32) emsecs);
899
900 preempt_enable();
901
902 vfree(addr);
903
904done:
905 /* disarm piobuf, so it's available again */
906 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(pbnum));
907 qib_sendbuf_done(dd, pbnum);
908 dd->f_set_armlaunch(dd, 1);
909}
910
911
912void qib_free_devdata(struct qib_devdata *dd)
913{
914 unsigned long flags;
915
916 spin_lock_irqsave(&qib_devs_lock, flags);
917 idr_remove(&qib_unit_table, dd->unit);
918 list_del(&dd->list);
919 spin_unlock_irqrestore(&qib_devs_lock, flags);
920
921 ib_dealloc_device(&dd->verbs_dev.ibdev);
922}
923
924/*
925 * Allocate our primary per-unit data structure. Must be done via verbs
926 * allocator, because the verbs cleanup process both does cleanup and
927 * free of the data structure.
928 * "extra" is for chip-specific data.
929 *
930 * Use the idr mechanism to get a unit number for this unit.
931 */
932struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra)
933{
934 unsigned long flags;
935 struct qib_devdata *dd;
936 int ret;
937
938 if (!idr_pre_get(&qib_unit_table, GFP_KERNEL)) {
939 dd = ERR_PTR(-ENOMEM);
940 goto bail;
941 }
942
943 dd = (struct qib_devdata *) ib_alloc_device(sizeof(*dd) + extra);
944 if (!dd) {
945 dd = ERR_PTR(-ENOMEM);
946 goto bail;
947 }
948
949 spin_lock_irqsave(&qib_devs_lock, flags);
950 ret = idr_get_new(&qib_unit_table, dd, &dd->unit);
951 if (ret >= 0)
952 list_add(&dd->list, &qib_dev_list);
953 spin_unlock_irqrestore(&qib_devs_lock, flags);
954
955 if (ret < 0) {
956 qib_early_err(&pdev->dev,
957 "Could not allocate unit ID: error %d\n", -ret);
958 ib_dealloc_device(&dd->verbs_dev.ibdev);
959 dd = ERR_PTR(ret);
960 goto bail;
961 }
962
963 if (!qib_cpulist_count) {
964 u32 count = num_online_cpus();
965 qib_cpulist = kzalloc(BITS_TO_LONGS(count) *
966 sizeof(long), GFP_KERNEL);
967 if (qib_cpulist)
968 qib_cpulist_count = count;
969 else
970 qib_early_err(&pdev->dev, "Could not alloc cpulist "
971 "info, cpu affinity might be wrong\n");
972 }
973
974bail:
975 return dd;
976}
977
978/*
979 * Called from freeze mode handlers, and from PCI error
980 * reporting code. Should be paranoid about state of
981 * system and data structures.
982 */
983void qib_disable_after_error(struct qib_devdata *dd)
984{
985 if (dd->flags & QIB_INITTED) {
986 u32 pidx;
987
988 dd->flags &= ~QIB_INITTED;
989 if (dd->pport)
990 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
991 struct qib_pportdata *ppd;
992
993 ppd = dd->pport + pidx;
994 if (dd->flags & QIB_PRESENT) {
995 qib_set_linkstate(ppd,
996 QIB_IB_LINKDOWN_DISABLE);
997 dd->f_setextled(ppd, 0);
998 }
999 *ppd->statusp &= ~QIB_STATUS_IB_READY;
1000 }
1001 }
1002
1003 /*
1004 * Mark as having had an error for driver, and also
1005 * for /sys and status word mapped to user programs.
1006 * This marks unit as not usable, until reset.
1007 */
1008 if (dd->devstatusp)
1009 *dd->devstatusp |= QIB_STATUS_HWERROR;
1010}
1011
1012static void __devexit qib_remove_one(struct pci_dev *);
1013static int __devinit qib_init_one(struct pci_dev *,
1014 const struct pci_device_id *);
1015
1016#define DRIVER_LOAD_MSG "QLogic " QIB_DRV_NAME " loaded: "
1017#define PFX QIB_DRV_NAME ": "
1018
1019static DEFINE_PCI_DEVICE_TABLE(qib_pci_tbl) = {
1020 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_QLOGIC_IB_6120) },
1021 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7220) },
1022 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7322) },
1023 { 0, }
1024};
1025
1026MODULE_DEVICE_TABLE(pci, qib_pci_tbl);
1027
1028struct pci_driver qib_driver = {
1029 .name = QIB_DRV_NAME,
1030 .probe = qib_init_one,
1031 .remove = __devexit_p(qib_remove_one),
1032 .id_table = qib_pci_tbl,
1033 .err_handler = &qib_pci_err_handler,
1034};
1035
1036/*
1037 * Do all the generic driver unit- and chip-independent memory
1038 * allocation and initialization.
1039 */
1040static int __init qlogic_ib_init(void)
1041{
1042 int ret;
1043
1044 ret = qib_dev_init();
1045 if (ret)
1046 goto bail;
1047
1048 qib_cq_wq = create_singlethread_workqueue("qib_cq");
1049 if (!qib_cq_wq) {
1050 ret = -ENOMEM;
1051 goto bail_dev;
1052 }
1053
1054 /*
1055 * These must be called before the driver is registered with
1056 * the PCI subsystem.
1057 */
1058 idr_init(&qib_unit_table);
1059 if (!idr_pre_get(&qib_unit_table, GFP_KERNEL)) {
1060 printk(KERN_ERR QIB_DRV_NAME ": idr_pre_get() failed\n");
1061 ret = -ENOMEM;
1062 goto bail_cq_wq;
1063 }
1064
1065 ret = pci_register_driver(&qib_driver);
1066 if (ret < 0) {
1067 printk(KERN_ERR QIB_DRV_NAME
1068 ": Unable to register driver: error %d\n", -ret);
1069 goto bail_unit;
1070 }
1071
1072 /* not fatal if it doesn't work */
1073 if (qib_init_qibfs())
1074 printk(KERN_ERR QIB_DRV_NAME ": Unable to register ipathfs\n");
1075 goto bail; /* all OK */
1076
1077bail_unit:
1078 idr_destroy(&qib_unit_table);
1079bail_cq_wq:
1080 destroy_workqueue(qib_cq_wq);
1081bail_dev:
1082 qib_dev_cleanup();
1083bail:
1084 return ret;
1085}
1086
1087module_init(qlogic_ib_init);
1088
1089/*
1090 * Do the non-unit driver cleanup, memory free, etc. at unload.
1091 */
1092static void __exit qlogic_ib_cleanup(void)
1093{
1094 int ret;
1095
1096 ret = qib_exit_qibfs();
1097 if (ret)
1098 printk(KERN_ERR QIB_DRV_NAME ": "
1099 "Unable to cleanup counter filesystem: "
1100 "error %d\n", -ret);
1101
1102 pci_unregister_driver(&qib_driver);
1103
1104 destroy_workqueue(qib_cq_wq);
1105
1106 qib_cpulist_count = 0;
1107 kfree(qib_cpulist);
1108
1109 idr_destroy(&qib_unit_table);
1110 qib_dev_cleanup();
1111}
1112
1113module_exit(qlogic_ib_cleanup);
1114
1115/* this can only be called after a successful initialization */
1116static void cleanup_device_data(struct qib_devdata *dd)
1117{
1118 int ctxt;
1119 int pidx;
1120 struct qib_ctxtdata **tmp;
1121 unsigned long flags;
1122
1123 /* users can't do anything more with chip */
1124 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1125 if (dd->pport[pidx].statusp)
1126 *dd->pport[pidx].statusp &= ~QIB_STATUS_CHIP_PRESENT;
1127
1128 if (!qib_wc_pat)
1129 qib_disable_wc(dd);
1130
1131 if (dd->pioavailregs_dma) {
1132 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1133 (void *) dd->pioavailregs_dma,
1134 dd->pioavailregs_phys);
1135 dd->pioavailregs_dma = NULL;
1136 }
1137
1138 if (dd->pageshadow) {
1139 struct page **tmpp = dd->pageshadow;
1140 dma_addr_t *tmpd = dd->physshadow;
1141 int i, cnt = 0;
1142
1143 for (ctxt = 0; ctxt < dd->cfgctxts; ctxt++) {
1144 int ctxt_tidbase = ctxt * dd->rcvtidcnt;
1145 int maxtid = ctxt_tidbase + dd->rcvtidcnt;
1146
1147 for (i = ctxt_tidbase; i < maxtid; i++) {
1148 if (!tmpp[i])
1149 continue;
1150 pci_unmap_page(dd->pcidev, tmpd[i],
1151 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1152 qib_release_user_pages(&tmpp[i], 1);
1153 tmpp[i] = NULL;
1154 cnt++;
1155 }
1156 }
1157
1158 tmpp = dd->pageshadow;
1159 dd->pageshadow = NULL;
1160 vfree(tmpp);
1161 }
1162
1163 /*
1164 * Free any resources still in use (usually just kernel contexts)
1165 * at unload; we do for ctxtcnt, because that's what we allocate.
1166 * We acquire lock to be really paranoid that rcd isn't being
1167 * accessed from some interrupt-related code (that should not happen,
1168 * but best to be sure).
1169 */
1170 spin_lock_irqsave(&dd->uctxt_lock, flags);
1171 tmp = dd->rcd;
1172 dd->rcd = NULL;
1173 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
1174 for (ctxt = 0; tmp && ctxt < dd->ctxtcnt; ctxt++) {
1175 struct qib_ctxtdata *rcd = tmp[ctxt];
1176
1177 tmp[ctxt] = NULL; /* debugging paranoia */
1178 qib_free_ctxtdata(dd, rcd);
1179 }
1180 kfree(tmp);
1181 kfree(dd->boardname);
1182}
1183
1184/*
1185 * Clean up on unit shutdown, or error during unit load after
1186 * successful initialization.
1187 */
1188static void qib_postinit_cleanup(struct qib_devdata *dd)
1189{
1190 /*
1191 * Clean up chip-specific stuff.
1192 * We check for NULL here, because it's outside
1193 * the kregbase check, and we need to call it
1194 * after the free_irq. Thus it's possible that
1195 * the function pointers were never initialized.
1196 */
1197 if (dd->f_cleanup)
1198 dd->f_cleanup(dd);
1199
1200 qib_pcie_ddcleanup(dd);
1201
1202 cleanup_device_data(dd);
1203
1204 qib_free_devdata(dd);
1205}
1206
1207static int __devinit qib_init_one(struct pci_dev *pdev,
1208 const struct pci_device_id *ent)
1209{
1210 int ret, j, pidx, initfail;
1211 struct qib_devdata *dd = NULL;
1212
1213 ret = qib_pcie_init(pdev, ent);
1214 if (ret)
1215 goto bail;
1216
1217 /*
1218 * Do device-specific initialiation, function table setup, dd
1219 * allocation, etc.
1220 */
1221 switch (ent->device) {
1222 case PCI_DEVICE_ID_QLOGIC_IB_6120:
1223#ifdef CONFIG_PCI_MSI
1224 dd = qib_init_iba6120_funcs(pdev, ent);
1225#else
1226 qib_early_err(&pdev->dev, "QLogic PCIE device 0x%x cannot "
1227 "work if CONFIG_PCI_MSI is not enabled\n",
1228 ent->device);
1229 dd = ERR_PTR(-ENODEV);
1230#endif
1231 break;
1232
1233 case PCI_DEVICE_ID_QLOGIC_IB_7220:
1234 dd = qib_init_iba7220_funcs(pdev, ent);
1235 break;
1236
1237 case PCI_DEVICE_ID_QLOGIC_IB_7322:
1238 dd = qib_init_iba7322_funcs(pdev, ent);
1239 break;
1240
1241 default:
1242 qib_early_err(&pdev->dev, "Failing on unknown QLogic "
1243 "deviceid 0x%x\n", ent->device);
1244 ret = -ENODEV;
1245 }
1246
1247 if (IS_ERR(dd))
1248 ret = PTR_ERR(dd);
1249 if (ret)
1250 goto bail; /* error already printed */
1251
1252 /* do the generic initialization */
1253 initfail = qib_init(dd, 0);
1254
1255 ret = qib_register_ib_device(dd);
1256
1257 /*
1258 * Now ready for use. this should be cleared whenever we
1259 * detect a reset, or initiate one. If earlier failure,
1260 * we still create devices, so diags, etc. can be used
1261 * to determine cause of problem.
1262 */
1263 if (!qib_mini_init && !initfail && !ret)
1264 dd->flags |= QIB_INITTED;
1265
1266 j = qib_device_create(dd);
1267 if (j)
1268 qib_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1269 j = qibfs_add(dd);
1270 if (j)
1271 qib_dev_err(dd, "Failed filesystem setup for counters: %d\n",
1272 -j);
1273
1274 if (qib_mini_init || initfail || ret) {
1275 qib_stop_timers(dd);
1276 flush_workqueue(ib_wq);
1277 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1278 dd->f_quiet_serdes(dd->pport + pidx);
1279 if (qib_mini_init)
1280 goto bail;
1281 if (!j) {
1282 (void) qibfs_remove(dd);
1283 qib_device_remove(dd);
1284 }
1285 if (!ret)
1286 qib_unregister_ib_device(dd);
1287 qib_postinit_cleanup(dd);
1288 if (initfail)
1289 ret = initfail;
1290 goto bail;
1291 }
1292
1293 if (!qib_wc_pat) {
1294 ret = qib_enable_wc(dd);
1295 if (ret) {
1296 qib_dev_err(dd, "Write combining not enabled "
1297 "(err %d): performance may be poor\n",
1298 -ret);
1299 ret = 0;
1300 }
1301 }
1302
1303 qib_verify_pioperf(dd);
1304bail:
1305 return ret;
1306}
1307
1308static void __devexit qib_remove_one(struct pci_dev *pdev)
1309{
1310 struct qib_devdata *dd = pci_get_drvdata(pdev);
1311 int ret;
1312
1313 /* unregister from IB core */
1314 qib_unregister_ib_device(dd);
1315
1316 /*
1317 * Disable the IB link, disable interrupts on the device,
1318 * clear dma engines, etc.
1319 */
1320 if (!qib_mini_init)
1321 qib_shutdown_device(dd);
1322
1323 qib_stop_timers(dd);
1324
1325 /* wait until all of our (qsfp) queue_work() calls complete */
1326 flush_workqueue(ib_wq);
1327
1328 ret = qibfs_remove(dd);
1329 if (ret)
1330 qib_dev_err(dd, "Failed counters filesystem cleanup: %d\n",
1331 -ret);
1332
1333 qib_device_remove(dd);
1334
1335 qib_postinit_cleanup(dd);
1336}
1337
1338/**
1339 * qib_create_rcvhdrq - create a receive header queue
1340 * @dd: the qlogic_ib device
1341 * @rcd: the context data
1342 *
1343 * This must be contiguous memory (from an i/o perspective), and must be
1344 * DMA'able (which means for some systems, it will go through an IOMMU,
1345 * or be forced into a low address range).
1346 */
1347int qib_create_rcvhdrq(struct qib_devdata *dd, struct qib_ctxtdata *rcd)
1348{
1349 unsigned amt;
1350
1351 if (!rcd->rcvhdrq) {
1352 dma_addr_t phys_hdrqtail;
1353 gfp_t gfp_flags;
1354
1355 amt = ALIGN(dd->rcvhdrcnt * dd->rcvhdrentsize *
1356 sizeof(u32), PAGE_SIZE);
1357 gfp_flags = (rcd->ctxt >= dd->first_user_ctxt) ?
1358 GFP_USER : GFP_KERNEL;
1359 rcd->rcvhdrq = dma_alloc_coherent(
1360 &dd->pcidev->dev, amt, &rcd->rcvhdrq_phys,
1361 gfp_flags | __GFP_COMP);
1362
1363 if (!rcd->rcvhdrq) {
1364 qib_dev_err(dd, "attempt to allocate %d bytes "
1365 "for ctxt %u rcvhdrq failed\n",
1366 amt, rcd->ctxt);
1367 goto bail;
1368 }
1369
1370 if (rcd->ctxt >= dd->first_user_ctxt) {
1371 rcd->user_event_mask = vmalloc_user(PAGE_SIZE);
1372 if (!rcd->user_event_mask)
1373 goto bail_free_hdrq;
1374 }
1375
1376 if (!(dd->flags & QIB_NODMA_RTAIL)) {
1377 rcd->rcvhdrtail_kvaddr = dma_alloc_coherent(
1378 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1379 gfp_flags);
1380 if (!rcd->rcvhdrtail_kvaddr)
1381 goto bail_free;
1382 rcd->rcvhdrqtailaddr_phys = phys_hdrqtail;
1383 }
1384
1385 rcd->rcvhdrq_size = amt;
1386 }
1387
1388 /* clear for security and sanity on each use */
1389 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
1390 if (rcd->rcvhdrtail_kvaddr)
1391 memset(rcd->rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1392 return 0;
1393
1394bail_free:
1395 qib_dev_err(dd, "attempt to allocate 1 page for ctxt %u "
1396 "rcvhdrqtailaddr failed\n", rcd->ctxt);
1397 vfree(rcd->user_event_mask);
1398 rcd->user_event_mask = NULL;
1399bail_free_hdrq:
1400 dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1401 rcd->rcvhdrq_phys);
1402 rcd->rcvhdrq = NULL;
1403bail:
1404 return -ENOMEM;
1405}
1406
1407/**
1408 * allocate eager buffers, both kernel and user contexts.
1409 * @rcd: the context we are setting up.
1410 *
1411 * Allocate the eager TID buffers and program them into hip.
1412 * They are no longer completely contiguous, we do multiple allocation
1413 * calls. Otherwise we get the OOM code involved, by asking for too
1414 * much per call, with disastrous results on some kernels.
1415 */
1416int qib_setup_eagerbufs(struct qib_ctxtdata *rcd)
1417{
1418 struct qib_devdata *dd = rcd->dd;
1419 unsigned e, egrcnt, egrperchunk, chunk, egrsize, egroff;
1420 size_t size;
1421 gfp_t gfp_flags;
1422
1423 /*
1424 * GFP_USER, but without GFP_FS, so buffer cache can be
1425 * coalesced (we hope); otherwise, even at order 4,
1426 * heavy filesystem activity makes these fail, and we can
1427 * use compound pages.
1428 */
1429 gfp_flags = __GFP_WAIT | __GFP_IO | __GFP_COMP;
1430
1431 egrcnt = rcd->rcvegrcnt;
1432 egroff = rcd->rcvegr_tid_base;
1433 egrsize = dd->rcvegrbufsize;
1434
1435 chunk = rcd->rcvegrbuf_chunks;
1436 egrperchunk = rcd->rcvegrbufs_perchunk;
1437 size = rcd->rcvegrbuf_size;
1438 if (!rcd->rcvegrbuf) {
1439 rcd->rcvegrbuf =
1440 kzalloc(chunk * sizeof(rcd->rcvegrbuf[0]),
1441 GFP_KERNEL);
1442 if (!rcd->rcvegrbuf)
1443 goto bail;
1444 }
1445 if (!rcd->rcvegrbuf_phys) {
1446 rcd->rcvegrbuf_phys =
1447 kmalloc(chunk * sizeof(rcd->rcvegrbuf_phys[0]),
1448 GFP_KERNEL);
1449 if (!rcd->rcvegrbuf_phys)
1450 goto bail_rcvegrbuf;
1451 }
1452 for (e = 0; e < rcd->rcvegrbuf_chunks; e++) {
1453 if (rcd->rcvegrbuf[e])
1454 continue;
1455 rcd->rcvegrbuf[e] =
1456 dma_alloc_coherent(&dd->pcidev->dev, size,
1457 &rcd->rcvegrbuf_phys[e],
1458 gfp_flags);
1459 if (!rcd->rcvegrbuf[e])
1460 goto bail_rcvegrbuf_phys;
1461 }
1462
1463 rcd->rcvegr_phys = rcd->rcvegrbuf_phys[0];
1464
1465 for (e = chunk = 0; chunk < rcd->rcvegrbuf_chunks; chunk++) {
1466 dma_addr_t pa = rcd->rcvegrbuf_phys[chunk];
1467 unsigned i;
1468
1469 /* clear for security and sanity on each use */
1470 memset(rcd->rcvegrbuf[chunk], 0, size);
1471
1472 for (i = 0; e < egrcnt && i < egrperchunk; e++, i++) {
1473 dd->f_put_tid(dd, e + egroff +
1474 (u64 __iomem *)
1475 ((char __iomem *)
1476 dd->kregbase +
1477 dd->rcvegrbase),
1478 RCVHQ_RCV_TYPE_EAGER, pa);
1479 pa += egrsize;
1480 }
1481 cond_resched(); /* don't hog the cpu */
1482 }
1483
1484 return 0;
1485
1486bail_rcvegrbuf_phys:
1487 for (e = 0; e < rcd->rcvegrbuf_chunks && rcd->rcvegrbuf[e]; e++)
1488 dma_free_coherent(&dd->pcidev->dev, size,
1489 rcd->rcvegrbuf[e], rcd->rcvegrbuf_phys[e]);
1490 kfree(rcd->rcvegrbuf_phys);
1491 rcd->rcvegrbuf_phys = NULL;
1492bail_rcvegrbuf:
1493 kfree(rcd->rcvegrbuf);
1494 rcd->rcvegrbuf = NULL;
1495bail:
1496 return -ENOMEM;
1497}
1498
1499/*
1500 * Note: Changes to this routine should be mirrored
1501 * for the diagnostics routine qib_remap_ioaddr32().
1502 * There is also related code for VL15 buffers in qib_init_7322_variables().
1503 * The teardown code that unmaps is in qib_pcie_ddcleanup()
1504 */
1505int init_chip_wc_pat(struct qib_devdata *dd, u32 vl15buflen)
1506{
1507 u64 __iomem *qib_kregbase = NULL;
1508 void __iomem *qib_piobase = NULL;
1509 u64 __iomem *qib_userbase = NULL;
1510 u64 qib_kreglen;
1511 u64 qib_pio2koffset = dd->piobufbase & 0xffffffff;
1512 u64 qib_pio4koffset = dd->piobufbase >> 32;
1513 u64 qib_pio2klen = dd->piobcnt2k * dd->palign;
1514 u64 qib_pio4klen = dd->piobcnt4k * dd->align4k;
1515 u64 qib_physaddr = dd->physaddr;
1516 u64 qib_piolen;
1517 u64 qib_userlen = 0;
1518
1519 /*
1520 * Free the old mapping because the kernel will try to reuse the
1521 * old mapping and not create a new mapping with the
1522 * write combining attribute.
1523 */
1524 iounmap(dd->kregbase);
1525 dd->kregbase = NULL;
1526
1527 /*
1528 * Assumes chip address space looks like:
1529 * - kregs + sregs + cregs + uregs (in any order)
1530 * - piobufs (2K and 4K bufs in either order)
1531 * or:
1532 * - kregs + sregs + cregs (in any order)
1533 * - piobufs (2K and 4K bufs in either order)
1534 * - uregs
1535 */
1536 if (dd->piobcnt4k == 0) {
1537 qib_kreglen = qib_pio2koffset;
1538 qib_piolen = qib_pio2klen;
1539 } else if (qib_pio2koffset < qib_pio4koffset) {
1540 qib_kreglen = qib_pio2koffset;
1541 qib_piolen = qib_pio4koffset + qib_pio4klen - qib_kreglen;
1542 } else {
1543 qib_kreglen = qib_pio4koffset;
1544 qib_piolen = qib_pio2koffset + qib_pio2klen - qib_kreglen;
1545 }
1546 qib_piolen += vl15buflen;
1547 /* Map just the configured ports (not all hw ports) */
1548 if (dd->uregbase > qib_kreglen)
1549 qib_userlen = dd->ureg_align * dd->cfgctxts;
1550
1551 /* Sanity checks passed, now create the new mappings */
1552 qib_kregbase = ioremap_nocache(qib_physaddr, qib_kreglen);
1553 if (!qib_kregbase)
1554 goto bail;
1555
1556 qib_piobase = ioremap_wc(qib_physaddr + qib_kreglen, qib_piolen);
1557 if (!qib_piobase)
1558 goto bail_kregbase;
1559
1560 if (qib_userlen) {
1561 qib_userbase = ioremap_nocache(qib_physaddr + dd->uregbase,
1562 qib_userlen);
1563 if (!qib_userbase)
1564 goto bail_piobase;
1565 }
1566
1567 dd->kregbase = qib_kregbase;
1568 dd->kregend = (u64 __iomem *)
1569 ((char __iomem *) qib_kregbase + qib_kreglen);
1570 dd->piobase = qib_piobase;
1571 dd->pio2kbase = (void __iomem *)
1572 (((char __iomem *) dd->piobase) +
1573 qib_pio2koffset - qib_kreglen);
1574 if (dd->piobcnt4k)
1575 dd->pio4kbase = (void __iomem *)
1576 (((char __iomem *) dd->piobase) +
1577 qib_pio4koffset - qib_kreglen);
1578 if (qib_userlen)
1579 /* ureg will now be accessed relative to dd->userbase */
1580 dd->userbase = qib_userbase;
1581 return 0;
1582
1583bail_piobase:
1584 iounmap(qib_piobase);
1585bail_kregbase:
1586 iounmap(qib_kregbase);
1587bail:
1588 return -ENOMEM;
1589}