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1/*
2 * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
3 * module (C) 2006 Tim Small
4 *
5 * This file may be distributed under the terms of the GNU General
6 * Public License.
7 *
8 * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
9 * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
10 * others.
11 *
12 * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
13 *
14 * Written with reference to 82443BX Host Bridge Datasheet:
15 * http://download.intel.com/design/chipsets/datashts/29063301.pdf
16 * references to this document given in [].
17 *
18 * This module doesn't support the 440LX, but it may be possible to
19 * make it do so (the 440LX's register definitions are different, but
20 * not completely so - I haven't studied them in enough detail to know
21 * how easy this would be).
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26
27#include <linux/pci.h>
28#include <linux/pci_ids.h>
29
30
31#include <linux/edac.h>
32#include "edac_module.h"
33
34#define EDAC_MOD_STR "i82443bxgx_edac"
35
36/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
37 * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
38 * rows" "The 82443BX supports multiple-bit error detection and
39 * single-bit error correction when ECC mode is enabled and
40 * single/multi-bit error detection when correction is disabled.
41 * During writes to the DRAM, the 82443BX generates ECC for the data
42 * on a QWord basis. Partial QWord writes require a read-modify-write
43 * cycle when ECC is enabled."
44*/
45
46/* "Additionally, the 82443BX ensures that the data is corrected in
47 * main memory so that accumulation of errors is prevented. Another
48 * error within the same QWord would result in a double-bit error
49 * which is unrecoverable. This is known as hardware scrubbing since
50 * it requires no software intervention to correct the data in memory."
51 */
52
53/* [Also see page 100 (section 4.3), "DRAM Interface"]
54 * [Also see page 112 (section 4.6.1.4), ECC]
55 */
56
57#define I82443BXGX_NR_CSROWS 8
58#define I82443BXGX_NR_CHANS 1
59#define I82443BXGX_NR_DIMMS 4
60
61/* 82443 PCI Device 0 */
62#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
63 * config space offset */
64#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
65 * row is non-ECC */
66#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
67
68#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
69#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
70#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
71#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
72#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
73
74#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
75
76/* 82443 PCI Device 0 */
77#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
78 * config space offset, Error Address
79 * Pointer Register */
80#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
81#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
82#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
83
84#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
85 * config space offset. */
86#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
87#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
88
89#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
90 * config space offset. */
91#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
92#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
93#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
94#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
95
96#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
97 * config space offset. */
98#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
99#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
100#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
101#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
102
103#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
104 * config space offset. */
105
106/* FIXME - don't poll when ECC disabled? */
107
108struct i82443bxgx_edacmc_error_info {
109 u32 eap;
110};
111
112static struct edac_pci_ctl_info *i82443bxgx_pci;
113
114static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
115 * already registered driver
116 */
117
118static int i82443bxgx_registered = 1;
119
120static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
121 struct i82443bxgx_edacmc_error_info
122 *info)
123{
124 struct pci_dev *pdev;
125 pdev = to_pci_dev(mci->pdev);
126 pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
127 if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
128 /* Clear error to allow next error to be reported [p.61] */
129 pci_write_bits32(pdev, I82443BXGX_EAP,
130 I82443BXGX_EAP_OFFSET_SBE,
131 I82443BXGX_EAP_OFFSET_SBE);
132
133 if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
134 /* Clear error to allow next error to be reported [p.61] */
135 pci_write_bits32(pdev, I82443BXGX_EAP,
136 I82443BXGX_EAP_OFFSET_MBE,
137 I82443BXGX_EAP_OFFSET_MBE);
138}
139
140static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
141 struct
142 i82443bxgx_edacmc_error_info
143 *info, int handle_errors)
144{
145 int error_found = 0;
146 u32 eapaddr, page, pageoffset;
147
148 /* bits 30:12 hold the 4kb block in which the error occurred
149 * [p.61] */
150 eapaddr = (info->eap & 0xfffff000);
151 page = eapaddr >> PAGE_SHIFT;
152 pageoffset = eapaddr - (page << PAGE_SHIFT);
153
154 if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
155 error_found = 1;
156 if (handle_errors)
157 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
158 page, pageoffset, 0,
159 edac_mc_find_csrow_by_page(mci, page),
160 0, -1, mci->ctl_name, "");
161 }
162
163 if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
164 error_found = 1;
165 if (handle_errors)
166 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
167 page, pageoffset, 0,
168 edac_mc_find_csrow_by_page(mci, page),
169 0, -1, mci->ctl_name, "");
170 }
171
172 return error_found;
173}
174
175static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
176{
177 struct i82443bxgx_edacmc_error_info info;
178
179 i82443bxgx_edacmc_get_error_info(mci, &info);
180 i82443bxgx_edacmc_process_error_info(mci, &info, 1);
181}
182
183static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
184 struct pci_dev *pdev,
185 enum edac_type edac_mode,
186 enum mem_type mtype)
187{
188 struct csrow_info *csrow;
189 struct dimm_info *dimm;
190 int index;
191 u8 drbar, dramc;
192 u32 row_base, row_high_limit, row_high_limit_last;
193
194 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
195 row_high_limit_last = 0;
196 for (index = 0; index < mci->nr_csrows; index++) {
197 csrow = mci->csrows[index];
198 dimm = csrow->channels[0]->dimm;
199
200 pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
201 edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n",
202 mci->mc_idx, index, drbar);
203 row_high_limit = ((u32) drbar << 23);
204 /* find the DRAM Chip Select Base address and mask */
205 edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n",
206 mci->mc_idx, index, row_high_limit,
207 row_high_limit_last);
208
209 /* 440GX goes to 2GB, represented with a DRB of 0. */
210 if (row_high_limit_last && !row_high_limit)
211 row_high_limit = 1UL << 31;
212
213 /* This row is empty [p.49] */
214 if (row_high_limit == row_high_limit_last)
215 continue;
216 row_base = row_high_limit_last;
217 csrow->first_page = row_base >> PAGE_SHIFT;
218 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
219 dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
220 /* EAP reports in 4kilobyte granularity [61] */
221 dimm->grain = 1 << 12;
222 dimm->mtype = mtype;
223 /* I don't think 440BX can tell you device type? FIXME? */
224 dimm->dtype = DEV_UNKNOWN;
225 /* Mode is global to all rows on 440BX */
226 dimm->edac_mode = edac_mode;
227 row_high_limit_last = row_high_limit;
228 }
229}
230
231static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
232{
233 struct mem_ctl_info *mci;
234 struct edac_mc_layer layers[2];
235 u8 dramc;
236 u32 nbxcfg, ecc_mode;
237 enum mem_type mtype;
238 enum edac_type edac_mode;
239
240 edac_dbg(0, "MC:\n");
241
242 /* Something is really hosed if PCI config space reads from
243 * the MC aren't working.
244 */
245 if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
246 return -EIO;
247
248 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
249 layers[0].size = I82443BXGX_NR_CSROWS;
250 layers[0].is_virt_csrow = true;
251 layers[1].type = EDAC_MC_LAYER_CHANNEL;
252 layers[1].size = I82443BXGX_NR_CHANS;
253 layers[1].is_virt_csrow = false;
254 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
255 if (mci == NULL)
256 return -ENOMEM;
257
258 edac_dbg(0, "MC: mci = %p\n", mci);
259 mci->pdev = &pdev->dev;
260 mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
261 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
262 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
263 switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
264 case I82443BXGX_DRAMC_DRAM_IS_EDO:
265 mtype = MEM_EDO;
266 break;
267 case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
268 mtype = MEM_SDR;
269 break;
270 case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
271 mtype = MEM_RDR;
272 break;
273 default:
274 edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n");
275 mtype = -MEM_UNKNOWN;
276 }
277
278 if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
279 mci->edac_cap = mci->edac_ctl_cap;
280 else
281 mci->edac_cap = EDAC_FLAG_NONE;
282
283 mci->scrub_cap = SCRUB_FLAG_HW_SRC;
284 pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
285 ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
286 (BIT(0) | BIT(1)));
287
288 mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
289 ? SCRUB_HW_SRC : SCRUB_NONE;
290
291 switch (ecc_mode) {
292 case I82443BXGX_NBXCFG_INTEGRITY_NONE:
293 edac_mode = EDAC_NONE;
294 break;
295 case I82443BXGX_NBXCFG_INTEGRITY_EC:
296 edac_mode = EDAC_EC;
297 break;
298 case I82443BXGX_NBXCFG_INTEGRITY_ECC:
299 case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
300 edac_mode = EDAC_SECDED;
301 break;
302 default:
303 edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n");
304 edac_mode = EDAC_UNKNOWN;
305 break;
306 }
307
308 i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
309
310 /* Many BIOSes don't clear error flags on boot, so do this
311 * here, or we get "phantom" errors occurring at module-load
312 * time. */
313 pci_write_bits32(pdev, I82443BXGX_EAP,
314 (I82443BXGX_EAP_OFFSET_SBE |
315 I82443BXGX_EAP_OFFSET_MBE),
316 (I82443BXGX_EAP_OFFSET_SBE |
317 I82443BXGX_EAP_OFFSET_MBE));
318
319 mci->mod_name = EDAC_MOD_STR;
320 mci->ctl_name = "I82443BXGX";
321 mci->dev_name = pci_name(pdev);
322 mci->edac_check = i82443bxgx_edacmc_check;
323 mci->ctl_page_to_phys = NULL;
324
325 if (edac_mc_add_mc(mci)) {
326 edac_dbg(3, "failed edac_mc_add_mc()\n");
327 goto fail;
328 }
329
330 /* allocating generic PCI control info */
331 i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
332 if (!i82443bxgx_pci) {
333 printk(KERN_WARNING
334 "%s(): Unable to create PCI control\n",
335 __func__);
336 printk(KERN_WARNING
337 "%s(): PCI error report via EDAC not setup\n",
338 __func__);
339 }
340
341 edac_dbg(3, "MC: success\n");
342 return 0;
343
344fail:
345 edac_mc_free(mci);
346 return -ENODEV;
347}
348
349/* returns count (>= 0), or negative on error */
350static int i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
351 const struct pci_device_id *ent)
352{
353 int rc;
354
355 edac_dbg(0, "MC:\n");
356
357 /* don't need to call pci_enable_device() */
358 rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
359
360 if (mci_pdev == NULL)
361 mci_pdev = pci_dev_get(pdev);
362
363 return rc;
364}
365
366static void i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
367{
368 struct mem_ctl_info *mci;
369
370 edac_dbg(0, "\n");
371
372 if (i82443bxgx_pci)
373 edac_pci_release_generic_ctl(i82443bxgx_pci);
374
375 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
376 return;
377
378 edac_mc_free(mci);
379}
380
381static const struct pci_device_id i82443bxgx_pci_tbl[] = {
382 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
383 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
384 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
385 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
386 {0,} /* 0 terminated list. */
387};
388
389MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
390
391static struct pci_driver i82443bxgx_edacmc_driver = {
392 .name = EDAC_MOD_STR,
393 .probe = i82443bxgx_edacmc_init_one,
394 .remove = i82443bxgx_edacmc_remove_one,
395 .id_table = i82443bxgx_pci_tbl,
396};
397
398static int __init i82443bxgx_edacmc_init(void)
399{
400 int pci_rc;
401 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
402 opstate_init();
403
404 pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
405 if (pci_rc < 0)
406 goto fail0;
407
408 if (mci_pdev == NULL) {
409 const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
410 int i = 0;
411 i82443bxgx_registered = 0;
412
413 while (mci_pdev == NULL && id->vendor != 0) {
414 mci_pdev = pci_get_device(id->vendor,
415 id->device, NULL);
416 i++;
417 id = &i82443bxgx_pci_tbl[i];
418 }
419 if (!mci_pdev) {
420 edac_dbg(0, "i82443bxgx pci_get_device fail\n");
421 pci_rc = -ENODEV;
422 goto fail1;
423 }
424
425 pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);
426
427 if (pci_rc < 0) {
428 edac_dbg(0, "i82443bxgx init fail\n");
429 pci_rc = -ENODEV;
430 goto fail1;
431 }
432 }
433
434 return 0;
435
436fail1:
437 pci_unregister_driver(&i82443bxgx_edacmc_driver);
438
439fail0:
440 pci_dev_put(mci_pdev);
441 return pci_rc;
442}
443
444static void __exit i82443bxgx_edacmc_exit(void)
445{
446 pci_unregister_driver(&i82443bxgx_edacmc_driver);
447
448 if (!i82443bxgx_registered)
449 i82443bxgx_edacmc_remove_one(mci_pdev);
450
451 pci_dev_put(mci_pdev);
452}
453
454module_init(i82443bxgx_edacmc_init);
455module_exit(i82443bxgx_edacmc_exit);
456
457MODULE_LICENSE("GPL");
458MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
459MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
460
461module_param(edac_op_state, int, 0444);
462MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1/*
2 * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
3 * module (C) 2006 Tim Small
4 *
5 * This file may be distributed under the terms of the GNU General
6 * Public License.
7 *
8 * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
9 * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
10 * others.
11 *
12 * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
13 *
14 * Written with reference to 82443BX Host Bridge Datasheet:
15 * http://download.intel.com/design/chipsets/datashts/29063301.pdf
16 * references to this document given in [].
17 *
18 * This module doesn't support the 440LX, but it may be possible to
19 * make it do so (the 440LX's register definitions are different, but
20 * not completely so - I haven't studied them in enough detail to know
21 * how easy this would be).
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26
27#include <linux/pci.h>
28#include <linux/pci_ids.h>
29
30
31#include <linux/edac.h>
32#include "edac_core.h"
33
34#define I82443_REVISION "0.1"
35
36#define EDAC_MOD_STR "i82443bxgx_edac"
37
38/* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
39 * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
40 * rows" "The 82443BX supports multiple-bit error detection and
41 * single-bit error correction when ECC mode is enabled and
42 * single/multi-bit error detection when correction is disabled.
43 * During writes to the DRAM, the 82443BX generates ECC for the data
44 * on a QWord basis. Partial QWord writes require a read-modify-write
45 * cycle when ECC is enabled."
46*/
47
48/* "Additionally, the 82443BX ensures that the data is corrected in
49 * main memory so that accumulation of errors is prevented. Another
50 * error within the same QWord would result in a double-bit error
51 * which is unrecoverable. This is known as hardware scrubbing since
52 * it requires no software intervention to correct the data in memory."
53 */
54
55/* [Also see page 100 (section 4.3), "DRAM Interface"]
56 * [Also see page 112 (section 4.6.1.4), ECC]
57 */
58
59#define I82443BXGX_NR_CSROWS 8
60#define I82443BXGX_NR_CHANS 1
61#define I82443BXGX_NR_DIMMS 4
62
63/* 82443 PCI Device 0 */
64#define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
65 * config space offset */
66#define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
67 * row is non-ECC */
68#define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
69
70#define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
71#define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
72#define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
73#define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
74#define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
75
76#define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
77
78/* 82443 PCI Device 0 */
79#define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
80 * config space offset, Error Address
81 * Pointer Register */
82#define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
83#define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
84#define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
85
86#define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
87 * config space offset. */
88#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
89#define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
90
91#define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
92 * config space offset. */
93#define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
94#define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
95#define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
96#define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
97
98#define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
99 * config space offset. */
100#define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
101#define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
102#define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
103#define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
104
105#define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
106 * config space offset. */
107
108/* FIXME - don't poll when ECC disabled? */
109
110struct i82443bxgx_edacmc_error_info {
111 u32 eap;
112};
113
114static struct edac_pci_ctl_info *i82443bxgx_pci;
115
116static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
117 * already registered driver
118 */
119
120static int i82443bxgx_registered = 1;
121
122static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
123 struct i82443bxgx_edacmc_error_info
124 *info)
125{
126 struct pci_dev *pdev;
127 pdev = to_pci_dev(mci->dev);
128 pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
129 if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
130 /* Clear error to allow next error to be reported [p.61] */
131 pci_write_bits32(pdev, I82443BXGX_EAP,
132 I82443BXGX_EAP_OFFSET_SBE,
133 I82443BXGX_EAP_OFFSET_SBE);
134
135 if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
136 /* Clear error to allow next error to be reported [p.61] */
137 pci_write_bits32(pdev, I82443BXGX_EAP,
138 I82443BXGX_EAP_OFFSET_MBE,
139 I82443BXGX_EAP_OFFSET_MBE);
140}
141
142static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
143 struct
144 i82443bxgx_edacmc_error_info
145 *info, int handle_errors)
146{
147 int error_found = 0;
148 u32 eapaddr, page, pageoffset;
149
150 /* bits 30:12 hold the 4kb block in which the error occurred
151 * [p.61] */
152 eapaddr = (info->eap & 0xfffff000);
153 page = eapaddr >> PAGE_SHIFT;
154 pageoffset = eapaddr - (page << PAGE_SHIFT);
155
156 if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
157 error_found = 1;
158 if (handle_errors)
159 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
160 page, pageoffset, 0,
161 edac_mc_find_csrow_by_page(mci, page),
162 0, -1, mci->ctl_name, "", NULL);
163 }
164
165 if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
166 error_found = 1;
167 if (handle_errors)
168 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
169 page, pageoffset, 0,
170 edac_mc_find_csrow_by_page(mci, page),
171 0, -1, mci->ctl_name, "", NULL);
172 }
173
174 return error_found;
175}
176
177static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
178{
179 struct i82443bxgx_edacmc_error_info info;
180
181 debugf1("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__);
182 i82443bxgx_edacmc_get_error_info(mci, &info);
183 i82443bxgx_edacmc_process_error_info(mci, &info, 1);
184}
185
186static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
187 struct pci_dev *pdev,
188 enum edac_type edac_mode,
189 enum mem_type mtype)
190{
191 struct csrow_info *csrow;
192 struct dimm_info *dimm;
193 int index;
194 u8 drbar, dramc;
195 u32 row_base, row_high_limit, row_high_limit_last;
196
197 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
198 row_high_limit_last = 0;
199 for (index = 0; index < mci->nr_csrows; index++) {
200 csrow = &mci->csrows[index];
201 dimm = csrow->channels[0].dimm;
202
203 pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
204 debugf1("MC%d: %s: %s() Row=%d DRB = %#0x\n",
205 mci->mc_idx, __FILE__, __func__, index, drbar);
206 row_high_limit = ((u32) drbar << 23);
207 /* find the DRAM Chip Select Base address and mask */
208 debugf1("MC%d: %s: %s() Row=%d, "
209 "Boundary Address=%#0x, Last = %#0x\n",
210 mci->mc_idx, __FILE__, __func__, index, row_high_limit,
211 row_high_limit_last);
212
213 /* 440GX goes to 2GB, represented with a DRB of 0. */
214 if (row_high_limit_last && !row_high_limit)
215 row_high_limit = 1UL << 31;
216
217 /* This row is empty [p.49] */
218 if (row_high_limit == row_high_limit_last)
219 continue;
220 row_base = row_high_limit_last;
221 csrow->first_page = row_base >> PAGE_SHIFT;
222 csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
223 dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
224 /* EAP reports in 4kilobyte granularity [61] */
225 dimm->grain = 1 << 12;
226 dimm->mtype = mtype;
227 /* I don't think 440BX can tell you device type? FIXME? */
228 dimm->dtype = DEV_UNKNOWN;
229 /* Mode is global to all rows on 440BX */
230 dimm->edac_mode = edac_mode;
231 row_high_limit_last = row_high_limit;
232 }
233}
234
235static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
236{
237 struct mem_ctl_info *mci;
238 struct edac_mc_layer layers[2];
239 u8 dramc;
240 u32 nbxcfg, ecc_mode;
241 enum mem_type mtype;
242 enum edac_type edac_mode;
243
244 debugf0("MC: %s: %s()\n", __FILE__, __func__);
245
246 /* Something is really hosed if PCI config space reads from
247 * the MC aren't working.
248 */
249 if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
250 return -EIO;
251
252 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
253 layers[0].size = I82443BXGX_NR_CSROWS;
254 layers[0].is_virt_csrow = true;
255 layers[1].type = EDAC_MC_LAYER_CHANNEL;
256 layers[1].size = I82443BXGX_NR_CHANS;
257 layers[1].is_virt_csrow = false;
258 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
259 if (mci == NULL)
260 return -ENOMEM;
261
262 debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci);
263 mci->dev = &pdev->dev;
264 mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
265 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
266 pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
267 switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
268 case I82443BXGX_DRAMC_DRAM_IS_EDO:
269 mtype = MEM_EDO;
270 break;
271 case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
272 mtype = MEM_SDR;
273 break;
274 case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
275 mtype = MEM_RDR;
276 break;
277 default:
278 debugf0("Unknown/reserved DRAM type value "
279 "in DRAMC register!\n");
280 mtype = -MEM_UNKNOWN;
281 }
282
283 if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
284 mci->edac_cap = mci->edac_ctl_cap;
285 else
286 mci->edac_cap = EDAC_FLAG_NONE;
287
288 mci->scrub_cap = SCRUB_FLAG_HW_SRC;
289 pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
290 ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
291 (BIT(0) | BIT(1)));
292
293 mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
294 ? SCRUB_HW_SRC : SCRUB_NONE;
295
296 switch (ecc_mode) {
297 case I82443BXGX_NBXCFG_INTEGRITY_NONE:
298 edac_mode = EDAC_NONE;
299 break;
300 case I82443BXGX_NBXCFG_INTEGRITY_EC:
301 edac_mode = EDAC_EC;
302 break;
303 case I82443BXGX_NBXCFG_INTEGRITY_ECC:
304 case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
305 edac_mode = EDAC_SECDED;
306 break;
307 default:
308 debugf0("%s(): Unknown/reserved ECC state "
309 "in NBXCFG register!\n", __func__);
310 edac_mode = EDAC_UNKNOWN;
311 break;
312 }
313
314 i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
315
316 /* Many BIOSes don't clear error flags on boot, so do this
317 * here, or we get "phantom" errors occurring at module-load
318 * time. */
319 pci_write_bits32(pdev, I82443BXGX_EAP,
320 (I82443BXGX_EAP_OFFSET_SBE |
321 I82443BXGX_EAP_OFFSET_MBE),
322 (I82443BXGX_EAP_OFFSET_SBE |
323 I82443BXGX_EAP_OFFSET_MBE));
324
325 mci->mod_name = EDAC_MOD_STR;
326 mci->mod_ver = I82443_REVISION;
327 mci->ctl_name = "I82443BXGX";
328 mci->dev_name = pci_name(pdev);
329 mci->edac_check = i82443bxgx_edacmc_check;
330 mci->ctl_page_to_phys = NULL;
331
332 if (edac_mc_add_mc(mci)) {
333 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
334 goto fail;
335 }
336
337 /* allocating generic PCI control info */
338 i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
339 if (!i82443bxgx_pci) {
340 printk(KERN_WARNING
341 "%s(): Unable to create PCI control\n",
342 __func__);
343 printk(KERN_WARNING
344 "%s(): PCI error report via EDAC not setup\n",
345 __func__);
346 }
347
348 debugf3("MC: %s: %s(): success\n", __FILE__, __func__);
349 return 0;
350
351fail:
352 edac_mc_free(mci);
353 return -ENODEV;
354}
355
356EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1);
357
358/* returns count (>= 0), or negative on error */
359static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
360 const struct pci_device_id *ent)
361{
362 int rc;
363
364 debugf0("MC: %s: %s()\n", __FILE__, __func__);
365
366 /* don't need to call pci_enable_device() */
367 rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
368
369 if (mci_pdev == NULL)
370 mci_pdev = pci_dev_get(pdev);
371
372 return rc;
373}
374
375static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
376{
377 struct mem_ctl_info *mci;
378
379 debugf0("%s: %s()\n", __FILE__, __func__);
380
381 if (i82443bxgx_pci)
382 edac_pci_release_generic_ctl(i82443bxgx_pci);
383
384 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
385 return;
386
387 edac_mc_free(mci);
388}
389
390EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);
391
392static DEFINE_PCI_DEVICE_TABLE(i82443bxgx_pci_tbl) = {
393 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
394 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
395 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
396 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
397 {0,} /* 0 terminated list. */
398};
399
400MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
401
402static struct pci_driver i82443bxgx_edacmc_driver = {
403 .name = EDAC_MOD_STR,
404 .probe = i82443bxgx_edacmc_init_one,
405 .remove = __devexit_p(i82443bxgx_edacmc_remove_one),
406 .id_table = i82443bxgx_pci_tbl,
407};
408
409static int __init i82443bxgx_edacmc_init(void)
410{
411 int pci_rc;
412 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
413 opstate_init();
414
415 pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
416 if (pci_rc < 0)
417 goto fail0;
418
419 if (mci_pdev == NULL) {
420 const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
421 int i = 0;
422 i82443bxgx_registered = 0;
423
424 while (mci_pdev == NULL && id->vendor != 0) {
425 mci_pdev = pci_get_device(id->vendor,
426 id->device, NULL);
427 i++;
428 id = &i82443bxgx_pci_tbl[i];
429 }
430 if (!mci_pdev) {
431 debugf0("i82443bxgx pci_get_device fail\n");
432 pci_rc = -ENODEV;
433 goto fail1;
434 }
435
436 pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);
437
438 if (pci_rc < 0) {
439 debugf0("i82443bxgx init fail\n");
440 pci_rc = -ENODEV;
441 goto fail1;
442 }
443 }
444
445 return 0;
446
447fail1:
448 pci_unregister_driver(&i82443bxgx_edacmc_driver);
449
450fail0:
451 if (mci_pdev != NULL)
452 pci_dev_put(mci_pdev);
453
454 return pci_rc;
455}
456
457static void __exit i82443bxgx_edacmc_exit(void)
458{
459 pci_unregister_driver(&i82443bxgx_edacmc_driver);
460
461 if (!i82443bxgx_registered)
462 i82443bxgx_edacmc_remove_one(mci_pdev);
463
464 if (mci_pdev)
465 pci_dev_put(mci_pdev);
466}
467
468module_init(i82443bxgx_edacmc_init);
469module_exit(i82443bxgx_edacmc_exit);
470
471MODULE_LICENSE("GPL");
472MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
473MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
474
475module_param(edac_op_state, int, 0444);
476MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");