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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * (C) 2001 Dave Jones, Arjan van de ven.
4 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
5 *
6 * Based upon reverse engineered information, and on Intel documentation
7 * for chipsets ICH2-M and ICH3-M.
8 *
9 * Many thanks to Ducrot Bruno for finding and fixing the last
10 * "missing link" for ICH2-M/ICH3-M support, and to Thomas Winkler
11 * for extensive testing.
12 *
13 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
14 */
15
16
17/*********************************************************************
18 * SPEEDSTEP - DEFINITIONS *
19 *********************************************************************/
20
21#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/cpufreq.h>
27#include <linux/pci.h>
28#include <linux/sched.h>
29
30#include <asm/cpu_device_id.h>
31
32#include "speedstep-lib.h"
33
34
35/* speedstep_chipset:
36 * It is necessary to know which chipset is used. As accesses to
37 * this device occur at various places in this module, we need a
38 * static struct pci_dev * pointing to that device.
39 */
40static struct pci_dev *speedstep_chipset_dev;
41
42
43/* speedstep_processor
44 */
45static enum speedstep_processor speedstep_processor;
46
47static u32 pmbase;
48
49/*
50 * There are only two frequency states for each processor. Values
51 * are in kHz for the time being.
52 */
53static struct cpufreq_frequency_table speedstep_freqs[] = {
54 {0, SPEEDSTEP_HIGH, 0},
55 {0, SPEEDSTEP_LOW, 0},
56 {0, 0, CPUFREQ_TABLE_END},
57};
58
59
60/**
61 * speedstep_find_register - read the PMBASE address
62 *
63 * Returns: -ENODEV if no register could be found
64 */
65static int speedstep_find_register(void)
66{
67 if (!speedstep_chipset_dev)
68 return -ENODEV;
69
70 /* get PMBASE */
71 pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
72 if (!(pmbase & 0x01)) {
73 pr_err("could not find speedstep register\n");
74 return -ENODEV;
75 }
76
77 pmbase &= 0xFFFFFFFE;
78 if (!pmbase) {
79 pr_err("could not find speedstep register\n");
80 return -ENODEV;
81 }
82
83 pr_debug("pmbase is 0x%x\n", pmbase);
84 return 0;
85}
86
87/**
88 * speedstep_set_state - set the SpeedStep state
89 * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
90 *
91 * Tries to change the SpeedStep state. Can be called from
92 * smp_call_function_single.
93 */
94static void speedstep_set_state(unsigned int state)
95{
96 u8 pm2_blk;
97 u8 value;
98 unsigned long flags;
99
100 if (state > 0x1)
101 return;
102
103 /* Disable IRQs */
104 local_irq_save(flags);
105
106 /* read state */
107 value = inb(pmbase + 0x50);
108
109 pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
110
111 /* write new state */
112 value &= 0xFE;
113 value |= state;
114
115 pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);
116
117 /* Disable bus master arbitration */
118 pm2_blk = inb(pmbase + 0x20);
119 pm2_blk |= 0x01;
120 outb(pm2_blk, (pmbase + 0x20));
121
122 /* Actual transition */
123 outb(value, (pmbase + 0x50));
124
125 /* Restore bus master arbitration */
126 pm2_blk &= 0xfe;
127 outb(pm2_blk, (pmbase + 0x20));
128
129 /* check if transition was successful */
130 value = inb(pmbase + 0x50);
131
132 /* Enable IRQs */
133 local_irq_restore(flags);
134
135 pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
136
137 if (state == (value & 0x1))
138 pr_debug("change to %u MHz succeeded\n",
139 speedstep_get_frequency(speedstep_processor) / 1000);
140 else
141 pr_err("change failed - I/O error\n");
142
143 return;
144}
145
146/* Wrapper for smp_call_function_single. */
147static void _speedstep_set_state(void *_state)
148{
149 speedstep_set_state(*(unsigned int *)_state);
150}
151
152/**
153 * speedstep_activate - activate SpeedStep control in the chipset
154 *
155 * Tries to activate the SpeedStep status and control registers.
156 * Returns -EINVAL on an unsupported chipset, and zero on success.
157 */
158static int speedstep_activate(void)
159{
160 u16 value = 0;
161
162 if (!speedstep_chipset_dev)
163 return -EINVAL;
164
165 pci_read_config_word(speedstep_chipset_dev, 0x00A0, &value);
166 if (!(value & 0x08)) {
167 value |= 0x08;
168 pr_debug("activating SpeedStep (TM) registers\n");
169 pci_write_config_word(speedstep_chipset_dev, 0x00A0, value);
170 }
171
172 return 0;
173}
174
175
176/**
177 * speedstep_detect_chipset - detect the Southbridge which contains SpeedStep logic
178 *
179 * Detects ICH2-M, ICH3-M and ICH4-M so far. The pci_dev points to
180 * the LPC bridge / PM module which contains all power-management
181 * functions. Returns the SPEEDSTEP_CHIPSET_-number for the detected
182 * chipset, or zero on failure.
183 */
184static unsigned int speedstep_detect_chipset(void)
185{
186 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
187 PCI_DEVICE_ID_INTEL_82801DB_12,
188 PCI_ANY_ID, PCI_ANY_ID,
189 NULL);
190 if (speedstep_chipset_dev)
191 return 4; /* 4-M */
192
193 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
194 PCI_DEVICE_ID_INTEL_82801CA_12,
195 PCI_ANY_ID, PCI_ANY_ID,
196 NULL);
197 if (speedstep_chipset_dev)
198 return 3; /* 3-M */
199
200
201 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
202 PCI_DEVICE_ID_INTEL_82801BA_10,
203 PCI_ANY_ID, PCI_ANY_ID,
204 NULL);
205 if (speedstep_chipset_dev) {
206 /* speedstep.c causes lockups on Dell Inspirons 8000 and
207 * 8100 which use a pretty old revision of the 82815
208 * host bridge. Abort on these systems.
209 */
210 struct pci_dev *hostbridge;
211
212 hostbridge = pci_get_subsys(PCI_VENDOR_ID_INTEL,
213 PCI_DEVICE_ID_INTEL_82815_MC,
214 PCI_ANY_ID, PCI_ANY_ID,
215 NULL);
216
217 if (!hostbridge)
218 return 2; /* 2-M */
219
220 if (hostbridge->revision < 5) {
221 pr_debug("hostbridge does not support speedstep\n");
222 speedstep_chipset_dev = NULL;
223 pci_dev_put(hostbridge);
224 return 0;
225 }
226
227 pci_dev_put(hostbridge);
228 return 2; /* 2-M */
229 }
230
231 return 0;
232}
233
234static void get_freq_data(void *_speed)
235{
236 unsigned int *speed = _speed;
237
238 *speed = speedstep_get_frequency(speedstep_processor);
239}
240
241static unsigned int speedstep_get(unsigned int cpu)
242{
243 unsigned int speed;
244
245 /* You're supposed to ensure CPU is online. */
246 BUG_ON(smp_call_function_single(cpu, get_freq_data, &speed, 1));
247
248 pr_debug("detected %u kHz as current frequency\n", speed);
249 return speed;
250}
251
252/**
253 * speedstep_target - set a new CPUFreq policy
254 * @policy: new policy
255 * @index: index of target frequency
256 *
257 * Sets a new CPUFreq policy.
258 */
259static int speedstep_target(struct cpufreq_policy *policy, unsigned int index)
260{
261 unsigned int policy_cpu;
262
263 policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
264
265 smp_call_function_single(policy_cpu, _speedstep_set_state, &index,
266 true);
267
268 return 0;
269}
270
271
272struct get_freqs {
273 struct cpufreq_policy *policy;
274 int ret;
275};
276
277static void get_freqs_on_cpu(void *_get_freqs)
278{
279 struct get_freqs *get_freqs = _get_freqs;
280
281 get_freqs->ret =
282 speedstep_get_freqs(speedstep_processor,
283 &speedstep_freqs[SPEEDSTEP_LOW].frequency,
284 &speedstep_freqs[SPEEDSTEP_HIGH].frequency,
285 &get_freqs->policy->cpuinfo.transition_latency,
286 &speedstep_set_state);
287}
288
289static int speedstep_cpu_init(struct cpufreq_policy *policy)
290{
291 unsigned int policy_cpu;
292 struct get_freqs gf;
293
294 /* only run on CPU to be set, or on its sibling */
295#ifdef CONFIG_SMP
296 cpumask_copy(policy->cpus, topology_sibling_cpumask(policy->cpu));
297#endif
298 policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
299
300 /* detect low and high frequency and transition latency */
301 gf.policy = policy;
302 smp_call_function_single(policy_cpu, get_freqs_on_cpu, &gf, 1);
303 if (gf.ret)
304 return gf.ret;
305
306 policy->freq_table = speedstep_freqs;
307
308 return 0;
309}
310
311
312static struct cpufreq_driver speedstep_driver = {
313 .name = "speedstep-ich",
314 .verify = cpufreq_generic_frequency_table_verify,
315 .target_index = speedstep_target,
316 .init = speedstep_cpu_init,
317 .get = speedstep_get,
318 .attr = cpufreq_generic_attr,
319};
320
321static const struct x86_cpu_id ss_smi_ids[] = {
322 X86_MATCH_VENDOR_FAM_MODEL(INTEL, 6, 0x8, 0),
323 X86_MATCH_VENDOR_FAM_MODEL(INTEL, 6, 0xb, 0),
324 X86_MATCH_VENDOR_FAM_MODEL(INTEL, 15, 0x2, 0),
325 {}
326};
327
328/**
329 * speedstep_init - initializes the SpeedStep CPUFreq driver
330 *
331 * Initializes the SpeedStep support. Returns -ENODEV on unsupported
332 * devices, -EINVAL on problems during initiatization, and zero on
333 * success.
334 */
335static int __init speedstep_init(void)
336{
337 if (!x86_match_cpu(ss_smi_ids))
338 return -ENODEV;
339
340 /* detect processor */
341 speedstep_processor = speedstep_detect_processor();
342 if (!speedstep_processor) {
343 pr_debug("Intel(R) SpeedStep(TM) capable processor "
344 "not found\n");
345 return -ENODEV;
346 }
347
348 /* detect chipset */
349 if (!speedstep_detect_chipset()) {
350 pr_debug("Intel(R) SpeedStep(TM) for this chipset not "
351 "(yet) available.\n");
352 return -ENODEV;
353 }
354
355 /* activate speedstep support */
356 if (speedstep_activate()) {
357 pci_dev_put(speedstep_chipset_dev);
358 return -EINVAL;
359 }
360
361 if (speedstep_find_register())
362 return -ENODEV;
363
364 return cpufreq_register_driver(&speedstep_driver);
365}
366
367
368/**
369 * speedstep_exit - unregisters SpeedStep support
370 *
371 * Unregisters SpeedStep support.
372 */
373static void __exit speedstep_exit(void)
374{
375 pci_dev_put(speedstep_chipset_dev);
376 cpufreq_unregister_driver(&speedstep_driver);
377}
378
379
380MODULE_AUTHOR("Dave Jones, Dominik Brodowski <linux@brodo.de>");
381MODULE_DESCRIPTION("Speedstep driver for Intel mobile processors on chipsets "
382 "with ICH-M southbridges.");
383MODULE_LICENSE("GPL");
384
385module_init(speedstep_init);
386module_exit(speedstep_exit);
1/*
2 * (C) 2001 Dave Jones, Arjan van de ven.
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
4 *
5 * Licensed under the terms of the GNU GPL License version 2.
6 * Based upon reverse engineered information, and on Intel documentation
7 * for chipsets ICH2-M and ICH3-M.
8 *
9 * Many thanks to Ducrot Bruno for finding and fixing the last
10 * "missing link" for ICH2-M/ICH3-M support, and to Thomas Winkler
11 * for extensive testing.
12 *
13 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
14 */
15
16
17/*********************************************************************
18 * SPEEDSTEP - DEFINITIONS *
19 *********************************************************************/
20
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/cpufreq.h>
25#include <linux/pci.h>
26#include <linux/sched.h>
27
28#include <asm/cpu_device_id.h>
29
30#include "speedstep-lib.h"
31
32
33/* speedstep_chipset:
34 * It is necessary to know which chipset is used. As accesses to
35 * this device occur at various places in this module, we need a
36 * static struct pci_dev * pointing to that device.
37 */
38static struct pci_dev *speedstep_chipset_dev;
39
40
41/* speedstep_processor
42 */
43static enum speedstep_processor speedstep_processor;
44
45static u32 pmbase;
46
47/*
48 * There are only two frequency states for each processor. Values
49 * are in kHz for the time being.
50 */
51static struct cpufreq_frequency_table speedstep_freqs[] = {
52 {SPEEDSTEP_HIGH, 0},
53 {SPEEDSTEP_LOW, 0},
54 {0, CPUFREQ_TABLE_END},
55};
56
57
58/**
59 * speedstep_find_register - read the PMBASE address
60 *
61 * Returns: -ENODEV if no register could be found
62 */
63static int speedstep_find_register(void)
64{
65 if (!speedstep_chipset_dev)
66 return -ENODEV;
67
68 /* get PMBASE */
69 pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
70 if (!(pmbase & 0x01)) {
71 printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
72 return -ENODEV;
73 }
74
75 pmbase &= 0xFFFFFFFE;
76 if (!pmbase) {
77 printk(KERN_ERR "speedstep-ich: could not find speedstep register\n");
78 return -ENODEV;
79 }
80
81 pr_debug("pmbase is 0x%x\n", pmbase);
82 return 0;
83}
84
85/**
86 * speedstep_set_state - set the SpeedStep state
87 * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
88 *
89 * Tries to change the SpeedStep state. Can be called from
90 * smp_call_function_single.
91 */
92static void speedstep_set_state(unsigned int state)
93{
94 u8 pm2_blk;
95 u8 value;
96 unsigned long flags;
97
98 if (state > 0x1)
99 return;
100
101 /* Disable IRQs */
102 local_irq_save(flags);
103
104 /* read state */
105 value = inb(pmbase + 0x50);
106
107 pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
108
109 /* write new state */
110 value &= 0xFE;
111 value |= state;
112
113 pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);
114
115 /* Disable bus master arbitration */
116 pm2_blk = inb(pmbase + 0x20);
117 pm2_blk |= 0x01;
118 outb(pm2_blk, (pmbase + 0x20));
119
120 /* Actual transition */
121 outb(value, (pmbase + 0x50));
122
123 /* Restore bus master arbitration */
124 pm2_blk &= 0xfe;
125 outb(pm2_blk, (pmbase + 0x20));
126
127 /* check if transition was successful */
128 value = inb(pmbase + 0x50);
129
130 /* Enable IRQs */
131 local_irq_restore(flags);
132
133 pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
134
135 if (state == (value & 0x1))
136 pr_debug("change to %u MHz succeeded\n",
137 speedstep_get_frequency(speedstep_processor) / 1000);
138 else
139 printk(KERN_ERR "cpufreq: change failed - I/O error\n");
140
141 return;
142}
143
144/* Wrapper for smp_call_function_single. */
145static void _speedstep_set_state(void *_state)
146{
147 speedstep_set_state(*(unsigned int *)_state);
148}
149
150/**
151 * speedstep_activate - activate SpeedStep control in the chipset
152 *
153 * Tries to activate the SpeedStep status and control registers.
154 * Returns -EINVAL on an unsupported chipset, and zero on success.
155 */
156static int speedstep_activate(void)
157{
158 u16 value = 0;
159
160 if (!speedstep_chipset_dev)
161 return -EINVAL;
162
163 pci_read_config_word(speedstep_chipset_dev, 0x00A0, &value);
164 if (!(value & 0x08)) {
165 value |= 0x08;
166 pr_debug("activating SpeedStep (TM) registers\n");
167 pci_write_config_word(speedstep_chipset_dev, 0x00A0, value);
168 }
169
170 return 0;
171}
172
173
174/**
175 * speedstep_detect_chipset - detect the Southbridge which contains SpeedStep logic
176 *
177 * Detects ICH2-M, ICH3-M and ICH4-M so far. The pci_dev points to
178 * the LPC bridge / PM module which contains all power-management
179 * functions. Returns the SPEEDSTEP_CHIPSET_-number for the detected
180 * chipset, or zero on failure.
181 */
182static unsigned int speedstep_detect_chipset(void)
183{
184 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
185 PCI_DEVICE_ID_INTEL_82801DB_12,
186 PCI_ANY_ID, PCI_ANY_ID,
187 NULL);
188 if (speedstep_chipset_dev)
189 return 4; /* 4-M */
190
191 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
192 PCI_DEVICE_ID_INTEL_82801CA_12,
193 PCI_ANY_ID, PCI_ANY_ID,
194 NULL);
195 if (speedstep_chipset_dev)
196 return 3; /* 3-M */
197
198
199 speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
200 PCI_DEVICE_ID_INTEL_82801BA_10,
201 PCI_ANY_ID, PCI_ANY_ID,
202 NULL);
203 if (speedstep_chipset_dev) {
204 /* speedstep.c causes lockups on Dell Inspirons 8000 and
205 * 8100 which use a pretty old revision of the 82815
206 * host brige. Abort on these systems.
207 */
208 static struct pci_dev *hostbridge;
209
210 hostbridge = pci_get_subsys(PCI_VENDOR_ID_INTEL,
211 PCI_DEVICE_ID_INTEL_82815_MC,
212 PCI_ANY_ID, PCI_ANY_ID,
213 NULL);
214
215 if (!hostbridge)
216 return 2; /* 2-M */
217
218 if (hostbridge->revision < 5) {
219 pr_debug("hostbridge does not support speedstep\n");
220 speedstep_chipset_dev = NULL;
221 pci_dev_put(hostbridge);
222 return 0;
223 }
224
225 pci_dev_put(hostbridge);
226 return 2; /* 2-M */
227 }
228
229 return 0;
230}
231
232static void get_freq_data(void *_speed)
233{
234 unsigned int *speed = _speed;
235
236 *speed = speedstep_get_frequency(speedstep_processor);
237}
238
239static unsigned int speedstep_get(unsigned int cpu)
240{
241 unsigned int speed;
242
243 /* You're supposed to ensure CPU is online. */
244 if (smp_call_function_single(cpu, get_freq_data, &speed, 1) != 0)
245 BUG();
246
247 pr_debug("detected %u kHz as current frequency\n", speed);
248 return speed;
249}
250
251/**
252 * speedstep_target - set a new CPUFreq policy
253 * @policy: new policy
254 * @target_freq: the target frequency
255 * @relation: how that frequency relates to achieved frequency
256 * (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
257 *
258 * Sets a new CPUFreq policy.
259 */
260static int speedstep_target(struct cpufreq_policy *policy,
261 unsigned int target_freq,
262 unsigned int relation)
263{
264 unsigned int newstate = 0, policy_cpu;
265 struct cpufreq_freqs freqs;
266 int i;
267
268 if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0],
269 target_freq, relation, &newstate))
270 return -EINVAL;
271
272 policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
273 freqs.old = speedstep_get(policy_cpu);
274 freqs.new = speedstep_freqs[newstate].frequency;
275 freqs.cpu = policy->cpu;
276
277 pr_debug("transiting from %u to %u kHz\n", freqs.old, freqs.new);
278
279 /* no transition necessary */
280 if (freqs.old == freqs.new)
281 return 0;
282
283 for_each_cpu(i, policy->cpus) {
284 freqs.cpu = i;
285 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
286 }
287
288 smp_call_function_single(policy_cpu, _speedstep_set_state, &newstate,
289 true);
290
291 for_each_cpu(i, policy->cpus) {
292 freqs.cpu = i;
293 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
294 }
295
296 return 0;
297}
298
299
300/**
301 * speedstep_verify - verifies a new CPUFreq policy
302 * @policy: new policy
303 *
304 * Limit must be within speedstep_low_freq and speedstep_high_freq, with
305 * at least one border included.
306 */
307static int speedstep_verify(struct cpufreq_policy *policy)
308{
309 return cpufreq_frequency_table_verify(policy, &speedstep_freqs[0]);
310}
311
312struct get_freqs {
313 struct cpufreq_policy *policy;
314 int ret;
315};
316
317static void get_freqs_on_cpu(void *_get_freqs)
318{
319 struct get_freqs *get_freqs = _get_freqs;
320
321 get_freqs->ret =
322 speedstep_get_freqs(speedstep_processor,
323 &speedstep_freqs[SPEEDSTEP_LOW].frequency,
324 &speedstep_freqs[SPEEDSTEP_HIGH].frequency,
325 &get_freqs->policy->cpuinfo.transition_latency,
326 &speedstep_set_state);
327}
328
329static int speedstep_cpu_init(struct cpufreq_policy *policy)
330{
331 int result;
332 unsigned int policy_cpu, speed;
333 struct get_freqs gf;
334
335 /* only run on CPU to be set, or on its sibling */
336#ifdef CONFIG_SMP
337 cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu));
338#endif
339 policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
340
341 /* detect low and high frequency and transition latency */
342 gf.policy = policy;
343 smp_call_function_single(policy_cpu, get_freqs_on_cpu, &gf, 1);
344 if (gf.ret)
345 return gf.ret;
346
347 /* get current speed setting */
348 speed = speedstep_get(policy_cpu);
349 if (!speed)
350 return -EIO;
351
352 pr_debug("currently at %s speed setting - %i MHz\n",
353 (speed == speedstep_freqs[SPEEDSTEP_LOW].frequency)
354 ? "low" : "high",
355 (speed / 1000));
356
357 /* cpuinfo and default policy values */
358 policy->cur = speed;
359
360 result = cpufreq_frequency_table_cpuinfo(policy, speedstep_freqs);
361 if (result)
362 return result;
363
364 cpufreq_frequency_table_get_attr(speedstep_freqs, policy->cpu);
365
366 return 0;
367}
368
369
370static int speedstep_cpu_exit(struct cpufreq_policy *policy)
371{
372 cpufreq_frequency_table_put_attr(policy->cpu);
373 return 0;
374}
375
376static struct freq_attr *speedstep_attr[] = {
377 &cpufreq_freq_attr_scaling_available_freqs,
378 NULL,
379};
380
381
382static struct cpufreq_driver speedstep_driver = {
383 .name = "speedstep-ich",
384 .verify = speedstep_verify,
385 .target = speedstep_target,
386 .init = speedstep_cpu_init,
387 .exit = speedstep_cpu_exit,
388 .get = speedstep_get,
389 .owner = THIS_MODULE,
390 .attr = speedstep_attr,
391};
392
393static const struct x86_cpu_id ss_smi_ids[] = {
394 { X86_VENDOR_INTEL, 6, 0xb, },
395 { X86_VENDOR_INTEL, 6, 0x8, },
396 { X86_VENDOR_INTEL, 15, 2 },
397 {}
398};
399#if 0
400/* Autoload or not? Do not for now. */
401MODULE_DEVICE_TABLE(x86cpu, ss_smi_ids);
402#endif
403
404/**
405 * speedstep_init - initializes the SpeedStep CPUFreq driver
406 *
407 * Initializes the SpeedStep support. Returns -ENODEV on unsupported
408 * devices, -EINVAL on problems during initiatization, and zero on
409 * success.
410 */
411static int __init speedstep_init(void)
412{
413 if (!x86_match_cpu(ss_smi_ids))
414 return -ENODEV;
415
416 /* detect processor */
417 speedstep_processor = speedstep_detect_processor();
418 if (!speedstep_processor) {
419 pr_debug("Intel(R) SpeedStep(TM) capable processor "
420 "not found\n");
421 return -ENODEV;
422 }
423
424 /* detect chipset */
425 if (!speedstep_detect_chipset()) {
426 pr_debug("Intel(R) SpeedStep(TM) for this chipset not "
427 "(yet) available.\n");
428 return -ENODEV;
429 }
430
431 /* activate speedstep support */
432 if (speedstep_activate()) {
433 pci_dev_put(speedstep_chipset_dev);
434 return -EINVAL;
435 }
436
437 if (speedstep_find_register())
438 return -ENODEV;
439
440 return cpufreq_register_driver(&speedstep_driver);
441}
442
443
444/**
445 * speedstep_exit - unregisters SpeedStep support
446 *
447 * Unregisters SpeedStep support.
448 */
449static void __exit speedstep_exit(void)
450{
451 pci_dev_put(speedstep_chipset_dev);
452 cpufreq_unregister_driver(&speedstep_driver);
453}
454
455
456MODULE_AUTHOR("Dave Jones <davej@redhat.com>, "
457 "Dominik Brodowski <linux@brodo.de>");
458MODULE_DESCRIPTION("Speedstep driver for Intel mobile processors on chipsets "
459 "with ICH-M southbridges.");
460MODULE_LICENSE("GPL");
461
462module_init(speedstep_init);
463module_exit(speedstep_exit);