1// SPDX-License-Identifier: GPL-2.0
  2//
  3// Register cache access API
  4//
  5// Copyright 2011 Wolfson Microelectronics plc
  6//
  7// Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
 
 
 
 
  8
  9#include <linux/bsearch.h>
 10#include <linux/device.h>
 11#include <linux/export.h>
 12#include <linux/slab.h>
 
 
 
 
 13#include <linux/sort.h>
 14
 15#include "trace.h"
 16#include "internal.h"
 17
 18static const struct regcache_ops *cache_types[] = {
 19	&regcache_rbtree_ops,
 20	&regcache_maple_ops,
 21	&regcache_flat_ops,
 22};
 23
 24static int regcache_hw_init(struct regmap *map)
 25{
 26	int i, j;
 27	int ret;
 28	int count;
 29	unsigned int reg, val;
 30	void *tmp_buf;
 31
 32	if (!map->num_reg_defaults_raw)
 33		return -EINVAL;
 34
 35	/* calculate the size of reg_defaults */
 36	for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
 37		if (regmap_readable(map, i * map->reg_stride) &&
 38		    !regmap_volatile(map, i * map->reg_stride))
 39			count++;
 40
 41	/* all registers are unreadable or volatile, so just bypass */
 42	if (!count) {
 43		map->cache_bypass = true;
 44		return 0;
 45	}
 46
 47	map->num_reg_defaults = count;
 48	map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
 49					  GFP_KERNEL);
 50	if (!map->reg_defaults)
 51		return -ENOMEM;
 52
 53	if (!map->reg_defaults_raw) {
 54		bool cache_bypass = map->cache_bypass;
 55		dev_warn(map->dev, "No cache defaults, reading back from HW\n");
 56
 57		/* Bypass the cache access till data read from HW */
 58		map->cache_bypass = true;
 59		tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
 60		if (!tmp_buf) {
 61			ret = -ENOMEM;
 62			goto err_free;
 63		}
 64		ret = regmap_raw_read(map, 0, tmp_buf,
 65				      map->cache_size_raw);
 66		map->cache_bypass = cache_bypass;
 67		if (ret == 0) {
 68			map->reg_defaults_raw = tmp_buf;
 69			map->cache_free = true;
 70		} else {
 71			kfree(tmp_buf);
 
 72		}
 
 
 73	}
 74
 75	/* fill the reg_defaults */
 76	for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
 77		reg = i * map->reg_stride;
 78
 79		if (!regmap_readable(map, reg))
 80			continue;
 81
 82		if (regmap_volatile(map, reg))
 83			continue;
 
 
 84
 85		if (map->reg_defaults_raw) {
 86			val = regcache_get_val(map, map->reg_defaults_raw, i);
 87		} else {
 88			bool cache_bypass = map->cache_bypass;
 89
 90			map->cache_bypass = true;
 91			ret = regmap_read(map, reg, &val);
 92			map->cache_bypass = cache_bypass;
 93			if (ret != 0) {
 94				dev_err(map->dev, "Failed to read %d: %d\n",
 95					reg, ret);
 96				goto err_free;
 97			}
 98		}
 99
100		map->reg_defaults[j].reg = reg;
 
 
 
 
 
 
 
101		map->reg_defaults[j].def = val;
102		j++;
103	}
104
105	return 0;
106
107err_free:
108	kfree(map->reg_defaults);
 
109
110	return ret;
111}
112
113int regcache_init(struct regmap *map, const struct regmap_config *config)
114{
115	int ret;
116	int i;
117	void *tmp_buf;
118
119	if (map->cache_type == REGCACHE_NONE) {
120		if (config->reg_defaults || config->num_reg_defaults_raw)
121			dev_warn(map->dev,
122				 "No cache used with register defaults set!\n");
123
 
124		map->cache_bypass = true;
125		return 0;
126	}
127
128	if (config->reg_defaults && !config->num_reg_defaults) {
129		dev_err(map->dev,
130			 "Register defaults are set without the number!\n");
131		return -EINVAL;
132	}
133
134	if (config->num_reg_defaults && !config->reg_defaults) {
135		dev_err(map->dev,
136			"Register defaults number are set without the reg!\n");
137		return -EINVAL;
138	}
139
140	for (i = 0; i < config->num_reg_defaults; i++)
141		if (config->reg_defaults[i].reg % map->reg_stride)
142			return -EINVAL;
143
144	for (i = 0; i < ARRAY_SIZE(cache_types); i++)
145		if (cache_types[i]->type == map->cache_type)
146			break;
147
148	if (i == ARRAY_SIZE(cache_types)) {
149		dev_err(map->dev, "Could not match cache type: %d\n",
150			map->cache_type);
151		return -EINVAL;
152	}
153
154	map->num_reg_defaults = config->num_reg_defaults;
155	map->num_reg_defaults_raw = config->num_reg_defaults_raw;
156	map->reg_defaults_raw = config->reg_defaults_raw;
157	map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
158	map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
159
160	map->cache = NULL;
161	map->cache_ops = cache_types[i];
162
163	if (!map->cache_ops->read ||
164	    !map->cache_ops->write ||
165	    !map->cache_ops->name)
166		return -EINVAL;
167
168	/* We still need to ensure that the reg_defaults
169	 * won't vanish from under us.  We'll need to make
170	 * a copy of it.
171	 */
172	if (config->reg_defaults) {
 
 
173		tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
174				  sizeof(struct reg_default), GFP_KERNEL);
175		if (!tmp_buf)
176			return -ENOMEM;
177		map->reg_defaults = tmp_buf;
178	} else if (map->num_reg_defaults_raw) {
179		/* Some devices such as PMICs don't have cache defaults,
180		 * we cope with this by reading back the HW registers and
181		 * crafting the cache defaults by hand.
182		 */
183		ret = regcache_hw_init(map);
184		if (ret < 0)
185			return ret;
186		if (map->cache_bypass)
187			return 0;
188	}
189
190	if (!map->max_register && map->num_reg_defaults_raw)
191		map->max_register = (map->num_reg_defaults_raw  - 1) * map->reg_stride;
192
193	if (map->cache_ops->init) {
194		dev_dbg(map->dev, "Initializing %s cache\n",
195			map->cache_ops->name);
196		ret = map->cache_ops->init(map);
197		if (ret)
198			goto err_free;
199	}
200	return 0;
201
202err_free:
203	kfree(map->reg_defaults);
204	if (map->cache_free)
205		kfree(map->reg_defaults_raw);
206
207	return ret;
208}
209
210void regcache_exit(struct regmap *map)
211{
212	if (map->cache_type == REGCACHE_NONE)
213		return;
214
215	BUG_ON(!map->cache_ops);
216
217	kfree(map->reg_defaults);
218	if (map->cache_free)
219		kfree(map->reg_defaults_raw);
220
221	if (map->cache_ops->exit) {
222		dev_dbg(map->dev, "Destroying %s cache\n",
223			map->cache_ops->name);
224		map->cache_ops->exit(map);
225	}
226}
227
228/**
229 * regcache_read - Fetch the value of a given register from the cache.
230 *
231 * @map: map to configure.
232 * @reg: The register index.
233 * @value: The value to be returned.
234 *
235 * Return a negative value on failure, 0 on success.
236 */
237int regcache_read(struct regmap *map,
238		  unsigned int reg, unsigned int *value)
239{
240	int ret;
241
242	if (map->cache_type == REGCACHE_NONE)
243		return -EINVAL;
244
245	BUG_ON(!map->cache_ops);
246
247	if (!regmap_volatile(map, reg)) {
248		ret = map->cache_ops->read(map, reg, value);
249
250		if (ret == 0)
251			trace_regmap_reg_read_cache(map, reg, *value);
252
253		return ret;
254	}
255
256	return -EINVAL;
257}
258
259/**
260 * regcache_write - Set the value of a given register in the cache.
261 *
262 * @map: map to configure.
263 * @reg: The register index.
264 * @value: The new register value.
265 *
266 * Return a negative value on failure, 0 on success.
267 */
268int regcache_write(struct regmap *map,
269		   unsigned int reg, unsigned int value)
270{
271	if (map->cache_type == REGCACHE_NONE)
272		return 0;
273
274	BUG_ON(!map->cache_ops);
275
276	if (!regmap_volatile(map, reg))
277		return map->cache_ops->write(map, reg, value);
278
279	return 0;
280}
281
282bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
283			     unsigned int val)
284{
285	int ret;
286
287	if (!regmap_writeable(map, reg))
288		return false;
289
290	/* If we don't know the chip just got reset, then sync everything. */
291	if (!map->no_sync_defaults)
292		return true;
293
294	/* Is this the hardware default?  If so skip. */
295	ret = regcache_lookup_reg(map, reg);
296	if (ret >= 0 && val == map->reg_defaults[ret].def)
297		return false;
298	return true;
299}
300
301static int regcache_default_sync(struct regmap *map, unsigned int min,
302				 unsigned int max)
303{
304	unsigned int reg;
305
306	for (reg = min; reg <= max; reg += map->reg_stride) {
307		unsigned int val;
308		int ret;
309
310		if (regmap_volatile(map, reg) ||
311		    !regmap_writeable(map, reg))
312			continue;
313
314		ret = regcache_read(map, reg, &val);
315		if (ret == -ENOENT)
316			continue;
317		if (ret)
318			return ret;
319
320		if (!regcache_reg_needs_sync(map, reg, val))
321			continue;
322
323		map->cache_bypass = true;
324		ret = _regmap_write(map, reg, val);
325		map->cache_bypass = false;
326		if (ret) {
327			dev_err(map->dev, "Unable to sync register %#x. %d\n",
328				reg, ret);
329			return ret;
330		}
331		dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
332	}
333
334	return 0;
335}
336
337static int rbtree_all(const void *key, const struct rb_node *node)
338{
339	return 0;
340}
341
342/**
343 * regcache_sync - Sync the register cache with the hardware.
344 *
345 * @map: map to configure.
346 *
347 * Any registers that should not be synced should be marked as
348 * volatile.  In general drivers can choose not to use the provided
349 * syncing functionality if they so require.
350 *
351 * Return a negative value on failure, 0 on success.
352 */
353int regcache_sync(struct regmap *map)
354{
355	int ret = 0;
356	unsigned int i;
357	const char *name;
358	bool bypass;
359	struct rb_node *node;
360
361	if (WARN_ON(map->cache_type == REGCACHE_NONE))
362		return -EINVAL;
363
364	BUG_ON(!map->cache_ops);
365
366	map->lock(map->lock_arg);
367	/* Remember the initial bypass state */
368	bypass = map->cache_bypass;
369	dev_dbg(map->dev, "Syncing %s cache\n",
370		map->cache_ops->name);
371	name = map->cache_ops->name;
372	trace_regcache_sync(map, name, "start");
373
374	if (!map->cache_dirty)
375		goto out;
376
377	/* Apply any patch first */
378	map->cache_bypass = true;
379	for (i = 0; i < map->patch_regs; i++) {
 
 
 
 
380		ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
381		if (ret != 0) {
382			dev_err(map->dev, "Failed to write %x = %x: %d\n",
383				map->patch[i].reg, map->patch[i].def, ret);
384			goto out;
385		}
386	}
387	map->cache_bypass = false;
388
389	if (map->cache_ops->sync)
390		ret = map->cache_ops->sync(map, 0, map->max_register);
391	else
392		ret = regcache_default_sync(map, 0, map->max_register);
393
394	if (ret == 0)
395		map->cache_dirty = false;
396
397out:
 
398	/* Restore the bypass state */
399	map->cache_bypass = bypass;
400	map->no_sync_defaults = false;
401
402	/*
403	 * If we did any paging with cache bypassed and a cached
404	 * paging register then the register and cache state might
405	 * have gone out of sync, force writes of all the paging
406	 * registers.
407	 */
408	rb_for_each(node, 0, &map->range_tree, rbtree_all) {
409		struct regmap_range_node *this =
410			rb_entry(node, struct regmap_range_node, node);
411
412		/* If there's nothing in the cache there's nothing to sync */
413		if (regcache_read(map, this->selector_reg, &i) != 0)
414			continue;
415
416		ret = _regmap_write(map, this->selector_reg, i);
417		if (ret != 0) {
418			dev_err(map->dev, "Failed to write %x = %x: %d\n",
419				this->selector_reg, i, ret);
420			break;
421		}
422	}
423
424	map->unlock(map->lock_arg);
425
426	regmap_async_complete(map);
427
428	trace_regcache_sync(map, name, "stop");
429
430	return ret;
431}
432EXPORT_SYMBOL_GPL(regcache_sync);
433
434/**
435 * regcache_sync_region - Sync part  of the register cache with the hardware.
436 *
437 * @map: map to sync.
438 * @min: first register to sync
439 * @max: last register to sync
440 *
441 * Write all non-default register values in the specified region to
442 * the hardware.
443 *
444 * Return a negative value on failure, 0 on success.
445 */
446int regcache_sync_region(struct regmap *map, unsigned int min,
447			 unsigned int max)
448{
449	int ret = 0;
450	const char *name;
451	bool bypass;
452
453	if (WARN_ON(map->cache_type == REGCACHE_NONE))
454		return -EINVAL;
455
456	BUG_ON(!map->cache_ops);
457
458	map->lock(map->lock_arg);
459
460	/* Remember the initial bypass state */
461	bypass = map->cache_bypass;
462
463	name = map->cache_ops->name;
464	dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
465
466	trace_regcache_sync(map, name, "start region");
467
468	if (!map->cache_dirty)
469		goto out;
470
471	map->async = true;
472
473	if (map->cache_ops->sync)
474		ret = map->cache_ops->sync(map, min, max);
475	else
476		ret = regcache_default_sync(map, min, max);
477
478out:
 
479	/* Restore the bypass state */
480	map->cache_bypass = bypass;
481	map->async = false;
482	map->no_sync_defaults = false;
483	map->unlock(map->lock_arg);
484
485	regmap_async_complete(map);
486
487	trace_regcache_sync(map, name, "stop region");
488
489	return ret;
490}
491EXPORT_SYMBOL_GPL(regcache_sync_region);
492
493/**
494 * regcache_drop_region - Discard part of the register cache
495 *
496 * @map: map to operate on
497 * @min: first register to discard
498 * @max: last register to discard
499 *
500 * Discard part of the register cache.
501 *
502 * Return a negative value on failure, 0 on success.
503 */
504int regcache_drop_region(struct regmap *map, unsigned int min,
505			 unsigned int max)
506{
507	int ret = 0;
508
509	if (!map->cache_ops || !map->cache_ops->drop)
510		return -EINVAL;
511
512	map->lock(map->lock_arg);
513
514	trace_regcache_drop_region(map, min, max);
515
516	ret = map->cache_ops->drop(map, min, max);
517
518	map->unlock(map->lock_arg);
519
520	return ret;
521}
522EXPORT_SYMBOL_GPL(regcache_drop_region);
523
524/**
525 * regcache_cache_only - Put a register map into cache only mode
526 *
527 * @map: map to configure
528 * @enable: flag if changes should be written to the hardware
529 *
530 * When a register map is marked as cache only writes to the register
531 * map API will only update the register cache, they will not cause
532 * any hardware changes.  This is useful for allowing portions of
533 * drivers to act as though the device were functioning as normal when
534 * it is disabled for power saving reasons.
535 */
536void regcache_cache_only(struct regmap *map, bool enable)
537{
538	map->lock(map->lock_arg);
539	WARN_ON(map->cache_type != REGCACHE_NONE &&
540		map->cache_bypass && enable);
541	map->cache_only = enable;
542	trace_regmap_cache_only(map, enable);
543	map->unlock(map->lock_arg);
544}
545EXPORT_SYMBOL_GPL(regcache_cache_only);
546
547/**
548 * regcache_mark_dirty - Indicate that HW registers were reset to default values
549 *
550 * @map: map to mark
551 *
552 * Inform regcache that the device has been powered down or reset, so that
553 * on resume, regcache_sync() knows to write out all non-default values
554 * stored in the cache.
555 *
556 * If this function is not called, regcache_sync() will assume that
557 * the hardware state still matches the cache state, modulo any writes that
558 * happened when cache_only was true.
559 */
560void regcache_mark_dirty(struct regmap *map)
561{
562	map->lock(map->lock_arg);
563	map->cache_dirty = true;
564	map->no_sync_defaults = true;
565	map->unlock(map->lock_arg);
566}
567EXPORT_SYMBOL_GPL(regcache_mark_dirty);
568
569/**
570 * regcache_cache_bypass - Put a register map into cache bypass mode
571 *
572 * @map: map to configure
573 * @enable: flag if changes should not be written to the cache
574 *
575 * When a register map is marked with the cache bypass option, writes
576 * to the register map API will only update the hardware and not
577 * the cache directly.  This is useful when syncing the cache back to
578 * the hardware.
579 */
580void regcache_cache_bypass(struct regmap *map, bool enable)
581{
582	map->lock(map->lock_arg);
583	WARN_ON(map->cache_only && enable);
584	map->cache_bypass = enable;
585	trace_regmap_cache_bypass(map, enable);
586	map->unlock(map->lock_arg);
587}
588EXPORT_SYMBOL_GPL(regcache_cache_bypass);
589
590/**
591 * regcache_reg_cached - Check if a register is cached
592 *
593 * @map: map to check
594 * @reg: register to check
595 *
596 * Reports if a register is cached.
597 */
598bool regcache_reg_cached(struct regmap *map, unsigned int reg)
599{
600	unsigned int val;
601	int ret;
602
603	map->lock(map->lock_arg);
604
605	ret = regcache_read(map, reg, &val);
606
607	map->unlock(map->lock_arg);
608
609	return ret == 0;
610}
611EXPORT_SYMBOL_GPL(regcache_reg_cached);
612
613void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
614		      unsigned int val)
615{
616	/* Use device native format if possible */
617	if (map->format.format_val) {
618		map->format.format_val(base + (map->cache_word_size * idx),
619				       val, 0);
620		return;
621	}
622
623	switch (map->cache_word_size) {
624	case 1: {
625		u8 *cache = base;
626
 
627		cache[idx] = val;
628		break;
629	}
630	case 2: {
631		u16 *cache = base;
632
 
633		cache[idx] = val;
634		break;
635	}
636	case 4: {
637		u32 *cache = base;
638
 
639		cache[idx] = val;
640		break;
641	}
642	default:
643		BUG();
644	}
 
645}
646
647unsigned int regcache_get_val(struct regmap *map, const void *base,
648			      unsigned int idx)
649{
650	if (!base)
651		return -EINVAL;
652
653	/* Use device native format if possible */
654	if (map->format.parse_val)
655		return map->format.parse_val(regcache_get_val_addr(map, base,
656								   idx));
657
658	switch (map->cache_word_size) {
659	case 1: {
660		const u8 *cache = base;
661
662		return cache[idx];
663	}
664	case 2: {
665		const u16 *cache = base;
666
667		return cache[idx];
668	}
669	case 4: {
670		const u32 *cache = base;
671
672		return cache[idx];
673	}
674	default:
675		BUG();
676	}
677	/* unreachable */
678	return -1;
679}
680
681static int regcache_default_cmp(const void *a, const void *b)
682{
683	const struct reg_default *_a = a;
684	const struct reg_default *_b = b;
685
686	return _a->reg - _b->reg;
687}
688
689int regcache_lookup_reg(struct regmap *map, unsigned int reg)
690{
691	struct reg_default key;
692	struct reg_default *r;
693
694	key.reg = reg;
695	key.def = 0;
696
697	r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
698		    sizeof(struct reg_default), regcache_default_cmp);
699
700	if (r)
701		return r - map->reg_defaults;
702	else
703		return -ENOENT;
704}
705
706static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
707{
708	if (!cache_present)
709		return true;
710
711	return test_bit(idx, cache_present);
712}
713
714int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
715{
716	int ret;
717
718	if (!regcache_reg_needs_sync(map, reg, val))
719		return 0;
720
721	map->cache_bypass = true;
722
723	ret = _regmap_write(map, reg, val);
724
725	map->cache_bypass = false;
726
727	if (ret != 0) {
728		dev_err(map->dev, "Unable to sync register %#x. %d\n",
729			reg, ret);
730		return ret;
731	}
732	dev_dbg(map->dev, "Synced register %#x, value %#x\n",
733		reg, val);
734
735	return 0;
736}
737
738static int regcache_sync_block_single(struct regmap *map, void *block,
739				      unsigned long *cache_present,
740				      unsigned int block_base,
741				      unsigned int start, unsigned int end)
742{
743	unsigned int i, regtmp, val;
744	int ret;
745
746	for (i = start; i < end; i++) {
747		regtmp = block_base + (i * map->reg_stride);
748
749		if (!regcache_reg_present(cache_present, i) ||
750		    !regmap_writeable(map, regtmp))
751			continue;
752
753		val = regcache_get_val(map, block, i);
754		ret = regcache_sync_val(map, regtmp, val);
755		if (ret != 0)
756			return ret;
757	}
758
759	return 0;
760}
761
762static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
763					 unsigned int base, unsigned int cur)
764{
765	size_t val_bytes = map->format.val_bytes;
766	int ret, count;
767
768	if (*data == NULL)
769		return 0;
770
771	count = (cur - base) / map->reg_stride;
772
773	dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
774		count * val_bytes, count, base, cur - map->reg_stride);
775
776	map->cache_bypass = true;
777
778	ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
779	if (ret)
780		dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
781			base, cur - map->reg_stride, ret);
782
783	map->cache_bypass = false;
784
785	*data = NULL;
786
787	return ret;
788}
789
790static int regcache_sync_block_raw(struct regmap *map, void *block,
791			    unsigned long *cache_present,
792			    unsigned int block_base, unsigned int start,
793			    unsigned int end)
794{
795	unsigned int i, val;
796	unsigned int regtmp = 0;
797	unsigned int base = 0;
798	const void *data = NULL;
799	int ret;
800
801	for (i = start; i < end; i++) {
802		regtmp = block_base + (i * map->reg_stride);
803
804		if (!regcache_reg_present(cache_present, i) ||
805		    !regmap_writeable(map, regtmp)) {
806			ret = regcache_sync_block_raw_flush(map, &data,
807							    base, regtmp);
808			if (ret != 0)
809				return ret;
810			continue;
811		}
812
813		val = regcache_get_val(map, block, i);
814		if (!regcache_reg_needs_sync(map, regtmp, val)) {
815			ret = regcache_sync_block_raw_flush(map, &data,
816							    base, regtmp);
817			if (ret != 0)
818				return ret;
819			continue;
820		}
821
822		if (!data) {
823			data = regcache_get_val_addr(map, block, i);
824			base = regtmp;
825		}
826	}
827
828	return regcache_sync_block_raw_flush(map, &data, base, regtmp +
829			map->reg_stride);
830}
831
832int regcache_sync_block(struct regmap *map, void *block,
833			unsigned long *cache_present,
834			unsigned int block_base, unsigned int start,
835			unsigned int end)
836{
837	if (regmap_can_raw_write(map) && !map->use_single_write)
838		return regcache_sync_block_raw(map, block, cache_present,
839					       block_base, start, end);
840	else
841		return regcache_sync_block_single(map, block, cache_present,
842						  block_base, start, end);
843}