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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Numascale NumaConnect-Specific APIC Code
7 *
8 * Copyright (C) 2011 Numascale AS. All rights reserved.
9 *
10 * Send feedback to <support@numascale.com>
11 *
12 */
13#include <linux/types.h>
14#include <linux/init.h>
15#include <linux/pgtable.h>
16
17#include <asm/numachip/numachip.h>
18#include <asm/numachip/numachip_csr.h>
19
20
21#include "local.h"
22
23u8 numachip_system __read_mostly;
24static const struct apic apic_numachip1;
25static const struct apic apic_numachip2;
26static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly;
27
28static u32 numachip1_get_apic_id(u32 x)
29{
30 unsigned long value;
31 unsigned int id = (x >> 24) & 0xff;
32
33 if (static_cpu_has(X86_FEATURE_NODEID_MSR)) {
34 rdmsrl(MSR_FAM10H_NODE_ID, value);
35 id |= (value << 2) & 0xff00;
36 }
37
38 return id;
39}
40
41static u32 numachip1_set_apic_id(u32 id)
42{
43 return (id & 0xff) << 24;
44}
45
46static u32 numachip2_get_apic_id(u32 x)
47{
48 u64 mcfg;
49
50 rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg);
51 return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24);
52}
53
54static u32 numachip2_set_apic_id(u32 id)
55{
56 return id << 24;
57}
58
59static u32 numachip_phys_pkg_id(u32 initial_apic_id, int index_msb)
60{
61 return initial_apic_id >> index_msb;
62}
63
64static void numachip1_apic_icr_write(int apicid, unsigned int val)
65{
66 write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val);
67}
68
69static void numachip2_apic_icr_write(int apicid, unsigned int val)
70{
71 numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val);
72}
73
74static int numachip_wakeup_secondary(u32 phys_apicid, unsigned long start_rip)
75{
76 numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);
77 numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |
78 (start_rip >> 12));
79
80 return 0;
81}
82
83static void numachip_send_IPI_one(int cpu, int vector)
84{
85 int local_apicid, apicid = per_cpu(x86_cpu_to_apicid, cpu);
86 unsigned int dmode;
87
88 preempt_disable();
89 local_apicid = __this_cpu_read(x86_cpu_to_apicid);
90
91 /* Send via local APIC where non-local part matches */
92 if (!((apicid ^ local_apicid) >> NUMACHIP_LAPIC_BITS)) {
93 unsigned long flags;
94
95 local_irq_save(flags);
96 __default_send_IPI_dest_field(apicid, vector,
97 APIC_DEST_PHYSICAL);
98 local_irq_restore(flags);
99 preempt_enable();
100 return;
101 }
102 preempt_enable();
103
104 dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED;
105 numachip_apic_icr_write(apicid, dmode | vector);
106}
107
108static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
109{
110 unsigned int cpu;
111
112 for_each_cpu(cpu, mask)
113 numachip_send_IPI_one(cpu, vector);
114}
115
116static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
117 int vector)
118{
119 unsigned int this_cpu = smp_processor_id();
120 unsigned int cpu;
121
122 for_each_cpu(cpu, mask) {
123 if (cpu != this_cpu)
124 numachip_send_IPI_one(cpu, vector);
125 }
126}
127
128static void numachip_send_IPI_allbutself(int vector)
129{
130 unsigned int this_cpu = smp_processor_id();
131 unsigned int cpu;
132
133 for_each_online_cpu(cpu) {
134 if (cpu != this_cpu)
135 numachip_send_IPI_one(cpu, vector);
136 }
137}
138
139static void numachip_send_IPI_all(int vector)
140{
141 numachip_send_IPI_mask(cpu_online_mask, vector);
142}
143
144static void numachip_send_IPI_self(int vector)
145{
146 apic_write(APIC_SELF_IPI, vector);
147}
148
149static int __init numachip1_probe(void)
150{
151 return apic == &apic_numachip1;
152}
153
154static int __init numachip2_probe(void)
155{
156 return apic == &apic_numachip2;
157}
158
159static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
160{
161 u64 val;
162 u32 nodes = 1;
163
164 c->topo.llc_id = node;
165
166 /* Account for nodes per socket in multi-core-module processors */
167 if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
168 rdmsrl(MSR_FAM10H_NODE_ID, val);
169 nodes = ((val >> 3) & 7) + 1;
170 }
171
172 c->topo.pkg_id = node / nodes;
173}
174
175static int __init numachip_system_init(void)
176{
177 /* Map the LCSR area and set up the apic_icr_write function */
178 switch (numachip_system) {
179 case 1:
180 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
181 numachip_apic_icr_write = numachip1_apic_icr_write;
182 break;
183 case 2:
184 init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE);
185 numachip_apic_icr_write = numachip2_apic_icr_write;
186 break;
187 default:
188 return 0;
189 }
190
191 x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
192 x86_init.pci.arch_init = pci_numachip_init;
193
194 return 0;
195}
196early_initcall(numachip_system_init);
197
198static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
199{
200 if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
201 (strncmp(oem_table_id, "NCONNECT", 8) != 0))
202 return 0;
203
204 numachip_system = 1;
205
206 return 1;
207}
208
209static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
210{
211 if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
212 (strncmp(oem_table_id, "NCONECT2", 8) != 0))
213 return 0;
214
215 numachip_system = 2;
216
217 return 1;
218}
219
220static const struct apic apic_numachip1 __refconst = {
221 .name = "NumaConnect system",
222 .probe = numachip1_probe,
223 .acpi_madt_oem_check = numachip1_acpi_madt_oem_check,
224
225 .dest_mode_logical = false,
226
227 .disable_esr = 0,
228
229 .cpu_present_to_apicid = default_cpu_present_to_apicid,
230 .phys_pkg_id = numachip_phys_pkg_id,
231
232 .max_apic_id = UINT_MAX,
233 .get_apic_id = numachip1_get_apic_id,
234 .set_apic_id = numachip1_set_apic_id,
235
236 .calc_dest_apicid = apic_default_calc_apicid,
237
238 .send_IPI = numachip_send_IPI_one,
239 .send_IPI_mask = numachip_send_IPI_mask,
240 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
241 .send_IPI_allbutself = numachip_send_IPI_allbutself,
242 .send_IPI_all = numachip_send_IPI_all,
243 .send_IPI_self = numachip_send_IPI_self,
244
245 .wakeup_secondary_cpu = numachip_wakeup_secondary,
246
247 .read = native_apic_mem_read,
248 .write = native_apic_mem_write,
249 .eoi = native_apic_mem_eoi,
250 .icr_read = native_apic_icr_read,
251 .icr_write = native_apic_icr_write,
252};
253
254apic_driver(apic_numachip1);
255
256static const struct apic apic_numachip2 __refconst = {
257 .name = "NumaConnect2 system",
258 .probe = numachip2_probe,
259 .acpi_madt_oem_check = numachip2_acpi_madt_oem_check,
260
261 .dest_mode_logical = false,
262
263 .disable_esr = 0,
264
265 .cpu_present_to_apicid = default_cpu_present_to_apicid,
266 .phys_pkg_id = numachip_phys_pkg_id,
267
268 .max_apic_id = UINT_MAX,
269 .get_apic_id = numachip2_get_apic_id,
270 .set_apic_id = numachip2_set_apic_id,
271
272 .calc_dest_apicid = apic_default_calc_apicid,
273
274 .send_IPI = numachip_send_IPI_one,
275 .send_IPI_mask = numachip_send_IPI_mask,
276 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
277 .send_IPI_allbutself = numachip_send_IPI_allbutself,
278 .send_IPI_all = numachip_send_IPI_all,
279 .send_IPI_self = numachip_send_IPI_self,
280
281 .wakeup_secondary_cpu = numachip_wakeup_secondary,
282
283 .read = native_apic_mem_read,
284 .write = native_apic_mem_write,
285 .eoi = native_apic_mem_eoi,
286 .icr_read = native_apic_icr_read,
287 .icr_write = native_apic_icr_write,
288};
289
290apic_driver(apic_numachip2);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Numascale NumaConnect-Specific APIC Code
7 *
8 * Copyright (C) 2011 Numascale AS. All rights reserved.
9 *
10 * Send feedback to <support@numascale.com>
11 *
12 */
13
14#include <linux/errno.h>
15#include <linux/threads.h>
16#include <linux/cpumask.h>
17#include <linux/string.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/ctype.h>
21#include <linux/init.h>
22#include <linux/hardirq.h>
23#include <linux/delay.h>
24
25#include <asm/numachip/numachip_csr.h>
26#include <asm/smp.h>
27#include <asm/apic.h>
28#include <asm/ipi.h>
29#include <asm/apic_flat_64.h>
30
31static int numachip_system __read_mostly;
32
33static struct apic apic_numachip __read_mostly;
34
35static unsigned int get_apic_id(unsigned long x)
36{
37 unsigned long value;
38 unsigned int id;
39
40 rdmsrl(MSR_FAM10H_NODE_ID, value);
41 id = ((x >> 24) & 0xffU) | ((value << 2) & 0x3f00U);
42
43 return id;
44}
45
46static unsigned long set_apic_id(unsigned int id)
47{
48 unsigned long x;
49
50 x = ((id & 0xffU) << 24);
51 return x;
52}
53
54static unsigned int read_xapic_id(void)
55{
56 return get_apic_id(apic_read(APIC_ID));
57}
58
59static int numachip_apic_id_valid(int apicid)
60{
61 /* Trust what bootloader passes in MADT */
62 return 1;
63}
64
65static int numachip_apic_id_registered(void)
66{
67 return physid_isset(read_xapic_id(), phys_cpu_present_map);
68}
69
70static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
71{
72 return initial_apic_id >> index_msb;
73}
74
75static const struct cpumask *numachip_target_cpus(void)
76{
77 return cpu_online_mask;
78}
79
80static void numachip_vector_allocation_domain(int cpu, struct cpumask *retmask)
81{
82 cpumask_clear(retmask);
83 cpumask_set_cpu(cpu, retmask);
84}
85
86static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
87{
88 union numachip_csr_g3_ext_irq_gen int_gen;
89
90 int_gen.s._destination_apic_id = phys_apicid;
91 int_gen.s._vector = 0;
92 int_gen.s._msgtype = APIC_DM_INIT >> 8;
93 int_gen.s._index = 0;
94
95 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
96
97 int_gen.s._msgtype = APIC_DM_STARTUP >> 8;
98 int_gen.s._vector = start_rip >> 12;
99
100 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
101
102 atomic_set(&init_deasserted, 1);
103 return 0;
104}
105
106static void numachip_send_IPI_one(int cpu, int vector)
107{
108 union numachip_csr_g3_ext_irq_gen int_gen;
109 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
110
111 int_gen.s._destination_apic_id = apicid;
112 int_gen.s._vector = vector;
113 int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8;
114 int_gen.s._index = 0;
115
116 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
117}
118
119static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
120{
121 unsigned int cpu;
122
123 for_each_cpu(cpu, mask)
124 numachip_send_IPI_one(cpu, vector);
125}
126
127static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
128 int vector)
129{
130 unsigned int this_cpu = smp_processor_id();
131 unsigned int cpu;
132
133 for_each_cpu(cpu, mask) {
134 if (cpu != this_cpu)
135 numachip_send_IPI_one(cpu, vector);
136 }
137}
138
139static void numachip_send_IPI_allbutself(int vector)
140{
141 unsigned int this_cpu = smp_processor_id();
142 unsigned int cpu;
143
144 for_each_online_cpu(cpu) {
145 if (cpu != this_cpu)
146 numachip_send_IPI_one(cpu, vector);
147 }
148}
149
150static void numachip_send_IPI_all(int vector)
151{
152 numachip_send_IPI_mask(cpu_online_mask, vector);
153}
154
155static void numachip_send_IPI_self(int vector)
156{
157 __default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
158}
159
160static unsigned int numachip_cpu_mask_to_apicid(const struct cpumask *cpumask)
161{
162 int cpu;
163
164 /*
165 * We're using fixed IRQ delivery, can only return one phys APIC ID.
166 * May as well be the first.
167 */
168 cpu = cpumask_first(cpumask);
169 if (likely((unsigned)cpu < nr_cpu_ids))
170 return per_cpu(x86_cpu_to_apicid, cpu);
171
172 return BAD_APICID;
173}
174
175static unsigned int
176numachip_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
177 const struct cpumask *andmask)
178{
179 int cpu;
180
181 /*
182 * We're using fixed IRQ delivery, can only return one phys APIC ID.
183 * May as well be the first.
184 */
185 for_each_cpu_and(cpu, cpumask, andmask) {
186 if (cpumask_test_cpu(cpu, cpu_online_mask))
187 break;
188 }
189 return per_cpu(x86_cpu_to_apicid, cpu);
190}
191
192static int __init numachip_probe(void)
193{
194 return apic == &apic_numachip;
195}
196
197static void __init map_csrs(void)
198{
199 printk(KERN_INFO "NumaChip: Mapping local CSR space (%016llx - %016llx)\n",
200 NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_BASE + NUMACHIP_LCSR_SIZE - 1);
201 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
202
203 printk(KERN_INFO "NumaChip: Mapping global CSR space (%016llx - %016llx)\n",
204 NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_BASE + NUMACHIP_GCSR_SIZE - 1);
205 init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);
206}
207
208static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
209{
210
211 if (c->phys_proc_id != node) {
212 c->phys_proc_id = node;
213 per_cpu(cpu_llc_id, smp_processor_id()) = node;
214 }
215}
216
217static int __init numachip_system_init(void)
218{
219 unsigned int val;
220
221 if (!numachip_system)
222 return 0;
223
224 x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
225
226 map_csrs();
227
228 val = read_lcsr(CSR_G0_NODE_IDS);
229 printk(KERN_INFO "NumaChip: Local NodeID = %08x\n", val);
230
231 return 0;
232}
233early_initcall(numachip_system_init);
234
235static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
236{
237 if (!strncmp(oem_id, "NUMASC", 6)) {
238 numachip_system = 1;
239 return 1;
240 }
241
242 return 0;
243}
244
245static struct apic apic_numachip __refconst = {
246
247 .name = "NumaConnect system",
248 .probe = numachip_probe,
249 .acpi_madt_oem_check = numachip_acpi_madt_oem_check,
250 .apic_id_valid = numachip_apic_id_valid,
251 .apic_id_registered = numachip_apic_id_registered,
252
253 .irq_delivery_mode = dest_Fixed,
254 .irq_dest_mode = 0, /* physical */
255
256 .target_cpus = numachip_target_cpus,
257 .disable_esr = 0,
258 .dest_logical = 0,
259 .check_apicid_used = NULL,
260 .check_apicid_present = NULL,
261
262 .vector_allocation_domain = numachip_vector_allocation_domain,
263 .init_apic_ldr = flat_init_apic_ldr,
264
265 .ioapic_phys_id_map = NULL,
266 .setup_apic_routing = NULL,
267 .multi_timer_check = NULL,
268 .cpu_present_to_apicid = default_cpu_present_to_apicid,
269 .apicid_to_cpu_present = NULL,
270 .setup_portio_remap = NULL,
271 .check_phys_apicid_present = default_check_phys_apicid_present,
272 .enable_apic_mode = NULL,
273 .phys_pkg_id = numachip_phys_pkg_id,
274 .mps_oem_check = NULL,
275
276 .get_apic_id = get_apic_id,
277 .set_apic_id = set_apic_id,
278 .apic_id_mask = 0xffU << 24,
279
280 .cpu_mask_to_apicid = numachip_cpu_mask_to_apicid,
281 .cpu_mask_to_apicid_and = numachip_cpu_mask_to_apicid_and,
282
283 .send_IPI_mask = numachip_send_IPI_mask,
284 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
285 .send_IPI_allbutself = numachip_send_IPI_allbutself,
286 .send_IPI_all = numachip_send_IPI_all,
287 .send_IPI_self = numachip_send_IPI_self,
288
289 .wakeup_secondary_cpu = numachip_wakeup_secondary,
290 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
291 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
292 .wait_for_init_deassert = NULL,
293 .smp_callin_clear_local_apic = NULL,
294 .inquire_remote_apic = NULL, /* REMRD not supported */
295
296 .read = native_apic_mem_read,
297 .write = native_apic_mem_write,
298 .eoi_write = native_apic_mem_write,
299 .icr_read = native_apic_icr_read,
300 .icr_write = native_apic_icr_write,
301 .wait_icr_idle = native_apic_wait_icr_idle,
302 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
303};
304apic_driver(apic_numachip);
305