1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
 4 *
 5 * Author: Tony Li <tony.li@freescale.com>
 6 *	   Jason Jin <Jason.jin@freescale.com>
 
 
 
 
 
 
 7 */
 8#ifndef _POWERPC_SYSDEV_FSL_MSI_H
 9#define _POWERPC_SYSDEV_FSL_MSI_H
10
11#include <linux/of.h>
12#include <asm/msi_bitmap.h>
13
14#define NR_MSI_REG_MSIIR	8  /* MSIIR can index 8 MSI registers */
15#define NR_MSI_REG_MSIIR1	16 /* MSIIR1 can index 16 MSI registers */
16#define NR_MSI_REG_MAX		NR_MSI_REG_MSIIR1
17#define IRQS_PER_MSI_REG	32
18#define NR_MSI_IRQS_MAX	(NR_MSI_REG_MAX * IRQS_PER_MSI_REG)
19
20#define FSL_PIC_IP_MASK   0x0000000F
21#define FSL_PIC_IP_MPIC   0x00000001
22#define FSL_PIC_IP_IPIC   0x00000002
23#define FSL_PIC_IP_VMPIC  0x00000003
24
25#define MSI_HW_ERRATA_ENDIAN 0x00000010
26
27struct fsl_msi_cascade_data;
28
29struct fsl_msi {
30	struct irq_domain *irqhost;
31
32	unsigned long cascade_irq;
33
34	u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
35	u32 ibs_shift; /* Shift of interrupt bit select */
36	u32 srs_shift; /* Shift of the shared interrupt register select */
37	void __iomem *msi_regs;
38	u32 feature;
39	struct fsl_msi_cascade_data *cascade_array[NR_MSI_REG_MAX];
40
41	struct msi_bitmap bitmap;
42
43	struct list_head list;          /* support multiple MSI banks */
44
45	phandle phandle;
46};
47
48#endif /* _POWERPC_SYSDEV_FSL_MSI_H */
49

 
 1/*
 2 * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
 3 *
 4 * Author: Tony Li <tony.li@freescale.com>
 5 *	   Jason Jin <Jason.jin@freescale.com>
 6 *
 7 * This program is free software; you can redistribute it and/or
 8 * modify it under the terms of the GNU General Public License
 9 * as published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 */
13#ifndef _POWERPC_SYSDEV_FSL_MSI_H
14#define _POWERPC_SYSDEV_FSL_MSI_H
15
16#include <linux/of.h>
17#include <asm/msi_bitmap.h>
18
19#define NR_MSI_REG		8
 
 
20#define IRQS_PER_MSI_REG	32
21#define NR_MSI_IRQS	(NR_MSI_REG * IRQS_PER_MSI_REG)
22
23#define FSL_PIC_IP_MASK   0x0000000F
24#define FSL_PIC_IP_MPIC   0x00000001
25#define FSL_PIC_IP_IPIC   0x00000002
26#define FSL_PIC_IP_VMPIC  0x00000003
27
 
 
 
 
28struct fsl_msi {
29	struct irq_domain *irqhost;
30
31	unsigned long cascade_irq;
32
33	u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
 
 
34	void __iomem *msi_regs;
35	u32 feature;
36	int msi_virqs[NR_MSI_REG];
37
38	struct msi_bitmap bitmap;
39
40	struct list_head list;          /* support multiple MSI banks */
41
42	phandle phandle;
43};
44
45#endif /* _POWERPC_SYSDEV_FSL_MSI_H */
46