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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
5 *
6 * Author: Varun Sethi <varun.sethi@freescale.com>
7 * Author: Scott Wood <scotwood@freescale.com>
8 * Author: Mihai Caraman <mihai.caraman@freescale.com>
9 *
10 * This file is derived from arch/powerpc/kvm/booke_interrupts.S
11 */
12
13#include <asm/ppc_asm.h>
14#include <asm/kvm_asm.h>
15#include <asm/reg.h>
16#include <asm/page.h>
17#include <asm/asm-compat.h>
18#include <asm/asm-offsets.h>
19#include <asm/bitsperlong.h>
20
21#ifdef CONFIG_64BIT
22#include <asm/exception-64e.h>
23#include <asm/hw_irq.h>
24#include <asm/irqflags.h>
25#else
26#include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
27#endif
28
29#define LONGBYTES (BITS_PER_LONG / 8)
30
31#define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES))
32
33/* The host stack layout: */
34#define HOST_R1 0 /* Implied by stwu. */
35#define HOST_CALLEE_LR PPC_LR_STKOFF
36#define HOST_RUN (HOST_CALLEE_LR + LONGBYTES)
37/*
38 * r2 is special: it holds 'current', and it made nonvolatile in the
39 * kernel with the -ffixed-r2 gcc option.
40 */
41#define HOST_R2 (HOST_RUN + LONGBYTES)
42#define HOST_CR (HOST_R2 + LONGBYTES)
43#define HOST_NV_GPRS (HOST_CR + LONGBYTES)
44#define __HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
45#define HOST_NV_GPR(n) __HOST_NV_GPR(__REG_##n)
46#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + LONGBYTES)
47#define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
48/* LR in caller stack frame. */
49#define HOST_STACK_LR (HOST_STACK_SIZE + PPC_LR_STKOFF)
50
51#define NEED_EMU 0x00000001 /* emulation -- save nv regs */
52#define NEED_DEAR 0x00000002 /* save faulting DEAR */
53#define NEED_ESR 0x00000004 /* save faulting ESR */
54
55/*
56 * On entry:
57 * r4 = vcpu, r5 = srr0, r6 = srr1
58 * saved in vcpu: cr, ctr, r3-r13
59 */
60.macro kvm_handler_common intno, srr0, flags
61 /* Restore host stack pointer */
62 PPC_STL r1, VCPU_GPR(R1)(r4)
63 PPC_STL r2, VCPU_GPR(R2)(r4)
64 PPC_LL r1, VCPU_HOST_STACK(r4)
65 PPC_LL r2, HOST_R2(r1)
66
67START_BTB_FLUSH_SECTION
68 BTB_FLUSH(r10)
69END_BTB_FLUSH_SECTION
70
71 mfspr r10, SPRN_PID
72 lwz r8, VCPU_HOST_PID(r4)
73 PPC_LL r11, VCPU_SHARED(r4)
74 PPC_STL r14, VCPU_GPR(R14)(r4) /* We need a non-volatile GPR. */
75 li r14, \intno
76
77 stw r10, VCPU_GUEST_PID(r4)
78 mtspr SPRN_PID, r8
79
80#ifdef CONFIG_KVM_EXIT_TIMING
81 /* save exit time */
821: mfspr r7, SPRN_TBRU
83 mfspr r8, SPRN_TBRL
84 mfspr r9, SPRN_TBRU
85 cmpw r9, r7
86 stw r8, VCPU_TIMING_EXIT_TBL(r4)
87 bne- 1b
88 stw r9, VCPU_TIMING_EXIT_TBU(r4)
89#endif
90
91 oris r8, r6, MSR_CE@h
92 PPC_STD(r6, VCPU_SHARED_MSR, r11)
93 ori r8, r8, MSR_ME | MSR_RI
94 PPC_STL r5, VCPU_PC(r4)
95
96 /*
97 * Make sure CE/ME/RI are set (if appropriate for exception type)
98 * whether or not the guest had it set. Since mfmsr/mtmsr are
99 * somewhat expensive, skip in the common case where the guest
100 * had all these bits set (and thus they're still set if
101 * appropriate for the exception type).
102 */
103 cmpw r6, r8
104 beq 1f
105 mfmsr r7
106 .if \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0
107 oris r7, r7, MSR_CE@h
108 .endif
109 .if \srr0 != SPRN_MCSRR0
110 ori r7, r7, MSR_ME | MSR_RI
111 .endif
112 mtmsr r7
1131:
114
115 .if \flags & NEED_EMU
116 PPC_STL r15, VCPU_GPR(R15)(r4)
117 PPC_STL r16, VCPU_GPR(R16)(r4)
118 PPC_STL r17, VCPU_GPR(R17)(r4)
119 PPC_STL r18, VCPU_GPR(R18)(r4)
120 PPC_STL r19, VCPU_GPR(R19)(r4)
121 PPC_STL r20, VCPU_GPR(R20)(r4)
122 PPC_STL r21, VCPU_GPR(R21)(r4)
123 PPC_STL r22, VCPU_GPR(R22)(r4)
124 PPC_STL r23, VCPU_GPR(R23)(r4)
125 PPC_STL r24, VCPU_GPR(R24)(r4)
126 PPC_STL r25, VCPU_GPR(R25)(r4)
127 PPC_STL r26, VCPU_GPR(R26)(r4)
128 PPC_STL r27, VCPU_GPR(R27)(r4)
129 PPC_STL r28, VCPU_GPR(R28)(r4)
130 PPC_STL r29, VCPU_GPR(R29)(r4)
131 PPC_STL r30, VCPU_GPR(R30)(r4)
132 PPC_STL r31, VCPU_GPR(R31)(r4)
133
134 /*
135 * We don't use external PID support. lwepx faults would need to be
136 * handled by KVM and this implies aditional code in DO_KVM (for
137 * DTB_MISS, DSI and LRAT) to check ESR[EPID] and EPLC[EGS] which
138 * is too intrusive for the host. Get last instuction in
139 * kvmppc_get_last_inst().
140 */
141 li r9, KVM_INST_FETCH_FAILED
142 PPC_STL r9, VCPU_LAST_INST(r4)
143 .endif
144
145 .if \flags & NEED_ESR
146 mfspr r8, SPRN_ESR
147 PPC_STL r8, VCPU_FAULT_ESR(r4)
148 .endif
149
150 .if \flags & NEED_DEAR
151 mfspr r9, SPRN_DEAR
152 PPC_STL r9, VCPU_FAULT_DEAR(r4)
153 .endif
154
155 b kvmppc_resume_host
156.endm
157
158#ifdef CONFIG_64BIT
159/* Exception types */
160#define EX_GEN 1
161#define EX_GDBELL 2
162#define EX_DBG 3
163#define EX_MC 4
164#define EX_CRIT 5
165#define EX_TLB 6
166
167/*
168 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
169 */
170.macro kvm_handler intno type scratch, paca_ex, ex_r10, ex_r11, srr0, srr1, flags
171 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
172 mr r11, r4
173 /*
174 * Get vcpu from Paca: paca->__current.thread->kvm_vcpu
175 */
176 PPC_LL r4, PACACURRENT(r13)
177 PPC_LL r4, (THREAD + THREAD_KVM_VCPU)(r4)
178 PPC_STL r10, VCPU_CR(r4)
179 PPC_STL r11, VCPU_GPR(R4)(r4)
180 PPC_STL r5, VCPU_GPR(R5)(r4)
181 PPC_STL r6, VCPU_GPR(R6)(r4)
182 PPC_STL r8, VCPU_GPR(R8)(r4)
183 PPC_STL r9, VCPU_GPR(R9)(r4)
184 .if \type == EX_TLB
185 PPC_LL r5, EX_TLB_R13(r12)
186 PPC_LL r6, EX_TLB_R10(r12)
187 PPC_LL r8, EX_TLB_R11(r12)
188 mfspr r12, \scratch
189 .else
190 mfspr r5, \scratch
191 PPC_LL r6, (\paca_ex + \ex_r10)(r13)
192 PPC_LL r8, (\paca_ex + \ex_r11)(r13)
193 .endif
194 PPC_STL r5, VCPU_GPR(R13)(r4)
195 PPC_STL r3, VCPU_GPR(R3)(r4)
196 PPC_STL r7, VCPU_GPR(R7)(r4)
197 PPC_STL r12, VCPU_GPR(R12)(r4)
198 PPC_STL r6, VCPU_GPR(R10)(r4)
199 PPC_STL r8, VCPU_GPR(R11)(r4)
200 mfctr r5
201 PPC_STL r5, VCPU_CTR(r4)
202 mfspr r5, \srr0
203 mfspr r6, \srr1
204 kvm_handler_common \intno, \srr0, \flags
205.endm
206
207#define EX_PARAMS(type) \
208 EX_##type, \
209 SPRN_SPRG_##type##_SCRATCH, \
210 PACA_EX##type, \
211 EX_R10, \
212 EX_R11
213
214#define EX_PARAMS_TLB \
215 EX_TLB, \
216 SPRN_SPRG_GEN_SCRATCH, \
217 PACA_EXTLB, \
218 EX_TLB_R10, \
219 EX_TLB_R11
220
221kvm_handler BOOKE_INTERRUPT_CRITICAL, EX_PARAMS(CRIT), \
222 SPRN_CSRR0, SPRN_CSRR1, 0
223kvm_handler BOOKE_INTERRUPT_MACHINE_CHECK, EX_PARAMS(MC), \
224 SPRN_MCSRR0, SPRN_MCSRR1, 0
225kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, EX_PARAMS(GEN), \
226 SPRN_SRR0, SPRN_SRR1,(NEED_EMU | NEED_DEAR | NEED_ESR)
227kvm_handler BOOKE_INTERRUPT_INST_STORAGE, EX_PARAMS(GEN), \
228 SPRN_SRR0, SPRN_SRR1, NEED_ESR
229kvm_handler BOOKE_INTERRUPT_EXTERNAL, EX_PARAMS(GEN), \
230 SPRN_SRR0, SPRN_SRR1, 0
231kvm_handler BOOKE_INTERRUPT_ALIGNMENT, EX_PARAMS(GEN), \
232 SPRN_SRR0, SPRN_SRR1,(NEED_DEAR | NEED_ESR)
233kvm_handler BOOKE_INTERRUPT_PROGRAM, EX_PARAMS(GEN), \
234 SPRN_SRR0, SPRN_SRR1, (NEED_ESR | NEED_EMU)
235kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, EX_PARAMS(GEN), \
236 SPRN_SRR0, SPRN_SRR1, 0
237kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, EX_PARAMS(GEN), \
238 SPRN_SRR0, SPRN_SRR1, 0
239kvm_handler BOOKE_INTERRUPT_DECREMENTER, EX_PARAMS(GEN), \
240 SPRN_SRR0, SPRN_SRR1, 0
241kvm_handler BOOKE_INTERRUPT_FIT, EX_PARAMS(GEN), \
242 SPRN_SRR0, SPRN_SRR1, 0
243kvm_handler BOOKE_INTERRUPT_WATCHDOG, EX_PARAMS(CRIT),\
244 SPRN_CSRR0, SPRN_CSRR1, 0
245/*
246 * Only bolted TLB miss exception handlers are supported for now
247 */
248kvm_handler BOOKE_INTERRUPT_DTLB_MISS, EX_PARAMS_TLB, \
249 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
250kvm_handler BOOKE_INTERRUPT_ITLB_MISS, EX_PARAMS_TLB, \
251 SPRN_SRR0, SPRN_SRR1, 0
252kvm_handler BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, EX_PARAMS(GEN), \
253 SPRN_SRR0, SPRN_SRR1, 0
254kvm_handler BOOKE_INTERRUPT_ALTIVEC_ASSIST, EX_PARAMS(GEN), \
255 SPRN_SRR0, SPRN_SRR1, 0
256kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, EX_PARAMS(GEN), \
257 SPRN_SRR0, SPRN_SRR1, 0
258kvm_handler BOOKE_INTERRUPT_DOORBELL, EX_PARAMS(GEN), \
259 SPRN_SRR0, SPRN_SRR1, 0
260kvm_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, EX_PARAMS(CRIT), \
261 SPRN_CSRR0, SPRN_CSRR1, 0
262kvm_handler BOOKE_INTERRUPT_HV_PRIV, EX_PARAMS(GEN), \
263 SPRN_SRR0, SPRN_SRR1, NEED_EMU
264kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, EX_PARAMS(GEN), \
265 SPRN_SRR0, SPRN_SRR1, 0
266kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, EX_PARAMS(GDBELL), \
267 SPRN_GSRR0, SPRN_GSRR1, 0
268kvm_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, EX_PARAMS(CRIT), \
269 SPRN_CSRR0, SPRN_CSRR1, 0
270kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(DBG), \
271 SPRN_DSRR0, SPRN_DSRR1, 0
272kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(CRIT), \
273 SPRN_CSRR0, SPRN_CSRR1, 0
274kvm_handler BOOKE_INTERRUPT_LRAT_ERROR, EX_PARAMS(GEN), \
275 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
276#else
277/*
278 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
279 */
280.macro kvm_handler intno srr0, srr1, flags
281_GLOBAL(kvmppc_handler_\intno\()_\srr1)
282 PPC_LL r11, THREAD_KVM_VCPU(r10)
283 PPC_STL r3, VCPU_GPR(R3)(r11)
284 mfspr r3, SPRN_SPRG_RSCRATCH0
285 PPC_STL r4, VCPU_GPR(R4)(r11)
286 PPC_LL r4, THREAD_NORMSAVE(0)(r10)
287 PPC_STL r5, VCPU_GPR(R5)(r11)
288 PPC_STL r13, VCPU_CR(r11)
289 mfspr r5, \srr0
290 PPC_STL r3, VCPU_GPR(R10)(r11)
291 PPC_LL r3, THREAD_NORMSAVE(2)(r10)
292 PPC_STL r6, VCPU_GPR(R6)(r11)
293 PPC_STL r4, VCPU_GPR(R11)(r11)
294 mfspr r6, \srr1
295 PPC_STL r7, VCPU_GPR(R7)(r11)
296 PPC_STL r8, VCPU_GPR(R8)(r11)
297 PPC_STL r9, VCPU_GPR(R9)(r11)
298 PPC_STL r3, VCPU_GPR(R13)(r11)
299 mfctr r7
300 PPC_STL r12, VCPU_GPR(R12)(r11)
301 PPC_STL r7, VCPU_CTR(r11)
302 mr r4, r11
303 kvm_handler_common \intno, \srr0, \flags
304.endm
305
306.macro kvm_lvl_handler intno scratch srr0, srr1, flags
307_GLOBAL(kvmppc_handler_\intno\()_\srr1)
308 mfspr r10, SPRN_SPRG_THREAD
309 PPC_LL r11, THREAD_KVM_VCPU(r10)
310 PPC_STL r3, VCPU_GPR(R3)(r11)
311 mfspr r3, \scratch
312 PPC_STL r4, VCPU_GPR(R4)(r11)
313 PPC_LL r4, GPR9(r8)
314 PPC_STL r5, VCPU_GPR(R5)(r11)
315 PPC_STL r9, VCPU_CR(r11)
316 mfspr r5, \srr0
317 PPC_STL r3, VCPU_GPR(R8)(r11)
318 PPC_LL r3, GPR10(r8)
319 PPC_STL r6, VCPU_GPR(R6)(r11)
320 PPC_STL r4, VCPU_GPR(R9)(r11)
321 mfspr r6, \srr1
322 PPC_LL r4, GPR11(r8)
323 PPC_STL r7, VCPU_GPR(R7)(r11)
324 PPC_STL r3, VCPU_GPR(R10)(r11)
325 mfctr r7
326 PPC_STL r12, VCPU_GPR(R12)(r11)
327 PPC_STL r13, VCPU_GPR(R13)(r11)
328 PPC_STL r4, VCPU_GPR(R11)(r11)
329 PPC_STL r7, VCPU_CTR(r11)
330 mr r4, r11
331 kvm_handler_common \intno, \srr0, \flags
332.endm
333
334kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
335 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
336kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
337 SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
338kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
339 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
340kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
341kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
342kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
343 SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
344kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, (NEED_ESR | NEED_EMU)
345kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
346kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
347kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
348kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
349kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
350kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
351 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
352kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
353 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
354kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
355kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
356kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
357kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
358 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
359kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
360kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
361kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
362kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
363 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
364kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
365 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
366kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
367 SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
368#endif
369
370/* Registers:
371 * SPRG_SCRATCH0: guest r10
372 * r4: vcpu pointer
373 * r11: vcpu->arch.shared
374 * r14: KVM exit number
375 */
376_GLOBAL(kvmppc_resume_host)
377 /* Save remaining volatile guest register state to vcpu. */
378 mfspr r3, SPRN_VRSAVE
379 PPC_STL r0, VCPU_GPR(R0)(r4)
380 mflr r5
381 mfspr r6, SPRN_SPRG4
382 PPC_STL r5, VCPU_LR(r4)
383 mfspr r7, SPRN_SPRG5
384 stw r3, VCPU_VRSAVE(r4)
385#ifdef CONFIG_64BIT
386 PPC_LL r3, PACA_SPRG_VDSO(r13)
387#endif
388 mfspr r5, SPRN_SPRG9
389 PPC_STD(r6, VCPU_SHARED_SPRG4, r11)
390 mfspr r8, SPRN_SPRG6
391 PPC_STD(r7, VCPU_SHARED_SPRG5, r11)
392 mfspr r9, SPRN_SPRG7
393#ifdef CONFIG_64BIT
394 mtspr SPRN_SPRG_VDSO_WRITE, r3
395#endif
396 PPC_STD(r5, VCPU_SPRG9, r4)
397 PPC_STD(r8, VCPU_SHARED_SPRG6, r11)
398 mfxer r3
399 PPC_STD(r9, VCPU_SHARED_SPRG7, r11)
400
401 /* save guest MAS registers and restore host mas4 & mas6 */
402 mfspr r5, SPRN_MAS0
403 PPC_STL r3, VCPU_XER(r4)
404 mfspr r6, SPRN_MAS1
405 stw r5, VCPU_SHARED_MAS0(r11)
406 mfspr r7, SPRN_MAS2
407 stw r6, VCPU_SHARED_MAS1(r11)
408 PPC_STD(r7, VCPU_SHARED_MAS2, r11)
409 mfspr r5, SPRN_MAS3
410 mfspr r6, SPRN_MAS4
411 stw r5, VCPU_SHARED_MAS7_3+4(r11)
412 mfspr r7, SPRN_MAS6
413 stw r6, VCPU_SHARED_MAS4(r11)
414 mfspr r5, SPRN_MAS7
415 lwz r6, VCPU_HOST_MAS4(r4)
416 stw r7, VCPU_SHARED_MAS6(r11)
417 lwz r8, VCPU_HOST_MAS6(r4)
418 mtspr SPRN_MAS4, r6
419 stw r5, VCPU_SHARED_MAS7_3+0(r11)
420 mtspr SPRN_MAS6, r8
421 /* Enable MAS register updates via exception */
422 mfspr r3, SPRN_EPCR
423 rlwinm r3, r3, 0, ~SPRN_EPCR_DMIUH
424 mtspr SPRN_EPCR, r3
425 isync
426
427 /* Switch to kernel stack and jump to handler. */
428 mr r3, r4
429 mr r5, r14 /* intno */
430 mr r14, r4 /* Save vcpu pointer. */
431 mr r4, r5
432 bl kvmppc_handle_exit
433
434 /* Restore vcpu pointer and the nonvolatiles we used. */
435 mr r4, r14
436 PPC_LL r14, VCPU_GPR(R14)(r4)
437
438 andi. r5, r3, RESUME_FLAG_NV
439 beq skip_nv_load
440 PPC_LL r15, VCPU_GPR(R15)(r4)
441 PPC_LL r16, VCPU_GPR(R16)(r4)
442 PPC_LL r17, VCPU_GPR(R17)(r4)
443 PPC_LL r18, VCPU_GPR(R18)(r4)
444 PPC_LL r19, VCPU_GPR(R19)(r4)
445 PPC_LL r20, VCPU_GPR(R20)(r4)
446 PPC_LL r21, VCPU_GPR(R21)(r4)
447 PPC_LL r22, VCPU_GPR(R22)(r4)
448 PPC_LL r23, VCPU_GPR(R23)(r4)
449 PPC_LL r24, VCPU_GPR(R24)(r4)
450 PPC_LL r25, VCPU_GPR(R25)(r4)
451 PPC_LL r26, VCPU_GPR(R26)(r4)
452 PPC_LL r27, VCPU_GPR(R27)(r4)
453 PPC_LL r28, VCPU_GPR(R28)(r4)
454 PPC_LL r29, VCPU_GPR(R29)(r4)
455 PPC_LL r30, VCPU_GPR(R30)(r4)
456 PPC_LL r31, VCPU_GPR(R31)(r4)
457skip_nv_load:
458 /* Should we return to the guest? */
459 andi. r5, r3, RESUME_FLAG_HOST
460 beq lightweight_exit
461
462 srawi r3, r3, 2 /* Shift -ERR back down. */
463
464heavyweight_exit:
465 /* Not returning to guest. */
466 PPC_LL r5, HOST_STACK_LR(r1)
467 lwz r6, HOST_CR(r1)
468
469 /*
470 * We already saved guest volatile register state; now save the
471 * non-volatiles.
472 */
473
474 PPC_STL r15, VCPU_GPR(R15)(r4)
475 PPC_STL r16, VCPU_GPR(R16)(r4)
476 PPC_STL r17, VCPU_GPR(R17)(r4)
477 PPC_STL r18, VCPU_GPR(R18)(r4)
478 PPC_STL r19, VCPU_GPR(R19)(r4)
479 PPC_STL r20, VCPU_GPR(R20)(r4)
480 PPC_STL r21, VCPU_GPR(R21)(r4)
481 PPC_STL r22, VCPU_GPR(R22)(r4)
482 PPC_STL r23, VCPU_GPR(R23)(r4)
483 PPC_STL r24, VCPU_GPR(R24)(r4)
484 PPC_STL r25, VCPU_GPR(R25)(r4)
485 PPC_STL r26, VCPU_GPR(R26)(r4)
486 PPC_STL r27, VCPU_GPR(R27)(r4)
487 PPC_STL r28, VCPU_GPR(R28)(r4)
488 PPC_STL r29, VCPU_GPR(R29)(r4)
489 PPC_STL r30, VCPU_GPR(R30)(r4)
490 PPC_STL r31, VCPU_GPR(R31)(r4)
491
492 /* Load host non-volatile register state from host stack. */
493 PPC_LL r14, HOST_NV_GPR(R14)(r1)
494 PPC_LL r15, HOST_NV_GPR(R15)(r1)
495 PPC_LL r16, HOST_NV_GPR(R16)(r1)
496 PPC_LL r17, HOST_NV_GPR(R17)(r1)
497 PPC_LL r18, HOST_NV_GPR(R18)(r1)
498 PPC_LL r19, HOST_NV_GPR(R19)(r1)
499 PPC_LL r20, HOST_NV_GPR(R20)(r1)
500 PPC_LL r21, HOST_NV_GPR(R21)(r1)
501 PPC_LL r22, HOST_NV_GPR(R22)(r1)
502 PPC_LL r23, HOST_NV_GPR(R23)(r1)
503 PPC_LL r24, HOST_NV_GPR(R24)(r1)
504 PPC_LL r25, HOST_NV_GPR(R25)(r1)
505 PPC_LL r26, HOST_NV_GPR(R26)(r1)
506 PPC_LL r27, HOST_NV_GPR(R27)(r1)
507 PPC_LL r28, HOST_NV_GPR(R28)(r1)
508 PPC_LL r29, HOST_NV_GPR(R29)(r1)
509 PPC_LL r30, HOST_NV_GPR(R30)(r1)
510 PPC_LL r31, HOST_NV_GPR(R31)(r1)
511
512 /* Return to kvm_vcpu_run(). */
513 mtlr r5
514 mtcr r6
515 addi r1, r1, HOST_STACK_SIZE
516 /* r3 still contains the return code from kvmppc_handle_exit(). */
517 blr
518
519/* Registers:
520 * r3: vcpu pointer
521 */
522_GLOBAL(__kvmppc_vcpu_run)
523 stwu r1, -HOST_STACK_SIZE(r1)
524 PPC_STL r1, VCPU_HOST_STACK(r3) /* Save stack pointer to vcpu. */
525
526 /* Save host state to stack. */
527 mr r4, r3
528 mflr r3
529 mfcr r5
530 PPC_STL r3, HOST_STACK_LR(r1)
531
532 stw r5, HOST_CR(r1)
533
534 /* Save host non-volatile register state to stack. */
535 PPC_STL r14, HOST_NV_GPR(R14)(r1)
536 PPC_STL r15, HOST_NV_GPR(R15)(r1)
537 PPC_STL r16, HOST_NV_GPR(R16)(r1)
538 PPC_STL r17, HOST_NV_GPR(R17)(r1)
539 PPC_STL r18, HOST_NV_GPR(R18)(r1)
540 PPC_STL r19, HOST_NV_GPR(R19)(r1)
541 PPC_STL r20, HOST_NV_GPR(R20)(r1)
542 PPC_STL r21, HOST_NV_GPR(R21)(r1)
543 PPC_STL r22, HOST_NV_GPR(R22)(r1)
544 PPC_STL r23, HOST_NV_GPR(R23)(r1)
545 PPC_STL r24, HOST_NV_GPR(R24)(r1)
546 PPC_STL r25, HOST_NV_GPR(R25)(r1)
547 PPC_STL r26, HOST_NV_GPR(R26)(r1)
548 PPC_STL r27, HOST_NV_GPR(R27)(r1)
549 PPC_STL r28, HOST_NV_GPR(R28)(r1)
550 PPC_STL r29, HOST_NV_GPR(R29)(r1)
551 PPC_STL r30, HOST_NV_GPR(R30)(r1)
552 PPC_STL r31, HOST_NV_GPR(R31)(r1)
553
554 /* Load guest non-volatiles. */
555 PPC_LL r14, VCPU_GPR(R14)(r4)
556 PPC_LL r15, VCPU_GPR(R15)(r4)
557 PPC_LL r16, VCPU_GPR(R16)(r4)
558 PPC_LL r17, VCPU_GPR(R17)(r4)
559 PPC_LL r18, VCPU_GPR(R18)(r4)
560 PPC_LL r19, VCPU_GPR(R19)(r4)
561 PPC_LL r20, VCPU_GPR(R20)(r4)
562 PPC_LL r21, VCPU_GPR(R21)(r4)
563 PPC_LL r22, VCPU_GPR(R22)(r4)
564 PPC_LL r23, VCPU_GPR(R23)(r4)
565 PPC_LL r24, VCPU_GPR(R24)(r4)
566 PPC_LL r25, VCPU_GPR(R25)(r4)
567 PPC_LL r26, VCPU_GPR(R26)(r4)
568 PPC_LL r27, VCPU_GPR(R27)(r4)
569 PPC_LL r28, VCPU_GPR(R28)(r4)
570 PPC_LL r29, VCPU_GPR(R29)(r4)
571 PPC_LL r30, VCPU_GPR(R30)(r4)
572 PPC_LL r31, VCPU_GPR(R31)(r4)
573
574
575lightweight_exit:
576 PPC_STL r2, HOST_R2(r1)
577
578 mfspr r3, SPRN_PID
579 stw r3, VCPU_HOST_PID(r4)
580 lwz r3, VCPU_GUEST_PID(r4)
581 mtspr SPRN_PID, r3
582
583 PPC_LL r11, VCPU_SHARED(r4)
584 /* Disable MAS register updates via exception */
585 mfspr r3, SPRN_EPCR
586 oris r3, r3, SPRN_EPCR_DMIUH@h
587 mtspr SPRN_EPCR, r3
588 isync
589 /* Save host mas4 and mas6 and load guest MAS registers */
590 mfspr r3, SPRN_MAS4
591 stw r3, VCPU_HOST_MAS4(r4)
592 mfspr r3, SPRN_MAS6
593 stw r3, VCPU_HOST_MAS6(r4)
594 lwz r3, VCPU_SHARED_MAS0(r11)
595 lwz r5, VCPU_SHARED_MAS1(r11)
596 PPC_LD(r6, VCPU_SHARED_MAS2, r11)
597 lwz r7, VCPU_SHARED_MAS7_3+4(r11)
598 lwz r8, VCPU_SHARED_MAS4(r11)
599 mtspr SPRN_MAS0, r3
600 mtspr SPRN_MAS1, r5
601 mtspr SPRN_MAS2, r6
602 mtspr SPRN_MAS3, r7
603 mtspr SPRN_MAS4, r8
604 lwz r3, VCPU_SHARED_MAS6(r11)
605 lwz r5, VCPU_SHARED_MAS7_3+0(r11)
606 mtspr SPRN_MAS6, r3
607 mtspr SPRN_MAS7, r5
608
609 /*
610 * Host interrupt handlers may have clobbered these guest-readable
611 * SPRGs, so we need to reload them here with the guest's values.
612 */
613 lwz r3, VCPU_VRSAVE(r4)
614 PPC_LD(r5, VCPU_SHARED_SPRG4, r11)
615 mtspr SPRN_VRSAVE, r3
616 PPC_LD(r6, VCPU_SHARED_SPRG5, r11)
617 mtspr SPRN_SPRG4W, r5
618 PPC_LD(r7, VCPU_SHARED_SPRG6, r11)
619 mtspr SPRN_SPRG5W, r6
620 PPC_LD(r8, VCPU_SHARED_SPRG7, r11)
621 mtspr SPRN_SPRG6W, r7
622 PPC_LD(r5, VCPU_SPRG9, r4)
623 mtspr SPRN_SPRG7W, r8
624 mtspr SPRN_SPRG9, r5
625
626 /* Load some guest volatiles. */
627 PPC_LL r3, VCPU_LR(r4)
628 PPC_LL r5, VCPU_XER(r4)
629 PPC_LL r6, VCPU_CTR(r4)
630 PPC_LL r7, VCPU_CR(r4)
631 PPC_LL r8, VCPU_PC(r4)
632 PPC_LD(r9, VCPU_SHARED_MSR, r11)
633 PPC_LL r0, VCPU_GPR(R0)(r4)
634 PPC_LL r1, VCPU_GPR(R1)(r4)
635 PPC_LL r2, VCPU_GPR(R2)(r4)
636 PPC_LL r10, VCPU_GPR(R10)(r4)
637 PPC_LL r11, VCPU_GPR(R11)(r4)
638 PPC_LL r12, VCPU_GPR(R12)(r4)
639 PPC_LL r13, VCPU_GPR(R13)(r4)
640 mtlr r3
641 mtxer r5
642 mtctr r6
643 mtsrr0 r8
644 mtsrr1 r9
645
646#ifdef CONFIG_KVM_EXIT_TIMING
647 /* save enter time */
6481:
649 mfspr r6, SPRN_TBRU
650 mfspr r9, SPRN_TBRL
651 mfspr r8, SPRN_TBRU
652 cmpw r8, r6
653 stw r9, VCPU_TIMING_LAST_ENTER_TBL(r4)
654 bne 1b
655 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
656#endif
657
658 /*
659 * Don't execute any instruction which can change CR after
660 * below instruction.
661 */
662 mtcr r7
663
664 /* Finish loading guest volatiles and jump to guest. */
665 PPC_LL r5, VCPU_GPR(R5)(r4)
666 PPC_LL r6, VCPU_GPR(R6)(r4)
667 PPC_LL r7, VCPU_GPR(R7)(r4)
668 PPC_LL r8, VCPU_GPR(R8)(r4)
669 PPC_LL r9, VCPU_GPR(R9)(r4)
670
671 PPC_LL r3, VCPU_GPR(R3)(r4)
672 PPC_LL r4, VCPU_GPR(R4)(r4)
673 rfi
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
16 *
17 * Author: Varun Sethi <varun.sethi@freescale.com>
18 * Author: Scott Wood <scotwood@freescale.com>
19 *
20 * This file is derived from arch/powerpc/kvm/booke_interrupts.S
21 */
22
23#include <asm/ppc_asm.h>
24#include <asm/kvm_asm.h>
25#include <asm/reg.h>
26#include <asm/mmu-44x.h>
27#include <asm/page.h>
28#include <asm/asm-compat.h>
29#include <asm/asm-offsets.h>
30#include <asm/bitsperlong.h>
31#include <asm/thread_info.h>
32
33#include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
34
35#define GET_VCPU(vcpu, thread) \
36 PPC_LL vcpu, THREAD_KVM_VCPU(thread)
37
38#define LONGBYTES (BITS_PER_LONG / 8)
39
40#define VCPU_GPR(n) (VCPU_GPRS + (n * LONGBYTES))
41#define VCPU_GUEST_SPRG(n) (VCPU_GUEST_SPRGS + (n * LONGBYTES))
42
43/* The host stack layout: */
44#define HOST_R1 (0 * LONGBYTES) /* Implied by stwu. */
45#define HOST_CALLEE_LR (1 * LONGBYTES)
46#define HOST_RUN (2 * LONGBYTES) /* struct kvm_run */
47/*
48 * r2 is special: it holds 'current', and it made nonvolatile in the
49 * kernel with the -ffixed-r2 gcc option.
50 */
51#define HOST_R2 (3 * LONGBYTES)
52#define HOST_CR (4 * LONGBYTES)
53#define HOST_NV_GPRS (5 * LONGBYTES)
54#define HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
55#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES)
56#define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
57#define HOST_STACK_LR (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */
58
59#define NEED_EMU 0x00000001 /* emulation -- save nv regs */
60#define NEED_DEAR 0x00000002 /* save faulting DEAR */
61#define NEED_ESR 0x00000004 /* save faulting ESR */
62
63/*
64 * On entry:
65 * r4 = vcpu, r5 = srr0, r6 = srr1
66 * saved in vcpu: cr, ctr, r3-r13
67 */
68.macro kvm_handler_common intno, srr0, flags
69 /* Restore host stack pointer */
70 PPC_STL r1, VCPU_GPR(r1)(r4)
71 PPC_STL r2, VCPU_GPR(r2)(r4)
72 PPC_LL r1, VCPU_HOST_STACK(r4)
73 PPC_LL r2, HOST_R2(r1)
74
75 mfspr r10, SPRN_PID
76 lwz r8, VCPU_HOST_PID(r4)
77 PPC_LL r11, VCPU_SHARED(r4)
78 PPC_STL r14, VCPU_GPR(r14)(r4) /* We need a non-volatile GPR. */
79 li r14, \intno
80
81 stw r10, VCPU_GUEST_PID(r4)
82 mtspr SPRN_PID, r8
83
84#ifdef CONFIG_KVM_EXIT_TIMING
85 /* save exit time */
861: mfspr r7, SPRN_TBRU
87 mfspr r8, SPRN_TBRL
88 mfspr r9, SPRN_TBRU
89 cmpw r9, r7
90 stw r8, VCPU_TIMING_EXIT_TBL(r4)
91 bne- 1b
92 stw r9, VCPU_TIMING_EXIT_TBU(r4)
93#endif
94
95 oris r8, r6, MSR_CE@h
96 PPC_STD(r6, VCPU_SHARED_MSR, r11)
97 ori r8, r8, MSR_ME | MSR_RI
98 PPC_STL r5, VCPU_PC(r4)
99
100 /*
101 * Make sure CE/ME/RI are set (if appropriate for exception type)
102 * whether or not the guest had it set. Since mfmsr/mtmsr are
103 * somewhat expensive, skip in the common case where the guest
104 * had all these bits set (and thus they're still set if
105 * appropriate for the exception type).
106 */
107 cmpw r6, r8
108 beq 1f
109 mfmsr r7
110 .if \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0
111 oris r7, r7, MSR_CE@h
112 .endif
113 .if \srr0 != SPRN_MCSRR0
114 ori r7, r7, MSR_ME | MSR_RI
115 .endif
116 mtmsr r7
1171:
118
119 .if \flags & NEED_EMU
120 /*
121 * This assumes you have external PID support.
122 * To support a bookehv CPU without external PID, you'll
123 * need to look up the TLB entry and create a temporary mapping.
124 *
125 * FIXME: we don't currently handle if the lwepx faults. PR-mode
126 * booke doesn't handle it either. Since Linux doesn't use
127 * broadcast tlbivax anymore, the only way this should happen is
128 * if the guest maps its memory execute-but-not-read, or if we
129 * somehow take a TLB miss in the middle of this entry code and
130 * evict the relevant entry. On e500mc, all kernel lowmem is
131 * bolted into TLB1 large page mappings, and we don't use
132 * broadcast invalidates, so we should not take a TLB miss here.
133 *
134 * Later we'll need to deal with faults here. Disallowing guest
135 * mappings that are execute-but-not-read could be an option on
136 * e500mc, but not on chips with an LRAT if it is used.
137 */
138
139 mfspr r3, SPRN_EPLC /* will already have correct ELPID and EGS */
140 PPC_STL r15, VCPU_GPR(r15)(r4)
141 PPC_STL r16, VCPU_GPR(r16)(r4)
142 PPC_STL r17, VCPU_GPR(r17)(r4)
143 PPC_STL r18, VCPU_GPR(r18)(r4)
144 PPC_STL r19, VCPU_GPR(r19)(r4)
145 mr r8, r3
146 PPC_STL r20, VCPU_GPR(r20)(r4)
147 rlwimi r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS
148 PPC_STL r21, VCPU_GPR(r21)(r4)
149 rlwimi r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR
150 PPC_STL r22, VCPU_GPR(r22)(r4)
151 rlwimi r8, r10, EPC_EPID_SHIFT, EPC_EPID
152 PPC_STL r23, VCPU_GPR(r23)(r4)
153 PPC_STL r24, VCPU_GPR(r24)(r4)
154 PPC_STL r25, VCPU_GPR(r25)(r4)
155 PPC_STL r26, VCPU_GPR(r26)(r4)
156 PPC_STL r27, VCPU_GPR(r27)(r4)
157 PPC_STL r28, VCPU_GPR(r28)(r4)
158 PPC_STL r29, VCPU_GPR(r29)(r4)
159 PPC_STL r30, VCPU_GPR(r30)(r4)
160 PPC_STL r31, VCPU_GPR(r31)(r4)
161 mtspr SPRN_EPLC, r8
162
163 /* disable preemption, so we are sure we hit the fixup handler */
164#ifdef CONFIG_PPC64
165 clrrdi r8,r1,THREAD_SHIFT
166#else
167 rlwinm r8,r1,0,0,31-THREAD_SHIFT /* current thread_info */
168#endif
169 li r7, 1
170 stw r7, TI_PREEMPT(r8)
171
172 isync
173
174 /*
175 * In case the read goes wrong, we catch it and write an invalid value
176 * in LAST_INST instead.
177 */
1781: lwepx r9, 0, r5
1792:
180.section .fixup, "ax"
1813: li r9, KVM_INST_FETCH_FAILED
182 b 2b
183.previous
184.section __ex_table,"a"
185 PPC_LONG_ALIGN
186 PPC_LONG 1b,3b
187.previous
188
189 mtspr SPRN_EPLC, r3
190 li r7, 0
191 stw r7, TI_PREEMPT(r8)
192 stw r9, VCPU_LAST_INST(r4)
193 .endif
194
195 .if \flags & NEED_ESR
196 mfspr r8, SPRN_ESR
197 PPC_STL r8, VCPU_FAULT_ESR(r4)
198 .endif
199
200 .if \flags & NEED_DEAR
201 mfspr r9, SPRN_DEAR
202 PPC_STL r9, VCPU_FAULT_DEAR(r4)
203 .endif
204
205 b kvmppc_resume_host
206.endm
207
208/*
209 * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
210 */
211.macro kvm_handler intno srr0, srr1, flags
212_GLOBAL(kvmppc_handler_\intno\()_\srr1)
213 GET_VCPU(r11, r10)
214 PPC_STL r3, VCPU_GPR(r3)(r11)
215 mfspr r3, SPRN_SPRG_RSCRATCH0
216 PPC_STL r4, VCPU_GPR(r4)(r11)
217 PPC_LL r4, THREAD_NORMSAVE(0)(r10)
218 PPC_STL r5, VCPU_GPR(r5)(r11)
219 stw r13, VCPU_CR(r11)
220 mfspr r5, \srr0
221 PPC_STL r3, VCPU_GPR(r10)(r11)
222 PPC_LL r3, THREAD_NORMSAVE(2)(r10)
223 PPC_STL r6, VCPU_GPR(r6)(r11)
224 PPC_STL r4, VCPU_GPR(r11)(r11)
225 mfspr r6, \srr1
226 PPC_STL r7, VCPU_GPR(r7)(r11)
227 PPC_STL r8, VCPU_GPR(r8)(r11)
228 PPC_STL r9, VCPU_GPR(r9)(r11)
229 PPC_STL r3, VCPU_GPR(r13)(r11)
230 mfctr r7
231 PPC_STL r12, VCPU_GPR(r12)(r11)
232 PPC_STL r7, VCPU_CTR(r11)
233 mr r4, r11
234 kvm_handler_common \intno, \srr0, \flags
235.endm
236
237.macro kvm_lvl_handler intno scratch srr0, srr1, flags
238_GLOBAL(kvmppc_handler_\intno\()_\srr1)
239 mfspr r10, SPRN_SPRG_THREAD
240 GET_VCPU(r11, r10)
241 PPC_STL r3, VCPU_GPR(r3)(r11)
242 mfspr r3, \scratch
243 PPC_STL r4, VCPU_GPR(r4)(r11)
244 PPC_LL r4, GPR9(r8)
245 PPC_STL r5, VCPU_GPR(r5)(r11)
246 stw r9, VCPU_CR(r11)
247 mfspr r5, \srr0
248 PPC_STL r3, VCPU_GPR(r8)(r11)
249 PPC_LL r3, GPR10(r8)
250 PPC_STL r6, VCPU_GPR(r6)(r11)
251 PPC_STL r4, VCPU_GPR(r9)(r11)
252 mfspr r6, \srr1
253 PPC_LL r4, GPR11(r8)
254 PPC_STL r7, VCPU_GPR(r7)(r11)
255 PPC_STL r3, VCPU_GPR(r10)(r11)
256 mfctr r7
257 PPC_STL r12, VCPU_GPR(r12)(r11)
258 PPC_STL r13, VCPU_GPR(r13)(r11)
259 PPC_STL r4, VCPU_GPR(r11)(r11)
260 PPC_STL r7, VCPU_CTR(r11)
261 mr r4, r11
262 kvm_handler_common \intno, \srr0, \flags
263.endm
264
265kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
266 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
267kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
268 SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
269kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
270 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR)
271kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
272kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
273kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
274 SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
275kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, NEED_ESR
276kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
277kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
278kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
279kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
280kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
281kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
282 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
283kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
284 SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
285kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
286kvm_handler BOOKE_INTERRUPT_SPE_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
287kvm_handler BOOKE_INTERRUPT_SPE_FP_DATA, SPRN_SRR0, SPRN_SRR1, 0
288kvm_handler BOOKE_INTERRUPT_SPE_FP_ROUND, SPRN_SRR0, SPRN_SRR1, 0
289kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
290kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
291kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
292 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
293kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
294kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
295kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
296kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
297 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
298kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
299 SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
300kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
301 SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
302
303
304/* Registers:
305 * SPRG_SCRATCH0: guest r10
306 * r4: vcpu pointer
307 * r11: vcpu->arch.shared
308 * r14: KVM exit number
309 */
310_GLOBAL(kvmppc_resume_host)
311 /* Save remaining volatile guest register state to vcpu. */
312 mfspr r3, SPRN_VRSAVE
313 PPC_STL r0, VCPU_GPR(r0)(r4)
314 mflr r5
315 mfspr r6, SPRN_SPRG4
316 PPC_STL r5, VCPU_LR(r4)
317 mfspr r7, SPRN_SPRG5
318 stw r3, VCPU_VRSAVE(r4)
319 PPC_STD(r6, VCPU_SHARED_SPRG4, r11)
320 mfspr r8, SPRN_SPRG6
321 PPC_STD(r7, VCPU_SHARED_SPRG5, r11)
322 mfspr r9, SPRN_SPRG7
323 PPC_STD(r8, VCPU_SHARED_SPRG6, r11)
324 mfxer r3
325 PPC_STD(r9, VCPU_SHARED_SPRG7, r11)
326
327 /* save guest MAS registers and restore host mas4 & mas6 */
328 mfspr r5, SPRN_MAS0
329 PPC_STL r3, VCPU_XER(r4)
330 mfspr r6, SPRN_MAS1
331 stw r5, VCPU_SHARED_MAS0(r11)
332 mfspr r7, SPRN_MAS2
333 stw r6, VCPU_SHARED_MAS1(r11)
334 PPC_STD(r7, VCPU_SHARED_MAS2, r11)
335 mfspr r5, SPRN_MAS3
336 mfspr r6, SPRN_MAS4
337 stw r5, VCPU_SHARED_MAS7_3+4(r11)
338 mfspr r7, SPRN_MAS6
339 stw r6, VCPU_SHARED_MAS4(r11)
340 mfspr r5, SPRN_MAS7
341 lwz r6, VCPU_HOST_MAS4(r4)
342 stw r7, VCPU_SHARED_MAS6(r11)
343 lwz r8, VCPU_HOST_MAS6(r4)
344 mtspr SPRN_MAS4, r6
345 stw r5, VCPU_SHARED_MAS7_3+0(r11)
346 mtspr SPRN_MAS6, r8
347 /* Enable MAS register updates via exception */
348 mfspr r3, SPRN_EPCR
349 rlwinm r3, r3, 0, ~SPRN_EPCR_DMIUH
350 mtspr SPRN_EPCR, r3
351 isync
352
353 /* Switch to kernel stack and jump to handler. */
354 PPC_LL r3, HOST_RUN(r1)
355 mr r5, r14 /* intno */
356 mr r14, r4 /* Save vcpu pointer. */
357 bl kvmppc_handle_exit
358
359 /* Restore vcpu pointer and the nonvolatiles we used. */
360 mr r4, r14
361 PPC_LL r14, VCPU_GPR(r14)(r4)
362
363 andi. r5, r3, RESUME_FLAG_NV
364 beq skip_nv_load
365 PPC_LL r15, VCPU_GPR(r15)(r4)
366 PPC_LL r16, VCPU_GPR(r16)(r4)
367 PPC_LL r17, VCPU_GPR(r17)(r4)
368 PPC_LL r18, VCPU_GPR(r18)(r4)
369 PPC_LL r19, VCPU_GPR(r19)(r4)
370 PPC_LL r20, VCPU_GPR(r20)(r4)
371 PPC_LL r21, VCPU_GPR(r21)(r4)
372 PPC_LL r22, VCPU_GPR(r22)(r4)
373 PPC_LL r23, VCPU_GPR(r23)(r4)
374 PPC_LL r24, VCPU_GPR(r24)(r4)
375 PPC_LL r25, VCPU_GPR(r25)(r4)
376 PPC_LL r26, VCPU_GPR(r26)(r4)
377 PPC_LL r27, VCPU_GPR(r27)(r4)
378 PPC_LL r28, VCPU_GPR(r28)(r4)
379 PPC_LL r29, VCPU_GPR(r29)(r4)
380 PPC_LL r30, VCPU_GPR(r30)(r4)
381 PPC_LL r31, VCPU_GPR(r31)(r4)
382skip_nv_load:
383 /* Should we return to the guest? */
384 andi. r5, r3, RESUME_FLAG_HOST
385 beq lightweight_exit
386
387 srawi r3, r3, 2 /* Shift -ERR back down. */
388
389heavyweight_exit:
390 /* Not returning to guest. */
391 PPC_LL r5, HOST_STACK_LR(r1)
392 lwz r6, HOST_CR(r1)
393
394 /*
395 * We already saved guest volatile register state; now save the
396 * non-volatiles.
397 */
398
399 PPC_STL r15, VCPU_GPR(r15)(r4)
400 PPC_STL r16, VCPU_GPR(r16)(r4)
401 PPC_STL r17, VCPU_GPR(r17)(r4)
402 PPC_STL r18, VCPU_GPR(r18)(r4)
403 PPC_STL r19, VCPU_GPR(r19)(r4)
404 PPC_STL r20, VCPU_GPR(r20)(r4)
405 PPC_STL r21, VCPU_GPR(r21)(r4)
406 PPC_STL r22, VCPU_GPR(r22)(r4)
407 PPC_STL r23, VCPU_GPR(r23)(r4)
408 PPC_STL r24, VCPU_GPR(r24)(r4)
409 PPC_STL r25, VCPU_GPR(r25)(r4)
410 PPC_STL r26, VCPU_GPR(r26)(r4)
411 PPC_STL r27, VCPU_GPR(r27)(r4)
412 PPC_STL r28, VCPU_GPR(r28)(r4)
413 PPC_STL r29, VCPU_GPR(r29)(r4)
414 PPC_STL r30, VCPU_GPR(r30)(r4)
415 PPC_STL r31, VCPU_GPR(r31)(r4)
416
417 /* Load host non-volatile register state from host stack. */
418 PPC_LL r14, HOST_NV_GPR(r14)(r1)
419 PPC_LL r15, HOST_NV_GPR(r15)(r1)
420 PPC_LL r16, HOST_NV_GPR(r16)(r1)
421 PPC_LL r17, HOST_NV_GPR(r17)(r1)
422 PPC_LL r18, HOST_NV_GPR(r18)(r1)
423 PPC_LL r19, HOST_NV_GPR(r19)(r1)
424 PPC_LL r20, HOST_NV_GPR(r20)(r1)
425 PPC_LL r21, HOST_NV_GPR(r21)(r1)
426 PPC_LL r22, HOST_NV_GPR(r22)(r1)
427 PPC_LL r23, HOST_NV_GPR(r23)(r1)
428 PPC_LL r24, HOST_NV_GPR(r24)(r1)
429 PPC_LL r25, HOST_NV_GPR(r25)(r1)
430 PPC_LL r26, HOST_NV_GPR(r26)(r1)
431 PPC_LL r27, HOST_NV_GPR(r27)(r1)
432 PPC_LL r28, HOST_NV_GPR(r28)(r1)
433 PPC_LL r29, HOST_NV_GPR(r29)(r1)
434 PPC_LL r30, HOST_NV_GPR(r30)(r1)
435 PPC_LL r31, HOST_NV_GPR(r31)(r1)
436
437 /* Return to kvm_vcpu_run(). */
438 mtlr r5
439 mtcr r6
440 addi r1, r1, HOST_STACK_SIZE
441 /* r3 still contains the return code from kvmppc_handle_exit(). */
442 blr
443
444/* Registers:
445 * r3: kvm_run pointer
446 * r4: vcpu pointer
447 */
448_GLOBAL(__kvmppc_vcpu_run)
449 stwu r1, -HOST_STACK_SIZE(r1)
450 PPC_STL r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
451
452 /* Save host state to stack. */
453 PPC_STL r3, HOST_RUN(r1)
454 mflr r3
455 mfcr r5
456 PPC_STL r3, HOST_STACK_LR(r1)
457
458 stw r5, HOST_CR(r1)
459
460 /* Save host non-volatile register state to stack. */
461 PPC_STL r14, HOST_NV_GPR(r14)(r1)
462 PPC_STL r15, HOST_NV_GPR(r15)(r1)
463 PPC_STL r16, HOST_NV_GPR(r16)(r1)
464 PPC_STL r17, HOST_NV_GPR(r17)(r1)
465 PPC_STL r18, HOST_NV_GPR(r18)(r1)
466 PPC_STL r19, HOST_NV_GPR(r19)(r1)
467 PPC_STL r20, HOST_NV_GPR(r20)(r1)
468 PPC_STL r21, HOST_NV_GPR(r21)(r1)
469 PPC_STL r22, HOST_NV_GPR(r22)(r1)
470 PPC_STL r23, HOST_NV_GPR(r23)(r1)
471 PPC_STL r24, HOST_NV_GPR(r24)(r1)
472 PPC_STL r25, HOST_NV_GPR(r25)(r1)
473 PPC_STL r26, HOST_NV_GPR(r26)(r1)
474 PPC_STL r27, HOST_NV_GPR(r27)(r1)
475 PPC_STL r28, HOST_NV_GPR(r28)(r1)
476 PPC_STL r29, HOST_NV_GPR(r29)(r1)
477 PPC_STL r30, HOST_NV_GPR(r30)(r1)
478 PPC_STL r31, HOST_NV_GPR(r31)(r1)
479
480 /* Load guest non-volatiles. */
481 PPC_LL r14, VCPU_GPR(r14)(r4)
482 PPC_LL r15, VCPU_GPR(r15)(r4)
483 PPC_LL r16, VCPU_GPR(r16)(r4)
484 PPC_LL r17, VCPU_GPR(r17)(r4)
485 PPC_LL r18, VCPU_GPR(r18)(r4)
486 PPC_LL r19, VCPU_GPR(r19)(r4)
487 PPC_LL r20, VCPU_GPR(r20)(r4)
488 PPC_LL r21, VCPU_GPR(r21)(r4)
489 PPC_LL r22, VCPU_GPR(r22)(r4)
490 PPC_LL r23, VCPU_GPR(r23)(r4)
491 PPC_LL r24, VCPU_GPR(r24)(r4)
492 PPC_LL r25, VCPU_GPR(r25)(r4)
493 PPC_LL r26, VCPU_GPR(r26)(r4)
494 PPC_LL r27, VCPU_GPR(r27)(r4)
495 PPC_LL r28, VCPU_GPR(r28)(r4)
496 PPC_LL r29, VCPU_GPR(r29)(r4)
497 PPC_LL r30, VCPU_GPR(r30)(r4)
498 PPC_LL r31, VCPU_GPR(r31)(r4)
499
500
501lightweight_exit:
502 PPC_STL r2, HOST_R2(r1)
503
504 mfspr r3, SPRN_PID
505 stw r3, VCPU_HOST_PID(r4)
506 lwz r3, VCPU_GUEST_PID(r4)
507 mtspr SPRN_PID, r3
508
509 PPC_LL r11, VCPU_SHARED(r4)
510 /* Disable MAS register updates via exception */
511 mfspr r3, SPRN_EPCR
512 oris r3, r3, SPRN_EPCR_DMIUH@h
513 mtspr SPRN_EPCR, r3
514 isync
515 /* Save host mas4 and mas6 and load guest MAS registers */
516 mfspr r3, SPRN_MAS4
517 stw r3, VCPU_HOST_MAS4(r4)
518 mfspr r3, SPRN_MAS6
519 stw r3, VCPU_HOST_MAS6(r4)
520 lwz r3, VCPU_SHARED_MAS0(r11)
521 lwz r5, VCPU_SHARED_MAS1(r11)
522 PPC_LD(r6, VCPU_SHARED_MAS2, r11)
523 lwz r7, VCPU_SHARED_MAS7_3+4(r11)
524 lwz r8, VCPU_SHARED_MAS4(r11)
525 mtspr SPRN_MAS0, r3
526 mtspr SPRN_MAS1, r5
527 mtspr SPRN_MAS2, r6
528 mtspr SPRN_MAS3, r7
529 mtspr SPRN_MAS4, r8
530 lwz r3, VCPU_SHARED_MAS6(r11)
531 lwz r5, VCPU_SHARED_MAS7_3+0(r11)
532 mtspr SPRN_MAS6, r3
533 mtspr SPRN_MAS7, r5
534
535 /*
536 * Host interrupt handlers may have clobbered these guest-readable
537 * SPRGs, so we need to reload them here with the guest's values.
538 */
539 lwz r3, VCPU_VRSAVE(r4)
540 PPC_LD(r5, VCPU_SHARED_SPRG4, r11)
541 mtspr SPRN_VRSAVE, r3
542 PPC_LD(r6, VCPU_SHARED_SPRG5, r11)
543 mtspr SPRN_SPRG4W, r5
544 PPC_LD(r7, VCPU_SHARED_SPRG6, r11)
545 mtspr SPRN_SPRG5W, r6
546 PPC_LD(r8, VCPU_SHARED_SPRG7, r11)
547 mtspr SPRN_SPRG6W, r7
548 mtspr SPRN_SPRG7W, r8
549
550 /* Load some guest volatiles. */
551 PPC_LL r3, VCPU_LR(r4)
552 PPC_LL r5, VCPU_XER(r4)
553 PPC_LL r6, VCPU_CTR(r4)
554 lwz r7, VCPU_CR(r4)
555 PPC_LL r8, VCPU_PC(r4)
556 PPC_LD(r9, VCPU_SHARED_MSR, r11)
557 PPC_LL r0, VCPU_GPR(r0)(r4)
558 PPC_LL r1, VCPU_GPR(r1)(r4)
559 PPC_LL r2, VCPU_GPR(r2)(r4)
560 PPC_LL r10, VCPU_GPR(r10)(r4)
561 PPC_LL r11, VCPU_GPR(r11)(r4)
562 PPC_LL r12, VCPU_GPR(r12)(r4)
563 PPC_LL r13, VCPU_GPR(r13)(r4)
564 mtlr r3
565 mtxer r5
566 mtctr r6
567 mtsrr0 r8
568 mtsrr1 r9
569
570#ifdef CONFIG_KVM_EXIT_TIMING
571 /* save enter time */
5721:
573 mfspr r6, SPRN_TBRU
574 mfspr r9, SPRN_TBRL
575 mfspr r8, SPRN_TBRU
576 cmpw r8, r6
577 stw r9, VCPU_TIMING_LAST_ENTER_TBL(r4)
578 bne 1b
579 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
580#endif
581
582 /*
583 * Don't execute any instruction which can change CR after
584 * below instruction.
585 */
586 mtcr r7
587
588 /* Finish loading guest volatiles and jump to guest. */
589 PPC_LL r5, VCPU_GPR(r5)(r4)
590 PPC_LL r6, VCPU_GPR(r6)(r4)
591 PPC_LL r7, VCPU_GPR(r7)(r4)
592 PPC_LL r8, VCPU_GPR(r8)(r4)
593 PPC_LL r9, VCPU_GPR(r9)(r4)
594
595 PPC_LL r3, VCPU_GPR(r3)(r4)
596 PPC_LL r4, VCPU_GPR(r4)(r4)
597 rfi