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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Copyright IBM Corp. 2007
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
8 */
9
10#include <asm/ppc_asm.h>
11#include <asm/kvm_asm.h>
12#include <asm/reg.h>
13#include <asm/page.h>
14#include <asm/asm-offsets.h>
15
16/* The host stack layout: */
17#define HOST_R1 0 /* Implied by stwu. */
18#define HOST_CALLEE_LR 4
19#define HOST_RUN 8
20/* r2 is special: it holds 'current', and it made nonvolatile in the
21 * kernel with the -ffixed-r2 gcc option. */
22#define HOST_R2 12
23#define HOST_CR 16
24#define HOST_NV_GPRS 20
25#define __HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * 4))
26#define HOST_NV_GPR(n) __HOST_NV_GPR(__REG_##n)
27#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + 4)
28#define HOST_STACK_SIZE (((HOST_MIN_STACK_SIZE + 15) / 16) * 16) /* Align. */
29#define HOST_STACK_LR (HOST_STACK_SIZE + 4) /* In caller stack frame. */
30
31#define NEED_INST_MASK ((1<<BOOKE_INTERRUPT_PROGRAM) | \
32 (1<<BOOKE_INTERRUPT_DTLB_MISS) | \
33 (1<<BOOKE_INTERRUPT_DEBUG))
34
35#define NEED_DEAR_MASK ((1<<BOOKE_INTERRUPT_DATA_STORAGE) | \
36 (1<<BOOKE_INTERRUPT_DTLB_MISS) | \
37 (1<<BOOKE_INTERRUPT_ALIGNMENT))
38
39#define NEED_ESR_MASK ((1<<BOOKE_INTERRUPT_DATA_STORAGE) | \
40 (1<<BOOKE_INTERRUPT_INST_STORAGE) | \
41 (1<<BOOKE_INTERRUPT_PROGRAM) | \
42 (1<<BOOKE_INTERRUPT_DTLB_MISS) | \
43 (1<<BOOKE_INTERRUPT_ALIGNMENT))
44
45.macro __KVM_HANDLER ivor_nr scratch srr0
46 /* Get pointer to vcpu and record exit number. */
47 mtspr \scratch , r4
48 mfspr r4, SPRN_SPRG_THREAD
49 lwz r4, THREAD_KVM_VCPU(r4)
50 stw r3, VCPU_GPR(R3)(r4)
51 stw r5, VCPU_GPR(R5)(r4)
52 stw r6, VCPU_GPR(R6)(r4)
53 mfspr r3, \scratch
54 mfctr r5
55 stw r3, VCPU_GPR(R4)(r4)
56 stw r5, VCPU_CTR(r4)
57 mfspr r3, \srr0
58 lis r6, kvmppc_resume_host@h
59 stw r3, VCPU_PC(r4)
60 li r5, \ivor_nr
61 ori r6, r6, kvmppc_resume_host@l
62 mtctr r6
63 bctr
64.endm
65
66.macro KVM_HANDLER ivor_nr scratch srr0
67_GLOBAL(kvmppc_handler_\ivor_nr)
68 __KVM_HANDLER \ivor_nr \scratch \srr0
69.endm
70
71.macro KVM_DBG_HANDLER ivor_nr scratch srr0
72_GLOBAL(kvmppc_handler_\ivor_nr)
73 mtspr \scratch, r4
74 mfspr r4, SPRN_SPRG_THREAD
75 lwz r4, THREAD_KVM_VCPU(r4)
76 stw r3, VCPU_CRIT_SAVE(r4)
77 mfcr r3
78 mfspr r4, SPRN_CSRR1
79 andi. r4, r4, MSR_PR
80 bne 1f
81 /* debug interrupt happened in enter/exit path */
82 mfspr r4, SPRN_CSRR1
83 rlwinm r4, r4, 0, ~MSR_DE
84 mtspr SPRN_CSRR1, r4
85 lis r4, 0xffff
86 ori r4, r4, 0xffff
87 mtspr SPRN_DBSR, r4
88 mfspr r4, SPRN_SPRG_THREAD
89 lwz r4, THREAD_KVM_VCPU(r4)
90 mtcr r3
91 lwz r3, VCPU_CRIT_SAVE(r4)
92 mfspr r4, \scratch
93 rfci
941: /* debug interrupt happened in guest */
95 mtcr r3
96 mfspr r4, SPRN_SPRG_THREAD
97 lwz r4, THREAD_KVM_VCPU(r4)
98 lwz r3, VCPU_CRIT_SAVE(r4)
99 mfspr r4, \scratch
100 __KVM_HANDLER \ivor_nr \scratch \srr0
101.endm
102
103.macro KVM_HANDLER_ADDR ivor_nr
104 .long kvmppc_handler_\ivor_nr
105.endm
106
107.macro KVM_HANDLER_END
108 .long kvmppc_handlers_end
109.endm
110
111_GLOBAL(kvmppc_handlers_start)
112KVM_HANDLER BOOKE_INTERRUPT_CRITICAL SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
113KVM_HANDLER BOOKE_INTERRUPT_MACHINE_CHECK SPRN_SPRG_RSCRATCH_MC SPRN_MCSRR0
114KVM_HANDLER BOOKE_INTERRUPT_DATA_STORAGE SPRN_SPRG_RSCRATCH0 SPRN_SRR0
115KVM_HANDLER BOOKE_INTERRUPT_INST_STORAGE SPRN_SPRG_RSCRATCH0 SPRN_SRR0
116KVM_HANDLER BOOKE_INTERRUPT_EXTERNAL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
117KVM_HANDLER BOOKE_INTERRUPT_ALIGNMENT SPRN_SPRG_RSCRATCH0 SPRN_SRR0
118KVM_HANDLER BOOKE_INTERRUPT_PROGRAM SPRN_SPRG_RSCRATCH0 SPRN_SRR0
119KVM_HANDLER BOOKE_INTERRUPT_FP_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
120KVM_HANDLER BOOKE_INTERRUPT_SYSCALL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
121KVM_HANDLER BOOKE_INTERRUPT_AP_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
122KVM_HANDLER BOOKE_INTERRUPT_DECREMENTER SPRN_SPRG_RSCRATCH0 SPRN_SRR0
123KVM_HANDLER BOOKE_INTERRUPT_FIT SPRN_SPRG_RSCRATCH0 SPRN_SRR0
124KVM_HANDLER BOOKE_INTERRUPT_WATCHDOG SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
125KVM_HANDLER BOOKE_INTERRUPT_DTLB_MISS SPRN_SPRG_RSCRATCH0 SPRN_SRR0
126KVM_HANDLER BOOKE_INTERRUPT_ITLB_MISS SPRN_SPRG_RSCRATCH0 SPRN_SRR0
127KVM_DBG_HANDLER BOOKE_INTERRUPT_DEBUG SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
128KVM_HANDLER BOOKE_INTERRUPT_SPE_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
129KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_DATA SPRN_SPRG_RSCRATCH0 SPRN_SRR0
130KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_ROUND SPRN_SPRG_RSCRATCH0 SPRN_SRR0
131_GLOBAL(kvmppc_handlers_end)
132
133/* Registers:
134 * SPRG_SCRATCH0: guest r4
135 * r4: vcpu pointer
136 * r5: KVM exit number
137 */
138_GLOBAL(kvmppc_resume_host)
139 mfcr r3
140 stw r3, VCPU_CR(r4)
141 stw r7, VCPU_GPR(R7)(r4)
142 stw r8, VCPU_GPR(R8)(r4)
143 stw r9, VCPU_GPR(R9)(r4)
144
145 li r6, 1
146 slw r6, r6, r5
147
148#ifdef CONFIG_KVM_EXIT_TIMING
149 /* save exit time */
1501:
151 mfspr r7, SPRN_TBRU
152 mfspr r8, SPRN_TBRL
153 mfspr r9, SPRN_TBRU
154 cmpw r9, r7
155 bne 1b
156 stw r8, VCPU_TIMING_EXIT_TBL(r4)
157 stw r9, VCPU_TIMING_EXIT_TBU(r4)
158#endif
159
160 /* Save the faulting instruction and all GPRs for emulation. */
161 andi. r7, r6, NEED_INST_MASK
162 beq ..skip_inst_copy
163 mfspr r9, SPRN_SRR0
164 mfmsr r8
165 ori r7, r8, MSR_DS
166 mtmsr r7
167 isync
168 lwz r9, 0(r9)
169 mtmsr r8
170 isync
171 stw r9, VCPU_LAST_INST(r4)
172
173 stw r15, VCPU_GPR(R15)(r4)
174 stw r16, VCPU_GPR(R16)(r4)
175 stw r17, VCPU_GPR(R17)(r4)
176 stw r18, VCPU_GPR(R18)(r4)
177 stw r19, VCPU_GPR(R19)(r4)
178 stw r20, VCPU_GPR(R20)(r4)
179 stw r21, VCPU_GPR(R21)(r4)
180 stw r22, VCPU_GPR(R22)(r4)
181 stw r23, VCPU_GPR(R23)(r4)
182 stw r24, VCPU_GPR(R24)(r4)
183 stw r25, VCPU_GPR(R25)(r4)
184 stw r26, VCPU_GPR(R26)(r4)
185 stw r27, VCPU_GPR(R27)(r4)
186 stw r28, VCPU_GPR(R28)(r4)
187 stw r29, VCPU_GPR(R29)(r4)
188 stw r30, VCPU_GPR(R30)(r4)
189 stw r31, VCPU_GPR(R31)(r4)
190..skip_inst_copy:
191
192 /* Also grab DEAR and ESR before the host can clobber them. */
193
194 andi. r7, r6, NEED_DEAR_MASK
195 beq ..skip_dear
196 mfspr r9, SPRN_DEAR
197 stw r9, VCPU_FAULT_DEAR(r4)
198..skip_dear:
199
200 andi. r7, r6, NEED_ESR_MASK
201 beq ..skip_esr
202 mfspr r9, SPRN_ESR
203 stw r9, VCPU_FAULT_ESR(r4)
204..skip_esr:
205
206 /* Save remaining volatile guest register state to vcpu. */
207 stw r0, VCPU_GPR(R0)(r4)
208 stw r1, VCPU_GPR(R1)(r4)
209 stw r2, VCPU_GPR(R2)(r4)
210 stw r10, VCPU_GPR(R10)(r4)
211 stw r11, VCPU_GPR(R11)(r4)
212 stw r12, VCPU_GPR(R12)(r4)
213 stw r13, VCPU_GPR(R13)(r4)
214 stw r14, VCPU_GPR(R14)(r4) /* We need a NV GPR below. */
215 mflr r3
216 stw r3, VCPU_LR(r4)
217 mfxer r3
218 stw r3, VCPU_XER(r4)
219
220 /* Restore host stack pointer and PID before IVPR, since the host
221 * exception handlers use them. */
222 lwz r1, VCPU_HOST_STACK(r4)
223 lwz r3, VCPU_HOST_PID(r4)
224 mtspr SPRN_PID, r3
225
226#ifdef CONFIG_PPC_85xx
227 /* we cheat and know that Linux doesn't use PID1 which is always 0 */
228 lis r3, 0
229 mtspr SPRN_PID1, r3
230#endif
231
232 /* Restore host IVPR before re-enabling interrupts. We cheat and know
233 * that Linux IVPR is always 0xc0000000. */
234 lis r3, 0xc000
235 mtspr SPRN_IVPR, r3
236
237 /* Switch to kernel stack and jump to handler. */
238 LOAD_REG_ADDR(r3, kvmppc_handle_exit)
239 mtctr r3
240 mr r3, r4
241 lwz r2, HOST_R2(r1)
242 mr r14, r4 /* Save vcpu pointer. */
243
244 bctrl /* kvmppc_handle_exit() */
245
246 /* Restore vcpu pointer and the nonvolatiles we used. */
247 mr r4, r14
248 lwz r14, VCPU_GPR(R14)(r4)
249
250 /* Sometimes instruction emulation must restore complete GPR state. */
251 andi. r5, r3, RESUME_FLAG_NV
252 beq ..skip_nv_load
253 lwz r15, VCPU_GPR(R15)(r4)
254 lwz r16, VCPU_GPR(R16)(r4)
255 lwz r17, VCPU_GPR(R17)(r4)
256 lwz r18, VCPU_GPR(R18)(r4)
257 lwz r19, VCPU_GPR(R19)(r4)
258 lwz r20, VCPU_GPR(R20)(r4)
259 lwz r21, VCPU_GPR(R21)(r4)
260 lwz r22, VCPU_GPR(R22)(r4)
261 lwz r23, VCPU_GPR(R23)(r4)
262 lwz r24, VCPU_GPR(R24)(r4)
263 lwz r25, VCPU_GPR(R25)(r4)
264 lwz r26, VCPU_GPR(R26)(r4)
265 lwz r27, VCPU_GPR(R27)(r4)
266 lwz r28, VCPU_GPR(R28)(r4)
267 lwz r29, VCPU_GPR(R29)(r4)
268 lwz r30, VCPU_GPR(R30)(r4)
269 lwz r31, VCPU_GPR(R31)(r4)
270..skip_nv_load:
271
272 /* Should we return to the guest? */
273 andi. r5, r3, RESUME_FLAG_HOST
274 beq lightweight_exit
275
276 srawi r3, r3, 2 /* Shift -ERR back down. */
277
278heavyweight_exit:
279 /* Not returning to guest. */
280
281#ifdef CONFIG_SPE
282 /* save guest SPEFSCR and load host SPEFSCR */
283 mfspr r9, SPRN_SPEFSCR
284 stw r9, VCPU_SPEFSCR(r4)
285 lwz r9, VCPU_HOST_SPEFSCR(r4)
286 mtspr SPRN_SPEFSCR, r9
287#endif
288
289 /* We already saved guest volatile register state; now save the
290 * non-volatiles. */
291 stw r15, VCPU_GPR(R15)(r4)
292 stw r16, VCPU_GPR(R16)(r4)
293 stw r17, VCPU_GPR(R17)(r4)
294 stw r18, VCPU_GPR(R18)(r4)
295 stw r19, VCPU_GPR(R19)(r4)
296 stw r20, VCPU_GPR(R20)(r4)
297 stw r21, VCPU_GPR(R21)(r4)
298 stw r22, VCPU_GPR(R22)(r4)
299 stw r23, VCPU_GPR(R23)(r4)
300 stw r24, VCPU_GPR(R24)(r4)
301 stw r25, VCPU_GPR(R25)(r4)
302 stw r26, VCPU_GPR(R26)(r4)
303 stw r27, VCPU_GPR(R27)(r4)
304 stw r28, VCPU_GPR(R28)(r4)
305 stw r29, VCPU_GPR(R29)(r4)
306 stw r30, VCPU_GPR(R30)(r4)
307 stw r31, VCPU_GPR(R31)(r4)
308
309 /* Load host non-volatile register state from host stack. */
310 lwz r14, HOST_NV_GPR(R14)(r1)
311 lwz r15, HOST_NV_GPR(R15)(r1)
312 lwz r16, HOST_NV_GPR(R16)(r1)
313 lwz r17, HOST_NV_GPR(R17)(r1)
314 lwz r18, HOST_NV_GPR(R18)(r1)
315 lwz r19, HOST_NV_GPR(R19)(r1)
316 lwz r20, HOST_NV_GPR(R20)(r1)
317 lwz r21, HOST_NV_GPR(R21)(r1)
318 lwz r22, HOST_NV_GPR(R22)(r1)
319 lwz r23, HOST_NV_GPR(R23)(r1)
320 lwz r24, HOST_NV_GPR(R24)(r1)
321 lwz r25, HOST_NV_GPR(R25)(r1)
322 lwz r26, HOST_NV_GPR(R26)(r1)
323 lwz r27, HOST_NV_GPR(R27)(r1)
324 lwz r28, HOST_NV_GPR(R28)(r1)
325 lwz r29, HOST_NV_GPR(R29)(r1)
326 lwz r30, HOST_NV_GPR(R30)(r1)
327 lwz r31, HOST_NV_GPR(R31)(r1)
328
329 /* Return to kvm_vcpu_run(). */
330 lwz r4, HOST_STACK_LR(r1)
331 lwz r5, HOST_CR(r1)
332 addi r1, r1, HOST_STACK_SIZE
333 mtlr r4
334 mtcr r5
335 /* r3 still contains the return code from kvmppc_handle_exit(). */
336 blr
337
338
339/* Registers:
340 * r3: vcpu pointer
341 */
342_GLOBAL(__kvmppc_vcpu_run)
343 stwu r1, -HOST_STACK_SIZE(r1)
344 stw r1, VCPU_HOST_STACK(r3) /* Save stack pointer to vcpu. */
345
346 /* Save host state to stack. */
347 mr r4, r3
348 mflr r3
349 stw r3, HOST_STACK_LR(r1)
350 mfcr r5
351 stw r5, HOST_CR(r1)
352
353 /* Save host non-volatile register state to stack. */
354 stw r14, HOST_NV_GPR(R14)(r1)
355 stw r15, HOST_NV_GPR(R15)(r1)
356 stw r16, HOST_NV_GPR(R16)(r1)
357 stw r17, HOST_NV_GPR(R17)(r1)
358 stw r18, HOST_NV_GPR(R18)(r1)
359 stw r19, HOST_NV_GPR(R19)(r1)
360 stw r20, HOST_NV_GPR(R20)(r1)
361 stw r21, HOST_NV_GPR(R21)(r1)
362 stw r22, HOST_NV_GPR(R22)(r1)
363 stw r23, HOST_NV_GPR(R23)(r1)
364 stw r24, HOST_NV_GPR(R24)(r1)
365 stw r25, HOST_NV_GPR(R25)(r1)
366 stw r26, HOST_NV_GPR(R26)(r1)
367 stw r27, HOST_NV_GPR(R27)(r1)
368 stw r28, HOST_NV_GPR(R28)(r1)
369 stw r29, HOST_NV_GPR(R29)(r1)
370 stw r30, HOST_NV_GPR(R30)(r1)
371 stw r31, HOST_NV_GPR(R31)(r1)
372
373 /* Load guest non-volatiles. */
374 lwz r14, VCPU_GPR(R14)(r4)
375 lwz r15, VCPU_GPR(R15)(r4)
376 lwz r16, VCPU_GPR(R16)(r4)
377 lwz r17, VCPU_GPR(R17)(r4)
378 lwz r18, VCPU_GPR(R18)(r4)
379 lwz r19, VCPU_GPR(R19)(r4)
380 lwz r20, VCPU_GPR(R20)(r4)
381 lwz r21, VCPU_GPR(R21)(r4)
382 lwz r22, VCPU_GPR(R22)(r4)
383 lwz r23, VCPU_GPR(R23)(r4)
384 lwz r24, VCPU_GPR(R24)(r4)
385 lwz r25, VCPU_GPR(R25)(r4)
386 lwz r26, VCPU_GPR(R26)(r4)
387 lwz r27, VCPU_GPR(R27)(r4)
388 lwz r28, VCPU_GPR(R28)(r4)
389 lwz r29, VCPU_GPR(R29)(r4)
390 lwz r30, VCPU_GPR(R30)(r4)
391 lwz r31, VCPU_GPR(R31)(r4)
392
393#ifdef CONFIG_SPE
394 /* save host SPEFSCR and load guest SPEFSCR */
395 mfspr r3, SPRN_SPEFSCR
396 stw r3, VCPU_HOST_SPEFSCR(r4)
397 lwz r3, VCPU_SPEFSCR(r4)
398 mtspr SPRN_SPEFSCR, r3
399#endif
400
401lightweight_exit:
402 stw r2, HOST_R2(r1)
403
404 mfspr r3, SPRN_PID
405 stw r3, VCPU_HOST_PID(r4)
406 lwz r3, VCPU_SHADOW_PID(r4)
407 mtspr SPRN_PID, r3
408
409#ifdef CONFIG_PPC_85xx
410 lwz r3, VCPU_SHADOW_PID1(r4)
411 mtspr SPRN_PID1, r3
412#endif
413
414 /* Load some guest volatiles. */
415 lwz r0, VCPU_GPR(R0)(r4)
416 lwz r2, VCPU_GPR(R2)(r4)
417 lwz r9, VCPU_GPR(R9)(r4)
418 lwz r10, VCPU_GPR(R10)(r4)
419 lwz r11, VCPU_GPR(R11)(r4)
420 lwz r12, VCPU_GPR(R12)(r4)
421 lwz r13, VCPU_GPR(R13)(r4)
422 lwz r3, VCPU_LR(r4)
423 mtlr r3
424 lwz r3, VCPU_XER(r4)
425 mtxer r3
426
427 /* Switch the IVPR. XXX If we take a TLB miss after this we're screwed,
428 * so how do we make sure vcpu won't fault? */
429 lis r8, kvmppc_booke_handlers@ha
430 lwz r8, kvmppc_booke_handlers@l(r8)
431 mtspr SPRN_IVPR, r8
432
433 lwz r5, VCPU_SHARED(r4)
434
435 /* Can't switch the stack pointer until after IVPR is switched,
436 * because host interrupt handlers would get confused. */
437 lwz r1, VCPU_GPR(R1)(r4)
438
439 /*
440 * Host interrupt handlers may have clobbered these
441 * guest-readable SPRGs, or the guest kernel may have
442 * written directly to the shared area, so we
443 * need to reload them here with the guest's values.
444 */
445 PPC_LD(r3, VCPU_SHARED_SPRG4, r5)
446 mtspr SPRN_SPRG4W, r3
447 PPC_LD(r3, VCPU_SHARED_SPRG5, r5)
448 mtspr SPRN_SPRG5W, r3
449 PPC_LD(r3, VCPU_SHARED_SPRG6, r5)
450 mtspr SPRN_SPRG6W, r3
451 PPC_LD(r3, VCPU_SHARED_SPRG7, r5)
452 mtspr SPRN_SPRG7W, r3
453
454#ifdef CONFIG_KVM_EXIT_TIMING
455 /* save enter time */
4561:
457 mfspr r6, SPRN_TBRU
458 mfspr r7, SPRN_TBRL
459 mfspr r8, SPRN_TBRU
460 cmpw r8, r6
461 bne 1b
462 stw r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
463 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
464#endif
465
466 /* Finish loading guest volatiles and jump to guest. */
467 lwz r3, VCPU_CTR(r4)
468 lwz r5, VCPU_CR(r4)
469 lwz r6, VCPU_PC(r4)
470 lwz r7, VCPU_SHADOW_MSR(r4)
471 mtctr r3
472 mtcr r5
473 mtsrr0 r6
474 mtsrr1 r7
475 lwz r5, VCPU_GPR(R5)(r4)
476 lwz r6, VCPU_GPR(R6)(r4)
477 lwz r7, VCPU_GPR(R7)(r4)
478 lwz r8, VCPU_GPR(R8)(r4)
479
480 /* Clear any debug events which occurred since we disabled MSR[DE].
481 * XXX This gives us a 3-instruction window in which a breakpoint
482 * intended for guest context could fire in the host instead. */
483 lis r3, 0xffff
484 ori r3, r3, 0xffff
485 mtspr SPRN_DBSR, r3
486
487 lwz r3, VCPU_GPR(R3)(r4)
488 lwz r4, VCPU_GPR(R4)(r4)
489 rfi
490
491 .data
492 .align 4
493 .globl kvmppc_booke_handler_addr
494kvmppc_booke_handler_addr:
495KVM_HANDLER_ADDR BOOKE_INTERRUPT_CRITICAL
496KVM_HANDLER_ADDR BOOKE_INTERRUPT_MACHINE_CHECK
497KVM_HANDLER_ADDR BOOKE_INTERRUPT_DATA_STORAGE
498KVM_HANDLER_ADDR BOOKE_INTERRUPT_INST_STORAGE
499KVM_HANDLER_ADDR BOOKE_INTERRUPT_EXTERNAL
500KVM_HANDLER_ADDR BOOKE_INTERRUPT_ALIGNMENT
501KVM_HANDLER_ADDR BOOKE_INTERRUPT_PROGRAM
502KVM_HANDLER_ADDR BOOKE_INTERRUPT_FP_UNAVAIL
503KVM_HANDLER_ADDR BOOKE_INTERRUPT_SYSCALL
504KVM_HANDLER_ADDR BOOKE_INTERRUPT_AP_UNAVAIL
505KVM_HANDLER_ADDR BOOKE_INTERRUPT_DECREMENTER
506KVM_HANDLER_ADDR BOOKE_INTERRUPT_FIT
507KVM_HANDLER_ADDR BOOKE_INTERRUPT_WATCHDOG
508KVM_HANDLER_ADDR BOOKE_INTERRUPT_DTLB_MISS
509KVM_HANDLER_ADDR BOOKE_INTERRUPT_ITLB_MISS
510KVM_HANDLER_ADDR BOOKE_INTERRUPT_DEBUG
511KVM_HANDLER_ADDR BOOKE_INTERRUPT_SPE_UNAVAIL
512KVM_HANDLER_ADDR BOOKE_INTERRUPT_SPE_FP_DATA
513KVM_HANDLER_ADDR BOOKE_INTERRUPT_SPE_FP_ROUND
514KVM_HANDLER_END /*Always keep this in end*/
515
516#ifdef CONFIG_SPE
517_GLOBAL(kvmppc_save_guest_spe)
518 cmpi 0,r3,0
519 beqlr-
520 SAVE_32EVRS(0, r4, r3, VCPU_EVR)
521 evxor evr6, evr6, evr6
522 evmwumiaa evr6, evr6, evr6
523 li r4,VCPU_ACC
524 evstddx evr6, r4, r3 /* save acc */
525 blr
526
527_GLOBAL(kvmppc_load_guest_spe)
528 cmpi 0,r3,0
529 beqlr-
530 li r4,VCPU_ACC
531 evlddx evr6,r4,r3
532 evmra evr6,evr6 /* load acc */
533 REST_32EVRS(0, r4, r3, VCPU_EVR)
534 blr
535#endif
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
16 * Copyright 2011 Freescale Semiconductor, Inc.
17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 */
20
21#include <asm/ppc_asm.h>
22#include <asm/kvm_asm.h>
23#include <asm/reg.h>
24#include <asm/mmu-44x.h>
25#include <asm/page.h>
26#include <asm/asm-offsets.h>
27
28#define VCPU_GPR(n) (VCPU_GPRS + (n * 4))
29
30/* The host stack layout: */
31#define HOST_R1 0 /* Implied by stwu. */
32#define HOST_CALLEE_LR 4
33#define HOST_RUN 8
34/* r2 is special: it holds 'current', and it made nonvolatile in the
35 * kernel with the -ffixed-r2 gcc option. */
36#define HOST_R2 12
37#define HOST_CR 16
38#define HOST_NV_GPRS 20
39#define HOST_NV_GPR(n) (HOST_NV_GPRS + ((n - 14) * 4))
40#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + 4)
41#define HOST_STACK_SIZE (((HOST_MIN_STACK_SIZE + 15) / 16) * 16) /* Align. */
42#define HOST_STACK_LR (HOST_STACK_SIZE + 4) /* In caller stack frame. */
43
44#define NEED_INST_MASK ((1<<BOOKE_INTERRUPT_PROGRAM) | \
45 (1<<BOOKE_INTERRUPT_DTLB_MISS) | \
46 (1<<BOOKE_INTERRUPT_DEBUG))
47
48#define NEED_DEAR_MASK ((1<<BOOKE_INTERRUPT_DATA_STORAGE) | \
49 (1<<BOOKE_INTERRUPT_DTLB_MISS))
50
51#define NEED_ESR_MASK ((1<<BOOKE_INTERRUPT_DATA_STORAGE) | \
52 (1<<BOOKE_INTERRUPT_INST_STORAGE) | \
53 (1<<BOOKE_INTERRUPT_PROGRAM) | \
54 (1<<BOOKE_INTERRUPT_DTLB_MISS))
55
56.macro KVM_HANDLER ivor_nr
57_GLOBAL(kvmppc_handler_\ivor_nr)
58 /* Get pointer to vcpu and record exit number. */
59 mtspr SPRN_SPRG_WSCRATCH0, r4
60 mfspr r4, SPRN_SPRG_RVCPU
61 stw r5, VCPU_GPR(r5)(r4)
62 stw r6, VCPU_GPR(r6)(r4)
63 mfctr r5
64 lis r6, kvmppc_resume_host@h
65 stw r5, VCPU_CTR(r4)
66 li r5, \ivor_nr
67 ori r6, r6, kvmppc_resume_host@l
68 mtctr r6
69 bctr
70.endm
71
72_GLOBAL(kvmppc_handlers_start)
73KVM_HANDLER BOOKE_INTERRUPT_CRITICAL
74KVM_HANDLER BOOKE_INTERRUPT_MACHINE_CHECK
75KVM_HANDLER BOOKE_INTERRUPT_DATA_STORAGE
76KVM_HANDLER BOOKE_INTERRUPT_INST_STORAGE
77KVM_HANDLER BOOKE_INTERRUPT_EXTERNAL
78KVM_HANDLER BOOKE_INTERRUPT_ALIGNMENT
79KVM_HANDLER BOOKE_INTERRUPT_PROGRAM
80KVM_HANDLER BOOKE_INTERRUPT_FP_UNAVAIL
81KVM_HANDLER BOOKE_INTERRUPT_SYSCALL
82KVM_HANDLER BOOKE_INTERRUPT_AP_UNAVAIL
83KVM_HANDLER BOOKE_INTERRUPT_DECREMENTER
84KVM_HANDLER BOOKE_INTERRUPT_FIT
85KVM_HANDLER BOOKE_INTERRUPT_WATCHDOG
86KVM_HANDLER BOOKE_INTERRUPT_DTLB_MISS
87KVM_HANDLER BOOKE_INTERRUPT_ITLB_MISS
88KVM_HANDLER BOOKE_INTERRUPT_DEBUG
89KVM_HANDLER BOOKE_INTERRUPT_SPE_UNAVAIL
90KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_DATA
91KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_ROUND
92
93_GLOBAL(kvmppc_handler_len)
94 .long kvmppc_handler_1 - kvmppc_handler_0
95
96
97/* Registers:
98 * SPRG_SCRATCH0: guest r4
99 * r4: vcpu pointer
100 * r5: KVM exit number
101 */
102_GLOBAL(kvmppc_resume_host)
103 stw r3, VCPU_GPR(r3)(r4)
104 mfcr r3
105 stw r3, VCPU_CR(r4)
106 stw r7, VCPU_GPR(r7)(r4)
107 stw r8, VCPU_GPR(r8)(r4)
108 stw r9, VCPU_GPR(r9)(r4)
109
110 li r6, 1
111 slw r6, r6, r5
112
113#ifdef CONFIG_KVM_EXIT_TIMING
114 /* save exit time */
1151:
116 mfspr r7, SPRN_TBRU
117 mfspr r8, SPRN_TBRL
118 mfspr r9, SPRN_TBRU
119 cmpw r9, r7
120 bne 1b
121 stw r8, VCPU_TIMING_EXIT_TBL(r4)
122 stw r9, VCPU_TIMING_EXIT_TBU(r4)
123#endif
124
125 /* Save the faulting instruction and all GPRs for emulation. */
126 andi. r7, r6, NEED_INST_MASK
127 beq ..skip_inst_copy
128 mfspr r9, SPRN_SRR0
129 mfmsr r8
130 ori r7, r8, MSR_DS
131 mtmsr r7
132 isync
133 lwz r9, 0(r9)
134 mtmsr r8
135 isync
136 stw r9, VCPU_LAST_INST(r4)
137
138 stw r15, VCPU_GPR(r15)(r4)
139 stw r16, VCPU_GPR(r16)(r4)
140 stw r17, VCPU_GPR(r17)(r4)
141 stw r18, VCPU_GPR(r18)(r4)
142 stw r19, VCPU_GPR(r19)(r4)
143 stw r20, VCPU_GPR(r20)(r4)
144 stw r21, VCPU_GPR(r21)(r4)
145 stw r22, VCPU_GPR(r22)(r4)
146 stw r23, VCPU_GPR(r23)(r4)
147 stw r24, VCPU_GPR(r24)(r4)
148 stw r25, VCPU_GPR(r25)(r4)
149 stw r26, VCPU_GPR(r26)(r4)
150 stw r27, VCPU_GPR(r27)(r4)
151 stw r28, VCPU_GPR(r28)(r4)
152 stw r29, VCPU_GPR(r29)(r4)
153 stw r30, VCPU_GPR(r30)(r4)
154 stw r31, VCPU_GPR(r31)(r4)
155..skip_inst_copy:
156
157 /* Also grab DEAR and ESR before the host can clobber them. */
158
159 andi. r7, r6, NEED_DEAR_MASK
160 beq ..skip_dear
161 mfspr r9, SPRN_DEAR
162 stw r9, VCPU_FAULT_DEAR(r4)
163..skip_dear:
164
165 andi. r7, r6, NEED_ESR_MASK
166 beq ..skip_esr
167 mfspr r9, SPRN_ESR
168 stw r9, VCPU_FAULT_ESR(r4)
169..skip_esr:
170
171 /* Save remaining volatile guest register state to vcpu. */
172 stw r0, VCPU_GPR(r0)(r4)
173 stw r1, VCPU_GPR(r1)(r4)
174 stw r2, VCPU_GPR(r2)(r4)
175 stw r10, VCPU_GPR(r10)(r4)
176 stw r11, VCPU_GPR(r11)(r4)
177 stw r12, VCPU_GPR(r12)(r4)
178 stw r13, VCPU_GPR(r13)(r4)
179 stw r14, VCPU_GPR(r14)(r4) /* We need a NV GPR below. */
180 mflr r3
181 stw r3, VCPU_LR(r4)
182 mfxer r3
183 stw r3, VCPU_XER(r4)
184 mfspr r3, SPRN_SPRG_RSCRATCH0
185 stw r3, VCPU_GPR(r4)(r4)
186 mfspr r3, SPRN_SRR0
187 stw r3, VCPU_PC(r4)
188
189 /* Restore host stack pointer and PID before IVPR, since the host
190 * exception handlers use them. */
191 lwz r1, VCPU_HOST_STACK(r4)
192 lwz r3, VCPU_HOST_PID(r4)
193 mtspr SPRN_PID, r3
194
195#ifdef CONFIG_FSL_BOOKE
196 /* we cheat and know that Linux doesn't use PID1 which is always 0 */
197 lis r3, 0
198 mtspr SPRN_PID1, r3
199#endif
200
201 /* Restore host IVPR before re-enabling interrupts. We cheat and know
202 * that Linux IVPR is always 0xc0000000. */
203 lis r3, 0xc000
204 mtspr SPRN_IVPR, r3
205
206 /* Switch to kernel stack and jump to handler. */
207 LOAD_REG_ADDR(r3, kvmppc_handle_exit)
208 mtctr r3
209 lwz r3, HOST_RUN(r1)
210 lwz r2, HOST_R2(r1)
211 mr r14, r4 /* Save vcpu pointer. */
212
213 bctrl /* kvmppc_handle_exit() */
214
215 /* Restore vcpu pointer and the nonvolatiles we used. */
216 mr r4, r14
217 lwz r14, VCPU_GPR(r14)(r4)
218
219 /* Sometimes instruction emulation must restore complete GPR state. */
220 andi. r5, r3, RESUME_FLAG_NV
221 beq ..skip_nv_load
222 lwz r15, VCPU_GPR(r15)(r4)
223 lwz r16, VCPU_GPR(r16)(r4)
224 lwz r17, VCPU_GPR(r17)(r4)
225 lwz r18, VCPU_GPR(r18)(r4)
226 lwz r19, VCPU_GPR(r19)(r4)
227 lwz r20, VCPU_GPR(r20)(r4)
228 lwz r21, VCPU_GPR(r21)(r4)
229 lwz r22, VCPU_GPR(r22)(r4)
230 lwz r23, VCPU_GPR(r23)(r4)
231 lwz r24, VCPU_GPR(r24)(r4)
232 lwz r25, VCPU_GPR(r25)(r4)
233 lwz r26, VCPU_GPR(r26)(r4)
234 lwz r27, VCPU_GPR(r27)(r4)
235 lwz r28, VCPU_GPR(r28)(r4)
236 lwz r29, VCPU_GPR(r29)(r4)
237 lwz r30, VCPU_GPR(r30)(r4)
238 lwz r31, VCPU_GPR(r31)(r4)
239..skip_nv_load:
240
241 /* Should we return to the guest? */
242 andi. r5, r3, RESUME_FLAG_HOST
243 beq lightweight_exit
244
245 srawi r3, r3, 2 /* Shift -ERR back down. */
246
247heavyweight_exit:
248 /* Not returning to guest. */
249
250#ifdef CONFIG_SPE
251 /* save guest SPEFSCR and load host SPEFSCR */
252 mfspr r9, SPRN_SPEFSCR
253 stw r9, VCPU_SPEFSCR(r4)
254 lwz r9, VCPU_HOST_SPEFSCR(r4)
255 mtspr SPRN_SPEFSCR, r9
256#endif
257
258 /* We already saved guest volatile register state; now save the
259 * non-volatiles. */
260 stw r15, VCPU_GPR(r15)(r4)
261 stw r16, VCPU_GPR(r16)(r4)
262 stw r17, VCPU_GPR(r17)(r4)
263 stw r18, VCPU_GPR(r18)(r4)
264 stw r19, VCPU_GPR(r19)(r4)
265 stw r20, VCPU_GPR(r20)(r4)
266 stw r21, VCPU_GPR(r21)(r4)
267 stw r22, VCPU_GPR(r22)(r4)
268 stw r23, VCPU_GPR(r23)(r4)
269 stw r24, VCPU_GPR(r24)(r4)
270 stw r25, VCPU_GPR(r25)(r4)
271 stw r26, VCPU_GPR(r26)(r4)
272 stw r27, VCPU_GPR(r27)(r4)
273 stw r28, VCPU_GPR(r28)(r4)
274 stw r29, VCPU_GPR(r29)(r4)
275 stw r30, VCPU_GPR(r30)(r4)
276 stw r31, VCPU_GPR(r31)(r4)
277
278 /* Load host non-volatile register state from host stack. */
279 lwz r14, HOST_NV_GPR(r14)(r1)
280 lwz r15, HOST_NV_GPR(r15)(r1)
281 lwz r16, HOST_NV_GPR(r16)(r1)
282 lwz r17, HOST_NV_GPR(r17)(r1)
283 lwz r18, HOST_NV_GPR(r18)(r1)
284 lwz r19, HOST_NV_GPR(r19)(r1)
285 lwz r20, HOST_NV_GPR(r20)(r1)
286 lwz r21, HOST_NV_GPR(r21)(r1)
287 lwz r22, HOST_NV_GPR(r22)(r1)
288 lwz r23, HOST_NV_GPR(r23)(r1)
289 lwz r24, HOST_NV_GPR(r24)(r1)
290 lwz r25, HOST_NV_GPR(r25)(r1)
291 lwz r26, HOST_NV_GPR(r26)(r1)
292 lwz r27, HOST_NV_GPR(r27)(r1)
293 lwz r28, HOST_NV_GPR(r28)(r1)
294 lwz r29, HOST_NV_GPR(r29)(r1)
295 lwz r30, HOST_NV_GPR(r30)(r1)
296 lwz r31, HOST_NV_GPR(r31)(r1)
297
298 /* Return to kvm_vcpu_run(). */
299 lwz r4, HOST_STACK_LR(r1)
300 lwz r5, HOST_CR(r1)
301 addi r1, r1, HOST_STACK_SIZE
302 mtlr r4
303 mtcr r5
304 /* r3 still contains the return code from kvmppc_handle_exit(). */
305 blr
306
307
308/* Registers:
309 * r3: kvm_run pointer
310 * r4: vcpu pointer
311 */
312_GLOBAL(__kvmppc_vcpu_run)
313 stwu r1, -HOST_STACK_SIZE(r1)
314 stw r1, VCPU_HOST_STACK(r4) /* Save stack pointer to vcpu. */
315
316 /* Save host state to stack. */
317 stw r3, HOST_RUN(r1)
318 mflr r3
319 stw r3, HOST_STACK_LR(r1)
320 mfcr r5
321 stw r5, HOST_CR(r1)
322
323 /* Save host non-volatile register state to stack. */
324 stw r14, HOST_NV_GPR(r14)(r1)
325 stw r15, HOST_NV_GPR(r15)(r1)
326 stw r16, HOST_NV_GPR(r16)(r1)
327 stw r17, HOST_NV_GPR(r17)(r1)
328 stw r18, HOST_NV_GPR(r18)(r1)
329 stw r19, HOST_NV_GPR(r19)(r1)
330 stw r20, HOST_NV_GPR(r20)(r1)
331 stw r21, HOST_NV_GPR(r21)(r1)
332 stw r22, HOST_NV_GPR(r22)(r1)
333 stw r23, HOST_NV_GPR(r23)(r1)
334 stw r24, HOST_NV_GPR(r24)(r1)
335 stw r25, HOST_NV_GPR(r25)(r1)
336 stw r26, HOST_NV_GPR(r26)(r1)
337 stw r27, HOST_NV_GPR(r27)(r1)
338 stw r28, HOST_NV_GPR(r28)(r1)
339 stw r29, HOST_NV_GPR(r29)(r1)
340 stw r30, HOST_NV_GPR(r30)(r1)
341 stw r31, HOST_NV_GPR(r31)(r1)
342
343 /* Load guest non-volatiles. */
344 lwz r14, VCPU_GPR(r14)(r4)
345 lwz r15, VCPU_GPR(r15)(r4)
346 lwz r16, VCPU_GPR(r16)(r4)
347 lwz r17, VCPU_GPR(r17)(r4)
348 lwz r18, VCPU_GPR(r18)(r4)
349 lwz r19, VCPU_GPR(r19)(r4)
350 lwz r20, VCPU_GPR(r20)(r4)
351 lwz r21, VCPU_GPR(r21)(r4)
352 lwz r22, VCPU_GPR(r22)(r4)
353 lwz r23, VCPU_GPR(r23)(r4)
354 lwz r24, VCPU_GPR(r24)(r4)
355 lwz r25, VCPU_GPR(r25)(r4)
356 lwz r26, VCPU_GPR(r26)(r4)
357 lwz r27, VCPU_GPR(r27)(r4)
358 lwz r28, VCPU_GPR(r28)(r4)
359 lwz r29, VCPU_GPR(r29)(r4)
360 lwz r30, VCPU_GPR(r30)(r4)
361 lwz r31, VCPU_GPR(r31)(r4)
362
363#ifdef CONFIG_SPE
364 /* save host SPEFSCR and load guest SPEFSCR */
365 mfspr r3, SPRN_SPEFSCR
366 stw r3, VCPU_HOST_SPEFSCR(r4)
367 lwz r3, VCPU_SPEFSCR(r4)
368 mtspr SPRN_SPEFSCR, r3
369#endif
370
371lightweight_exit:
372 stw r2, HOST_R2(r1)
373
374 mfspr r3, SPRN_PID
375 stw r3, VCPU_HOST_PID(r4)
376 lwz r3, VCPU_SHADOW_PID(r4)
377 mtspr SPRN_PID, r3
378
379#ifdef CONFIG_FSL_BOOKE
380 lwz r3, VCPU_SHADOW_PID1(r4)
381 mtspr SPRN_PID1, r3
382#endif
383
384#ifdef CONFIG_44x
385 iccci 0, 0 /* XXX hack */
386#endif
387
388 /* Load some guest volatiles. */
389 lwz r0, VCPU_GPR(r0)(r4)
390 lwz r2, VCPU_GPR(r2)(r4)
391 lwz r9, VCPU_GPR(r9)(r4)
392 lwz r10, VCPU_GPR(r10)(r4)
393 lwz r11, VCPU_GPR(r11)(r4)
394 lwz r12, VCPU_GPR(r12)(r4)
395 lwz r13, VCPU_GPR(r13)(r4)
396 lwz r3, VCPU_LR(r4)
397 mtlr r3
398 lwz r3, VCPU_XER(r4)
399 mtxer r3
400
401 /* Switch the IVPR. XXX If we take a TLB miss after this we're screwed,
402 * so how do we make sure vcpu won't fault? */
403 lis r8, kvmppc_booke_handlers@ha
404 lwz r8, kvmppc_booke_handlers@l(r8)
405 mtspr SPRN_IVPR, r8
406
407 /* Save vcpu pointer for the exception handlers. */
408 mtspr SPRN_SPRG_WVCPU, r4
409
410 lwz r5, VCPU_SHARED(r4)
411
412 /* Can't switch the stack pointer until after IVPR is switched,
413 * because host interrupt handlers would get confused. */
414 lwz r1, VCPU_GPR(r1)(r4)
415
416 /*
417 * Host interrupt handlers may have clobbered these
418 * guest-readable SPRGs, or the guest kernel may have
419 * written directly to the shared area, so we
420 * need to reload them here with the guest's values.
421 */
422 PPC_LD(r3, VCPU_SHARED_SPRG4, r5)
423 mtspr SPRN_SPRG4W, r3
424 PPC_LD(r3, VCPU_SHARED_SPRG5, r5)
425 mtspr SPRN_SPRG5W, r3
426 PPC_LD(r3, VCPU_SHARED_SPRG6, r5)
427 mtspr SPRN_SPRG6W, r3
428 PPC_LD(r3, VCPU_SHARED_SPRG7, r5)
429 mtspr SPRN_SPRG7W, r3
430
431#ifdef CONFIG_KVM_EXIT_TIMING
432 /* save enter time */
4331:
434 mfspr r6, SPRN_TBRU
435 mfspr r7, SPRN_TBRL
436 mfspr r8, SPRN_TBRU
437 cmpw r8, r6
438 bne 1b
439 stw r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
440 stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
441#endif
442
443 /* Finish loading guest volatiles and jump to guest. */
444 lwz r3, VCPU_CTR(r4)
445 lwz r5, VCPU_CR(r4)
446 lwz r6, VCPU_PC(r4)
447 lwz r7, VCPU_SHADOW_MSR(r4)
448 mtctr r3
449 mtcr r5
450 mtsrr0 r6
451 mtsrr1 r7
452 lwz r5, VCPU_GPR(r5)(r4)
453 lwz r6, VCPU_GPR(r6)(r4)
454 lwz r7, VCPU_GPR(r7)(r4)
455 lwz r8, VCPU_GPR(r8)(r4)
456
457 /* Clear any debug events which occurred since we disabled MSR[DE].
458 * XXX This gives us a 3-instruction window in which a breakpoint
459 * intended for guest context could fire in the host instead. */
460 lis r3, 0xffff
461 ori r3, r3, 0xffff
462 mtspr SPRN_DBSR, r3
463
464 lwz r3, VCPU_GPR(r3)(r4)
465 lwz r4, VCPU_GPR(r4)(r4)
466 rfi
467
468#ifdef CONFIG_SPE
469_GLOBAL(kvmppc_save_guest_spe)
470 cmpi 0,r3,0
471 beqlr-
472 SAVE_32EVRS(0, r4, r3, VCPU_EVR)
473 evxor evr6, evr6, evr6
474 evmwumiaa evr6, evr6, evr6
475 li r4,VCPU_ACC
476 evstddx evr6, r4, r3 /* save acc */
477 blr
478
479_GLOBAL(kvmppc_load_guest_spe)
480 cmpi 0,r3,0
481 beqlr-
482 li r4,VCPU_ACC
483 evlddx evr6,r4,r3
484 evmra evr6,evr6 /* load acc */
485 REST_32EVRS(0, r4, r3, VCPU_EVR)
486 blr
487#endif