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1/*
2 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
3 *
4 * Copyright (C) 2010 Google, Inc.
5 * Copyright (C) 2009 - 2013 NVIDIA Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 */
18
19#include <linux/clk.h>
20#include <linux/dma-mapping.h>
21#include <linux/err.h>
22#include <linux/gpio.h>
23#include <linux/io.h>
24#include <linux/irq.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/of_device.h>
28#include <linux/of_gpio.h>
29#include <linux/platform_device.h>
30#include <linux/pm_runtime.h>
31#include <linux/reset.h>
32#include <linux/slab.h>
33#include <linux/usb/ehci_def.h>
34#include <linux/usb/tegra_usb_phy.h>
35#include <linux/usb.h>
36#include <linux/usb/hcd.h>
37#include <linux/usb/otg.h>
38
39#include "ehci.h"
40
41#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
42
43#define TEGRA_USB_DMA_ALIGN 32
44
45#define DRIVER_DESC "Tegra EHCI driver"
46#define DRV_NAME "tegra-ehci"
47
48static struct hc_driver __read_mostly tegra_ehci_hc_driver;
49
50struct tegra_ehci_soc_config {
51 bool has_hostpc;
52};
53
54static int (*orig_hub_control)(struct usb_hcd *hcd,
55 u16 typeReq, u16 wValue, u16 wIndex,
56 char *buf, u16 wLength);
57
58struct tegra_ehci_hcd {
59 struct tegra_usb_phy *phy;
60 struct clk *clk;
61 struct reset_control *rst;
62 int port_resuming;
63 bool needs_double_reset;
64 enum tegra_usb_phy_port_speed port_speed;
65};
66
67static int tegra_ehci_internal_port_reset(
68 struct ehci_hcd *ehci,
69 u32 __iomem *portsc_reg
70)
71{
72 u32 temp;
73 unsigned long flags;
74 int retval = 0;
75 int i, tries;
76 u32 saved_usbintr;
77
78 spin_lock_irqsave(&ehci->lock, flags);
79 saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
80 /* disable USB interrupt */
81 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
82 spin_unlock_irqrestore(&ehci->lock, flags);
83
84 /*
85 * Here we have to do Port Reset at most twice for
86 * Port Enable bit to be set.
87 */
88 for (i = 0; i < 2; i++) {
89 temp = ehci_readl(ehci, portsc_reg);
90 temp |= PORT_RESET;
91 ehci_writel(ehci, temp, portsc_reg);
92 mdelay(10);
93 temp &= ~PORT_RESET;
94 ehci_writel(ehci, temp, portsc_reg);
95 mdelay(1);
96 tries = 100;
97 do {
98 mdelay(1);
99 /*
100 * Up to this point, Port Enable bit is
101 * expected to be set after 2 ms waiting.
102 * USB1 usually takes extra 45 ms, for safety,
103 * we take 100 ms as timeout.
104 */
105 temp = ehci_readl(ehci, portsc_reg);
106 } while (!(temp & PORT_PE) && tries--);
107 if (temp & PORT_PE)
108 break;
109 }
110 if (i == 2)
111 retval = -ETIMEDOUT;
112
113 /*
114 * Clear Connect Status Change bit if it's set.
115 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
116 */
117 if (temp & PORT_CSC)
118 ehci_writel(ehci, PORT_CSC, portsc_reg);
119
120 /*
121 * Write to clear any interrupt status bits that might be set
122 * during port reset.
123 */
124 temp = ehci_readl(ehci, &ehci->regs->status);
125 ehci_writel(ehci, temp, &ehci->regs->status);
126
127 /* restore original interrupt enable bits */
128 ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
129 return retval;
130}
131
132static int tegra_ehci_hub_control(
133 struct usb_hcd *hcd,
134 u16 typeReq,
135 u16 wValue,
136 u16 wIndex,
137 char *buf,
138 u16 wLength
139)
140{
141 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
142 struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv;
143 u32 __iomem *status_reg;
144 u32 temp;
145 unsigned long flags;
146 int retval = 0;
147
148 status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
149
150 spin_lock_irqsave(&ehci->lock, flags);
151
152 if (typeReq == GetPortStatus) {
153 temp = ehci_readl(ehci, status_reg);
154 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
155 /* Resume completed, re-enable disconnect detection */
156 tegra->port_resuming = 0;
157 tegra_usb_phy_postresume(hcd->phy);
158 }
159 }
160
161 else if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
162 temp = ehci_readl(ehci, status_reg);
163 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
164 retval = -EPIPE;
165 goto done;
166 }
167
168 temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
169 temp |= PORT_WKDISC_E | PORT_WKOC_E;
170 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
171
172 /*
173 * If a transaction is in progress, there may be a delay in
174 * suspending the port. Poll until the port is suspended.
175 */
176 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
177 PORT_SUSPEND, 5000))
178 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
179
180 set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
181 goto done;
182 }
183
184 /* For USB1 port we need to issue Port Reset twice internally */
185 if (tegra->needs_double_reset &&
186 (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
187 spin_unlock_irqrestore(&ehci->lock, flags);
188 return tegra_ehci_internal_port_reset(ehci, status_reg);
189 }
190
191 /*
192 * Tegra host controller will time the resume operation to clear the bit
193 * when the port control state switches to HS or FS Idle. This behavior
194 * is different from EHCI where the host controller driver is required
195 * to set this bit to a zero after the resume duration is timed in the
196 * driver.
197 */
198 else if (typeReq == ClearPortFeature &&
199 wValue == USB_PORT_FEAT_SUSPEND) {
200 temp = ehci_readl(ehci, status_reg);
201 if ((temp & PORT_RESET) || !(temp & PORT_PE)) {
202 retval = -EPIPE;
203 goto done;
204 }
205
206 if (!(temp & PORT_SUSPEND))
207 goto done;
208
209 /* Disable disconnect detection during port resume */
210 tegra_usb_phy_preresume(hcd->phy);
211
212 ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
213
214 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
215 /* start resume signalling */
216 ehci_writel(ehci, temp | PORT_RESUME, status_reg);
217 set_bit(wIndex-1, &ehci->resuming_ports);
218
219 spin_unlock_irqrestore(&ehci->lock, flags);
220 msleep(20);
221 spin_lock_irqsave(&ehci->lock, flags);
222
223 /* Poll until the controller clears RESUME and SUSPEND */
224 if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 2000))
225 pr_err("%s: timeout waiting for RESUME\n", __func__);
226 if (ehci_handshake(ehci, status_reg, PORT_SUSPEND, 0, 2000))
227 pr_err("%s: timeout waiting for SUSPEND\n", __func__);
228
229 ehci->reset_done[wIndex-1] = 0;
230 clear_bit(wIndex-1, &ehci->resuming_ports);
231
232 tegra->port_resuming = 1;
233 goto done;
234 }
235
236 spin_unlock_irqrestore(&ehci->lock, flags);
237
238 /* Handle the hub control events here */
239 return orig_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
240
241done:
242 spin_unlock_irqrestore(&ehci->lock, flags);
243 return retval;
244}
245
246struct dma_aligned_buffer {
247 void *kmalloc_ptr;
248 void *old_xfer_buffer;
249 u8 data[0];
250};
251
252static void free_dma_aligned_buffer(struct urb *urb)
253{
254 struct dma_aligned_buffer *temp;
255
256 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
257 return;
258
259 temp = container_of(urb->transfer_buffer,
260 struct dma_aligned_buffer, data);
261
262 if (usb_urb_dir_in(urb))
263 memcpy(temp->old_xfer_buffer, temp->data,
264 urb->transfer_buffer_length);
265 urb->transfer_buffer = temp->old_xfer_buffer;
266 kfree(temp->kmalloc_ptr);
267
268 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
269}
270
271static int alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
272{
273 struct dma_aligned_buffer *temp, *kmalloc_ptr;
274 size_t kmalloc_size;
275
276 if (urb->num_sgs || urb->sg ||
277 urb->transfer_buffer_length == 0 ||
278 !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
279 return 0;
280
281 /* Allocate a buffer with enough padding for alignment */
282 kmalloc_size = urb->transfer_buffer_length +
283 sizeof(struct dma_aligned_buffer) + TEGRA_USB_DMA_ALIGN - 1;
284
285 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
286 if (!kmalloc_ptr)
287 return -ENOMEM;
288
289 /* Position our struct dma_aligned_buffer such that data is aligned */
290 temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
291 temp->kmalloc_ptr = kmalloc_ptr;
292 temp->old_xfer_buffer = urb->transfer_buffer;
293 if (usb_urb_dir_out(urb))
294 memcpy(temp->data, urb->transfer_buffer,
295 urb->transfer_buffer_length);
296 urb->transfer_buffer = temp->data;
297
298 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
299
300 return 0;
301}
302
303static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
304 gfp_t mem_flags)
305{
306 int ret;
307
308 ret = alloc_dma_aligned_buffer(urb, mem_flags);
309 if (ret)
310 return ret;
311
312 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
313 if (ret)
314 free_dma_aligned_buffer(urb);
315
316 return ret;
317}
318
319static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
320{
321 usb_hcd_unmap_urb_for_dma(hcd, urb);
322 free_dma_aligned_buffer(urb);
323}
324
325static const struct tegra_ehci_soc_config tegra30_soc_config = {
326 .has_hostpc = true,
327};
328
329static const struct tegra_ehci_soc_config tegra20_soc_config = {
330 .has_hostpc = false,
331};
332
333static struct of_device_id tegra_ehci_of_match[] = {
334 { .compatible = "nvidia,tegra30-ehci", .data = &tegra30_soc_config },
335 { .compatible = "nvidia,tegra20-ehci", .data = &tegra20_soc_config },
336 { },
337};
338
339static int tegra_ehci_probe(struct platform_device *pdev)
340{
341 const struct of_device_id *match;
342 const struct tegra_ehci_soc_config *soc_config;
343 struct resource *res;
344 struct usb_hcd *hcd;
345 struct ehci_hcd *ehci;
346 struct tegra_ehci_hcd *tegra;
347 int err = 0;
348 int irq;
349 struct usb_phy *u_phy;
350
351 match = of_match_device(tegra_ehci_of_match, &pdev->dev);
352 if (!match) {
353 dev_err(&pdev->dev, "Error: No device match found\n");
354 return -ENODEV;
355 }
356 soc_config = match->data;
357
358 /* Right now device-tree probed devices don't get dma_mask set.
359 * Since shared usb code relies on it, set it here for now.
360 * Once we have dma capability bindings this can go away.
361 */
362 err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
363 if (err)
364 return err;
365
366 hcd = usb_create_hcd(&tegra_ehci_hc_driver, &pdev->dev,
367 dev_name(&pdev->dev));
368 if (!hcd) {
369 dev_err(&pdev->dev, "Unable to create HCD\n");
370 return -ENOMEM;
371 }
372 platform_set_drvdata(pdev, hcd);
373 ehci = hcd_to_ehci(hcd);
374 tegra = (struct tegra_ehci_hcd *)ehci->priv;
375
376 hcd->has_tt = 1;
377
378 tegra->clk = devm_clk_get(&pdev->dev, NULL);
379 if (IS_ERR(tegra->clk)) {
380 dev_err(&pdev->dev, "Can't get ehci clock\n");
381 err = PTR_ERR(tegra->clk);
382 goto cleanup_hcd_create;
383 }
384
385 tegra->rst = devm_reset_control_get(&pdev->dev, "usb");
386 if (IS_ERR(tegra->rst)) {
387 dev_err(&pdev->dev, "Can't get ehci reset\n");
388 err = PTR_ERR(tegra->rst);
389 goto cleanup_hcd_create;
390 }
391
392 err = clk_prepare_enable(tegra->clk);
393 if (err)
394 goto cleanup_hcd_create;
395
396 reset_control_assert(tegra->rst);
397 udelay(1);
398 reset_control_deassert(tegra->rst);
399
400 u_phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
401 if (IS_ERR(u_phy)) {
402 err = PTR_ERR(u_phy);
403 goto cleanup_clk_en;
404 }
405 hcd->phy = u_phy;
406
407 tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
408 "nvidia,needs-double-reset");
409
410 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
411 if (!res) {
412 dev_err(&pdev->dev, "Failed to get I/O memory\n");
413 err = -ENXIO;
414 goto cleanup_clk_en;
415 }
416 hcd->rsrc_start = res->start;
417 hcd->rsrc_len = resource_size(res);
418 hcd->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
419 if (!hcd->regs) {
420 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
421 err = -ENOMEM;
422 goto cleanup_clk_en;
423 }
424 ehci->caps = hcd->regs + 0x100;
425 ehci->has_hostpc = soc_config->has_hostpc;
426
427 err = usb_phy_init(hcd->phy);
428 if (err) {
429 dev_err(&pdev->dev, "Failed to initialize phy\n");
430 goto cleanup_clk_en;
431 }
432
433 u_phy->otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
434 GFP_KERNEL);
435 if (!u_phy->otg) {
436 dev_err(&pdev->dev, "Failed to alloc memory for otg\n");
437 err = -ENOMEM;
438 goto cleanup_phy;
439 }
440 u_phy->otg->host = hcd_to_bus(hcd);
441
442 err = usb_phy_set_suspend(hcd->phy, 0);
443 if (err) {
444 dev_err(&pdev->dev, "Failed to power on the phy\n");
445 goto cleanup_phy;
446 }
447
448 irq = platform_get_irq(pdev, 0);
449 if (!irq) {
450 dev_err(&pdev->dev, "Failed to get IRQ\n");
451 err = -ENODEV;
452 goto cleanup_phy;
453 }
454
455 otg_set_host(u_phy->otg, &hcd->self);
456
457 err = usb_add_hcd(hcd, irq, IRQF_SHARED);
458 if (err) {
459 dev_err(&pdev->dev, "Failed to add USB HCD\n");
460 goto cleanup_otg_set_host;
461 }
462 device_wakeup_enable(hcd->self.controller);
463
464 return err;
465
466cleanup_otg_set_host:
467 otg_set_host(u_phy->otg, NULL);
468cleanup_phy:
469 usb_phy_shutdown(hcd->phy);
470cleanup_clk_en:
471 clk_disable_unprepare(tegra->clk);
472cleanup_hcd_create:
473 usb_put_hcd(hcd);
474 return err;
475}
476
477static int tegra_ehci_remove(struct platform_device *pdev)
478{
479 struct usb_hcd *hcd = platform_get_drvdata(pdev);
480 struct tegra_ehci_hcd *tegra =
481 (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
482
483 otg_set_host(hcd->phy->otg, NULL);
484
485 usb_phy_shutdown(hcd->phy);
486 usb_remove_hcd(hcd);
487 usb_put_hcd(hcd);
488
489 clk_disable_unprepare(tegra->clk);
490
491 return 0;
492}
493
494static void tegra_ehci_hcd_shutdown(struct platform_device *pdev)
495{
496 struct usb_hcd *hcd = platform_get_drvdata(pdev);
497
498 if (hcd->driver->shutdown)
499 hcd->driver->shutdown(hcd);
500}
501
502static struct platform_driver tegra_ehci_driver = {
503 .probe = tegra_ehci_probe,
504 .remove = tegra_ehci_remove,
505 .shutdown = tegra_ehci_hcd_shutdown,
506 .driver = {
507 .name = DRV_NAME,
508 .of_match_table = tegra_ehci_of_match,
509 }
510};
511
512static int tegra_ehci_reset(struct usb_hcd *hcd)
513{
514 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
515 int retval;
516 int txfifothresh;
517
518 retval = ehci_setup(hcd);
519 if (retval)
520 return retval;
521
522 /*
523 * We should really pull this value out of tegra_ehci_soc_config, but
524 * to avoid needing access to it, make use of the fact that Tegra20 is
525 * the only one so far that needs a value of 10, and Tegra20 is the
526 * only one which doesn't set has_hostpc.
527 */
528 txfifothresh = ehci->has_hostpc ? 0x10 : 10;
529 ehci_writel(ehci, txfifothresh << 16, &ehci->regs->txfill_tuning);
530
531 return 0;
532}
533
534static const struct ehci_driver_overrides tegra_overrides __initconst = {
535 .extra_priv_size = sizeof(struct tegra_ehci_hcd),
536 .reset = tegra_ehci_reset,
537};
538
539static int __init ehci_tegra_init(void)
540{
541 if (usb_disabled())
542 return -ENODEV;
543
544 pr_info(DRV_NAME ": " DRIVER_DESC "\n");
545
546 ehci_init_driver(&tegra_ehci_hc_driver, &tegra_overrides);
547
548 /*
549 * The Tegra HW has some unusual quirks, which require Tegra-specific
550 * workarounds. We override certain hc_driver functions here to
551 * achieve that. We explicitly do not enhance ehci_driver_overrides to
552 * allow this more easily, since this is an unusual case, and we don't
553 * want to encourage others to override these functions by making it
554 * too easy.
555 */
556
557 orig_hub_control = tegra_ehci_hc_driver.hub_control;
558
559 tegra_ehci_hc_driver.map_urb_for_dma = tegra_ehci_map_urb_for_dma;
560 tegra_ehci_hc_driver.unmap_urb_for_dma = tegra_ehci_unmap_urb_for_dma;
561 tegra_ehci_hc_driver.hub_control = tegra_ehci_hub_control;
562
563 return platform_driver_register(&tegra_ehci_driver);
564}
565module_init(ehci_tegra_init);
566
567static void __exit ehci_tegra_cleanup(void)
568{
569 platform_driver_unregister(&tegra_ehci_driver);
570}
571module_exit(ehci_tegra_cleanup);
572
573MODULE_DESCRIPTION(DRIVER_DESC);
574MODULE_LICENSE("GPL");
575MODULE_ALIAS("platform:" DRV_NAME);
576MODULE_DEVICE_TABLE(of, tegra_ehci_of_match);