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1/*
2 * Driver for CSR SiRFprimaII onboard UARTs.
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/ioport.h>
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/sysrq.h>
14#include <linux/console.h>
15#include <linux/tty.h>
16#include <linux/tty_flip.h>
17#include <linux/serial_core.h>
18#include <linux/serial.h>
19#include <linux/clk.h>
20#include <linux/of.h>
21#include <linux/slab.h>
22#include <linux/io.h>
23#include <linux/of_gpio.h>
24#include <linux/dmaengine.h>
25#include <linux/dma-direction.h>
26#include <linux/dma-mapping.h>
27#include <asm/irq.h>
28#include <asm/mach/irq.h>
29
30#include "sirfsoc_uart.h"
31
32static unsigned int
33sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
34static unsigned int
35sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
36static struct uart_driver sirfsoc_uart_drv;
37
38static void sirfsoc_uart_tx_dma_complete_callback(void *param);
39static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port);
40static void sirfsoc_uart_rx_dma_complete_callback(void *param);
41static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
42 {4000000, 2359296},
43 {3500000, 1310721},
44 {3000000, 1572865},
45 {2500000, 1245186},
46 {2000000, 1572866},
47 {1500000, 1245188},
48 {1152000, 1638404},
49 {1000000, 1572869},
50 {921600, 1114120},
51 {576000, 1245196},
52 {500000, 1245198},
53 {460800, 1572876},
54 {230400, 1310750},
55 {115200, 1310781},
56 {57600, 1310843},
57 {38400, 1114328},
58 {19200, 1114545},
59 {9600, 1114979},
60};
61
62static struct sirfsoc_uart_port sirfsoc_uart_ports[SIRFSOC_UART_NR] = {
63 [0] = {
64 .port = {
65 .iotype = UPIO_MEM,
66 .flags = UPF_BOOT_AUTOCONF,
67 .line = 0,
68 },
69 },
70 [1] = {
71 .port = {
72 .iotype = UPIO_MEM,
73 .flags = UPF_BOOT_AUTOCONF,
74 .line = 1,
75 },
76 },
77 [2] = {
78 .port = {
79 .iotype = UPIO_MEM,
80 .flags = UPF_BOOT_AUTOCONF,
81 .line = 2,
82 },
83 },
84 [3] = {
85 .port = {
86 .iotype = UPIO_MEM,
87 .flags = UPF_BOOT_AUTOCONF,
88 .line = 3,
89 },
90 },
91 [4] = {
92 .port = {
93 .iotype = UPIO_MEM,
94 .flags = UPF_BOOT_AUTOCONF,
95 .line = 4,
96 },
97 },
98 [5] = {
99 .port = {
100 .iotype = UPIO_MEM,
101 .flags = UPF_BOOT_AUTOCONF,
102 .line = 5,
103 },
104 },
105};
106
107static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
108{
109 return container_of(port, struct sirfsoc_uart_port, port);
110}
111
112static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
113{
114 unsigned long reg;
115 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
116 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
117 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
118 reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status);
119
120 return (reg & ufifo_st->ff_empty(port->line)) ? TIOCSER_TEMT : 0;
121}
122
123static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
124{
125 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
126 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
127 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
128 goto cts_asserted;
129 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
130 if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) &
131 SIRFUART_AFC_CTS_STATUS))
132 goto cts_asserted;
133 else
134 goto cts_deasserted;
135 } else {
136 if (!gpio_get_value(sirfport->cts_gpio))
137 goto cts_asserted;
138 else
139 goto cts_deasserted;
140 }
141cts_deasserted:
142 return TIOCM_CAR | TIOCM_DSR;
143cts_asserted:
144 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
145}
146
147static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
148{
149 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
150 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
151 unsigned int assert = mctrl & TIOCM_RTS;
152 unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
153 unsigned int current_val;
154
155 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
156 return;
157 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
158 current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF;
159 val |= current_val;
160 wr_regl(port, ureg->sirfsoc_afc_ctrl, val);
161 } else {
162 if (!val)
163 gpio_set_value(sirfport->rts_gpio, 1);
164 else
165 gpio_set_value(sirfport->rts_gpio, 0);
166 }
167}
168
169static void sirfsoc_uart_stop_tx(struct uart_port *port)
170{
171 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
172 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
173 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
174
175 if (sirfport->tx_dma_chan) {
176 if (sirfport->tx_dma_state == TX_DMA_RUNNING) {
177 dmaengine_pause(sirfport->tx_dma_chan);
178 sirfport->tx_dma_state = TX_DMA_PAUSE;
179 } else {
180 if (!sirfport->is_marco)
181 wr_regl(port, ureg->sirfsoc_int_en_reg,
182 rd_regl(port, ureg->sirfsoc_int_en_reg) &
183 ~uint_en->sirfsoc_txfifo_empty_en);
184 else
185 wr_regl(port, SIRFUART_INT_EN_CLR,
186 uint_en->sirfsoc_txfifo_empty_en);
187 }
188 } else {
189 if (!sirfport->is_marco)
190 wr_regl(port, ureg->sirfsoc_int_en_reg,
191 rd_regl(port, ureg->sirfsoc_int_en_reg) &
192 ~uint_en->sirfsoc_txfifo_empty_en);
193 else
194 wr_regl(port, SIRFUART_INT_EN_CLR,
195 uint_en->sirfsoc_txfifo_empty_en);
196 }
197}
198
199static void sirfsoc_uart_tx_with_dma(struct sirfsoc_uart_port *sirfport)
200{
201 struct uart_port *port = &sirfport->port;
202 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
203 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
204 struct circ_buf *xmit = &port->state->xmit;
205 unsigned long tran_size;
206 unsigned long tran_start;
207 unsigned long pio_tx_size;
208
209 tran_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
210 tran_start = (unsigned long)(xmit->buf + xmit->tail);
211 if (uart_circ_empty(xmit) || uart_tx_stopped(port) ||
212 !tran_size)
213 return;
214 if (sirfport->tx_dma_state == TX_DMA_PAUSE) {
215 dmaengine_resume(sirfport->tx_dma_chan);
216 return;
217 }
218 if (sirfport->tx_dma_state == TX_DMA_RUNNING)
219 return;
220 if (!sirfport->is_marco)
221 wr_regl(port, ureg->sirfsoc_int_en_reg,
222 rd_regl(port, ureg->sirfsoc_int_en_reg)&
223 ~(uint_en->sirfsoc_txfifo_empty_en));
224 else
225 wr_regl(port, SIRFUART_INT_EN_CLR,
226 uint_en->sirfsoc_txfifo_empty_en);
227 /*
228 * DMA requires buffer address and buffer length are both aligned with
229 * 4 bytes, so we use PIO for
230 * 1. if address is not aligned with 4bytes, use PIO for the first 1~3
231 * bytes, and move to DMA for the left part aligned with 4bytes
232 * 2. if buffer length is not aligned with 4bytes, use DMA for aligned
233 * part first, move to PIO for the left 1~3 bytes
234 */
235 if (tran_size < 4 || BYTES_TO_ALIGN(tran_start)) {
236 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
237 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
238 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)|
239 SIRFUART_IO_MODE);
240 if (BYTES_TO_ALIGN(tran_start)) {
241 pio_tx_size = sirfsoc_uart_pio_tx_chars(sirfport,
242 BYTES_TO_ALIGN(tran_start));
243 tran_size -= pio_tx_size;
244 }
245 if (tran_size < 4)
246 sirfsoc_uart_pio_tx_chars(sirfport, tran_size);
247 if (!sirfport->is_marco)
248 wr_regl(port, ureg->sirfsoc_int_en_reg,
249 rd_regl(port, ureg->sirfsoc_int_en_reg)|
250 uint_en->sirfsoc_txfifo_empty_en);
251 else
252 wr_regl(port, ureg->sirfsoc_int_en_reg,
253 uint_en->sirfsoc_txfifo_empty_en);
254 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
255 } else {
256 /* tx transfer mode switch into dma mode */
257 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
258 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
259 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)&
260 ~SIRFUART_IO_MODE);
261 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
262 tran_size &= ~(0x3);
263
264 sirfport->tx_dma_addr = dma_map_single(port->dev,
265 xmit->buf + xmit->tail,
266 tran_size, DMA_TO_DEVICE);
267 sirfport->tx_dma_desc = dmaengine_prep_slave_single(
268 sirfport->tx_dma_chan, sirfport->tx_dma_addr,
269 tran_size, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
270 if (!sirfport->tx_dma_desc) {
271 dev_err(port->dev, "DMA prep slave single fail\n");
272 return;
273 }
274 sirfport->tx_dma_desc->callback =
275 sirfsoc_uart_tx_dma_complete_callback;
276 sirfport->tx_dma_desc->callback_param = (void *)sirfport;
277 sirfport->transfer_size = tran_size;
278
279 dmaengine_submit(sirfport->tx_dma_desc);
280 dma_async_issue_pending(sirfport->tx_dma_chan);
281 sirfport->tx_dma_state = TX_DMA_RUNNING;
282 }
283}
284
285static void sirfsoc_uart_start_tx(struct uart_port *port)
286{
287 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
288 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
289 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
290 if (sirfport->tx_dma_chan)
291 sirfsoc_uart_tx_with_dma(sirfport);
292 else {
293 sirfsoc_uart_pio_tx_chars(sirfport, 1);
294 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
295 if (!sirfport->is_marco)
296 wr_regl(port, ureg->sirfsoc_int_en_reg,
297 rd_regl(port, ureg->sirfsoc_int_en_reg)|
298 uint_en->sirfsoc_txfifo_empty_en);
299 else
300 wr_regl(port, ureg->sirfsoc_int_en_reg,
301 uint_en->sirfsoc_txfifo_empty_en);
302 }
303}
304
305static void sirfsoc_uart_stop_rx(struct uart_port *port)
306{
307 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
308 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
309 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
310
311 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
312 if (sirfport->rx_dma_chan) {
313 if (!sirfport->is_marco)
314 wr_regl(port, ureg->sirfsoc_int_en_reg,
315 rd_regl(port, ureg->sirfsoc_int_en_reg) &
316 ~(SIRFUART_RX_DMA_INT_EN(port, uint_en) |
317 uint_en->sirfsoc_rx_done_en));
318 else
319 wr_regl(port, SIRFUART_INT_EN_CLR,
320 SIRFUART_RX_DMA_INT_EN(port, uint_en)|
321 uint_en->sirfsoc_rx_done_en);
322 dmaengine_terminate_all(sirfport->rx_dma_chan);
323 } else {
324 if (!sirfport->is_marco)
325 wr_regl(port, ureg->sirfsoc_int_en_reg,
326 rd_regl(port, ureg->sirfsoc_int_en_reg)&
327 ~(SIRFUART_RX_IO_INT_EN(port, uint_en)));
328 else
329 wr_regl(port, SIRFUART_INT_EN_CLR,
330 SIRFUART_RX_IO_INT_EN(port, uint_en));
331 }
332}
333
334static void sirfsoc_uart_disable_ms(struct uart_port *port)
335{
336 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
337 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
338 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
339
340 if (!sirfport->hw_flow_ctrl)
341 return;
342 sirfport->ms_enabled = false;
343 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
344 wr_regl(port, ureg->sirfsoc_afc_ctrl,
345 rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF);
346 if (!sirfport->is_marco)
347 wr_regl(port, ureg->sirfsoc_int_en_reg,
348 rd_regl(port, ureg->sirfsoc_int_en_reg)&
349 ~uint_en->sirfsoc_cts_en);
350 else
351 wr_regl(port, SIRFUART_INT_EN_CLR,
352 uint_en->sirfsoc_cts_en);
353 } else
354 disable_irq(gpio_to_irq(sirfport->cts_gpio));
355}
356
357static irqreturn_t sirfsoc_uart_usp_cts_handler(int irq, void *dev_id)
358{
359 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
360 struct uart_port *port = &sirfport->port;
361 if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled)
362 uart_handle_cts_change(port,
363 !gpio_get_value(sirfport->cts_gpio));
364 return IRQ_HANDLED;
365}
366
367static void sirfsoc_uart_enable_ms(struct uart_port *port)
368{
369 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
370 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
371 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
372
373 if (!sirfport->hw_flow_ctrl)
374 return;
375 sirfport->ms_enabled = true;
376 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
377 wr_regl(port, ureg->sirfsoc_afc_ctrl,
378 rd_regl(port, ureg->sirfsoc_afc_ctrl) |
379 SIRFUART_AFC_TX_EN | SIRFUART_AFC_RX_EN);
380 if (!sirfport->is_marco)
381 wr_regl(port, ureg->sirfsoc_int_en_reg,
382 rd_regl(port, ureg->sirfsoc_int_en_reg)
383 | uint_en->sirfsoc_cts_en);
384 else
385 wr_regl(port, ureg->sirfsoc_int_en_reg,
386 uint_en->sirfsoc_cts_en);
387 } else
388 enable_irq(gpio_to_irq(sirfport->cts_gpio));
389}
390
391static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
392{
393 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
394 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
395 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
396 unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl);
397 if (break_state)
398 ulcon |= SIRFUART_SET_BREAK;
399 else
400 ulcon &= ~SIRFUART_SET_BREAK;
401 wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon);
402 }
403}
404
405static unsigned int
406sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
407{
408 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
409 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
410 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
411 unsigned int ch, rx_count = 0;
412 struct tty_struct *tty;
413 tty = tty_port_tty_get(&port->state->port);
414 if (!tty)
415 return -ENODEV;
416 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
417 ufifo_st->ff_empty(port->line))) {
418 ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) |
419 SIRFUART_DUMMY_READ;
420 if (unlikely(uart_handle_sysrq_char(port, ch)))
421 continue;
422 uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
423 rx_count++;
424 if (rx_count >= max_rx_count)
425 break;
426 }
427
428 sirfport->rx_io_count += rx_count;
429 port->icount.rx += rx_count;
430
431 spin_unlock(&port->lock);
432 tty_flip_buffer_push(&port->state->port);
433 spin_lock(&port->lock);
434
435 return rx_count;
436}
437
438static unsigned int
439sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
440{
441 struct uart_port *port = &sirfport->port;
442 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
443 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
444 struct circ_buf *xmit = &port->state->xmit;
445 unsigned int num_tx = 0;
446 while (!uart_circ_empty(xmit) &&
447 !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
448 ufifo_st->ff_full(port->line)) &&
449 count--) {
450 wr_regl(port, ureg->sirfsoc_tx_fifo_data,
451 xmit->buf[xmit->tail]);
452 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
453 port->icount.tx++;
454 num_tx++;
455 }
456 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
457 uart_write_wakeup(port);
458 return num_tx;
459}
460
461static void sirfsoc_uart_tx_dma_complete_callback(void *param)
462{
463 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
464 struct uart_port *port = &sirfport->port;
465 struct circ_buf *xmit = &port->state->xmit;
466 unsigned long flags;
467
468 xmit->tail = (xmit->tail + sirfport->transfer_size) &
469 (UART_XMIT_SIZE - 1);
470 port->icount.tx += sirfport->transfer_size;
471 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
472 uart_write_wakeup(port);
473 if (sirfport->tx_dma_addr)
474 dma_unmap_single(port->dev, sirfport->tx_dma_addr,
475 sirfport->transfer_size, DMA_TO_DEVICE);
476 spin_lock_irqsave(&sirfport->tx_lock, flags);
477 sirfport->tx_dma_state = TX_DMA_IDLE;
478 sirfsoc_uart_tx_with_dma(sirfport);
479 spin_unlock_irqrestore(&sirfport->tx_lock, flags);
480}
481
482static void sirfsoc_uart_insert_rx_buf_to_tty(
483 struct sirfsoc_uart_port *sirfport, int count)
484{
485 struct uart_port *port = &sirfport->port;
486 struct tty_port *tport = &port->state->port;
487 int inserted;
488
489 inserted = tty_insert_flip_string(tport,
490 sirfport->rx_dma_items[sirfport->rx_completed].xmit.buf, count);
491 port->icount.rx += inserted;
492 tty_flip_buffer_push(tport);
493}
494
495static void sirfsoc_rx_submit_one_dma_desc(struct uart_port *port, int index)
496{
497 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
498
499 sirfport->rx_dma_items[index].xmit.tail =
500 sirfport->rx_dma_items[index].xmit.head = 0;
501 sirfport->rx_dma_items[index].desc =
502 dmaengine_prep_slave_single(sirfport->rx_dma_chan,
503 sirfport->rx_dma_items[index].dma_addr, SIRFSOC_RX_DMA_BUF_SIZE,
504 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
505 if (!sirfport->rx_dma_items[index].desc) {
506 dev_err(port->dev, "DMA slave single fail\n");
507 return;
508 }
509 sirfport->rx_dma_items[index].desc->callback =
510 sirfsoc_uart_rx_dma_complete_callback;
511 sirfport->rx_dma_items[index].desc->callback_param = sirfport;
512 sirfport->rx_dma_items[index].cookie =
513 dmaengine_submit(sirfport->rx_dma_items[index].desc);
514 dma_async_issue_pending(sirfport->rx_dma_chan);
515}
516
517static void sirfsoc_rx_tmo_process_tl(unsigned long param)
518{
519 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
520 struct uart_port *port = &sirfport->port;
521 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
522 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
523 struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
524 unsigned int count;
525 unsigned long flags;
526 struct dma_tx_state tx_state;
527
528 spin_lock_irqsave(&sirfport->rx_lock, flags);
529 while (DMA_COMPLETE == dmaengine_tx_status(sirfport->rx_dma_chan,
530 sirfport->rx_dma_items[sirfport->rx_completed].cookie, &tx_state)) {
531 sirfsoc_uart_insert_rx_buf_to_tty(sirfport,
532 SIRFSOC_RX_DMA_BUF_SIZE);
533 sirfport->rx_completed++;
534 sirfport->rx_completed %= SIRFSOC_RX_LOOP_BUF_CNT;
535 }
536 count = CIRC_CNT(sirfport->rx_dma_items[sirfport->rx_issued].xmit.head,
537 sirfport->rx_dma_items[sirfport->rx_issued].xmit.tail,
538 SIRFSOC_RX_DMA_BUF_SIZE);
539 if (count > 0)
540 sirfsoc_uart_insert_rx_buf_to_tty(sirfport, count);
541 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
542 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
543 SIRFUART_IO_MODE);
544 spin_unlock_irqrestore(&sirfport->rx_lock, flags);
545 spin_lock(&port->lock);
546 sirfsoc_uart_pio_rx_chars(port, 4 - sirfport->rx_io_count);
547 spin_unlock(&port->lock);
548 if (sirfport->rx_io_count == 4) {
549 spin_lock_irqsave(&sirfport->rx_lock, flags);
550 sirfport->rx_io_count = 0;
551 wr_regl(port, ureg->sirfsoc_int_st_reg,
552 uint_st->sirfsoc_rx_done);
553 if (!sirfport->is_marco)
554 wr_regl(port, ureg->sirfsoc_int_en_reg,
555 rd_regl(port, ureg->sirfsoc_int_en_reg) &
556 ~(uint_en->sirfsoc_rx_done_en));
557 else
558 wr_regl(port, SIRFUART_INT_EN_CLR,
559 uint_en->sirfsoc_rx_done_en);
560 spin_unlock_irqrestore(&sirfport->rx_lock, flags);
561
562 sirfsoc_uart_start_next_rx_dma(port);
563 } else {
564 spin_lock_irqsave(&sirfport->rx_lock, flags);
565 wr_regl(port, ureg->sirfsoc_int_st_reg,
566 uint_st->sirfsoc_rx_done);
567 if (!sirfport->is_marco)
568 wr_regl(port, ureg->sirfsoc_int_en_reg,
569 rd_regl(port, ureg->sirfsoc_int_en_reg) |
570 (uint_en->sirfsoc_rx_done_en));
571 else
572 wr_regl(port, ureg->sirfsoc_int_en_reg,
573 uint_en->sirfsoc_rx_done_en);
574 spin_unlock_irqrestore(&sirfport->rx_lock, flags);
575 }
576}
577
578static void sirfsoc_uart_handle_rx_tmo(struct sirfsoc_uart_port *sirfport)
579{
580 struct uart_port *port = &sirfport->port;
581 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
582 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
583 struct dma_tx_state tx_state;
584 spin_lock(&sirfport->rx_lock);
585
586 dmaengine_tx_status(sirfport->rx_dma_chan,
587 sirfport->rx_dma_items[sirfport->rx_issued].cookie, &tx_state);
588 dmaengine_terminate_all(sirfport->rx_dma_chan);
589 sirfport->rx_dma_items[sirfport->rx_issued].xmit.head =
590 SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue;
591 if (!sirfport->is_marco)
592 wr_regl(port, ureg->sirfsoc_int_en_reg,
593 rd_regl(port, ureg->sirfsoc_int_en_reg) &
594 ~(uint_en->sirfsoc_rx_timeout_en));
595 else
596 wr_regl(port, SIRFUART_INT_EN_CLR,
597 uint_en->sirfsoc_rx_timeout_en);
598 spin_unlock(&sirfport->rx_lock);
599 tasklet_schedule(&sirfport->rx_tmo_process_tasklet);
600}
601
602static void sirfsoc_uart_handle_rx_done(struct sirfsoc_uart_port *sirfport)
603{
604 struct uart_port *port = &sirfport->port;
605 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
606 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
607 struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
608
609 sirfsoc_uart_pio_rx_chars(port, 4 - sirfport->rx_io_count);
610 if (sirfport->rx_io_count == 4) {
611 sirfport->rx_io_count = 0;
612 if (!sirfport->is_marco)
613 wr_regl(port, ureg->sirfsoc_int_en_reg,
614 rd_regl(port, ureg->sirfsoc_int_en_reg) &
615 ~(uint_en->sirfsoc_rx_done_en));
616 else
617 wr_regl(port, SIRFUART_INT_EN_CLR,
618 uint_en->sirfsoc_rx_done_en);
619 wr_regl(port, ureg->sirfsoc_int_st_reg,
620 uint_st->sirfsoc_rx_timeout);
621 sirfsoc_uart_start_next_rx_dma(port);
622 }
623}
624
625static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
626{
627 unsigned long intr_status;
628 unsigned long cts_status;
629 unsigned long flag = TTY_NORMAL;
630 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
631 struct uart_port *port = &sirfport->port;
632 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
633 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
634 struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
635 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
636 struct uart_state *state = port->state;
637 struct circ_buf *xmit = &port->state->xmit;
638 spin_lock(&port->lock);
639 intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);
640 wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status);
641 intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg);
642 if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(port, uint_st)))) {
643 if (intr_status & uint_st->sirfsoc_rxd_brk) {
644 port->icount.brk++;
645 if (uart_handle_break(port))
646 goto recv_char;
647 }
648 if (intr_status & uint_st->sirfsoc_rx_oflow)
649 port->icount.overrun++;
650 if (intr_status & uint_st->sirfsoc_frm_err) {
651 port->icount.frame++;
652 flag = TTY_FRAME;
653 }
654 if (intr_status & uint_st->sirfsoc_parity_err)
655 flag = TTY_PARITY;
656 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
657 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
658 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
659 intr_status &= port->read_status_mask;
660 uart_insert_char(port, intr_status,
661 uint_en->sirfsoc_rx_oflow_en, 0, flag);
662 tty_flip_buffer_push(&state->port);
663 }
664recv_char:
665 if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) &&
666 (intr_status & SIRFUART_CTS_INT_ST(uint_st)) &&
667 !sirfport->tx_dma_state) {
668 cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &
669 SIRFUART_AFC_CTS_STATUS;
670 if (cts_status != 0)
671 cts_status = 0;
672 else
673 cts_status = 1;
674 uart_handle_cts_change(port, cts_status);
675 wake_up_interruptible(&state->port.delta_msr_wait);
676 }
677 if (sirfport->rx_dma_chan) {
678 if (intr_status & uint_st->sirfsoc_rx_timeout)
679 sirfsoc_uart_handle_rx_tmo(sirfport);
680 if (intr_status & uint_st->sirfsoc_rx_done)
681 sirfsoc_uart_handle_rx_done(sirfport);
682 } else {
683 if (intr_status & SIRFUART_RX_IO_INT_ST(uint_st))
684 sirfsoc_uart_pio_rx_chars(port,
685 SIRFSOC_UART_IO_RX_MAX_CNT);
686 }
687 if (intr_status & uint_st->sirfsoc_txfifo_empty) {
688 if (sirfport->tx_dma_chan)
689 sirfsoc_uart_tx_with_dma(sirfport);
690 else {
691 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
692 spin_unlock(&port->lock);
693 return IRQ_HANDLED;
694 } else {
695 sirfsoc_uart_pio_tx_chars(sirfport,
696 SIRFSOC_UART_IO_TX_REASONABLE_CNT);
697 if ((uart_circ_empty(xmit)) &&
698 (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
699 ufifo_st->ff_empty(port->line)))
700 sirfsoc_uart_stop_tx(port);
701 }
702 }
703 }
704 spin_unlock(&port->lock);
705 return IRQ_HANDLED;
706}
707
708static void sirfsoc_uart_rx_dma_complete_tl(unsigned long param)
709{
710 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
711 struct uart_port *port = &sirfport->port;
712 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
713 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
714 unsigned long flags;
715 struct dma_tx_state tx_state;
716 spin_lock_irqsave(&sirfport->rx_lock, flags);
717 while (DMA_COMPLETE == dmaengine_tx_status(sirfport->rx_dma_chan,
718 sirfport->rx_dma_items[sirfport->rx_completed].cookie, &tx_state)) {
719 sirfsoc_uart_insert_rx_buf_to_tty(sirfport,
720 SIRFSOC_RX_DMA_BUF_SIZE);
721 if (rd_regl(port, ureg->sirfsoc_int_en_reg) &
722 uint_en->sirfsoc_rx_timeout_en)
723 sirfsoc_rx_submit_one_dma_desc(port,
724 sirfport->rx_completed++);
725 else
726 sirfport->rx_completed++;
727 sirfport->rx_completed %= SIRFSOC_RX_LOOP_BUF_CNT;
728 }
729 spin_unlock_irqrestore(&sirfport->rx_lock, flags);
730}
731
732static void sirfsoc_uart_rx_dma_complete_callback(void *param)
733{
734 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
735 spin_lock(&sirfport->rx_lock);
736 sirfport->rx_issued++;
737 sirfport->rx_issued %= SIRFSOC_RX_LOOP_BUF_CNT;
738 spin_unlock(&sirfport->rx_lock);
739 tasklet_schedule(&sirfport->rx_dma_complete_tasklet);
740}
741
742/* submit rx dma task into dmaengine */
743static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port)
744{
745 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
746 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
747 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
748 unsigned long flags;
749 int i;
750 spin_lock_irqsave(&sirfport->rx_lock, flags);
751 sirfport->rx_io_count = 0;
752 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
753 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
754 ~SIRFUART_IO_MODE);
755 spin_unlock_irqrestore(&sirfport->rx_lock, flags);
756 for (i = 0; i < SIRFSOC_RX_LOOP_BUF_CNT; i++)
757 sirfsoc_rx_submit_one_dma_desc(port, i);
758 sirfport->rx_completed = sirfport->rx_issued = 0;
759 spin_lock_irqsave(&sirfport->rx_lock, flags);
760 if (!sirfport->is_marco)
761 wr_regl(port, ureg->sirfsoc_int_en_reg,
762 rd_regl(port, ureg->sirfsoc_int_en_reg) |
763 SIRFUART_RX_DMA_INT_EN(port, uint_en));
764 else
765 wr_regl(port, ureg->sirfsoc_int_en_reg,
766 SIRFUART_RX_DMA_INT_EN(port, uint_en));
767 spin_unlock_irqrestore(&sirfport->rx_lock, flags);
768}
769
770static void sirfsoc_uart_start_rx(struct uart_port *port)
771{
772 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
773 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
774 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
775
776 sirfport->rx_io_count = 0;
777 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
778 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
779 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
780 if (sirfport->rx_dma_chan)
781 sirfsoc_uart_start_next_rx_dma(port);
782 else {
783 if (!sirfport->is_marco)
784 wr_regl(port, ureg->sirfsoc_int_en_reg,
785 rd_regl(port, ureg->sirfsoc_int_en_reg) |
786 SIRFUART_RX_IO_INT_EN(port, uint_en));
787 else
788 wr_regl(port, ureg->sirfsoc_int_en_reg,
789 SIRFUART_RX_IO_INT_EN(port, uint_en));
790 }
791}
792
793static unsigned int
794sirfsoc_usp_calc_sample_div(unsigned long set_rate,
795 unsigned long ioclk_rate, unsigned long *sample_reg)
796{
797 unsigned long min_delta = ~0UL;
798 unsigned short sample_div;
799 unsigned long ioclk_div = 0;
800 unsigned long temp_delta;
801
802 for (sample_div = SIRF_MIN_SAMPLE_DIV;
803 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
804 temp_delta = ioclk_rate -
805 (ioclk_rate + (set_rate * sample_div) / 2)
806 / (set_rate * sample_div) * set_rate * sample_div;
807
808 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
809 if (temp_delta < min_delta) {
810 ioclk_div = (2 * ioclk_rate /
811 (set_rate * sample_div) + 1) / 2 - 1;
812 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
813 continue;
814 min_delta = temp_delta;
815 *sample_reg = sample_div;
816 if (!temp_delta)
817 break;
818 }
819 }
820 return ioclk_div;
821}
822
823static unsigned int
824sirfsoc_uart_calc_sample_div(unsigned long baud_rate,
825 unsigned long ioclk_rate, unsigned long *set_baud)
826{
827 unsigned long min_delta = ~0UL;
828 unsigned short sample_div;
829 unsigned int regv = 0;
830 unsigned long ioclk_div;
831 unsigned long baud_tmp;
832 int temp_delta;
833
834 for (sample_div = SIRF_MIN_SAMPLE_DIV;
835 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
836 ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
837 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
838 continue;
839 baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
840 temp_delta = baud_tmp - baud_rate;
841 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
842 if (temp_delta < min_delta) {
843 regv = regv & (~SIRF_IOCLK_DIV_MASK);
844 regv = regv | ioclk_div;
845 regv = regv & (~SIRF_SAMPLE_DIV_MASK);
846 regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
847 min_delta = temp_delta;
848 *set_baud = baud_tmp;
849 }
850 }
851 return regv;
852}
853
854static void sirfsoc_uart_set_termios(struct uart_port *port,
855 struct ktermios *termios,
856 struct ktermios *old)
857{
858 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
859 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
860 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
861 unsigned long config_reg = 0;
862 unsigned long baud_rate;
863 unsigned long set_baud;
864 unsigned long flags;
865 unsigned long ic;
866 unsigned int clk_div_reg = 0;
867 unsigned long txfifo_op_reg, ioclk_rate;
868 unsigned long rx_time_out;
869 int threshold_div;
870 u32 data_bit_len, stop_bit_len, len_val;
871 unsigned long sample_div_reg = 0xf;
872 ioclk_rate = port->uartclk;
873
874 switch (termios->c_cflag & CSIZE) {
875 default:
876 case CS8:
877 data_bit_len = 8;
878 config_reg |= SIRFUART_DATA_BIT_LEN_8;
879 break;
880 case CS7:
881 data_bit_len = 7;
882 config_reg |= SIRFUART_DATA_BIT_LEN_7;
883 break;
884 case CS6:
885 data_bit_len = 6;
886 config_reg |= SIRFUART_DATA_BIT_LEN_6;
887 break;
888 case CS5:
889 data_bit_len = 5;
890 config_reg |= SIRFUART_DATA_BIT_LEN_5;
891 break;
892 }
893 if (termios->c_cflag & CSTOPB) {
894 config_reg |= SIRFUART_STOP_BIT_LEN_2;
895 stop_bit_len = 2;
896 } else
897 stop_bit_len = 1;
898
899 spin_lock_irqsave(&port->lock, flags);
900 port->read_status_mask = uint_en->sirfsoc_rx_oflow_en;
901 port->ignore_status_mask = 0;
902 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
903 if (termios->c_iflag & INPCK)
904 port->read_status_mask |= uint_en->sirfsoc_frm_err_en |
905 uint_en->sirfsoc_parity_err_en;
906 } else {
907 if (termios->c_iflag & INPCK)
908 port->read_status_mask |= uint_en->sirfsoc_frm_err_en;
909 }
910 if (termios->c_iflag & (BRKINT | PARMRK))
911 port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en;
912 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
913 if (termios->c_iflag & IGNPAR)
914 port->ignore_status_mask |=
915 uint_en->sirfsoc_frm_err_en |
916 uint_en->sirfsoc_parity_err_en;
917 if (termios->c_cflag & PARENB) {
918 if (termios->c_cflag & CMSPAR) {
919 if (termios->c_cflag & PARODD)
920 config_reg |= SIRFUART_STICK_BIT_MARK;
921 else
922 config_reg |= SIRFUART_STICK_BIT_SPACE;
923 } else if (termios->c_cflag & PARODD) {
924 config_reg |= SIRFUART_STICK_BIT_ODD;
925 } else {
926 config_reg |= SIRFUART_STICK_BIT_EVEN;
927 }
928 }
929 } else {
930 if (termios->c_iflag & IGNPAR)
931 port->ignore_status_mask |=
932 uint_en->sirfsoc_frm_err_en;
933 if (termios->c_cflag & PARENB)
934 dev_warn(port->dev,
935 "USP-UART not support parity err\n");
936 }
937 if (termios->c_iflag & IGNBRK) {
938 port->ignore_status_mask |=
939 uint_en->sirfsoc_rxd_brk_en;
940 if (termios->c_iflag & IGNPAR)
941 port->ignore_status_mask |=
942 uint_en->sirfsoc_rx_oflow_en;
943 }
944 if ((termios->c_cflag & CREAD) == 0)
945 port->ignore_status_mask |= SIRFUART_DUMMY_READ;
946 /* Hardware Flow Control Settings */
947 if (UART_ENABLE_MS(port, termios->c_cflag)) {
948 if (!sirfport->ms_enabled)
949 sirfsoc_uart_enable_ms(port);
950 } else {
951 if (sirfport->ms_enabled)
952 sirfsoc_uart_disable_ms(port);
953 }
954 baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
955 if (ioclk_rate == 150000000) {
956 for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
957 if (baud_rate == baudrate_to_regv[ic].baud_rate)
958 clk_div_reg = baudrate_to_regv[ic].reg_val;
959 }
960 set_baud = baud_rate;
961 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
962 if (unlikely(clk_div_reg == 0))
963 clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate,
964 ioclk_rate, &set_baud);
965 wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg);
966 } else {
967 clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate,
968 ioclk_rate, &sample_div_reg);
969 sample_div_reg--;
970 set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) /
971 (sample_div_reg + 1));
972 /* setting usp mode 2 */
973 len_val = ((1 << SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET) |
974 (1 << SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET));
975 len_val |= ((clk_div_reg & SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK)
976 << SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET);
977 wr_regl(port, ureg->sirfsoc_mode2, len_val);
978 }
979 if (tty_termios_baud_rate(termios))
980 tty_termios_encode_baud_rate(termios, set_baud, set_baud);
981 /* set receive timeout && data bits len */
982 rx_time_out = SIRFSOC_UART_RX_TIMEOUT(set_baud, 20000);
983 rx_time_out = SIRFUART_RECV_TIMEOUT_VALUE(rx_time_out);
984 txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op);
985 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_STOP);
986 wr_regl(port, ureg->sirfsoc_tx_fifo_op,
987 (txfifo_op_reg & ~SIRFUART_FIFO_START));
988 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
989 config_reg |= SIRFUART_RECV_TIMEOUT(port, rx_time_out);
990 wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg);
991 } else {
992 /*tx frame ctrl*/
993 len_val = (data_bit_len - 1) << SIRFSOC_USP_TX_DATA_LEN_OFFSET;
994 len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
995 SIRFSOC_USP_TX_FRAME_LEN_OFFSET;
996 len_val |= ((data_bit_len - 1) <<
997 SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET);
998 len_val |= (((clk_div_reg & 0xc00) >> 10) <<
999 SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET);
1000 wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val);
1001 /*rx frame ctrl*/
1002 len_val = (data_bit_len - 1) << SIRFSOC_USP_RX_DATA_LEN_OFFSET;
1003 len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
1004 SIRFSOC_USP_RX_FRAME_LEN_OFFSET;
1005 len_val |= (data_bit_len - 1) <<
1006 SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET;
1007 len_val |= (((clk_div_reg & 0xf000) >> 12) <<
1008 SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET);
1009 wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val);
1010 /*async param*/
1011 wr_regl(port, ureg->sirfsoc_async_param_reg,
1012 (SIRFUART_RECV_TIMEOUT(port, rx_time_out)) |
1013 (sample_div_reg & SIRFSOC_USP_ASYNC_DIV2_MASK) <<
1014 SIRFSOC_USP_ASYNC_DIV2_OFFSET);
1015 }
1016 if (sirfport->tx_dma_chan)
1017 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_DMA_MODE);
1018 else
1019 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_IO_MODE);
1020 if (sirfport->rx_dma_chan)
1021 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, SIRFUART_DMA_MODE);
1022 else
1023 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, SIRFUART_IO_MODE);
1024 /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
1025 if (set_baud < 1000000)
1026 threshold_div = 1;
1027 else
1028 threshold_div = 2;
1029 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl,
1030 SIRFUART_FIFO_THD(port) / threshold_div);
1031 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl,
1032 SIRFUART_FIFO_THD(port) / threshold_div);
1033 txfifo_op_reg |= SIRFUART_FIFO_START;
1034 wr_regl(port, ureg->sirfsoc_tx_fifo_op, txfifo_op_reg);
1035 uart_update_timeout(port, termios->c_cflag, set_baud);
1036 sirfsoc_uart_start_rx(port);
1037 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_TX_EN | SIRFUART_RX_EN);
1038 spin_unlock_irqrestore(&port->lock, flags);
1039}
1040
1041static void sirfsoc_uart_pm(struct uart_port *port, unsigned int state,
1042 unsigned int oldstate)
1043{
1044 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1045 if (!state)
1046 clk_prepare_enable(sirfport->clk);
1047 else
1048 clk_disable_unprepare(sirfport->clk);
1049}
1050
1051static int sirfsoc_uart_startup(struct uart_port *port)
1052{
1053 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1054 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1055 unsigned int index = port->line;
1056 int ret;
1057 set_irq_flags(port->irq, IRQF_VALID | IRQF_NOAUTOEN);
1058 ret = request_irq(port->irq,
1059 sirfsoc_uart_isr,
1060 0,
1061 SIRFUART_PORT_NAME,
1062 sirfport);
1063 if (ret != 0) {
1064 dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
1065 index, port->irq);
1066 goto irq_err;
1067 }
1068
1069 /* initial hardware settings */
1070 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
1071 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) |
1072 SIRFUART_IO_MODE);
1073 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
1074 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
1075 SIRFUART_IO_MODE);
1076 wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0);
1077 wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0);
1078 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_RX_EN | SIRFUART_TX_EN);
1079 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
1080 wr_regl(port, ureg->sirfsoc_mode1,
1081 SIRFSOC_USP_ENDIAN_CTRL_LSBF |
1082 SIRFSOC_USP_EN);
1083 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_RESET);
1084 wr_regl(port, ureg->sirfsoc_tx_fifo_op, 0);
1085 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
1086 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
1087 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, SIRFUART_FIFO_THD(port));
1088 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, SIRFUART_FIFO_THD(port));
1089 if (sirfport->rx_dma_chan)
1090 wr_regl(port, ureg->sirfsoc_rx_fifo_level_chk,
1091 SIRFUART_RX_FIFO_CHK_SC(port->line, 0x4) |
1092 SIRFUART_RX_FIFO_CHK_LC(port->line, 0xe) |
1093 SIRFUART_RX_FIFO_CHK_HC(port->line, 0x1b));
1094 if (sirfport->tx_dma_chan) {
1095 sirfport->tx_dma_state = TX_DMA_IDLE;
1096 wr_regl(port, ureg->sirfsoc_tx_fifo_level_chk,
1097 SIRFUART_TX_FIFO_CHK_SC(port->line, 0x1b) |
1098 SIRFUART_TX_FIFO_CHK_LC(port->line, 0xe) |
1099 SIRFUART_TX_FIFO_CHK_HC(port->line, 0x4));
1100 }
1101 sirfport->ms_enabled = false;
1102 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
1103 sirfport->hw_flow_ctrl) {
1104 set_irq_flags(gpio_to_irq(sirfport->cts_gpio),
1105 IRQF_VALID | IRQF_NOAUTOEN);
1106 ret = request_irq(gpio_to_irq(sirfport->cts_gpio),
1107 sirfsoc_uart_usp_cts_handler, IRQF_TRIGGER_FALLING |
1108 IRQF_TRIGGER_RISING, "usp_cts_irq", sirfport);
1109 if (ret != 0) {
1110 dev_err(port->dev, "UART-USP:request gpio irq fail\n");
1111 goto init_rx_err;
1112 }
1113 }
1114
1115 enable_irq(port->irq);
1116
1117 return 0;
1118init_rx_err:
1119 free_irq(port->irq, sirfport);
1120irq_err:
1121 return ret;
1122}
1123
1124static void sirfsoc_uart_shutdown(struct uart_port *port)
1125{
1126 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1127 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1128 if (!sirfport->is_marco)
1129 wr_regl(port, ureg->sirfsoc_int_en_reg, 0);
1130 else
1131 wr_regl(port, SIRFUART_INT_EN_CLR, ~0UL);
1132
1133 free_irq(port->irq, sirfport);
1134 if (sirfport->ms_enabled)
1135 sirfsoc_uart_disable_ms(port);
1136 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
1137 sirfport->hw_flow_ctrl) {
1138 gpio_set_value(sirfport->rts_gpio, 1);
1139 free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport);
1140 }
1141 if (sirfport->tx_dma_chan)
1142 sirfport->tx_dma_state = TX_DMA_IDLE;
1143}
1144
1145static const char *sirfsoc_uart_type(struct uart_port *port)
1146{
1147 return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
1148}
1149
1150static int sirfsoc_uart_request_port(struct uart_port *port)
1151{
1152 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1153 struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param;
1154 void *ret;
1155 ret = request_mem_region(port->mapbase,
1156 SIRFUART_MAP_SIZE, uart_param->port_name);
1157 return ret ? 0 : -EBUSY;
1158}
1159
1160static void sirfsoc_uart_release_port(struct uart_port *port)
1161{
1162 release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
1163}
1164
1165static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
1166{
1167 if (flags & UART_CONFIG_TYPE) {
1168 port->type = SIRFSOC_PORT_TYPE;
1169 sirfsoc_uart_request_port(port);
1170 }
1171}
1172
1173static struct uart_ops sirfsoc_uart_ops = {
1174 .tx_empty = sirfsoc_uart_tx_empty,
1175 .get_mctrl = sirfsoc_uart_get_mctrl,
1176 .set_mctrl = sirfsoc_uart_set_mctrl,
1177 .stop_tx = sirfsoc_uart_stop_tx,
1178 .start_tx = sirfsoc_uart_start_tx,
1179 .stop_rx = sirfsoc_uart_stop_rx,
1180 .enable_ms = sirfsoc_uart_enable_ms,
1181 .break_ctl = sirfsoc_uart_break_ctl,
1182 .startup = sirfsoc_uart_startup,
1183 .shutdown = sirfsoc_uart_shutdown,
1184 .set_termios = sirfsoc_uart_set_termios,
1185 .pm = sirfsoc_uart_pm,
1186 .type = sirfsoc_uart_type,
1187 .release_port = sirfsoc_uart_release_port,
1188 .request_port = sirfsoc_uart_request_port,
1189 .config_port = sirfsoc_uart_config_port,
1190};
1191
1192#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
1193static int __init
1194sirfsoc_uart_console_setup(struct console *co, char *options)
1195{
1196 unsigned int baud = 115200;
1197 unsigned int bits = 8;
1198 unsigned int parity = 'n';
1199 unsigned int flow = 'n';
1200 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
1201 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1202 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1203 if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
1204 return -EINVAL;
1205
1206 if (!port->mapbase)
1207 return -ENODEV;
1208
1209 /* enable usp in mode1 register */
1210 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
1211 wr_regl(port, ureg->sirfsoc_mode1, SIRFSOC_USP_EN |
1212 SIRFSOC_USP_ENDIAN_CTRL_LSBF);
1213 if (options)
1214 uart_parse_options(options, &baud, &parity, &bits, &flow);
1215 port->cons = co;
1216
1217 /* default console tx/rx transfer using io mode */
1218 sirfport->rx_dma_chan = NULL;
1219 sirfport->tx_dma_chan = NULL;
1220 return uart_set_options(port, co, baud, parity, bits, flow);
1221}
1222
1223static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
1224{
1225 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1226 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1227 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
1228 while (rd_regl(port,
1229 ureg->sirfsoc_tx_fifo_status) & ufifo_st->ff_full(port->line))
1230 cpu_relax();
1231 wr_regb(port, ureg->sirfsoc_tx_fifo_data, ch);
1232}
1233
1234static void sirfsoc_uart_console_write(struct console *co, const char *s,
1235 unsigned int count)
1236{
1237 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
1238 uart_console_write(port, s, count, sirfsoc_uart_console_putchar);
1239}
1240
1241static struct console sirfsoc_uart_console = {
1242 .name = SIRFSOC_UART_NAME,
1243 .device = uart_console_device,
1244 .flags = CON_PRINTBUFFER,
1245 .index = -1,
1246 .write = sirfsoc_uart_console_write,
1247 .setup = sirfsoc_uart_console_setup,
1248 .data = &sirfsoc_uart_drv,
1249};
1250
1251static int __init sirfsoc_uart_console_init(void)
1252{
1253 register_console(&sirfsoc_uart_console);
1254 return 0;
1255}
1256console_initcall(sirfsoc_uart_console_init);
1257#endif
1258
1259static struct uart_driver sirfsoc_uart_drv = {
1260 .owner = THIS_MODULE,
1261 .driver_name = SIRFUART_PORT_NAME,
1262 .nr = SIRFSOC_UART_NR,
1263 .dev_name = SIRFSOC_UART_NAME,
1264 .major = SIRFSOC_UART_MAJOR,
1265 .minor = SIRFSOC_UART_MINOR,
1266#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
1267 .cons = &sirfsoc_uart_console,
1268#else
1269 .cons = NULL,
1270#endif
1271};
1272
1273static struct of_device_id sirfsoc_uart_ids[] = {
1274 { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,},
1275 { .compatible = "sirf,marco-uart", .data = &sirfsoc_uart},
1276 { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp},
1277 {}
1278};
1279MODULE_DEVICE_TABLE(of, sirfsoc_uart_ids);
1280
1281static int sirfsoc_uart_probe(struct platform_device *pdev)
1282{
1283 struct sirfsoc_uart_port *sirfport;
1284 struct uart_port *port;
1285 struct resource *res;
1286 int ret;
1287 int i, j;
1288 struct dma_slave_config slv_cfg = {
1289 .src_maxburst = 2,
1290 };
1291 struct dma_slave_config tx_slv_cfg = {
1292 .dst_maxburst = 2,
1293 };
1294 const struct of_device_id *match;
1295
1296 match = of_match_node(sirfsoc_uart_ids, pdev->dev.of_node);
1297 if (of_property_read_u32(pdev->dev.of_node, "cell-index", &pdev->id)) {
1298 dev_err(&pdev->dev,
1299 "Unable to find cell-index in uart node.\n");
1300 ret = -EFAULT;
1301 goto err;
1302 }
1303 if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-usp-uart"))
1304 pdev->id += ((struct sirfsoc_uart_register *)
1305 match->data)->uart_param.register_uart_nr;
1306 sirfport = &sirfsoc_uart_ports[pdev->id];
1307 port = &sirfport->port;
1308 port->dev = &pdev->dev;
1309 port->private_data = sirfport;
1310 sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data;
1311
1312 sirfport->hw_flow_ctrl = of_property_read_bool(pdev->dev.of_node,
1313 "sirf,uart-has-rtscts");
1314 if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-uart"))
1315 sirfport->uart_reg->uart_type = SIRF_REAL_UART;
1316 if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-usp-uart")) {
1317 sirfport->uart_reg->uart_type = SIRF_USP_UART;
1318 if (!sirfport->hw_flow_ctrl)
1319 goto usp_no_flow_control;
1320 if (of_find_property(pdev->dev.of_node, "cts-gpios", NULL))
1321 sirfport->cts_gpio = of_get_named_gpio(
1322 pdev->dev.of_node, "cts-gpios", 0);
1323 else
1324 sirfport->cts_gpio = -1;
1325 if (of_find_property(pdev->dev.of_node, "rts-gpios", NULL))
1326 sirfport->rts_gpio = of_get_named_gpio(
1327 pdev->dev.of_node, "rts-gpios", 0);
1328 else
1329 sirfport->rts_gpio = -1;
1330
1331 if ((!gpio_is_valid(sirfport->cts_gpio) ||
1332 !gpio_is_valid(sirfport->rts_gpio))) {
1333 ret = -EINVAL;
1334 dev_err(&pdev->dev,
1335 "Usp flow control must have cts and rts gpio");
1336 goto err;
1337 }
1338 ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio,
1339 "usp-cts-gpio");
1340 if (ret) {
1341 dev_err(&pdev->dev, "Unable request cts gpio");
1342 goto err;
1343 }
1344 gpio_direction_input(sirfport->cts_gpio);
1345 ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio,
1346 "usp-rts-gpio");
1347 if (ret) {
1348 dev_err(&pdev->dev, "Unable request rts gpio");
1349 goto err;
1350 }
1351 gpio_direction_output(sirfport->rts_gpio, 1);
1352 }
1353usp_no_flow_control:
1354 if (of_device_is_compatible(pdev->dev.of_node, "sirf,marco-uart"))
1355 sirfport->is_marco = true;
1356
1357 if (of_property_read_u32(pdev->dev.of_node,
1358 "fifosize",
1359 &port->fifosize)) {
1360 dev_err(&pdev->dev,
1361 "Unable to find fifosize in uart node.\n");
1362 ret = -EFAULT;
1363 goto err;
1364 }
1365
1366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1367 if (res == NULL) {
1368 dev_err(&pdev->dev, "Insufficient resources.\n");
1369 ret = -EFAULT;
1370 goto err;
1371 }
1372 spin_lock_init(&sirfport->rx_lock);
1373 spin_lock_init(&sirfport->tx_lock);
1374 tasklet_init(&sirfport->rx_dma_complete_tasklet,
1375 sirfsoc_uart_rx_dma_complete_tl, (unsigned long)sirfport);
1376 tasklet_init(&sirfport->rx_tmo_process_tasklet,
1377 sirfsoc_rx_tmo_process_tl, (unsigned long)sirfport);
1378 port->mapbase = res->start;
1379 port->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1380 if (!port->membase) {
1381 dev_err(&pdev->dev, "Cannot remap resource.\n");
1382 ret = -ENOMEM;
1383 goto err;
1384 }
1385 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1386 if (res == NULL) {
1387 dev_err(&pdev->dev, "Insufficient resources.\n");
1388 ret = -EFAULT;
1389 goto err;
1390 }
1391 port->irq = res->start;
1392
1393 sirfport->clk = clk_get(&pdev->dev, NULL);
1394 if (IS_ERR(sirfport->clk)) {
1395 ret = PTR_ERR(sirfport->clk);
1396 goto err;
1397 }
1398 port->uartclk = clk_get_rate(sirfport->clk);
1399
1400 port->ops = &sirfsoc_uart_ops;
1401 spin_lock_init(&port->lock);
1402
1403 platform_set_drvdata(pdev, sirfport);
1404 ret = uart_add_one_port(&sirfsoc_uart_drv, port);
1405 if (ret != 0) {
1406 dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
1407 goto port_err;
1408 }
1409
1410 sirfport->rx_dma_chan = dma_request_slave_channel(port->dev, "rx");
1411 for (i = 0; sirfport->rx_dma_chan && i < SIRFSOC_RX_LOOP_BUF_CNT; i++) {
1412 sirfport->rx_dma_items[i].xmit.buf =
1413 dma_alloc_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1414 &sirfport->rx_dma_items[i].dma_addr, GFP_KERNEL);
1415 if (!sirfport->rx_dma_items[i].xmit.buf) {
1416 dev_err(port->dev, "Uart alloc bufa failed\n");
1417 ret = -ENOMEM;
1418 goto alloc_coherent_err;
1419 }
1420 sirfport->rx_dma_items[i].xmit.head =
1421 sirfport->rx_dma_items[i].xmit.tail = 0;
1422 }
1423 if (sirfport->rx_dma_chan)
1424 dmaengine_slave_config(sirfport->rx_dma_chan, &slv_cfg);
1425 sirfport->tx_dma_chan = dma_request_slave_channel(port->dev, "tx");
1426 if (sirfport->tx_dma_chan)
1427 dmaengine_slave_config(sirfport->tx_dma_chan, &tx_slv_cfg);
1428
1429 return 0;
1430alloc_coherent_err:
1431 for (j = 0; j < i; j++)
1432 dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1433 sirfport->rx_dma_items[j].xmit.buf,
1434 sirfport->rx_dma_items[j].dma_addr);
1435 dma_release_channel(sirfport->rx_dma_chan);
1436port_err:
1437 clk_put(sirfport->clk);
1438err:
1439 return ret;
1440}
1441
1442static int sirfsoc_uart_remove(struct platform_device *pdev)
1443{
1444 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
1445 struct uart_port *port = &sirfport->port;
1446 clk_put(sirfport->clk);
1447 uart_remove_one_port(&sirfsoc_uart_drv, port);
1448 if (sirfport->rx_dma_chan) {
1449 int i;
1450 dmaengine_terminate_all(sirfport->rx_dma_chan);
1451 dma_release_channel(sirfport->rx_dma_chan);
1452 for (i = 0; i < SIRFSOC_RX_LOOP_BUF_CNT; i++)
1453 dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1454 sirfport->rx_dma_items[i].xmit.buf,
1455 sirfport->rx_dma_items[i].dma_addr);
1456 }
1457 if (sirfport->tx_dma_chan) {
1458 dmaengine_terminate_all(sirfport->tx_dma_chan);
1459 dma_release_channel(sirfport->tx_dma_chan);
1460 }
1461 return 0;
1462}
1463
1464#ifdef CONFIG_PM_SLEEP
1465static int
1466sirfsoc_uart_suspend(struct device *pdev)
1467{
1468 struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
1469 struct uart_port *port = &sirfport->port;
1470 uart_suspend_port(&sirfsoc_uart_drv, port);
1471 return 0;
1472}
1473
1474static int sirfsoc_uart_resume(struct device *pdev)
1475{
1476 struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
1477 struct uart_port *port = &sirfport->port;
1478 uart_resume_port(&sirfsoc_uart_drv, port);
1479 return 0;
1480}
1481#endif
1482
1483static const struct dev_pm_ops sirfsoc_uart_pm_ops = {
1484 SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_uart_suspend, sirfsoc_uart_resume)
1485};
1486
1487static struct platform_driver sirfsoc_uart_driver = {
1488 .probe = sirfsoc_uart_probe,
1489 .remove = sirfsoc_uart_remove,
1490 .driver = {
1491 .name = SIRFUART_PORT_NAME,
1492 .owner = THIS_MODULE,
1493 .of_match_table = sirfsoc_uart_ids,
1494 .pm = &sirfsoc_uart_pm_ops,
1495 },
1496};
1497
1498static int __init sirfsoc_uart_init(void)
1499{
1500 int ret = 0;
1501
1502 ret = uart_register_driver(&sirfsoc_uart_drv);
1503 if (ret)
1504 goto out;
1505
1506 ret = platform_driver_register(&sirfsoc_uart_driver);
1507 if (ret)
1508 uart_unregister_driver(&sirfsoc_uart_drv);
1509out:
1510 return ret;
1511}
1512module_init(sirfsoc_uart_init);
1513
1514static void __exit sirfsoc_uart_exit(void)
1515{
1516 platform_driver_unregister(&sirfsoc_uart_driver);
1517 uart_unregister_driver(&sirfsoc_uart_drv);
1518}
1519module_exit(sirfsoc_uart_exit);
1520
1521MODULE_LICENSE("GPL v2");
1522MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
1523MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");