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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
4 *
5 * FIXME According to the usermanual the status bits in the status register
6 * are only updated when the peripherals access the FIFO and not when the
7 * CPU access them. So since we use this bits to know when we stop writing
8 * and reading, they may not be updated in-time and a race condition may
9 * exists. But I haven't be able to prove this and I don't care. But if
10 * any problem arises, it might worth checking. The TX/RX FIFO Stats
11 * registers should be used in addition.
12 * Update: Actually, they seem updated ... At least the bits we use.
13 *
14 *
15 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
16 *
17 * Some of the code has been inspired/copied from the 2.4 code written
18 * by Dale Farnsworth <dfarnsworth@mvista.com>.
19 *
20 * Copyright (C) 2008 Freescale Semiconductor Inc.
21 * John Rigby <jrigby@gmail.com>
22 * Added support for MPC5121
23 * Copyright (C) 2006 Secret Lab Technologies Ltd.
24 * Grant Likely <grant.likely@secretlab.ca>
25 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
26 * Copyright (C) 2003 MontaVista, Software, Inc.
27 */
28
29#undef DEBUG
30
31#include <linux/device.h>
32#include <linux/module.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/delay.h>
39#include <linux/io.h>
40#include <linux/of.h>
41#include <linux/of_address.h>
42#include <linux/of_irq.h>
43#include <linux/platform_device.h>
44#include <linux/clk.h>
45
46#include <asm/mpc52xx.h>
47#include <asm/mpc52xx_psc.h>
48
49#include <linux/serial_core.h>
50
51
52/* We've been assigned a range on the "Low-density serial ports" major */
53#define SERIAL_PSC_MAJOR 204
54#define SERIAL_PSC_MINOR 148
55
56
57#define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
58
59
60static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
61 /* Rem: - We use the read_status_mask as a shadow of
62 * psc->mpc52xx_psc_imr
63 * - It's important that is array is all zero on start as we
64 * use it to know if it's initialized or not ! If it's not sure
65 * it's cleared, then a memset(...,0,...) should be added to
66 * the console_init
67 */
68
69/* lookup table for matching device nodes to index numbers */
70static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
71
72static void mpc52xx_uart_of_enumerate(void);
73
74
75#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
76
77
78/* Forward declaration of the interruption handling routine */
79static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
80static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
81
82/* ======================================================================== */
83/* PSC fifo operations for isolating differences between 52xx and 512x */
84/* ======================================================================== */
85
86struct psc_ops {
87 void (*fifo_init)(struct uart_port *port);
88 unsigned int (*raw_rx_rdy)(struct uart_port *port);
89 unsigned int (*raw_tx_rdy)(struct uart_port *port);
90 unsigned int (*rx_rdy)(struct uart_port *port);
91 unsigned int (*tx_rdy)(struct uart_port *port);
92 unsigned int (*tx_empty)(struct uart_port *port);
93 void (*stop_rx)(struct uart_port *port);
94 void (*start_tx)(struct uart_port *port);
95 void (*stop_tx)(struct uart_port *port);
96 void (*rx_clr_irq)(struct uart_port *port);
97 void (*tx_clr_irq)(struct uart_port *port);
98 void (*write_char)(struct uart_port *port, unsigned char c);
99 unsigned char (*read_char)(struct uart_port *port);
100 void (*cw_disable_ints)(struct uart_port *port);
101 void (*cw_restore_ints)(struct uart_port *port);
102 unsigned int (*set_baudrate)(struct uart_port *port,
103 struct ktermios *new,
104 const struct ktermios *old);
105 int (*clock_alloc)(struct uart_port *port);
106 void (*clock_relse)(struct uart_port *port);
107 int (*clock)(struct uart_port *port, int enable);
108 int (*fifoc_init)(void);
109 void (*fifoc_uninit)(void);
110 void (*get_irq)(struct uart_port *, struct device_node *);
111 irqreturn_t (*handle_irq)(struct uart_port *port);
112 u16 (*get_status)(struct uart_port *port);
113 u8 (*get_ipcr)(struct uart_port *port);
114 void (*command)(struct uart_port *port, u8 cmd);
115 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
116 void (*set_rts)(struct uart_port *port, int state);
117 void (*enable_ms)(struct uart_port *port);
118 void (*set_sicr)(struct uart_port *port, u32 val);
119 void (*set_imr)(struct uart_port *port, u16 val);
120 u8 (*get_mr1)(struct uart_port *port);
121};
122
123/* setting the prescaler and divisor reg is common for all chips */
124static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
125 u16 prescaler, unsigned int divisor)
126{
127 /* select prescaler */
128 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
129 out_8(&psc->ctur, divisor >> 8);
130 out_8(&psc->ctlr, divisor & 0xff);
131}
132
133static u16 mpc52xx_psc_get_status(struct uart_port *port)
134{
135 return in_be16(&PSC(port)->mpc52xx_psc_status);
136}
137
138static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
139{
140 return in_8(&PSC(port)->mpc52xx_psc_ipcr);
141}
142
143static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
144{
145 out_8(&PSC(port)->command, cmd);
146}
147
148static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
149{
150 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
151 out_8(&PSC(port)->mode, mr1);
152 out_8(&PSC(port)->mode, mr2);
153}
154
155static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
156{
157 if (state)
158 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
159 else
160 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
161}
162
163static void mpc52xx_psc_enable_ms(struct uart_port *port)
164{
165 struct mpc52xx_psc __iomem *psc = PSC(port);
166
167 /* clear D_*-bits by reading them */
168 in_8(&psc->mpc52xx_psc_ipcr);
169 /* enable CTS and DCD as IPC interrupts */
170 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
171
172 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
173 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
174}
175
176static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
177{
178 out_be32(&PSC(port)->sicr, val);
179}
180
181static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
182{
183 out_be16(&PSC(port)->mpc52xx_psc_imr, val);
184}
185
186static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
187{
188 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
189 return in_8(&PSC(port)->mode);
190}
191
192#ifdef CONFIG_PPC_MPC52xx
193#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
194static void mpc52xx_psc_fifo_init(struct uart_port *port)
195{
196 struct mpc52xx_psc __iomem *psc = PSC(port);
197 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
198
199 out_8(&fifo->rfcntl, 0x00);
200 out_be16(&fifo->rfalarm, 0x1ff);
201 out_8(&fifo->tfcntl, 0x07);
202 out_be16(&fifo->tfalarm, 0x80);
203
204 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
205 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
206}
207
208static unsigned int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
209{
210 return in_be16(&PSC(port)->mpc52xx_psc_status)
211 & MPC52xx_PSC_SR_RXRDY;
212}
213
214static unsigned int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
215{
216 return in_be16(&PSC(port)->mpc52xx_psc_status)
217 & MPC52xx_PSC_SR_TXRDY;
218}
219
220
221static unsigned int mpc52xx_psc_rx_rdy(struct uart_port *port)
222{
223 return in_be16(&PSC(port)->mpc52xx_psc_isr)
224 & port->read_status_mask
225 & MPC52xx_PSC_IMR_RXRDY;
226}
227
228static unsigned int mpc52xx_psc_tx_rdy(struct uart_port *port)
229{
230 return in_be16(&PSC(port)->mpc52xx_psc_isr)
231 & port->read_status_mask
232 & MPC52xx_PSC_IMR_TXRDY;
233}
234
235static unsigned int mpc52xx_psc_tx_empty(struct uart_port *port)
236{
237 u16 sts = in_be16(&PSC(port)->mpc52xx_psc_status);
238
239 return (sts & MPC52xx_PSC_SR_TXEMP) ? TIOCSER_TEMT : 0;
240}
241
242static void mpc52xx_psc_start_tx(struct uart_port *port)
243{
244 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
245 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
246}
247
248static void mpc52xx_psc_stop_tx(struct uart_port *port)
249{
250 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
251 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
252}
253
254static void mpc52xx_psc_stop_rx(struct uart_port *port)
255{
256 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
257 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
258}
259
260static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
261{
262}
263
264static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
265{
266}
267
268static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
269{
270 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
271}
272
273static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
274{
275 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
276}
277
278static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
279{
280 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
281}
282
283static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
284{
285 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
286}
287
288static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
289 struct ktermios *new,
290 const struct ktermios *old)
291{
292 unsigned int baud;
293 unsigned int divisor;
294
295 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
296 baud = uart_get_baud_rate(port, new, old,
297 port->uartclk / (32 * 0xffff) + 1,
298 port->uartclk / 32);
299 divisor = (port->uartclk + 16 * baud) / (32 * baud);
300
301 /* enable the /32 prescaler and set the divisor */
302 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
303 return baud;
304}
305
306static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
307 struct ktermios *new,
308 const struct ktermios *old)
309{
310 unsigned int baud;
311 unsigned int divisor;
312 u16 prescaler;
313
314 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
315 * ipb freq */
316 baud = uart_get_baud_rate(port, new, old,
317 port->uartclk / (32 * 0xffff) + 1,
318 port->uartclk / 4);
319 divisor = (port->uartclk + 2 * baud) / (4 * baud);
320
321 /* select the proper prescaler and set the divisor
322 * prefer high prescaler for more tolerance on low baudrates */
323 if (divisor > 0xffff || baud <= 115200) {
324 divisor = (divisor + 4) / 8;
325 prescaler = 0xdd00; /* /32 */
326 } else
327 prescaler = 0xff00; /* /4 */
328 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
329 return baud;
330}
331
332static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
333{
334 port->irqflags = 0;
335 port->irq = irq_of_parse_and_map(np, 0);
336}
337
338/* 52xx specific interrupt handler. The caller holds the port lock */
339static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
340{
341 return mpc5xxx_uart_process_int(port);
342}
343
344static const struct psc_ops mpc52xx_psc_ops = {
345 .fifo_init = mpc52xx_psc_fifo_init,
346 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
347 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
348 .rx_rdy = mpc52xx_psc_rx_rdy,
349 .tx_rdy = mpc52xx_psc_tx_rdy,
350 .tx_empty = mpc52xx_psc_tx_empty,
351 .stop_rx = mpc52xx_psc_stop_rx,
352 .start_tx = mpc52xx_psc_start_tx,
353 .stop_tx = mpc52xx_psc_stop_tx,
354 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
355 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
356 .write_char = mpc52xx_psc_write_char,
357 .read_char = mpc52xx_psc_read_char,
358 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
359 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
360 .set_baudrate = mpc5200_psc_set_baudrate,
361 .get_irq = mpc52xx_psc_get_irq,
362 .handle_irq = mpc52xx_psc_handle_irq,
363 .get_status = mpc52xx_psc_get_status,
364 .get_ipcr = mpc52xx_psc_get_ipcr,
365 .command = mpc52xx_psc_command,
366 .set_mode = mpc52xx_psc_set_mode,
367 .set_rts = mpc52xx_psc_set_rts,
368 .enable_ms = mpc52xx_psc_enable_ms,
369 .set_sicr = mpc52xx_psc_set_sicr,
370 .set_imr = mpc52xx_psc_set_imr,
371 .get_mr1 = mpc52xx_psc_get_mr1,
372};
373
374static const struct psc_ops mpc5200b_psc_ops = {
375 .fifo_init = mpc52xx_psc_fifo_init,
376 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
377 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
378 .rx_rdy = mpc52xx_psc_rx_rdy,
379 .tx_rdy = mpc52xx_psc_tx_rdy,
380 .tx_empty = mpc52xx_psc_tx_empty,
381 .stop_rx = mpc52xx_psc_stop_rx,
382 .start_tx = mpc52xx_psc_start_tx,
383 .stop_tx = mpc52xx_psc_stop_tx,
384 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
385 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
386 .write_char = mpc52xx_psc_write_char,
387 .read_char = mpc52xx_psc_read_char,
388 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
389 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
390 .set_baudrate = mpc5200b_psc_set_baudrate,
391 .get_irq = mpc52xx_psc_get_irq,
392 .handle_irq = mpc52xx_psc_handle_irq,
393 .get_status = mpc52xx_psc_get_status,
394 .get_ipcr = mpc52xx_psc_get_ipcr,
395 .command = mpc52xx_psc_command,
396 .set_mode = mpc52xx_psc_set_mode,
397 .set_rts = mpc52xx_psc_set_rts,
398 .enable_ms = mpc52xx_psc_enable_ms,
399 .set_sicr = mpc52xx_psc_set_sicr,
400 .set_imr = mpc52xx_psc_set_imr,
401 .get_mr1 = mpc52xx_psc_get_mr1,
402};
403
404#endif /* CONFIG_PPC_MPC52xx */
405
406#ifdef CONFIG_PPC_MPC512x
407#define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
408
409/* PSC FIFO Controller for mpc512x */
410struct psc_fifoc {
411 u32 fifoc_cmd;
412 u32 fifoc_int;
413 u32 fifoc_dma;
414 u32 fifoc_axe;
415 u32 fifoc_debug;
416};
417
418static struct psc_fifoc __iomem *psc_fifoc;
419static unsigned int psc_fifoc_irq;
420static struct clk *psc_fifoc_clk;
421
422static void mpc512x_psc_fifo_init(struct uart_port *port)
423{
424 /* /32 prescaler */
425 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
426
427 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
428 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
429 out_be32(&FIFO_512x(port)->txalarm, 1);
430 out_be32(&FIFO_512x(port)->tximr, 0);
431
432 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
433 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
434 out_be32(&FIFO_512x(port)->rxalarm, 1);
435 out_be32(&FIFO_512x(port)->rximr, 0);
436
437 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
438 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
439}
440
441static unsigned int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
442{
443 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
444}
445
446static unsigned int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
447{
448 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
449}
450
451static unsigned int mpc512x_psc_rx_rdy(struct uart_port *port)
452{
453 return in_be32(&FIFO_512x(port)->rxsr)
454 & in_be32(&FIFO_512x(port)->rximr)
455 & MPC512x_PSC_FIFO_ALARM;
456}
457
458static unsigned int mpc512x_psc_tx_rdy(struct uart_port *port)
459{
460 return in_be32(&FIFO_512x(port)->txsr)
461 & in_be32(&FIFO_512x(port)->tximr)
462 & MPC512x_PSC_FIFO_ALARM;
463}
464
465static unsigned int mpc512x_psc_tx_empty(struct uart_port *port)
466{
467 return in_be32(&FIFO_512x(port)->txsr)
468 & MPC512x_PSC_FIFO_EMPTY;
469}
470
471static void mpc512x_psc_stop_rx(struct uart_port *port)
472{
473 unsigned long rx_fifo_imr;
474
475 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
476 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
477 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
478}
479
480static void mpc512x_psc_start_tx(struct uart_port *port)
481{
482 unsigned long tx_fifo_imr;
483
484 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
485 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
486 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
487}
488
489static void mpc512x_psc_stop_tx(struct uart_port *port)
490{
491 unsigned long tx_fifo_imr;
492
493 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
494 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
495 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
496}
497
498static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
499{
500 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
501}
502
503static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
504{
505 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
506}
507
508static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
509{
510 out_8(&FIFO_512x(port)->txdata_8, c);
511}
512
513static unsigned char mpc512x_psc_read_char(struct uart_port *port)
514{
515 return in_8(&FIFO_512x(port)->rxdata_8);
516}
517
518static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
519{
520 port->read_status_mask =
521 in_be32(&FIFO_512x(port)->tximr) << 16 |
522 in_be32(&FIFO_512x(port)->rximr);
523 out_be32(&FIFO_512x(port)->tximr, 0);
524 out_be32(&FIFO_512x(port)->rximr, 0);
525}
526
527static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
528{
529 out_be32(&FIFO_512x(port)->tximr,
530 (port->read_status_mask >> 16) & 0x7f);
531 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
532}
533
534static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
535 struct ktermios *new,
536 const struct ktermios *old)
537{
538 unsigned int baud;
539 unsigned int divisor;
540
541 /*
542 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
543 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
544 * Furthermore, it states that "After reset, the prescaler by 10
545 * for the UART mode is selected", but the reset register value is
546 * 0x0000 which means a /32 prescaler. This is wrong.
547 *
548 * In reality using /32 prescaler doesn't work, as it is not supported!
549 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
550 * Chapter 4.1 PSC in UART Mode.
551 * Calculate with a /16 prescaler here.
552 */
553
554 /* uartclk contains the ips freq */
555 baud = uart_get_baud_rate(port, new, old,
556 port->uartclk / (16 * 0xffff) + 1,
557 port->uartclk / 16);
558 divisor = (port->uartclk + 8 * baud) / (16 * baud);
559
560 /* enable the /16 prescaler and set the divisor */
561 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
562 return baud;
563}
564
565/* Init PSC FIFO Controller */
566static int __init mpc512x_psc_fifoc_init(void)
567{
568 int err;
569 struct device_node *np;
570 struct clk *clk;
571
572 /* default error code, potentially overwritten by clock calls */
573 err = -ENODEV;
574
575 np = of_find_compatible_node(NULL, NULL,
576 "fsl,mpc5121-psc-fifo");
577 if (!np) {
578 pr_err("%s: Can't find FIFOC node\n", __func__);
579 goto out_err;
580 }
581
582 clk = of_clk_get(np, 0);
583 if (IS_ERR(clk)) {
584 /* backwards compat with device trees that lack clock specs */
585 clk = clk_get_sys(np->name, "ipg");
586 }
587 if (IS_ERR(clk)) {
588 pr_err("%s: Can't lookup FIFO clock\n", __func__);
589 err = PTR_ERR(clk);
590 goto out_ofnode_put;
591 }
592 if (clk_prepare_enable(clk)) {
593 pr_err("%s: Can't enable FIFO clock\n", __func__);
594 clk_put(clk);
595 goto out_ofnode_put;
596 }
597 psc_fifoc_clk = clk;
598
599 psc_fifoc = of_iomap(np, 0);
600 if (!psc_fifoc) {
601 pr_err("%s: Can't map FIFOC\n", __func__);
602 goto out_clk_disable;
603 }
604
605 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
606 if (psc_fifoc_irq == 0) {
607 pr_err("%s: Can't get FIFOC irq\n", __func__);
608 goto out_unmap;
609 }
610
611 of_node_put(np);
612 return 0;
613
614out_unmap:
615 iounmap(psc_fifoc);
616out_clk_disable:
617 clk_disable_unprepare(psc_fifoc_clk);
618 clk_put(psc_fifoc_clk);
619out_ofnode_put:
620 of_node_put(np);
621out_err:
622 return err;
623}
624
625static void __exit mpc512x_psc_fifoc_uninit(void)
626{
627 iounmap(psc_fifoc);
628
629 /* disable the clock, errors are not fatal */
630 if (psc_fifoc_clk) {
631 clk_disable_unprepare(psc_fifoc_clk);
632 clk_put(psc_fifoc_clk);
633 psc_fifoc_clk = NULL;
634 }
635}
636
637/* 512x specific interrupt handler. The caller holds the port lock */
638static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
639{
640 unsigned long fifoc_int;
641 int psc_num;
642
643 /* Read pending PSC FIFOC interrupts */
644 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
645
646 /* Check if it is an interrupt for this port */
647 psc_num = (port->mapbase & 0xf00) >> 8;
648 if (test_bit(psc_num, &fifoc_int) ||
649 test_bit(psc_num + 16, &fifoc_int))
650 return mpc5xxx_uart_process_int(port);
651
652 return IRQ_NONE;
653}
654
655static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
656static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM];
657
658/* called from within the .request_port() callback (allocation) */
659static int mpc512x_psc_alloc_clock(struct uart_port *port)
660{
661 int psc_num;
662 struct clk *clk;
663 int err;
664
665 psc_num = (port->mapbase & 0xf00) >> 8;
666
667 clk = devm_clk_get(port->dev, "mclk");
668 if (IS_ERR(clk)) {
669 dev_err(port->dev, "Failed to get MCLK!\n");
670 err = PTR_ERR(clk);
671 goto out_err;
672 }
673 err = clk_prepare_enable(clk);
674 if (err) {
675 dev_err(port->dev, "Failed to enable MCLK!\n");
676 goto out_err;
677 }
678 psc_mclk_clk[psc_num] = clk;
679
680 clk = devm_clk_get(port->dev, "ipg");
681 if (IS_ERR(clk)) {
682 dev_err(port->dev, "Failed to get IPG clock!\n");
683 err = PTR_ERR(clk);
684 goto out_err;
685 }
686 err = clk_prepare_enable(clk);
687 if (err) {
688 dev_err(port->dev, "Failed to enable IPG clock!\n");
689 goto out_err;
690 }
691 psc_ipg_clk[psc_num] = clk;
692
693 return 0;
694
695out_err:
696 if (psc_mclk_clk[psc_num]) {
697 clk_disable_unprepare(psc_mclk_clk[psc_num]);
698 psc_mclk_clk[psc_num] = NULL;
699 }
700 if (psc_ipg_clk[psc_num]) {
701 clk_disable_unprepare(psc_ipg_clk[psc_num]);
702 psc_ipg_clk[psc_num] = NULL;
703 }
704 return err;
705}
706
707/* called from within the .release_port() callback (release) */
708static void mpc512x_psc_relse_clock(struct uart_port *port)
709{
710 int psc_num;
711 struct clk *clk;
712
713 psc_num = (port->mapbase & 0xf00) >> 8;
714 clk = psc_mclk_clk[psc_num];
715 if (clk) {
716 clk_disable_unprepare(clk);
717 psc_mclk_clk[psc_num] = NULL;
718 }
719 if (psc_ipg_clk[psc_num]) {
720 clk_disable_unprepare(psc_ipg_clk[psc_num]);
721 psc_ipg_clk[psc_num] = NULL;
722 }
723}
724
725/* implementation of the .clock() callback (enable/disable) */
726static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
727{
728 int psc_num;
729 struct clk *psc_clk;
730 int ret;
731
732 if (uart_console(port))
733 return 0;
734
735 psc_num = (port->mapbase & 0xf00) >> 8;
736 psc_clk = psc_mclk_clk[psc_num];
737 if (!psc_clk) {
738 dev_err(port->dev, "Failed to get PSC clock entry!\n");
739 return -ENODEV;
740 }
741
742 dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
743 if (enable) {
744 ret = clk_enable(psc_clk);
745 if (ret)
746 dev_err(port->dev, "Failed to enable MCLK!\n");
747 return ret;
748 } else {
749 clk_disable(psc_clk);
750 return 0;
751 }
752}
753
754static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
755{
756 port->irqflags = IRQF_SHARED;
757 port->irq = psc_fifoc_irq;
758}
759
760#define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
761#define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
762
763static void mpc5125_psc_fifo_init(struct uart_port *port)
764{
765 /* /32 prescaler */
766 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
767
768 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
769 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
770 out_be32(&FIFO_5125(port)->txalarm, 1);
771 out_be32(&FIFO_5125(port)->tximr, 0);
772
773 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
774 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
775 out_be32(&FIFO_5125(port)->rxalarm, 1);
776 out_be32(&FIFO_5125(port)->rximr, 0);
777
778 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
779 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
780}
781
782static unsigned int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
783{
784 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
785}
786
787static unsigned int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
788{
789 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
790}
791
792static unsigned int mpc5125_psc_rx_rdy(struct uart_port *port)
793{
794 return in_be32(&FIFO_5125(port)->rxsr) &
795 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
796}
797
798static unsigned int mpc5125_psc_tx_rdy(struct uart_port *port)
799{
800 return in_be32(&FIFO_5125(port)->txsr) &
801 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
802}
803
804static unsigned int mpc5125_psc_tx_empty(struct uart_port *port)
805{
806 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
807}
808
809static void mpc5125_psc_stop_rx(struct uart_port *port)
810{
811 unsigned long rx_fifo_imr;
812
813 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
814 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
815 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
816}
817
818static void mpc5125_psc_start_tx(struct uart_port *port)
819{
820 unsigned long tx_fifo_imr;
821
822 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
823 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
824 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
825}
826
827static void mpc5125_psc_stop_tx(struct uart_port *port)
828{
829 unsigned long tx_fifo_imr;
830
831 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
832 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
833 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
834}
835
836static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
837{
838 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
839}
840
841static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
842{
843 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
844}
845
846static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
847{
848 out_8(&FIFO_5125(port)->txdata_8, c);
849}
850
851static unsigned char mpc5125_psc_read_char(struct uart_port *port)
852{
853 return in_8(&FIFO_5125(port)->rxdata_8);
854}
855
856static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
857{
858 port->read_status_mask =
859 in_be32(&FIFO_5125(port)->tximr) << 16 |
860 in_be32(&FIFO_5125(port)->rximr);
861 out_be32(&FIFO_5125(port)->tximr, 0);
862 out_be32(&FIFO_5125(port)->rximr, 0);
863}
864
865static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
866{
867 out_be32(&FIFO_5125(port)->tximr,
868 (port->read_status_mask >> 16) & 0x7f);
869 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
870}
871
872static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
873 u8 prescaler, unsigned int divisor)
874{
875 /* select prescaler */
876 out_8(&psc->mpc52xx_psc_clock_select, prescaler);
877 out_8(&psc->ctur, divisor >> 8);
878 out_8(&psc->ctlr, divisor & 0xff);
879}
880
881static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
882 struct ktermios *new,
883 const struct ktermios *old)
884{
885 unsigned int baud;
886 unsigned int divisor;
887
888 /*
889 * Calculate with a /16 prescaler here.
890 */
891
892 /* uartclk contains the ips freq */
893 baud = uart_get_baud_rate(port, new, old,
894 port->uartclk / (16 * 0xffff) + 1,
895 port->uartclk / 16);
896 divisor = (port->uartclk + 8 * baud) / (16 * baud);
897
898 /* enable the /16 prescaler and set the divisor */
899 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
900 return baud;
901}
902
903/*
904 * MPC5125 have compatible PSC FIFO Controller.
905 * Special init not needed.
906 */
907static u16 mpc5125_psc_get_status(struct uart_port *port)
908{
909 return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
910}
911
912static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
913{
914 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
915}
916
917static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
918{
919 out_8(&PSC_5125(port)->command, cmd);
920}
921
922static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
923{
924 out_8(&PSC_5125(port)->mr1, mr1);
925 out_8(&PSC_5125(port)->mr2, mr2);
926}
927
928static void mpc5125_psc_set_rts(struct uart_port *port, int state)
929{
930 if (state & TIOCM_RTS)
931 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
932 else
933 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
934}
935
936static void mpc5125_psc_enable_ms(struct uart_port *port)
937{
938 struct mpc5125_psc __iomem *psc = PSC_5125(port);
939
940 /* clear D_*-bits by reading them */
941 in_8(&psc->mpc52xx_psc_ipcr);
942 /* enable CTS and DCD as IPC interrupts */
943 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
944
945 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
946 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
947}
948
949static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
950{
951 out_be32(&PSC_5125(port)->sicr, val);
952}
953
954static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
955{
956 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
957}
958
959static u8 mpc5125_psc_get_mr1(struct uart_port *port)
960{
961 return in_8(&PSC_5125(port)->mr1);
962}
963
964static const struct psc_ops mpc5125_psc_ops = {
965 .fifo_init = mpc5125_psc_fifo_init,
966 .raw_rx_rdy = mpc5125_psc_raw_rx_rdy,
967 .raw_tx_rdy = mpc5125_psc_raw_tx_rdy,
968 .rx_rdy = mpc5125_psc_rx_rdy,
969 .tx_rdy = mpc5125_psc_tx_rdy,
970 .tx_empty = mpc5125_psc_tx_empty,
971 .stop_rx = mpc5125_psc_stop_rx,
972 .start_tx = mpc5125_psc_start_tx,
973 .stop_tx = mpc5125_psc_stop_tx,
974 .rx_clr_irq = mpc5125_psc_rx_clr_irq,
975 .tx_clr_irq = mpc5125_psc_tx_clr_irq,
976 .write_char = mpc5125_psc_write_char,
977 .read_char = mpc5125_psc_read_char,
978 .cw_disable_ints = mpc5125_psc_cw_disable_ints,
979 .cw_restore_ints = mpc5125_psc_cw_restore_ints,
980 .set_baudrate = mpc5125_psc_set_baudrate,
981 .clock_alloc = mpc512x_psc_alloc_clock,
982 .clock_relse = mpc512x_psc_relse_clock,
983 .clock = mpc512x_psc_endis_clock,
984 .fifoc_init = mpc512x_psc_fifoc_init,
985 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
986 .get_irq = mpc512x_psc_get_irq,
987 .handle_irq = mpc512x_psc_handle_irq,
988 .get_status = mpc5125_psc_get_status,
989 .get_ipcr = mpc5125_psc_get_ipcr,
990 .command = mpc5125_psc_command,
991 .set_mode = mpc5125_psc_set_mode,
992 .set_rts = mpc5125_psc_set_rts,
993 .enable_ms = mpc5125_psc_enable_ms,
994 .set_sicr = mpc5125_psc_set_sicr,
995 .set_imr = mpc5125_psc_set_imr,
996 .get_mr1 = mpc5125_psc_get_mr1,
997};
998
999static const struct psc_ops mpc512x_psc_ops = {
1000 .fifo_init = mpc512x_psc_fifo_init,
1001 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
1002 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
1003 .rx_rdy = mpc512x_psc_rx_rdy,
1004 .tx_rdy = mpc512x_psc_tx_rdy,
1005 .tx_empty = mpc512x_psc_tx_empty,
1006 .stop_rx = mpc512x_psc_stop_rx,
1007 .start_tx = mpc512x_psc_start_tx,
1008 .stop_tx = mpc512x_psc_stop_tx,
1009 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
1010 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
1011 .write_char = mpc512x_psc_write_char,
1012 .read_char = mpc512x_psc_read_char,
1013 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
1014 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
1015 .set_baudrate = mpc512x_psc_set_baudrate,
1016 .clock_alloc = mpc512x_psc_alloc_clock,
1017 .clock_relse = mpc512x_psc_relse_clock,
1018 .clock = mpc512x_psc_endis_clock,
1019 .fifoc_init = mpc512x_psc_fifoc_init,
1020 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
1021 .get_irq = mpc512x_psc_get_irq,
1022 .handle_irq = mpc512x_psc_handle_irq,
1023 .get_status = mpc52xx_psc_get_status,
1024 .get_ipcr = mpc52xx_psc_get_ipcr,
1025 .command = mpc52xx_psc_command,
1026 .set_mode = mpc52xx_psc_set_mode,
1027 .set_rts = mpc52xx_psc_set_rts,
1028 .enable_ms = mpc52xx_psc_enable_ms,
1029 .set_sicr = mpc52xx_psc_set_sicr,
1030 .set_imr = mpc52xx_psc_set_imr,
1031 .get_mr1 = mpc52xx_psc_get_mr1,
1032};
1033#endif /* CONFIG_PPC_MPC512x */
1034
1035
1036static const struct psc_ops *psc_ops;
1037
1038/* ======================================================================== */
1039/* UART operations */
1040/* ======================================================================== */
1041
1042static unsigned int
1043mpc52xx_uart_tx_empty(struct uart_port *port)
1044{
1045 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
1046}
1047
1048static void
1049mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1050{
1051 psc_ops->set_rts(port, mctrl & TIOCM_RTS);
1052}
1053
1054static unsigned int
1055mpc52xx_uart_get_mctrl(struct uart_port *port)
1056{
1057 unsigned int ret = TIOCM_DSR;
1058 u8 status = psc_ops->get_ipcr(port);
1059
1060 if (!(status & MPC52xx_PSC_CTS))
1061 ret |= TIOCM_CTS;
1062 if (!(status & MPC52xx_PSC_DCD))
1063 ret |= TIOCM_CAR;
1064
1065 return ret;
1066}
1067
1068static void
1069mpc52xx_uart_stop_tx(struct uart_port *port)
1070{
1071 /* port->lock taken by caller */
1072 psc_ops->stop_tx(port);
1073}
1074
1075static void
1076mpc52xx_uart_start_tx(struct uart_port *port)
1077{
1078 /* port->lock taken by caller */
1079 psc_ops->start_tx(port);
1080}
1081
1082static void
1083mpc52xx_uart_stop_rx(struct uart_port *port)
1084{
1085 /* port->lock taken by caller */
1086 psc_ops->stop_rx(port);
1087}
1088
1089static void
1090mpc52xx_uart_enable_ms(struct uart_port *port)
1091{
1092 psc_ops->enable_ms(port);
1093}
1094
1095static void
1096mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
1097{
1098 unsigned long flags;
1099 uart_port_lock_irqsave(port, &flags);
1100
1101 if (ctl == -1)
1102 psc_ops->command(port, MPC52xx_PSC_START_BRK);
1103 else
1104 psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
1105
1106 uart_port_unlock_irqrestore(port, flags);
1107}
1108
1109static int
1110mpc52xx_uart_startup(struct uart_port *port)
1111{
1112 int ret;
1113
1114 if (psc_ops->clock) {
1115 ret = psc_ops->clock(port, 1);
1116 if (ret)
1117 return ret;
1118 }
1119
1120 /* Request IRQ */
1121 ret = request_irq(port->irq, mpc52xx_uart_int,
1122 port->irqflags, "mpc52xx_psc_uart", port);
1123 if (ret)
1124 return ret;
1125
1126 /* Reset/activate the port, clear and enable interrupts */
1127 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1128 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1129
1130 /*
1131 * According to Freescale's support the RST_TX command can produce a
1132 * spike on the TX pin. So they recommend to delay "for one character".
1133 * One millisecond should be enough for everyone.
1134 */
1135 msleep(1);
1136
1137 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */
1138
1139 psc_ops->fifo_init(port);
1140
1141 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1142 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1143
1144 return 0;
1145}
1146
1147static void
1148mpc52xx_uart_shutdown(struct uart_port *port)
1149{
1150 /* Shut down the port. Leave TX active if on a console port */
1151 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1152 if (!uart_console(port))
1153 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1154
1155 port->read_status_mask = 0;
1156 psc_ops->set_imr(port, port->read_status_mask);
1157
1158 if (psc_ops->clock)
1159 psc_ops->clock(port, 0);
1160
1161 /* Disable interrupt */
1162 psc_ops->cw_disable_ints(port);
1163
1164 /* Release interrupt */
1165 free_irq(port->irq, port);
1166}
1167
1168static void
1169mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
1170 const struct ktermios *old)
1171{
1172 unsigned long flags;
1173 unsigned char mr1, mr2;
1174 unsigned int j;
1175 unsigned int baud;
1176
1177 /* Prepare what we're gonna write */
1178 mr1 = 0;
1179
1180 switch (new->c_cflag & CSIZE) {
1181 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
1182 break;
1183 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
1184 break;
1185 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
1186 break;
1187 case CS8:
1188 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
1189 }
1190
1191 if (new->c_cflag & PARENB) {
1192 if (new->c_cflag & CMSPAR)
1193 mr1 |= MPC52xx_PSC_MODE_PARFORCE;
1194
1195 /* With CMSPAR, PARODD also means high parity (same as termios) */
1196 mr1 |= (new->c_cflag & PARODD) ?
1197 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
1198 } else {
1199 mr1 |= MPC52xx_PSC_MODE_PARNONE;
1200 }
1201
1202 mr2 = 0;
1203
1204 if (new->c_cflag & CSTOPB)
1205 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
1206 else
1207 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
1208 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
1209 MPC52xx_PSC_MODE_ONE_STOP;
1210
1211 if (new->c_cflag & CRTSCTS) {
1212 mr1 |= MPC52xx_PSC_MODE_RXRTS;
1213 mr2 |= MPC52xx_PSC_MODE_TXCTS;
1214 }
1215
1216 /* Get the lock */
1217 uart_port_lock_irqsave(port, &flags);
1218
1219 /* Do our best to flush TX & RX, so we don't lose anything */
1220 /* But we don't wait indefinitely ! */
1221 j = 5000000; /* Maximum wait */
1222 /* FIXME Can't receive chars since set_termios might be called at early
1223 * boot for the console, all stuff is not yet ready to receive at that
1224 * time and that just makes the kernel oops */
1225 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
1226 while (!mpc52xx_uart_tx_empty(port) && --j)
1227 udelay(1);
1228
1229 if (!j)
1230 printk(KERN_ERR "mpc52xx_uart.c: "
1231 "Unable to flush RX & TX fifos in-time in set_termios."
1232 "Some chars may have been lost.\n");
1233
1234 /* Reset the TX & RX */
1235 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1236 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1237
1238 /* Send new mode settings */
1239 psc_ops->set_mode(port, mr1, mr2);
1240 baud = psc_ops->set_baudrate(port, new, old);
1241
1242 /* Update the per-port timeout */
1243 uart_update_timeout(port, new->c_cflag, baud);
1244
1245 if (UART_ENABLE_MS(port, new->c_cflag))
1246 mpc52xx_uart_enable_ms(port);
1247
1248 /* Reenable TX & RX */
1249 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1250 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1251
1252 /* We're all set, release the lock */
1253 uart_port_unlock_irqrestore(port, flags);
1254}
1255
1256static const char *
1257mpc52xx_uart_type(struct uart_port *port)
1258{
1259 /*
1260 * We keep using PORT_MPC52xx for historic reasons although it applies
1261 * for MPC512x, too, but print "MPC5xxx" to not irritate users
1262 */
1263 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1264}
1265
1266static void
1267mpc52xx_uart_release_port(struct uart_port *port)
1268{
1269 if (psc_ops->clock_relse)
1270 psc_ops->clock_relse(port);
1271
1272 /* remapped by us ? */
1273 if (port->flags & UPF_IOREMAP) {
1274 iounmap(port->membase);
1275 port->membase = NULL;
1276 }
1277
1278 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1279}
1280
1281static int
1282mpc52xx_uart_request_port(struct uart_port *port)
1283{
1284 int err;
1285
1286 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
1287 port->membase = ioremap(port->mapbase,
1288 sizeof(struct mpc52xx_psc));
1289
1290 if (!port->membase)
1291 return -EINVAL;
1292
1293 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
1294 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
1295
1296 if (err)
1297 goto out_membase;
1298
1299 if (psc_ops->clock_alloc) {
1300 err = psc_ops->clock_alloc(port);
1301 if (err)
1302 goto out_mapregion;
1303 }
1304
1305 return 0;
1306
1307out_mapregion:
1308 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1309out_membase:
1310 if (port->flags & UPF_IOREMAP) {
1311 iounmap(port->membase);
1312 port->membase = NULL;
1313 }
1314 return err;
1315}
1316
1317static void
1318mpc52xx_uart_config_port(struct uart_port *port, int flags)
1319{
1320 if ((flags & UART_CONFIG_TYPE)
1321 && (mpc52xx_uart_request_port(port) == 0))
1322 port->type = PORT_MPC52xx;
1323}
1324
1325static int
1326mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1327{
1328 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
1329 return -EINVAL;
1330
1331 if ((ser->irq != port->irq) ||
1332 (ser->io_type != UPIO_MEM) ||
1333 (ser->baud_base != port->uartclk) ||
1334 (ser->iomem_base != (void *)port->mapbase) ||
1335 (ser->hub6 != 0))
1336 return -EINVAL;
1337
1338 return 0;
1339}
1340
1341
1342static const struct uart_ops mpc52xx_uart_ops = {
1343 .tx_empty = mpc52xx_uart_tx_empty,
1344 .set_mctrl = mpc52xx_uart_set_mctrl,
1345 .get_mctrl = mpc52xx_uart_get_mctrl,
1346 .stop_tx = mpc52xx_uart_stop_tx,
1347 .start_tx = mpc52xx_uart_start_tx,
1348 .stop_rx = mpc52xx_uart_stop_rx,
1349 .enable_ms = mpc52xx_uart_enable_ms,
1350 .break_ctl = mpc52xx_uart_break_ctl,
1351 .startup = mpc52xx_uart_startup,
1352 .shutdown = mpc52xx_uart_shutdown,
1353 .set_termios = mpc52xx_uart_set_termios,
1354/* .pm = mpc52xx_uart_pm, Not supported yet */
1355 .type = mpc52xx_uart_type,
1356 .release_port = mpc52xx_uart_release_port,
1357 .request_port = mpc52xx_uart_request_port,
1358 .config_port = mpc52xx_uart_config_port,
1359 .verify_port = mpc52xx_uart_verify_port
1360};
1361
1362
1363/* ======================================================================== */
1364/* Interrupt handling */
1365/* ======================================================================== */
1366
1367static inline bool
1368mpc52xx_uart_int_rx_chars(struct uart_port *port)
1369{
1370 struct tty_port *tport = &port->state->port;
1371 unsigned char ch, flag;
1372 unsigned short status;
1373
1374 /* While we can read, do so ! */
1375 while (psc_ops->raw_rx_rdy(port)) {
1376 /* Get the char */
1377 ch = psc_ops->read_char(port);
1378
1379 /* Handle sysreq char */
1380 if (uart_handle_sysrq_char(port, ch))
1381 continue;
1382
1383 /* Store it */
1384
1385 flag = TTY_NORMAL;
1386 port->icount.rx++;
1387
1388 status = psc_ops->get_status(port);
1389
1390 if (status & (MPC52xx_PSC_SR_PE |
1391 MPC52xx_PSC_SR_FE |
1392 MPC52xx_PSC_SR_RB)) {
1393
1394 if (status & MPC52xx_PSC_SR_RB) {
1395 flag = TTY_BREAK;
1396 uart_handle_break(port);
1397 port->icount.brk++;
1398 } else if (status & MPC52xx_PSC_SR_PE) {
1399 flag = TTY_PARITY;
1400 port->icount.parity++;
1401 }
1402 else if (status & MPC52xx_PSC_SR_FE) {
1403 flag = TTY_FRAME;
1404 port->icount.frame++;
1405 }
1406
1407 /* Clear error condition */
1408 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
1409
1410 }
1411 tty_insert_flip_char(tport, ch, flag);
1412 if (status & MPC52xx_PSC_SR_OE) {
1413 /*
1414 * Overrun is special, since it's
1415 * reported immediately, and doesn't
1416 * affect the current character
1417 */
1418 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1419 port->icount.overrun++;
1420 }
1421 }
1422
1423 tty_flip_buffer_push(tport);
1424
1425 return psc_ops->raw_rx_rdy(port);
1426}
1427
1428static inline bool
1429mpc52xx_uart_int_tx_chars(struct uart_port *port)
1430{
1431 u8 ch;
1432
1433 return uart_port_tx(port, ch,
1434 psc_ops->raw_tx_rdy(port),
1435 psc_ops->write_char(port, ch));
1436}
1437
1438static irqreturn_t
1439mpc5xxx_uart_process_int(struct uart_port *port)
1440{
1441 unsigned long pass = ISR_PASS_LIMIT;
1442 bool keepgoing;
1443 u8 status;
1444
1445 /* While we have stuff to do, we continue */
1446 do {
1447 /* If we don't find anything to do, we stop */
1448 keepgoing = false;
1449
1450 psc_ops->rx_clr_irq(port);
1451 if (psc_ops->rx_rdy(port))
1452 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1453
1454 psc_ops->tx_clr_irq(port);
1455 if (psc_ops->tx_rdy(port))
1456 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1457
1458 status = psc_ops->get_ipcr(port);
1459 if (status & MPC52xx_PSC_D_DCD)
1460 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1461
1462 if (status & MPC52xx_PSC_D_CTS)
1463 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1464
1465 /* Limit number of iteration */
1466 if (!(--pass))
1467 keepgoing = false;
1468
1469 } while (keepgoing);
1470
1471 return IRQ_HANDLED;
1472}
1473
1474static irqreturn_t
1475mpc52xx_uart_int(int irq, void *dev_id)
1476{
1477 struct uart_port *port = dev_id;
1478 irqreturn_t ret;
1479
1480 uart_port_lock(port);
1481
1482 ret = psc_ops->handle_irq(port);
1483
1484 uart_port_unlock(port);
1485
1486 return ret;
1487}
1488
1489/* ======================================================================== */
1490/* Console ( if applicable ) */
1491/* ======================================================================== */
1492
1493#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1494
1495static void __init
1496mpc52xx_console_get_options(struct uart_port *port,
1497 int *baud, int *parity, int *bits, int *flow)
1498{
1499 unsigned char mr1;
1500
1501 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1502
1503 /* Read the mode registers */
1504 mr1 = psc_ops->get_mr1(port);
1505
1506 /* CT{U,L}R are write-only ! */
1507 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1508
1509 /* Parse them */
1510 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1511 case MPC52xx_PSC_MODE_5_BITS:
1512 *bits = 5;
1513 break;
1514 case MPC52xx_PSC_MODE_6_BITS:
1515 *bits = 6;
1516 break;
1517 case MPC52xx_PSC_MODE_7_BITS:
1518 *bits = 7;
1519 break;
1520 case MPC52xx_PSC_MODE_8_BITS:
1521 default:
1522 *bits = 8;
1523 }
1524
1525 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1526 *parity = 'n';
1527 else
1528 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1529}
1530
1531static void
1532mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1533{
1534 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1535 unsigned int i, j;
1536
1537 /* Disable interrupts */
1538 psc_ops->cw_disable_ints(port);
1539
1540 /* Wait the TX buffer to be empty */
1541 j = 5000000; /* Maximum wait */
1542 while (!mpc52xx_uart_tx_empty(port) && --j)
1543 udelay(1);
1544
1545 /* Write all the chars */
1546 for (i = 0; i < count; i++, s++) {
1547 /* Line return handling */
1548 if (*s == '\n')
1549 psc_ops->write_char(port, '\r');
1550
1551 /* Send the char */
1552 psc_ops->write_char(port, *s);
1553
1554 /* Wait the TX buffer to be empty */
1555 j = 20000; /* Maximum wait */
1556 while (!mpc52xx_uart_tx_empty(port) && --j)
1557 udelay(1);
1558 }
1559
1560 /* Restore interrupt state */
1561 psc_ops->cw_restore_ints(port);
1562}
1563
1564
1565static int __init
1566mpc52xx_console_setup(struct console *co, char *options)
1567{
1568 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1569 struct device_node *np = mpc52xx_uart_nodes[co->index];
1570 unsigned int uartclk;
1571 struct resource res;
1572 int ret;
1573
1574 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1575 int bits = 8;
1576 int parity = 'n';
1577 int flow = 'n';
1578
1579 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1580 co, co->index, options);
1581
1582 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1583 pr_debug("PSC%x out of range\n", co->index);
1584 return -EINVAL;
1585 }
1586
1587 if (!np) {
1588 pr_debug("PSC%x not found in device tree\n", co->index);
1589 return -EINVAL;
1590 }
1591
1592 pr_debug("Console on ttyPSC%x is %pOF\n",
1593 co->index, mpc52xx_uart_nodes[co->index]);
1594
1595 /* Fetch register locations */
1596 ret = of_address_to_resource(np, 0, &res);
1597 if (ret) {
1598 pr_debug("Could not get resources for PSC%x\n", co->index);
1599 return ret;
1600 }
1601
1602 uartclk = mpc5xxx_fwnode_get_bus_frequency(of_fwnode_handle(np));
1603 if (uartclk == 0) {
1604 pr_debug("Could not find uart clock frequency!\n");
1605 return -EINVAL;
1606 }
1607
1608 /* Basic port init. Needed since we use some uart_??? func before
1609 * real init for early access */
1610 spin_lock_init(&port->lock);
1611 port->uartclk = uartclk;
1612 port->ops = &mpc52xx_uart_ops;
1613 port->mapbase = res.start;
1614 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1615 port->irq = irq_of_parse_and_map(np, 0);
1616
1617 if (port->membase == NULL)
1618 return -EINVAL;
1619
1620 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1621 (void *)port->mapbase, port->membase,
1622 port->irq, port->uartclk);
1623
1624 /* Setup the port parameters accoding to options */
1625 if (options)
1626 uart_parse_options(options, &baud, &parity, &bits, &flow);
1627 else
1628 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1629
1630 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1631 baud, bits, parity, flow);
1632
1633 return uart_set_options(port, co, baud, parity, bits, flow);
1634}
1635
1636
1637static struct uart_driver mpc52xx_uart_driver;
1638
1639static struct console mpc52xx_console = {
1640 .name = "ttyPSC",
1641 .write = mpc52xx_console_write,
1642 .device = uart_console_device,
1643 .setup = mpc52xx_console_setup,
1644 .flags = CON_PRINTBUFFER,
1645 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1646 .data = &mpc52xx_uart_driver,
1647};
1648
1649
1650static int __init
1651mpc52xx_console_init(void)
1652{
1653 mpc52xx_uart_of_enumerate();
1654 register_console(&mpc52xx_console);
1655 return 0;
1656}
1657
1658console_initcall(mpc52xx_console_init);
1659
1660#define MPC52xx_PSC_CONSOLE &mpc52xx_console
1661#else
1662#define MPC52xx_PSC_CONSOLE NULL
1663#endif
1664
1665
1666/* ======================================================================== */
1667/* UART Driver */
1668/* ======================================================================== */
1669
1670static struct uart_driver mpc52xx_uart_driver = {
1671 .driver_name = "mpc52xx_psc_uart",
1672 .dev_name = "ttyPSC",
1673 .major = SERIAL_PSC_MAJOR,
1674 .minor = SERIAL_PSC_MINOR,
1675 .nr = MPC52xx_PSC_MAXNUM,
1676 .cons = MPC52xx_PSC_CONSOLE,
1677};
1678
1679/* ======================================================================== */
1680/* OF Platform Driver */
1681/* ======================================================================== */
1682
1683static const struct of_device_id mpc52xx_uart_of_match[] = {
1684#ifdef CONFIG_PPC_MPC52xx
1685 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1686 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1687 /* binding used by old lite5200 device trees: */
1688 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1689 /* binding used by efika: */
1690 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1691#endif
1692#ifdef CONFIG_PPC_MPC512x
1693 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1694 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
1695#endif
1696 {},
1697};
1698
1699static int mpc52xx_uart_of_probe(struct platform_device *op)
1700{
1701 int idx = -1;
1702 unsigned int uartclk;
1703 struct uart_port *port = NULL;
1704 struct resource res;
1705 int ret;
1706
1707 /* Check validity & presence */
1708 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1709 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1710 break;
1711 if (idx >= MPC52xx_PSC_MAXNUM)
1712 return -EINVAL;
1713 pr_debug("Found %pOF assigned to ttyPSC%x\n",
1714 mpc52xx_uart_nodes[idx], idx);
1715
1716 /* set the uart clock to the input clock of the psc, the different
1717 * prescalers are taken into account in the set_baudrate() methods
1718 * of the respective chip */
1719 uartclk = mpc5xxx_get_bus_frequency(&op->dev);
1720 if (uartclk == 0) {
1721 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1722 return -EINVAL;
1723 }
1724
1725 /* Init the port structure */
1726 port = &mpc52xx_uart_ports[idx];
1727
1728 spin_lock_init(&port->lock);
1729 port->uartclk = uartclk;
1730 port->fifosize = 512;
1731 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MPC52xx_CONSOLE);
1732 port->iotype = UPIO_MEM;
1733 port->flags = UPF_BOOT_AUTOCONF |
1734 (uart_console(port) ? 0 : UPF_IOREMAP);
1735 port->line = idx;
1736 port->ops = &mpc52xx_uart_ops;
1737 port->dev = &op->dev;
1738
1739 /* Search for IRQ and mapbase */
1740 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1741 if (ret)
1742 return ret;
1743
1744 port->mapbase = res.start;
1745 if (!port->mapbase) {
1746 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1747 return -EINVAL;
1748 }
1749
1750 psc_ops->get_irq(port, op->dev.of_node);
1751 if (port->irq == 0) {
1752 dev_dbg(&op->dev, "Could not get irq\n");
1753 return -EINVAL;
1754 }
1755
1756 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1757 (void *)port->mapbase, port->irq, port->uartclk);
1758
1759 /* Add the port to the uart sub-system */
1760 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1761 if (ret)
1762 return ret;
1763
1764 platform_set_drvdata(op, (void *)port);
1765 return 0;
1766}
1767
1768static void mpc52xx_uart_of_remove(struct platform_device *op)
1769{
1770 struct uart_port *port = platform_get_drvdata(op);
1771
1772 if (port)
1773 uart_remove_one_port(&mpc52xx_uart_driver, port);
1774}
1775
1776#ifdef CONFIG_PM
1777static int
1778mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1779{
1780 struct uart_port *port = platform_get_drvdata(op);
1781
1782 if (port)
1783 uart_suspend_port(&mpc52xx_uart_driver, port);
1784
1785 return 0;
1786}
1787
1788static int
1789mpc52xx_uart_of_resume(struct platform_device *op)
1790{
1791 struct uart_port *port = platform_get_drvdata(op);
1792
1793 if (port)
1794 uart_resume_port(&mpc52xx_uart_driver, port);
1795
1796 return 0;
1797}
1798#endif
1799
1800static void
1801mpc52xx_uart_of_assign(struct device_node *np)
1802{
1803 int i;
1804
1805 /* Find the first free PSC number */
1806 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1807 if (mpc52xx_uart_nodes[i] == NULL) {
1808 of_node_get(np);
1809 mpc52xx_uart_nodes[i] = np;
1810 return;
1811 }
1812 }
1813}
1814
1815static void
1816mpc52xx_uart_of_enumerate(void)
1817{
1818 static int enum_done;
1819 struct device_node *np;
1820 const struct of_device_id *match;
1821 int i;
1822
1823 if (enum_done)
1824 return;
1825
1826 /* Assign index to each PSC in device tree */
1827 for_each_matching_node(np, mpc52xx_uart_of_match) {
1828 match = of_match_node(mpc52xx_uart_of_match, np);
1829 psc_ops = match->data;
1830 mpc52xx_uart_of_assign(np);
1831 }
1832
1833 enum_done = 1;
1834
1835 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1836 if (mpc52xx_uart_nodes[i])
1837 pr_debug("%pOF assigned to ttyPSC%x\n",
1838 mpc52xx_uart_nodes[i], i);
1839 }
1840}
1841
1842MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1843
1844static struct platform_driver mpc52xx_uart_of_driver = {
1845 .probe = mpc52xx_uart_of_probe,
1846 .remove_new = mpc52xx_uart_of_remove,
1847#ifdef CONFIG_PM
1848 .suspend = mpc52xx_uart_of_suspend,
1849 .resume = mpc52xx_uart_of_resume,
1850#endif
1851 .driver = {
1852 .name = "mpc52xx-psc-uart",
1853 .of_match_table = mpc52xx_uart_of_match,
1854 },
1855};
1856
1857
1858/* ======================================================================== */
1859/* Module */
1860/* ======================================================================== */
1861
1862static int __init
1863mpc52xx_uart_init(void)
1864{
1865 int ret;
1866
1867 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1868
1869 ret = uart_register_driver(&mpc52xx_uart_driver);
1870 if (ret) {
1871 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1872 __FILE__, ret);
1873 return ret;
1874 }
1875
1876 mpc52xx_uart_of_enumerate();
1877
1878 /*
1879 * Map the PSC FIFO Controller and init if on MPC512x.
1880 */
1881 if (psc_ops && psc_ops->fifoc_init) {
1882 ret = psc_ops->fifoc_init();
1883 if (ret)
1884 goto err_init;
1885 }
1886
1887 ret = platform_driver_register(&mpc52xx_uart_of_driver);
1888 if (ret) {
1889 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
1890 __FILE__, ret);
1891 goto err_reg;
1892 }
1893
1894 return 0;
1895err_reg:
1896 if (psc_ops && psc_ops->fifoc_uninit)
1897 psc_ops->fifoc_uninit();
1898err_init:
1899 uart_unregister_driver(&mpc52xx_uart_driver);
1900 return ret;
1901}
1902
1903static void __exit
1904mpc52xx_uart_exit(void)
1905{
1906 if (psc_ops->fifoc_uninit)
1907 psc_ops->fifoc_uninit();
1908
1909 platform_driver_unregister(&mpc52xx_uart_of_driver);
1910 uart_unregister_driver(&mpc52xx_uart_driver);
1911}
1912
1913
1914module_init(mpc52xx_uart_init);
1915module_exit(mpc52xx_uart_exit);
1916
1917MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1918MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1919MODULE_LICENSE("GPL");
1/*
2 * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs.
3 *
4 * FIXME According to the usermanual the status bits in the status register
5 * are only updated when the peripherals access the FIFO and not when the
6 * CPU access them. So since we use this bits to know when we stop writing
7 * and reading, they may not be updated in-time and a race condition may
8 * exists. But I haven't be able to prove this and I don't care. But if
9 * any problem arises, it might worth checking. The TX/RX FIFO Stats
10 * registers should be used in addition.
11 * Update: Actually, they seem updated ... At least the bits we use.
12 *
13 *
14 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
15 *
16 * Some of the code has been inspired/copied from the 2.4 code written
17 * by Dale Farnsworth <dfarnsworth@mvista.com>.
18 *
19 * Copyright (C) 2008 Freescale Semiconductor Inc.
20 * John Rigby <jrigby@gmail.com>
21 * Added support for MPC5121
22 * Copyright (C) 2006 Secret Lab Technologies Ltd.
23 * Grant Likely <grant.likely@secretlab.ca>
24 * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com>
25 * Copyright (C) 2003 MontaVista, Software, Inc.
26 *
27 * This file is licensed under the terms of the GNU General Public License
28 * version 2. This program is licensed "as is" without any warranty of any
29 * kind, whether express or implied.
30 */
31
32#undef DEBUG
33
34#include <linux/device.h>
35#include <linux/module.h>
36#include <linux/tty.h>
37#include <linux/tty_flip.h>
38#include <linux/serial.h>
39#include <linux/sysrq.h>
40#include <linux/console.h>
41#include <linux/delay.h>
42#include <linux/io.h>
43#include <linux/of.h>
44#include <linux/of_platform.h>
45#include <linux/clk.h>
46
47#include <asm/mpc52xx.h>
48#include <asm/mpc52xx_psc.h>
49
50#if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
51#define SUPPORT_SYSRQ
52#endif
53
54#include <linux/serial_core.h>
55
56
57/* We've been assigned a range on the "Low-density serial ports" major */
58#define SERIAL_PSC_MAJOR 204
59#define SERIAL_PSC_MINOR 148
60
61
62#define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */
63
64
65static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM];
66 /* Rem: - We use the read_status_mask as a shadow of
67 * psc->mpc52xx_psc_imr
68 * - It's important that is array is all zero on start as we
69 * use it to know if it's initialized or not ! If it's not sure
70 * it's cleared, then a memset(...,0,...) should be added to
71 * the console_init
72 */
73
74/* lookup table for matching device nodes to index numbers */
75static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM];
76
77static void mpc52xx_uart_of_enumerate(void);
78
79
80#define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase))
81
82
83/* Forward declaration of the interruption handling routine */
84static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
85static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
86
87/* ======================================================================== */
88/* PSC fifo operations for isolating differences between 52xx and 512x */
89/* ======================================================================== */
90
91struct psc_ops {
92 void (*fifo_init)(struct uart_port *port);
93 int (*raw_rx_rdy)(struct uart_port *port);
94 int (*raw_tx_rdy)(struct uart_port *port);
95 int (*rx_rdy)(struct uart_port *port);
96 int (*tx_rdy)(struct uart_port *port);
97 int (*tx_empty)(struct uart_port *port);
98 void (*stop_rx)(struct uart_port *port);
99 void (*start_tx)(struct uart_port *port);
100 void (*stop_tx)(struct uart_port *port);
101 void (*rx_clr_irq)(struct uart_port *port);
102 void (*tx_clr_irq)(struct uart_port *port);
103 void (*write_char)(struct uart_port *port, unsigned char c);
104 unsigned char (*read_char)(struct uart_port *port);
105 void (*cw_disable_ints)(struct uart_port *port);
106 void (*cw_restore_ints)(struct uart_port *port);
107 unsigned int (*set_baudrate)(struct uart_port *port,
108 struct ktermios *new,
109 struct ktermios *old);
110 int (*clock_alloc)(struct uart_port *port);
111 void (*clock_relse)(struct uart_port *port);
112 int (*clock)(struct uart_port *port, int enable);
113 int (*fifoc_init)(void);
114 void (*fifoc_uninit)(void);
115 void (*get_irq)(struct uart_port *, struct device_node *);
116 irqreturn_t (*handle_irq)(struct uart_port *port);
117 u16 (*get_status)(struct uart_port *port);
118 u8 (*get_ipcr)(struct uart_port *port);
119 void (*command)(struct uart_port *port, u8 cmd);
120 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
121 void (*set_rts)(struct uart_port *port, int state);
122 void (*enable_ms)(struct uart_port *port);
123 void (*set_sicr)(struct uart_port *port, u32 val);
124 void (*set_imr)(struct uart_port *port, u16 val);
125 u8 (*get_mr1)(struct uart_port *port);
126};
127
128/* setting the prescaler and divisor reg is common for all chips */
129static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc,
130 u16 prescaler, unsigned int divisor)
131{
132 /* select prescaler */
133 out_be16(&psc->mpc52xx_psc_clock_select, prescaler);
134 out_8(&psc->ctur, divisor >> 8);
135 out_8(&psc->ctlr, divisor & 0xff);
136}
137
138static u16 mpc52xx_psc_get_status(struct uart_port *port)
139{
140 return in_be16(&PSC(port)->mpc52xx_psc_status);
141}
142
143static u8 mpc52xx_psc_get_ipcr(struct uart_port *port)
144{
145 return in_8(&PSC(port)->mpc52xx_psc_ipcr);
146}
147
148static void mpc52xx_psc_command(struct uart_port *port, u8 cmd)
149{
150 out_8(&PSC(port)->command, cmd);
151}
152
153static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
154{
155 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
156 out_8(&PSC(port)->mode, mr1);
157 out_8(&PSC(port)->mode, mr2);
158}
159
160static void mpc52xx_psc_set_rts(struct uart_port *port, int state)
161{
162 if (state)
163 out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS);
164 else
165 out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS);
166}
167
168static void mpc52xx_psc_enable_ms(struct uart_port *port)
169{
170 struct mpc52xx_psc __iomem *psc = PSC(port);
171
172 /* clear D_*-bits by reading them */
173 in_8(&psc->mpc52xx_psc_ipcr);
174 /* enable CTS and DCD as IPC interrupts */
175 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
176
177 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
178 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
179}
180
181static void mpc52xx_psc_set_sicr(struct uart_port *port, u32 val)
182{
183 out_be32(&PSC(port)->sicr, val);
184}
185
186static void mpc52xx_psc_set_imr(struct uart_port *port, u16 val)
187{
188 out_be16(&PSC(port)->mpc52xx_psc_imr, val);
189}
190
191static u8 mpc52xx_psc_get_mr1(struct uart_port *port)
192{
193 out_8(&PSC(port)->command, MPC52xx_PSC_SEL_MODE_REG_1);
194 return in_8(&PSC(port)->mode);
195}
196
197#ifdef CONFIG_PPC_MPC52xx
198#define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1))
199static void mpc52xx_psc_fifo_init(struct uart_port *port)
200{
201 struct mpc52xx_psc __iomem *psc = PSC(port);
202 struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port);
203
204 out_8(&fifo->rfcntl, 0x00);
205 out_be16(&fifo->rfalarm, 0x1ff);
206 out_8(&fifo->tfcntl, 0x07);
207 out_be16(&fifo->tfalarm, 0x80);
208
209 port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY;
210 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
211}
212
213static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port)
214{
215 return in_be16(&PSC(port)->mpc52xx_psc_status)
216 & MPC52xx_PSC_SR_RXRDY;
217}
218
219static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port)
220{
221 return in_be16(&PSC(port)->mpc52xx_psc_status)
222 & MPC52xx_PSC_SR_TXRDY;
223}
224
225
226static int mpc52xx_psc_rx_rdy(struct uart_port *port)
227{
228 return in_be16(&PSC(port)->mpc52xx_psc_isr)
229 & port->read_status_mask
230 & MPC52xx_PSC_IMR_RXRDY;
231}
232
233static int mpc52xx_psc_tx_rdy(struct uart_port *port)
234{
235 return in_be16(&PSC(port)->mpc52xx_psc_isr)
236 & port->read_status_mask
237 & MPC52xx_PSC_IMR_TXRDY;
238}
239
240static int mpc52xx_psc_tx_empty(struct uart_port *port)
241{
242 return in_be16(&PSC(port)->mpc52xx_psc_status)
243 & MPC52xx_PSC_SR_TXEMP;
244}
245
246static void mpc52xx_psc_start_tx(struct uart_port *port)
247{
248 port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY;
249 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
250}
251
252static void mpc52xx_psc_stop_tx(struct uart_port *port)
253{
254 port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY;
255 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
256}
257
258static void mpc52xx_psc_stop_rx(struct uart_port *port)
259{
260 port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY;
261 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
262}
263
264static void mpc52xx_psc_rx_clr_irq(struct uart_port *port)
265{
266}
267
268static void mpc52xx_psc_tx_clr_irq(struct uart_port *port)
269{
270}
271
272static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c)
273{
274 out_8(&PSC(port)->mpc52xx_psc_buffer_8, c);
275}
276
277static unsigned char mpc52xx_psc_read_char(struct uart_port *port)
278{
279 return in_8(&PSC(port)->mpc52xx_psc_buffer_8);
280}
281
282static void mpc52xx_psc_cw_disable_ints(struct uart_port *port)
283{
284 out_be16(&PSC(port)->mpc52xx_psc_imr, 0);
285}
286
287static void mpc52xx_psc_cw_restore_ints(struct uart_port *port)
288{
289 out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask);
290}
291
292static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port,
293 struct ktermios *new,
294 struct ktermios *old)
295{
296 unsigned int baud;
297 unsigned int divisor;
298
299 /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */
300 baud = uart_get_baud_rate(port, new, old,
301 port->uartclk / (32 * 0xffff) + 1,
302 port->uartclk / 32);
303 divisor = (port->uartclk + 16 * baud) / (32 * baud);
304
305 /* enable the /32 prescaler and set the divisor */
306 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
307 return baud;
308}
309
310static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port,
311 struct ktermios *new,
312 struct ktermios *old)
313{
314 unsigned int baud;
315 unsigned int divisor;
316 u16 prescaler;
317
318 /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the
319 * ipb freq */
320 baud = uart_get_baud_rate(port, new, old,
321 port->uartclk / (32 * 0xffff) + 1,
322 port->uartclk / 4);
323 divisor = (port->uartclk + 2 * baud) / (4 * baud);
324
325 /* select the proper prescaler and set the divisor
326 * prefer high prescaler for more tolerance on low baudrates */
327 if (divisor > 0xffff || baud <= 115200) {
328 divisor = (divisor + 4) / 8;
329 prescaler = 0xdd00; /* /32 */
330 } else
331 prescaler = 0xff00; /* /4 */
332 mpc52xx_set_divisor(PSC(port), prescaler, divisor);
333 return baud;
334}
335
336static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np)
337{
338 port->irqflags = 0;
339 port->irq = irq_of_parse_and_map(np, 0);
340}
341
342/* 52xx specific interrupt handler. The caller holds the port lock */
343static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port)
344{
345 return mpc5xxx_uart_process_int(port);
346}
347
348static struct psc_ops mpc52xx_psc_ops = {
349 .fifo_init = mpc52xx_psc_fifo_init,
350 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
351 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
352 .rx_rdy = mpc52xx_psc_rx_rdy,
353 .tx_rdy = mpc52xx_psc_tx_rdy,
354 .tx_empty = mpc52xx_psc_tx_empty,
355 .stop_rx = mpc52xx_psc_stop_rx,
356 .start_tx = mpc52xx_psc_start_tx,
357 .stop_tx = mpc52xx_psc_stop_tx,
358 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
359 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
360 .write_char = mpc52xx_psc_write_char,
361 .read_char = mpc52xx_psc_read_char,
362 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
363 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
364 .set_baudrate = mpc5200_psc_set_baudrate,
365 .get_irq = mpc52xx_psc_get_irq,
366 .handle_irq = mpc52xx_psc_handle_irq,
367 .get_status = mpc52xx_psc_get_status,
368 .get_ipcr = mpc52xx_psc_get_ipcr,
369 .command = mpc52xx_psc_command,
370 .set_mode = mpc52xx_psc_set_mode,
371 .set_rts = mpc52xx_psc_set_rts,
372 .enable_ms = mpc52xx_psc_enable_ms,
373 .set_sicr = mpc52xx_psc_set_sicr,
374 .set_imr = mpc52xx_psc_set_imr,
375 .get_mr1 = mpc52xx_psc_get_mr1,
376};
377
378static struct psc_ops mpc5200b_psc_ops = {
379 .fifo_init = mpc52xx_psc_fifo_init,
380 .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy,
381 .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy,
382 .rx_rdy = mpc52xx_psc_rx_rdy,
383 .tx_rdy = mpc52xx_psc_tx_rdy,
384 .tx_empty = mpc52xx_psc_tx_empty,
385 .stop_rx = mpc52xx_psc_stop_rx,
386 .start_tx = mpc52xx_psc_start_tx,
387 .stop_tx = mpc52xx_psc_stop_tx,
388 .rx_clr_irq = mpc52xx_psc_rx_clr_irq,
389 .tx_clr_irq = mpc52xx_psc_tx_clr_irq,
390 .write_char = mpc52xx_psc_write_char,
391 .read_char = mpc52xx_psc_read_char,
392 .cw_disable_ints = mpc52xx_psc_cw_disable_ints,
393 .cw_restore_ints = mpc52xx_psc_cw_restore_ints,
394 .set_baudrate = mpc5200b_psc_set_baudrate,
395 .get_irq = mpc52xx_psc_get_irq,
396 .handle_irq = mpc52xx_psc_handle_irq,
397 .get_status = mpc52xx_psc_get_status,
398 .get_ipcr = mpc52xx_psc_get_ipcr,
399 .command = mpc52xx_psc_command,
400 .set_mode = mpc52xx_psc_set_mode,
401 .set_rts = mpc52xx_psc_set_rts,
402 .enable_ms = mpc52xx_psc_enable_ms,
403 .set_sicr = mpc52xx_psc_set_sicr,
404 .set_imr = mpc52xx_psc_set_imr,
405 .get_mr1 = mpc52xx_psc_get_mr1,
406};
407
408#endif /* CONFIG_MPC52xx */
409
410#ifdef CONFIG_PPC_MPC512x
411#define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1))
412
413/* PSC FIFO Controller for mpc512x */
414struct psc_fifoc {
415 u32 fifoc_cmd;
416 u32 fifoc_int;
417 u32 fifoc_dma;
418 u32 fifoc_axe;
419 u32 fifoc_debug;
420};
421
422static struct psc_fifoc __iomem *psc_fifoc;
423static unsigned int psc_fifoc_irq;
424static struct clk *psc_fifoc_clk;
425
426static void mpc512x_psc_fifo_init(struct uart_port *port)
427{
428 /* /32 prescaler */
429 out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00);
430
431 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
432 out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
433 out_be32(&FIFO_512x(port)->txalarm, 1);
434 out_be32(&FIFO_512x(port)->tximr, 0);
435
436 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
437 out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
438 out_be32(&FIFO_512x(port)->rxalarm, 1);
439 out_be32(&FIFO_512x(port)->rximr, 0);
440
441 out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM);
442 out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM);
443}
444
445static int mpc512x_psc_raw_rx_rdy(struct uart_port *port)
446{
447 return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
448}
449
450static int mpc512x_psc_raw_tx_rdy(struct uart_port *port)
451{
452 return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL);
453}
454
455static int mpc512x_psc_rx_rdy(struct uart_port *port)
456{
457 return in_be32(&FIFO_512x(port)->rxsr)
458 & in_be32(&FIFO_512x(port)->rximr)
459 & MPC512x_PSC_FIFO_ALARM;
460}
461
462static int mpc512x_psc_tx_rdy(struct uart_port *port)
463{
464 return in_be32(&FIFO_512x(port)->txsr)
465 & in_be32(&FIFO_512x(port)->tximr)
466 & MPC512x_PSC_FIFO_ALARM;
467}
468
469static int mpc512x_psc_tx_empty(struct uart_port *port)
470{
471 return in_be32(&FIFO_512x(port)->txsr)
472 & MPC512x_PSC_FIFO_EMPTY;
473}
474
475static void mpc512x_psc_stop_rx(struct uart_port *port)
476{
477 unsigned long rx_fifo_imr;
478
479 rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr);
480 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
481 out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr);
482}
483
484static void mpc512x_psc_start_tx(struct uart_port *port)
485{
486 unsigned long tx_fifo_imr;
487
488 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
489 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
490 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
491}
492
493static void mpc512x_psc_stop_tx(struct uart_port *port)
494{
495 unsigned long tx_fifo_imr;
496
497 tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr);
498 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
499 out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr);
500}
501
502static void mpc512x_psc_rx_clr_irq(struct uart_port *port)
503{
504 out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr));
505}
506
507static void mpc512x_psc_tx_clr_irq(struct uart_port *port)
508{
509 out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr));
510}
511
512static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c)
513{
514 out_8(&FIFO_512x(port)->txdata_8, c);
515}
516
517static unsigned char mpc512x_psc_read_char(struct uart_port *port)
518{
519 return in_8(&FIFO_512x(port)->rxdata_8);
520}
521
522static void mpc512x_psc_cw_disable_ints(struct uart_port *port)
523{
524 port->read_status_mask =
525 in_be32(&FIFO_512x(port)->tximr) << 16 |
526 in_be32(&FIFO_512x(port)->rximr);
527 out_be32(&FIFO_512x(port)->tximr, 0);
528 out_be32(&FIFO_512x(port)->rximr, 0);
529}
530
531static void mpc512x_psc_cw_restore_ints(struct uart_port *port)
532{
533 out_be32(&FIFO_512x(port)->tximr,
534 (port->read_status_mask >> 16) & 0x7f);
535 out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f);
536}
537
538static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port,
539 struct ktermios *new,
540 struct ktermios *old)
541{
542 unsigned int baud;
543 unsigned int divisor;
544
545 /*
546 * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on
547 * pg. 30-10 that the chip supports a /32 and a /10 prescaler.
548 * Furthermore, it states that "After reset, the prescaler by 10
549 * for the UART mode is selected", but the reset register value is
550 * 0x0000 which means a /32 prescaler. This is wrong.
551 *
552 * In reality using /32 prescaler doesn't work, as it is not supported!
553 * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide",
554 * Chapter 4.1 PSC in UART Mode.
555 * Calculate with a /16 prescaler here.
556 */
557
558 /* uartclk contains the ips freq */
559 baud = uart_get_baud_rate(port, new, old,
560 port->uartclk / (16 * 0xffff) + 1,
561 port->uartclk / 16);
562 divisor = (port->uartclk + 8 * baud) / (16 * baud);
563
564 /* enable the /16 prescaler and set the divisor */
565 mpc52xx_set_divisor(PSC(port), 0xdd00, divisor);
566 return baud;
567}
568
569/* Init PSC FIFO Controller */
570static int __init mpc512x_psc_fifoc_init(void)
571{
572 int err;
573 struct device_node *np;
574 struct clk *clk;
575
576 /* default error code, potentially overwritten by clock calls */
577 err = -ENODEV;
578
579 np = of_find_compatible_node(NULL, NULL,
580 "fsl,mpc5121-psc-fifo");
581 if (!np) {
582 pr_err("%s: Can't find FIFOC node\n", __func__);
583 goto out_err;
584 }
585
586 clk = of_clk_get(np, 0);
587 if (IS_ERR(clk)) {
588 /* backwards compat with device trees that lack clock specs */
589 clk = clk_get_sys(np->name, "ipg");
590 }
591 if (IS_ERR(clk)) {
592 pr_err("%s: Can't lookup FIFO clock\n", __func__);
593 err = PTR_ERR(clk);
594 goto out_ofnode_put;
595 }
596 if (clk_prepare_enable(clk)) {
597 pr_err("%s: Can't enable FIFO clock\n", __func__);
598 clk_put(clk);
599 goto out_ofnode_put;
600 }
601 psc_fifoc_clk = clk;
602
603 psc_fifoc = of_iomap(np, 0);
604 if (!psc_fifoc) {
605 pr_err("%s: Can't map FIFOC\n", __func__);
606 goto out_clk_disable;
607 }
608
609 psc_fifoc_irq = irq_of_parse_and_map(np, 0);
610 if (psc_fifoc_irq == 0) {
611 pr_err("%s: Can't get FIFOC irq\n", __func__);
612 goto out_unmap;
613 }
614
615 of_node_put(np);
616 return 0;
617
618out_unmap:
619 iounmap(psc_fifoc);
620out_clk_disable:
621 clk_disable_unprepare(psc_fifoc_clk);
622 clk_put(psc_fifoc_clk);
623out_ofnode_put:
624 of_node_put(np);
625out_err:
626 return err;
627}
628
629static void __exit mpc512x_psc_fifoc_uninit(void)
630{
631 iounmap(psc_fifoc);
632
633 /* disable the clock, errors are not fatal */
634 if (psc_fifoc_clk) {
635 clk_disable_unprepare(psc_fifoc_clk);
636 clk_put(psc_fifoc_clk);
637 psc_fifoc_clk = NULL;
638 }
639}
640
641/* 512x specific interrupt handler. The caller holds the port lock */
642static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port)
643{
644 unsigned long fifoc_int;
645 int psc_num;
646
647 /* Read pending PSC FIFOC interrupts */
648 fifoc_int = in_be32(&psc_fifoc->fifoc_int);
649
650 /* Check if it is an interrupt for this port */
651 psc_num = (port->mapbase & 0xf00) >> 8;
652 if (test_bit(psc_num, &fifoc_int) ||
653 test_bit(psc_num + 16, &fifoc_int))
654 return mpc5xxx_uart_process_int(port);
655
656 return IRQ_NONE;
657}
658
659static struct clk *psc_mclk_clk[MPC52xx_PSC_MAXNUM];
660static struct clk *psc_ipg_clk[MPC52xx_PSC_MAXNUM];
661
662/* called from within the .request_port() callback (allocation) */
663static int mpc512x_psc_alloc_clock(struct uart_port *port)
664{
665 int psc_num;
666 struct clk *clk;
667 int err;
668
669 psc_num = (port->mapbase & 0xf00) >> 8;
670
671 clk = devm_clk_get(port->dev, "mclk");
672 if (IS_ERR(clk)) {
673 dev_err(port->dev, "Failed to get MCLK!\n");
674 err = PTR_ERR(clk);
675 goto out_err;
676 }
677 err = clk_prepare_enable(clk);
678 if (err) {
679 dev_err(port->dev, "Failed to enable MCLK!\n");
680 goto out_err;
681 }
682 psc_mclk_clk[psc_num] = clk;
683
684 clk = devm_clk_get(port->dev, "ipg");
685 if (IS_ERR(clk)) {
686 dev_err(port->dev, "Failed to get IPG clock!\n");
687 err = PTR_ERR(clk);
688 goto out_err;
689 }
690 err = clk_prepare_enable(clk);
691 if (err) {
692 dev_err(port->dev, "Failed to enable IPG clock!\n");
693 goto out_err;
694 }
695 psc_ipg_clk[psc_num] = clk;
696
697 return 0;
698
699out_err:
700 if (psc_mclk_clk[psc_num]) {
701 clk_disable_unprepare(psc_mclk_clk[psc_num]);
702 psc_mclk_clk[psc_num] = NULL;
703 }
704 if (psc_ipg_clk[psc_num]) {
705 clk_disable_unprepare(psc_ipg_clk[psc_num]);
706 psc_ipg_clk[psc_num] = NULL;
707 }
708 return err;
709}
710
711/* called from within the .release_port() callback (release) */
712static void mpc512x_psc_relse_clock(struct uart_port *port)
713{
714 int psc_num;
715 struct clk *clk;
716
717 psc_num = (port->mapbase & 0xf00) >> 8;
718 clk = psc_mclk_clk[psc_num];
719 if (clk) {
720 clk_disable_unprepare(clk);
721 psc_mclk_clk[psc_num] = NULL;
722 }
723 if (psc_ipg_clk[psc_num]) {
724 clk_disable_unprepare(psc_ipg_clk[psc_num]);
725 psc_ipg_clk[psc_num] = NULL;
726 }
727}
728
729/* implementation of the .clock() callback (enable/disable) */
730static int mpc512x_psc_endis_clock(struct uart_port *port, int enable)
731{
732 int psc_num;
733 struct clk *psc_clk;
734 int ret;
735
736 if (uart_console(port))
737 return 0;
738
739 psc_num = (port->mapbase & 0xf00) >> 8;
740 psc_clk = psc_mclk_clk[psc_num];
741 if (!psc_clk) {
742 dev_err(port->dev, "Failed to get PSC clock entry!\n");
743 return -ENODEV;
744 }
745
746 dev_dbg(port->dev, "mclk %sable\n", enable ? "en" : "dis");
747 if (enable) {
748 ret = clk_enable(psc_clk);
749 if (ret)
750 dev_err(port->dev, "Failed to enable MCLK!\n");
751 return ret;
752 } else {
753 clk_disable(psc_clk);
754 return 0;
755 }
756}
757
758static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np)
759{
760 port->irqflags = IRQF_SHARED;
761 port->irq = psc_fifoc_irq;
762}
763#endif
764
765#ifdef CONFIG_PPC_MPC512x
766
767#define PSC_5125(port) ((struct mpc5125_psc __iomem *)((port)->membase))
768#define FIFO_5125(port) ((struct mpc512x_psc_fifo __iomem *)(PSC_5125(port)+1))
769
770static void mpc5125_psc_fifo_init(struct uart_port *port)
771{
772 /* /32 prescaler */
773 out_8(&PSC_5125(port)->mpc52xx_psc_clock_select, 0xdd);
774
775 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE);
776 out_be32(&FIFO_5125(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
777 out_be32(&FIFO_5125(port)->txalarm, 1);
778 out_be32(&FIFO_5125(port)->tximr, 0);
779
780 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE);
781 out_be32(&FIFO_5125(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE);
782 out_be32(&FIFO_5125(port)->rxalarm, 1);
783 out_be32(&FIFO_5125(port)->rximr, 0);
784
785 out_be32(&FIFO_5125(port)->tximr, MPC512x_PSC_FIFO_ALARM);
786 out_be32(&FIFO_5125(port)->rximr, MPC512x_PSC_FIFO_ALARM);
787}
788
789static int mpc5125_psc_raw_rx_rdy(struct uart_port *port)
790{
791 return !(in_be32(&FIFO_5125(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY);
792}
793
794static int mpc5125_psc_raw_tx_rdy(struct uart_port *port)
795{
796 return !(in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_FULL);
797}
798
799static int mpc5125_psc_rx_rdy(struct uart_port *port)
800{
801 return in_be32(&FIFO_5125(port)->rxsr) &
802 in_be32(&FIFO_5125(port)->rximr) & MPC512x_PSC_FIFO_ALARM;
803}
804
805static int mpc5125_psc_tx_rdy(struct uart_port *port)
806{
807 return in_be32(&FIFO_5125(port)->txsr) &
808 in_be32(&FIFO_5125(port)->tximr) & MPC512x_PSC_FIFO_ALARM;
809}
810
811static int mpc5125_psc_tx_empty(struct uart_port *port)
812{
813 return in_be32(&FIFO_5125(port)->txsr) & MPC512x_PSC_FIFO_EMPTY;
814}
815
816static void mpc5125_psc_stop_rx(struct uart_port *port)
817{
818 unsigned long rx_fifo_imr;
819
820 rx_fifo_imr = in_be32(&FIFO_5125(port)->rximr);
821 rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
822 out_be32(&FIFO_5125(port)->rximr, rx_fifo_imr);
823}
824
825static void mpc5125_psc_start_tx(struct uart_port *port)
826{
827 unsigned long tx_fifo_imr;
828
829 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
830 tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM;
831 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
832}
833
834static void mpc5125_psc_stop_tx(struct uart_port *port)
835{
836 unsigned long tx_fifo_imr;
837
838 tx_fifo_imr = in_be32(&FIFO_5125(port)->tximr);
839 tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM;
840 out_be32(&FIFO_5125(port)->tximr, tx_fifo_imr);
841}
842
843static void mpc5125_psc_rx_clr_irq(struct uart_port *port)
844{
845 out_be32(&FIFO_5125(port)->rxisr, in_be32(&FIFO_5125(port)->rxisr));
846}
847
848static void mpc5125_psc_tx_clr_irq(struct uart_port *port)
849{
850 out_be32(&FIFO_5125(port)->txisr, in_be32(&FIFO_5125(port)->txisr));
851}
852
853static void mpc5125_psc_write_char(struct uart_port *port, unsigned char c)
854{
855 out_8(&FIFO_5125(port)->txdata_8, c);
856}
857
858static unsigned char mpc5125_psc_read_char(struct uart_port *port)
859{
860 return in_8(&FIFO_5125(port)->rxdata_8);
861}
862
863static void mpc5125_psc_cw_disable_ints(struct uart_port *port)
864{
865 port->read_status_mask =
866 in_be32(&FIFO_5125(port)->tximr) << 16 |
867 in_be32(&FIFO_5125(port)->rximr);
868 out_be32(&FIFO_5125(port)->tximr, 0);
869 out_be32(&FIFO_5125(port)->rximr, 0);
870}
871
872static void mpc5125_psc_cw_restore_ints(struct uart_port *port)
873{
874 out_be32(&FIFO_5125(port)->tximr,
875 (port->read_status_mask >> 16) & 0x7f);
876 out_be32(&FIFO_5125(port)->rximr, port->read_status_mask & 0x7f);
877}
878
879static inline void mpc5125_set_divisor(struct mpc5125_psc __iomem *psc,
880 u8 prescaler, unsigned int divisor)
881{
882 /* select prescaler */
883 out_8(&psc->mpc52xx_psc_clock_select, prescaler);
884 out_8(&psc->ctur, divisor >> 8);
885 out_8(&psc->ctlr, divisor & 0xff);
886}
887
888static unsigned int mpc5125_psc_set_baudrate(struct uart_port *port,
889 struct ktermios *new,
890 struct ktermios *old)
891{
892 unsigned int baud;
893 unsigned int divisor;
894
895 /*
896 * Calculate with a /16 prescaler here.
897 */
898
899 /* uartclk contains the ips freq */
900 baud = uart_get_baud_rate(port, new, old,
901 port->uartclk / (16 * 0xffff) + 1,
902 port->uartclk / 16);
903 divisor = (port->uartclk + 8 * baud) / (16 * baud);
904
905 /* enable the /16 prescaler and set the divisor */
906 mpc5125_set_divisor(PSC_5125(port), 0xdd, divisor);
907 return baud;
908}
909
910/*
911 * MPC5125 have compatible PSC FIFO Controller.
912 * Special init not needed.
913 */
914static u16 mpc5125_psc_get_status(struct uart_port *port)
915{
916 return in_be16(&PSC_5125(port)->mpc52xx_psc_status);
917}
918
919static u8 mpc5125_psc_get_ipcr(struct uart_port *port)
920{
921 return in_8(&PSC_5125(port)->mpc52xx_psc_ipcr);
922}
923
924static void mpc5125_psc_command(struct uart_port *port, u8 cmd)
925{
926 out_8(&PSC_5125(port)->command, cmd);
927}
928
929static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2)
930{
931 out_8(&PSC_5125(port)->mr1, mr1);
932 out_8(&PSC_5125(port)->mr2, mr2);
933}
934
935static void mpc5125_psc_set_rts(struct uart_port *port, int state)
936{
937 if (state & TIOCM_RTS)
938 out_8(&PSC_5125(port)->op1, MPC52xx_PSC_OP_RTS);
939 else
940 out_8(&PSC_5125(port)->op0, MPC52xx_PSC_OP_RTS);
941}
942
943static void mpc5125_psc_enable_ms(struct uart_port *port)
944{
945 struct mpc5125_psc __iomem *psc = PSC_5125(port);
946
947 /* clear D_*-bits by reading them */
948 in_8(&psc->mpc52xx_psc_ipcr);
949 /* enable CTS and DCD as IPC interrupts */
950 out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD);
951
952 port->read_status_mask |= MPC52xx_PSC_IMR_IPC;
953 out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask);
954}
955
956static void mpc5125_psc_set_sicr(struct uart_port *port, u32 val)
957{
958 out_be32(&PSC_5125(port)->sicr, val);
959}
960
961static void mpc5125_psc_set_imr(struct uart_port *port, u16 val)
962{
963 out_be16(&PSC_5125(port)->mpc52xx_psc_imr, val);
964}
965
966static u8 mpc5125_psc_get_mr1(struct uart_port *port)
967{
968 return in_8(&PSC_5125(port)->mr1);
969}
970
971static struct psc_ops mpc5125_psc_ops = {
972 .fifo_init = mpc5125_psc_fifo_init,
973 .raw_rx_rdy = mpc5125_psc_raw_rx_rdy,
974 .raw_tx_rdy = mpc5125_psc_raw_tx_rdy,
975 .rx_rdy = mpc5125_psc_rx_rdy,
976 .tx_rdy = mpc5125_psc_tx_rdy,
977 .tx_empty = mpc5125_psc_tx_empty,
978 .stop_rx = mpc5125_psc_stop_rx,
979 .start_tx = mpc5125_psc_start_tx,
980 .stop_tx = mpc5125_psc_stop_tx,
981 .rx_clr_irq = mpc5125_psc_rx_clr_irq,
982 .tx_clr_irq = mpc5125_psc_tx_clr_irq,
983 .write_char = mpc5125_psc_write_char,
984 .read_char = mpc5125_psc_read_char,
985 .cw_disable_ints = mpc5125_psc_cw_disable_ints,
986 .cw_restore_ints = mpc5125_psc_cw_restore_ints,
987 .set_baudrate = mpc5125_psc_set_baudrate,
988 .clock_alloc = mpc512x_psc_alloc_clock,
989 .clock_relse = mpc512x_psc_relse_clock,
990 .clock = mpc512x_psc_endis_clock,
991 .fifoc_init = mpc512x_psc_fifoc_init,
992 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
993 .get_irq = mpc512x_psc_get_irq,
994 .handle_irq = mpc512x_psc_handle_irq,
995 .get_status = mpc5125_psc_get_status,
996 .get_ipcr = mpc5125_psc_get_ipcr,
997 .command = mpc5125_psc_command,
998 .set_mode = mpc5125_psc_set_mode,
999 .set_rts = mpc5125_psc_set_rts,
1000 .enable_ms = mpc5125_psc_enable_ms,
1001 .set_sicr = mpc5125_psc_set_sicr,
1002 .set_imr = mpc5125_psc_set_imr,
1003 .get_mr1 = mpc5125_psc_get_mr1,
1004};
1005
1006static struct psc_ops mpc512x_psc_ops = {
1007 .fifo_init = mpc512x_psc_fifo_init,
1008 .raw_rx_rdy = mpc512x_psc_raw_rx_rdy,
1009 .raw_tx_rdy = mpc512x_psc_raw_tx_rdy,
1010 .rx_rdy = mpc512x_psc_rx_rdy,
1011 .tx_rdy = mpc512x_psc_tx_rdy,
1012 .tx_empty = mpc512x_psc_tx_empty,
1013 .stop_rx = mpc512x_psc_stop_rx,
1014 .start_tx = mpc512x_psc_start_tx,
1015 .stop_tx = mpc512x_psc_stop_tx,
1016 .rx_clr_irq = mpc512x_psc_rx_clr_irq,
1017 .tx_clr_irq = mpc512x_psc_tx_clr_irq,
1018 .write_char = mpc512x_psc_write_char,
1019 .read_char = mpc512x_psc_read_char,
1020 .cw_disable_ints = mpc512x_psc_cw_disable_ints,
1021 .cw_restore_ints = mpc512x_psc_cw_restore_ints,
1022 .set_baudrate = mpc512x_psc_set_baudrate,
1023 .clock_alloc = mpc512x_psc_alloc_clock,
1024 .clock_relse = mpc512x_psc_relse_clock,
1025 .clock = mpc512x_psc_endis_clock,
1026 .fifoc_init = mpc512x_psc_fifoc_init,
1027 .fifoc_uninit = mpc512x_psc_fifoc_uninit,
1028 .get_irq = mpc512x_psc_get_irq,
1029 .handle_irq = mpc512x_psc_handle_irq,
1030 .get_status = mpc52xx_psc_get_status,
1031 .get_ipcr = mpc52xx_psc_get_ipcr,
1032 .command = mpc52xx_psc_command,
1033 .set_mode = mpc52xx_psc_set_mode,
1034 .set_rts = mpc52xx_psc_set_rts,
1035 .enable_ms = mpc52xx_psc_enable_ms,
1036 .set_sicr = mpc52xx_psc_set_sicr,
1037 .set_imr = mpc52xx_psc_set_imr,
1038 .get_mr1 = mpc52xx_psc_get_mr1,
1039};
1040#endif /* CONFIG_PPC_MPC512x */
1041
1042
1043static const struct psc_ops *psc_ops;
1044
1045/* ======================================================================== */
1046/* UART operations */
1047/* ======================================================================== */
1048
1049static unsigned int
1050mpc52xx_uart_tx_empty(struct uart_port *port)
1051{
1052 return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0;
1053}
1054
1055static void
1056mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1057{
1058 psc_ops->set_rts(port, mctrl & TIOCM_RTS);
1059}
1060
1061static unsigned int
1062mpc52xx_uart_get_mctrl(struct uart_port *port)
1063{
1064 unsigned int ret = TIOCM_DSR;
1065 u8 status = psc_ops->get_ipcr(port);
1066
1067 if (!(status & MPC52xx_PSC_CTS))
1068 ret |= TIOCM_CTS;
1069 if (!(status & MPC52xx_PSC_DCD))
1070 ret |= TIOCM_CAR;
1071
1072 return ret;
1073}
1074
1075static void
1076mpc52xx_uart_stop_tx(struct uart_port *port)
1077{
1078 /* port->lock taken by caller */
1079 psc_ops->stop_tx(port);
1080}
1081
1082static void
1083mpc52xx_uart_start_tx(struct uart_port *port)
1084{
1085 /* port->lock taken by caller */
1086 psc_ops->start_tx(port);
1087}
1088
1089static void
1090mpc52xx_uart_send_xchar(struct uart_port *port, char ch)
1091{
1092 unsigned long flags;
1093 spin_lock_irqsave(&port->lock, flags);
1094
1095 port->x_char = ch;
1096 if (ch) {
1097 /* Make sure tx interrupts are on */
1098 /* Truly necessary ??? They should be anyway */
1099 psc_ops->start_tx(port);
1100 }
1101
1102 spin_unlock_irqrestore(&port->lock, flags);
1103}
1104
1105static void
1106mpc52xx_uart_stop_rx(struct uart_port *port)
1107{
1108 /* port->lock taken by caller */
1109 psc_ops->stop_rx(port);
1110}
1111
1112static void
1113mpc52xx_uart_enable_ms(struct uart_port *port)
1114{
1115 psc_ops->enable_ms(port);
1116}
1117
1118static void
1119mpc52xx_uart_break_ctl(struct uart_port *port, int ctl)
1120{
1121 unsigned long flags;
1122 spin_lock_irqsave(&port->lock, flags);
1123
1124 if (ctl == -1)
1125 psc_ops->command(port, MPC52xx_PSC_START_BRK);
1126 else
1127 psc_ops->command(port, MPC52xx_PSC_STOP_BRK);
1128
1129 spin_unlock_irqrestore(&port->lock, flags);
1130}
1131
1132static int
1133mpc52xx_uart_startup(struct uart_port *port)
1134{
1135 int ret;
1136
1137 if (psc_ops->clock) {
1138 ret = psc_ops->clock(port, 1);
1139 if (ret)
1140 return ret;
1141 }
1142
1143 /* Request IRQ */
1144 ret = request_irq(port->irq, mpc52xx_uart_int,
1145 port->irqflags, "mpc52xx_psc_uart", port);
1146 if (ret)
1147 return ret;
1148
1149 /* Reset/activate the port, clear and enable interrupts */
1150 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1151 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1152
1153 psc_ops->set_sicr(port, 0); /* UART mode DCD ignored */
1154
1155 psc_ops->fifo_init(port);
1156
1157 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1158 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1159
1160 return 0;
1161}
1162
1163static void
1164mpc52xx_uart_shutdown(struct uart_port *port)
1165{
1166 /* Shut down the port. Leave TX active if on a console port */
1167 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1168 if (!uart_console(port))
1169 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1170
1171 port->read_status_mask = 0;
1172 psc_ops->set_imr(port, port->read_status_mask);
1173
1174 if (psc_ops->clock)
1175 psc_ops->clock(port, 0);
1176
1177 /* Disable interrupt */
1178 psc_ops->cw_disable_ints(port);
1179
1180 /* Release interrupt */
1181 free_irq(port->irq, port);
1182}
1183
1184static void
1185mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new,
1186 struct ktermios *old)
1187{
1188 unsigned long flags;
1189 unsigned char mr1, mr2;
1190 unsigned int j;
1191 unsigned int baud;
1192
1193 /* Prepare what we're gonna write */
1194 mr1 = 0;
1195
1196 switch (new->c_cflag & CSIZE) {
1197 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS;
1198 break;
1199 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS;
1200 break;
1201 case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS;
1202 break;
1203 case CS8:
1204 default: mr1 |= MPC52xx_PSC_MODE_8_BITS;
1205 }
1206
1207 if (new->c_cflag & PARENB) {
1208 if (new->c_cflag & CMSPAR)
1209 mr1 |= MPC52xx_PSC_MODE_PARFORCE;
1210
1211 /* With CMSPAR, PARODD also means high parity (same as termios) */
1212 mr1 |= (new->c_cflag & PARODD) ?
1213 MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN;
1214 } else {
1215 mr1 |= MPC52xx_PSC_MODE_PARNONE;
1216 }
1217
1218 mr2 = 0;
1219
1220 if (new->c_cflag & CSTOPB)
1221 mr2 |= MPC52xx_PSC_MODE_TWO_STOP;
1222 else
1223 mr2 |= ((new->c_cflag & CSIZE) == CS5) ?
1224 MPC52xx_PSC_MODE_ONE_STOP_5_BITS :
1225 MPC52xx_PSC_MODE_ONE_STOP;
1226
1227 if (new->c_cflag & CRTSCTS) {
1228 mr1 |= MPC52xx_PSC_MODE_RXRTS;
1229 mr2 |= MPC52xx_PSC_MODE_TXCTS;
1230 }
1231
1232 /* Get the lock */
1233 spin_lock_irqsave(&port->lock, flags);
1234
1235 /* Do our best to flush TX & RX, so we don't lose anything */
1236 /* But we don't wait indefinitely ! */
1237 j = 5000000; /* Maximum wait */
1238 /* FIXME Can't receive chars since set_termios might be called at early
1239 * boot for the console, all stuff is not yet ready to receive at that
1240 * time and that just makes the kernel oops */
1241 /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */
1242 while (!mpc52xx_uart_tx_empty(port) && --j)
1243 udelay(1);
1244
1245 if (!j)
1246 printk(KERN_ERR "mpc52xx_uart.c: "
1247 "Unable to flush RX & TX fifos in-time in set_termios."
1248 "Some chars may have been lost.\n");
1249
1250 /* Reset the TX & RX */
1251 psc_ops->command(port, MPC52xx_PSC_RST_RX);
1252 psc_ops->command(port, MPC52xx_PSC_RST_TX);
1253
1254 /* Send new mode settings */
1255 psc_ops->set_mode(port, mr1, mr2);
1256 baud = psc_ops->set_baudrate(port, new, old);
1257
1258 /* Update the per-port timeout */
1259 uart_update_timeout(port, new->c_cflag, baud);
1260
1261 if (UART_ENABLE_MS(port, new->c_cflag))
1262 mpc52xx_uart_enable_ms(port);
1263
1264 /* Reenable TX & RX */
1265 psc_ops->command(port, MPC52xx_PSC_TX_ENABLE);
1266 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE);
1267
1268 /* We're all set, release the lock */
1269 spin_unlock_irqrestore(&port->lock, flags);
1270}
1271
1272static const char *
1273mpc52xx_uart_type(struct uart_port *port)
1274{
1275 /*
1276 * We keep using PORT_MPC52xx for historic reasons although it applies
1277 * for MPC512x, too, but print "MPC5xxx" to not irritate users
1278 */
1279 return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL;
1280}
1281
1282static void
1283mpc52xx_uart_release_port(struct uart_port *port)
1284{
1285 if (psc_ops->clock_relse)
1286 psc_ops->clock_relse(port);
1287
1288 /* remapped by us ? */
1289 if (port->flags & UPF_IOREMAP) {
1290 iounmap(port->membase);
1291 port->membase = NULL;
1292 }
1293
1294 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1295}
1296
1297static int
1298mpc52xx_uart_request_port(struct uart_port *port)
1299{
1300 int err;
1301
1302 if (port->flags & UPF_IOREMAP) /* Need to remap ? */
1303 port->membase = ioremap(port->mapbase,
1304 sizeof(struct mpc52xx_psc));
1305
1306 if (!port->membase)
1307 return -EINVAL;
1308
1309 err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc),
1310 "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY;
1311
1312 if (err)
1313 goto out_membase;
1314
1315 if (psc_ops->clock_alloc) {
1316 err = psc_ops->clock_alloc(port);
1317 if (err)
1318 goto out_mapregion;
1319 }
1320
1321 return 0;
1322
1323out_mapregion:
1324 release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc));
1325out_membase:
1326 if (port->flags & UPF_IOREMAP) {
1327 iounmap(port->membase);
1328 port->membase = NULL;
1329 }
1330 return err;
1331}
1332
1333static void
1334mpc52xx_uart_config_port(struct uart_port *port, int flags)
1335{
1336 if ((flags & UART_CONFIG_TYPE)
1337 && (mpc52xx_uart_request_port(port) == 0))
1338 port->type = PORT_MPC52xx;
1339}
1340
1341static int
1342mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1343{
1344 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx)
1345 return -EINVAL;
1346
1347 if ((ser->irq != port->irq) ||
1348 (ser->io_type != UPIO_MEM) ||
1349 (ser->baud_base != port->uartclk) ||
1350 (ser->iomem_base != (void *)port->mapbase) ||
1351 (ser->hub6 != 0))
1352 return -EINVAL;
1353
1354 return 0;
1355}
1356
1357
1358static struct uart_ops mpc52xx_uart_ops = {
1359 .tx_empty = mpc52xx_uart_tx_empty,
1360 .set_mctrl = mpc52xx_uart_set_mctrl,
1361 .get_mctrl = mpc52xx_uart_get_mctrl,
1362 .stop_tx = mpc52xx_uart_stop_tx,
1363 .start_tx = mpc52xx_uart_start_tx,
1364 .send_xchar = mpc52xx_uart_send_xchar,
1365 .stop_rx = mpc52xx_uart_stop_rx,
1366 .enable_ms = mpc52xx_uart_enable_ms,
1367 .break_ctl = mpc52xx_uart_break_ctl,
1368 .startup = mpc52xx_uart_startup,
1369 .shutdown = mpc52xx_uart_shutdown,
1370 .set_termios = mpc52xx_uart_set_termios,
1371/* .pm = mpc52xx_uart_pm, Not supported yet */
1372 .type = mpc52xx_uart_type,
1373 .release_port = mpc52xx_uart_release_port,
1374 .request_port = mpc52xx_uart_request_port,
1375 .config_port = mpc52xx_uart_config_port,
1376 .verify_port = mpc52xx_uart_verify_port
1377};
1378
1379
1380/* ======================================================================== */
1381/* Interrupt handling */
1382/* ======================================================================== */
1383
1384static inline int
1385mpc52xx_uart_int_rx_chars(struct uart_port *port)
1386{
1387 struct tty_port *tport = &port->state->port;
1388 unsigned char ch, flag;
1389 unsigned short status;
1390
1391 /* While we can read, do so ! */
1392 while (psc_ops->raw_rx_rdy(port)) {
1393 /* Get the char */
1394 ch = psc_ops->read_char(port);
1395
1396 /* Handle sysreq char */
1397#ifdef SUPPORT_SYSRQ
1398 if (uart_handle_sysrq_char(port, ch)) {
1399 port->sysrq = 0;
1400 continue;
1401 }
1402#endif
1403
1404 /* Store it */
1405
1406 flag = TTY_NORMAL;
1407 port->icount.rx++;
1408
1409 status = psc_ops->get_status(port);
1410
1411 if (status & (MPC52xx_PSC_SR_PE |
1412 MPC52xx_PSC_SR_FE |
1413 MPC52xx_PSC_SR_RB)) {
1414
1415 if (status & MPC52xx_PSC_SR_RB) {
1416 flag = TTY_BREAK;
1417 uart_handle_break(port);
1418 port->icount.brk++;
1419 } else if (status & MPC52xx_PSC_SR_PE) {
1420 flag = TTY_PARITY;
1421 port->icount.parity++;
1422 }
1423 else if (status & MPC52xx_PSC_SR_FE) {
1424 flag = TTY_FRAME;
1425 port->icount.frame++;
1426 }
1427
1428 /* Clear error condition */
1429 psc_ops->command(port, MPC52xx_PSC_RST_ERR_STAT);
1430
1431 }
1432 tty_insert_flip_char(tport, ch, flag);
1433 if (status & MPC52xx_PSC_SR_OE) {
1434 /*
1435 * Overrun is special, since it's
1436 * reported immediately, and doesn't
1437 * affect the current character
1438 */
1439 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1440 port->icount.overrun++;
1441 }
1442 }
1443
1444 spin_unlock(&port->lock);
1445 tty_flip_buffer_push(tport);
1446 spin_lock(&port->lock);
1447
1448 return psc_ops->raw_rx_rdy(port);
1449}
1450
1451static inline int
1452mpc52xx_uart_int_tx_chars(struct uart_port *port)
1453{
1454 struct circ_buf *xmit = &port->state->xmit;
1455
1456 /* Process out of band chars */
1457 if (port->x_char) {
1458 psc_ops->write_char(port, port->x_char);
1459 port->icount.tx++;
1460 port->x_char = 0;
1461 return 1;
1462 }
1463
1464 /* Nothing to do ? */
1465 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
1466 mpc52xx_uart_stop_tx(port);
1467 return 0;
1468 }
1469
1470 /* Send chars */
1471 while (psc_ops->raw_tx_rdy(port)) {
1472 psc_ops->write_char(port, xmit->buf[xmit->tail]);
1473 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1474 port->icount.tx++;
1475 if (uart_circ_empty(xmit))
1476 break;
1477 }
1478
1479 /* Wake up */
1480 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1481 uart_write_wakeup(port);
1482
1483 /* Maybe we're done after all */
1484 if (uart_circ_empty(xmit)) {
1485 mpc52xx_uart_stop_tx(port);
1486 return 0;
1487 }
1488
1489 return 1;
1490}
1491
1492static irqreturn_t
1493mpc5xxx_uart_process_int(struct uart_port *port)
1494{
1495 unsigned long pass = ISR_PASS_LIMIT;
1496 unsigned int keepgoing;
1497 u8 status;
1498
1499 /* While we have stuff to do, we continue */
1500 do {
1501 /* If we don't find anything to do, we stop */
1502 keepgoing = 0;
1503
1504 psc_ops->rx_clr_irq(port);
1505 if (psc_ops->rx_rdy(port))
1506 keepgoing |= mpc52xx_uart_int_rx_chars(port);
1507
1508 psc_ops->tx_clr_irq(port);
1509 if (psc_ops->tx_rdy(port))
1510 keepgoing |= mpc52xx_uart_int_tx_chars(port);
1511
1512 status = psc_ops->get_ipcr(port);
1513 if (status & MPC52xx_PSC_D_DCD)
1514 uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD));
1515
1516 if (status & MPC52xx_PSC_D_CTS)
1517 uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS));
1518
1519 /* Limit number of iteration */
1520 if (!(--pass))
1521 keepgoing = 0;
1522
1523 } while (keepgoing);
1524
1525 return IRQ_HANDLED;
1526}
1527
1528static irqreturn_t
1529mpc52xx_uart_int(int irq, void *dev_id)
1530{
1531 struct uart_port *port = dev_id;
1532 irqreturn_t ret;
1533
1534 spin_lock(&port->lock);
1535
1536 ret = psc_ops->handle_irq(port);
1537
1538 spin_unlock(&port->lock);
1539
1540 return ret;
1541}
1542
1543/* ======================================================================== */
1544/* Console ( if applicable ) */
1545/* ======================================================================== */
1546
1547#ifdef CONFIG_SERIAL_MPC52xx_CONSOLE
1548
1549static void __init
1550mpc52xx_console_get_options(struct uart_port *port,
1551 int *baud, int *parity, int *bits, int *flow)
1552{
1553 unsigned char mr1;
1554
1555 pr_debug("mpc52xx_console_get_options(port=%p)\n", port);
1556
1557 /* Read the mode registers */
1558 mr1 = psc_ops->get_mr1(port);
1559
1560 /* CT{U,L}R are write-only ! */
1561 *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1562
1563 /* Parse them */
1564 switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) {
1565 case MPC52xx_PSC_MODE_5_BITS:
1566 *bits = 5;
1567 break;
1568 case MPC52xx_PSC_MODE_6_BITS:
1569 *bits = 6;
1570 break;
1571 case MPC52xx_PSC_MODE_7_BITS:
1572 *bits = 7;
1573 break;
1574 case MPC52xx_PSC_MODE_8_BITS:
1575 default:
1576 *bits = 8;
1577 }
1578
1579 if (mr1 & MPC52xx_PSC_MODE_PARNONE)
1580 *parity = 'n';
1581 else
1582 *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e';
1583}
1584
1585static void
1586mpc52xx_console_write(struct console *co, const char *s, unsigned int count)
1587{
1588 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1589 unsigned int i, j;
1590
1591 /* Disable interrupts */
1592 psc_ops->cw_disable_ints(port);
1593
1594 /* Wait the TX buffer to be empty */
1595 j = 5000000; /* Maximum wait */
1596 while (!mpc52xx_uart_tx_empty(port) && --j)
1597 udelay(1);
1598
1599 /* Write all the chars */
1600 for (i = 0; i < count; i++, s++) {
1601 /* Line return handling */
1602 if (*s == '\n')
1603 psc_ops->write_char(port, '\r');
1604
1605 /* Send the char */
1606 psc_ops->write_char(port, *s);
1607
1608 /* Wait the TX buffer to be empty */
1609 j = 20000; /* Maximum wait */
1610 while (!mpc52xx_uart_tx_empty(port) && --j)
1611 udelay(1);
1612 }
1613
1614 /* Restore interrupt state */
1615 psc_ops->cw_restore_ints(port);
1616}
1617
1618
1619static int __init
1620mpc52xx_console_setup(struct console *co, char *options)
1621{
1622 struct uart_port *port = &mpc52xx_uart_ports[co->index];
1623 struct device_node *np = mpc52xx_uart_nodes[co->index];
1624 unsigned int uartclk;
1625 struct resource res;
1626 int ret;
1627
1628 int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD;
1629 int bits = 8;
1630 int parity = 'n';
1631 int flow = 'n';
1632
1633 pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n",
1634 co, co->index, options);
1635
1636 if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) {
1637 pr_debug("PSC%x out of range\n", co->index);
1638 return -EINVAL;
1639 }
1640
1641 if (!np) {
1642 pr_debug("PSC%x not found in device tree\n", co->index);
1643 return -EINVAL;
1644 }
1645
1646 pr_debug("Console on ttyPSC%x is %s\n",
1647 co->index, mpc52xx_uart_nodes[co->index]->full_name);
1648
1649 /* Fetch register locations */
1650 ret = of_address_to_resource(np, 0, &res);
1651 if (ret) {
1652 pr_debug("Could not get resources for PSC%x\n", co->index);
1653 return ret;
1654 }
1655
1656 uartclk = mpc5xxx_get_bus_frequency(np);
1657 if (uartclk == 0) {
1658 pr_debug("Could not find uart clock frequency!\n");
1659 return -EINVAL;
1660 }
1661
1662 /* Basic port init. Needed since we use some uart_??? func before
1663 * real init for early access */
1664 spin_lock_init(&port->lock);
1665 port->uartclk = uartclk;
1666 port->ops = &mpc52xx_uart_ops;
1667 port->mapbase = res.start;
1668 port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc));
1669 port->irq = irq_of_parse_and_map(np, 0);
1670
1671 if (port->membase == NULL)
1672 return -EINVAL;
1673
1674 pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n",
1675 (void *)port->mapbase, port->membase,
1676 port->irq, port->uartclk);
1677
1678 /* Setup the port parameters accoding to options */
1679 if (options)
1680 uart_parse_options(options, &baud, &parity, &bits, &flow);
1681 else
1682 mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow);
1683
1684 pr_debug("Setting console parameters: %i %i%c1 flow=%c\n",
1685 baud, bits, parity, flow);
1686
1687 return uart_set_options(port, co, baud, parity, bits, flow);
1688}
1689
1690
1691static struct uart_driver mpc52xx_uart_driver;
1692
1693static struct console mpc52xx_console = {
1694 .name = "ttyPSC",
1695 .write = mpc52xx_console_write,
1696 .device = uart_console_device,
1697 .setup = mpc52xx_console_setup,
1698 .flags = CON_PRINTBUFFER,
1699 .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */
1700 .data = &mpc52xx_uart_driver,
1701};
1702
1703
1704static int __init
1705mpc52xx_console_init(void)
1706{
1707 mpc52xx_uart_of_enumerate();
1708 register_console(&mpc52xx_console);
1709 return 0;
1710}
1711
1712console_initcall(mpc52xx_console_init);
1713
1714#define MPC52xx_PSC_CONSOLE &mpc52xx_console
1715#else
1716#define MPC52xx_PSC_CONSOLE NULL
1717#endif
1718
1719
1720/* ======================================================================== */
1721/* UART Driver */
1722/* ======================================================================== */
1723
1724static struct uart_driver mpc52xx_uart_driver = {
1725 .driver_name = "mpc52xx_psc_uart",
1726 .dev_name = "ttyPSC",
1727 .major = SERIAL_PSC_MAJOR,
1728 .minor = SERIAL_PSC_MINOR,
1729 .nr = MPC52xx_PSC_MAXNUM,
1730 .cons = MPC52xx_PSC_CONSOLE,
1731};
1732
1733/* ======================================================================== */
1734/* OF Platform Driver */
1735/* ======================================================================== */
1736
1737static struct of_device_id mpc52xx_uart_of_match[] = {
1738#ifdef CONFIG_PPC_MPC52xx
1739 { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, },
1740 { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1741 /* binding used by old lite5200 device trees: */
1742 { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, },
1743 /* binding used by efika: */
1744 { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, },
1745#endif
1746#ifdef CONFIG_PPC_MPC512x
1747 { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, },
1748 { .compatible = "fsl,mpc5125-psc-uart", .data = &mpc5125_psc_ops, },
1749#endif
1750 {},
1751};
1752
1753static int mpc52xx_uart_of_probe(struct platform_device *op)
1754{
1755 int idx = -1;
1756 unsigned int uartclk;
1757 struct uart_port *port = NULL;
1758 struct resource res;
1759 int ret;
1760
1761 /* Check validity & presence */
1762 for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++)
1763 if (mpc52xx_uart_nodes[idx] == op->dev.of_node)
1764 break;
1765 if (idx >= MPC52xx_PSC_MAXNUM)
1766 return -EINVAL;
1767 pr_debug("Found %s assigned to ttyPSC%x\n",
1768 mpc52xx_uart_nodes[idx]->full_name, idx);
1769
1770 /* set the uart clock to the input clock of the psc, the different
1771 * prescalers are taken into account in the set_baudrate() methods
1772 * of the respective chip */
1773 uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node);
1774 if (uartclk == 0) {
1775 dev_dbg(&op->dev, "Could not find uart clock frequency!\n");
1776 return -EINVAL;
1777 }
1778
1779 /* Init the port structure */
1780 port = &mpc52xx_uart_ports[idx];
1781
1782 spin_lock_init(&port->lock);
1783 port->uartclk = uartclk;
1784 port->fifosize = 512;
1785 port->iotype = UPIO_MEM;
1786 port->flags = UPF_BOOT_AUTOCONF |
1787 (uart_console(port) ? 0 : UPF_IOREMAP);
1788 port->line = idx;
1789 port->ops = &mpc52xx_uart_ops;
1790 port->dev = &op->dev;
1791
1792 /* Search for IRQ and mapbase */
1793 ret = of_address_to_resource(op->dev.of_node, 0, &res);
1794 if (ret)
1795 return ret;
1796
1797 port->mapbase = res.start;
1798 if (!port->mapbase) {
1799 dev_dbg(&op->dev, "Could not allocate resources for PSC\n");
1800 return -EINVAL;
1801 }
1802
1803 psc_ops->get_irq(port, op->dev.of_node);
1804 if (port->irq == 0) {
1805 dev_dbg(&op->dev, "Could not get irq\n");
1806 return -EINVAL;
1807 }
1808
1809 dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n",
1810 (void *)port->mapbase, port->irq, port->uartclk);
1811
1812 /* Add the port to the uart sub-system */
1813 ret = uart_add_one_port(&mpc52xx_uart_driver, port);
1814 if (ret)
1815 return ret;
1816
1817 platform_set_drvdata(op, (void *)port);
1818 return 0;
1819}
1820
1821static int
1822mpc52xx_uart_of_remove(struct platform_device *op)
1823{
1824 struct uart_port *port = platform_get_drvdata(op);
1825
1826 if (port)
1827 uart_remove_one_port(&mpc52xx_uart_driver, port);
1828
1829 return 0;
1830}
1831
1832#ifdef CONFIG_PM
1833static int
1834mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state)
1835{
1836 struct uart_port *port = platform_get_drvdata(op);
1837
1838 if (port)
1839 uart_suspend_port(&mpc52xx_uart_driver, port);
1840
1841 return 0;
1842}
1843
1844static int
1845mpc52xx_uart_of_resume(struct platform_device *op)
1846{
1847 struct uart_port *port = platform_get_drvdata(op);
1848
1849 if (port)
1850 uart_resume_port(&mpc52xx_uart_driver, port);
1851
1852 return 0;
1853}
1854#endif
1855
1856static void
1857mpc52xx_uart_of_assign(struct device_node *np)
1858{
1859 int i;
1860
1861 /* Find the first free PSC number */
1862 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1863 if (mpc52xx_uart_nodes[i] == NULL) {
1864 of_node_get(np);
1865 mpc52xx_uart_nodes[i] = np;
1866 return;
1867 }
1868 }
1869}
1870
1871static void
1872mpc52xx_uart_of_enumerate(void)
1873{
1874 static int enum_done;
1875 struct device_node *np;
1876 const struct of_device_id *match;
1877 int i;
1878
1879 if (enum_done)
1880 return;
1881
1882 /* Assign index to each PSC in device tree */
1883 for_each_matching_node(np, mpc52xx_uart_of_match) {
1884 match = of_match_node(mpc52xx_uart_of_match, np);
1885 psc_ops = match->data;
1886 mpc52xx_uart_of_assign(np);
1887 }
1888
1889 enum_done = 1;
1890
1891 for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) {
1892 if (mpc52xx_uart_nodes[i])
1893 pr_debug("%s assigned to ttyPSC%x\n",
1894 mpc52xx_uart_nodes[i]->full_name, i);
1895 }
1896}
1897
1898MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match);
1899
1900static struct platform_driver mpc52xx_uart_of_driver = {
1901 .probe = mpc52xx_uart_of_probe,
1902 .remove = mpc52xx_uart_of_remove,
1903#ifdef CONFIG_PM
1904 .suspend = mpc52xx_uart_of_suspend,
1905 .resume = mpc52xx_uart_of_resume,
1906#endif
1907 .driver = {
1908 .name = "mpc52xx-psc-uart",
1909 .owner = THIS_MODULE,
1910 .of_match_table = mpc52xx_uart_of_match,
1911 },
1912};
1913
1914
1915/* ======================================================================== */
1916/* Module */
1917/* ======================================================================== */
1918
1919static int __init
1920mpc52xx_uart_init(void)
1921{
1922 int ret;
1923
1924 printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n");
1925
1926 ret = uart_register_driver(&mpc52xx_uart_driver);
1927 if (ret) {
1928 printk(KERN_ERR "%s: uart_register_driver failed (%i)\n",
1929 __FILE__, ret);
1930 return ret;
1931 }
1932
1933 mpc52xx_uart_of_enumerate();
1934
1935 /*
1936 * Map the PSC FIFO Controller and init if on MPC512x.
1937 */
1938 if (psc_ops && psc_ops->fifoc_init) {
1939 ret = psc_ops->fifoc_init();
1940 if (ret)
1941 goto err_init;
1942 }
1943
1944 ret = platform_driver_register(&mpc52xx_uart_of_driver);
1945 if (ret) {
1946 printk(KERN_ERR "%s: platform_driver_register failed (%i)\n",
1947 __FILE__, ret);
1948 goto err_reg;
1949 }
1950
1951 return 0;
1952err_reg:
1953 if (psc_ops && psc_ops->fifoc_uninit)
1954 psc_ops->fifoc_uninit();
1955err_init:
1956 uart_unregister_driver(&mpc52xx_uart_driver);
1957 return ret;
1958}
1959
1960static void __exit
1961mpc52xx_uart_exit(void)
1962{
1963 if (psc_ops->fifoc_uninit)
1964 psc_ops->fifoc_uninit();
1965
1966 platform_driver_unregister(&mpc52xx_uart_of_driver);
1967 uart_unregister_driver(&mpc52xx_uart_driver);
1968}
1969
1970
1971module_init(mpc52xx_uart_init);
1972module_exit(mpc52xx_uart_exit);
1973
1974MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
1975MODULE_DESCRIPTION("Freescale MPC52xx PSC UART");
1976MODULE_LICENSE("GPL");