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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for CLPS711x serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 */
10
11#include <linux/module.h>
12#include <linux/device.h>
13#include <linux/console.h>
14#include <linux/serial_core.h>
15#include <linux/serial.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/ioport.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/regmap.h>
24
25#include <linux/mfd/syscon.h>
26#include <linux/mfd/syscon/clps711x.h>
27
28#include "serial_mctrl_gpio.h"
29
30#define UART_CLPS711X_DEVNAME "ttyCL"
31#define UART_CLPS711X_NR 2
32#define UART_CLPS711X_MAJOR 204
33#define UART_CLPS711X_MINOR 40
34
35#define UARTDR_OFFSET (0x00)
36#define UBRLCR_OFFSET (0x40)
37
38#define UARTDR_FRMERR (1 << 8)
39#define UARTDR_PARERR (1 << 9)
40#define UARTDR_OVERR (1 << 10)
41
42#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
43#define UBRLCR_BREAK (1 << 12)
44#define UBRLCR_PRTEN (1 << 13)
45#define UBRLCR_EVENPRT (1 << 14)
46#define UBRLCR_XSTOP (1 << 15)
47#define UBRLCR_FIFOEN (1 << 16)
48#define UBRLCR_WRDLEN5 (0 << 17)
49#define UBRLCR_WRDLEN6 (1 << 17)
50#define UBRLCR_WRDLEN7 (2 << 17)
51#define UBRLCR_WRDLEN8 (3 << 17)
52#define UBRLCR_WRDLEN_MASK (3 << 17)
53
54struct clps711x_port {
55 struct uart_port port;
56 unsigned int tx_enabled;
57 int rx_irq;
58 struct regmap *syscon;
59 struct mctrl_gpios *gpios;
60};
61
62static struct uart_driver clps711x_uart = {
63 .owner = THIS_MODULE,
64 .driver_name = UART_CLPS711X_DEVNAME,
65 .dev_name = UART_CLPS711X_DEVNAME,
66 .major = UART_CLPS711X_MAJOR,
67 .minor = UART_CLPS711X_MINOR,
68 .nr = UART_CLPS711X_NR,
69};
70
71static void uart_clps711x_stop_tx(struct uart_port *port)
72{
73 struct clps711x_port *s = dev_get_drvdata(port->dev);
74
75 if (s->tx_enabled) {
76 disable_irq(port->irq);
77 s->tx_enabled = 0;
78 }
79}
80
81static void uart_clps711x_start_tx(struct uart_port *port)
82{
83 struct clps711x_port *s = dev_get_drvdata(port->dev);
84
85 if (!s->tx_enabled) {
86 s->tx_enabled = 1;
87 enable_irq(port->irq);
88 }
89}
90
91static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id)
92{
93 struct uart_port *port = dev_id;
94 struct clps711x_port *s = dev_get_drvdata(port->dev);
95 unsigned int status;
96 u16 ch;
97 u8 flg;
98
99 for (;;) {
100 u32 sysflg = 0;
101
102 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
103 if (sysflg & SYSFLG_URXFE)
104 break;
105
106 ch = readw(port->membase + UARTDR_OFFSET);
107 status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR);
108 ch &= 0xff;
109
110 port->icount.rx++;
111 flg = TTY_NORMAL;
112
113 if (unlikely(status)) {
114 if (status & UARTDR_PARERR)
115 port->icount.parity++;
116 else if (status & UARTDR_FRMERR)
117 port->icount.frame++;
118 else if (status & UARTDR_OVERR)
119 port->icount.overrun++;
120
121 status &= port->read_status_mask;
122
123 if (status & UARTDR_PARERR)
124 flg = TTY_PARITY;
125 else if (status & UARTDR_FRMERR)
126 flg = TTY_FRAME;
127 else if (status & UARTDR_OVERR)
128 flg = TTY_OVERRUN;
129 }
130
131 if (uart_handle_sysrq_char(port, ch))
132 continue;
133
134 if (status & port->ignore_status_mask)
135 continue;
136
137 uart_insert_char(port, status, UARTDR_OVERR, ch, flg);
138 }
139
140 tty_flip_buffer_push(&port->state->port);
141
142 return IRQ_HANDLED;
143}
144
145static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id)
146{
147 struct uart_port *port = dev_id;
148 struct clps711x_port *s = dev_get_drvdata(port->dev);
149 struct circ_buf *xmit = &port->state->xmit;
150
151 if (port->x_char) {
152 writew(port->x_char, port->membase + UARTDR_OFFSET);
153 port->icount.tx++;
154 port->x_char = 0;
155 return IRQ_HANDLED;
156 }
157
158 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
159 if (s->tx_enabled) {
160 disable_irq_nosync(port->irq);
161 s->tx_enabled = 0;
162 }
163 return IRQ_HANDLED;
164 }
165
166 while (!uart_circ_empty(xmit)) {
167 u32 sysflg = 0;
168
169 writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET);
170 uart_xmit_advance(port, 1);
171
172 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
173 if (sysflg & SYSFLG_UTXFF)
174 break;
175 }
176
177 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
178 uart_write_wakeup(port);
179
180 return IRQ_HANDLED;
181}
182
183static unsigned int uart_clps711x_tx_empty(struct uart_port *port)
184{
185 struct clps711x_port *s = dev_get_drvdata(port->dev);
186 u32 sysflg = 0;
187
188 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
189
190 return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT;
191}
192
193static unsigned int uart_clps711x_get_mctrl(struct uart_port *port)
194{
195 unsigned int result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
196 struct clps711x_port *s = dev_get_drvdata(port->dev);
197
198 return mctrl_gpio_get(s->gpios, &result);
199}
200
201static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl)
202{
203 struct clps711x_port *s = dev_get_drvdata(port->dev);
204
205 mctrl_gpio_set(s->gpios, mctrl);
206}
207
208static void uart_clps711x_break_ctl(struct uart_port *port, int break_state)
209{
210 unsigned int ubrlcr;
211
212 ubrlcr = readl(port->membase + UBRLCR_OFFSET);
213 if (break_state)
214 ubrlcr |= UBRLCR_BREAK;
215 else
216 ubrlcr &= ~UBRLCR_BREAK;
217 writel(ubrlcr, port->membase + UBRLCR_OFFSET);
218}
219
220static void uart_clps711x_set_ldisc(struct uart_port *port,
221 struct ktermios *termios)
222{
223 if (!port->line) {
224 struct clps711x_port *s = dev_get_drvdata(port->dev);
225
226 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON1_SIREN,
227 (termios->c_line == N_IRDA) ? SYSCON1_SIREN : 0);
228 }
229}
230
231static int uart_clps711x_startup(struct uart_port *port)
232{
233 struct clps711x_port *s = dev_get_drvdata(port->dev);
234
235 /* Disable break */
236 writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK,
237 port->membase + UBRLCR_OFFSET);
238
239 /* Enable the port */
240 return regmap_update_bits(s->syscon, SYSCON_OFFSET,
241 SYSCON_UARTEN, SYSCON_UARTEN);
242}
243
244static void uart_clps711x_shutdown(struct uart_port *port)
245{
246 struct clps711x_port *s = dev_get_drvdata(port->dev);
247
248 /* Disable the port */
249 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
250}
251
252static void uart_clps711x_set_termios(struct uart_port *port,
253 struct ktermios *termios,
254 const struct ktermios *old)
255{
256 u32 ubrlcr;
257 unsigned int baud, quot;
258
259 /* Mask termios capabilities we don't support */
260 termios->c_cflag &= ~CMSPAR;
261 termios->c_iflag &= ~(BRKINT | IGNBRK);
262
263 /* Ask the core to calculate the divisor for us */
264 baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096,
265 port->uartclk / 16);
266 quot = uart_get_divisor(port, baud);
267
268 switch (termios->c_cflag & CSIZE) {
269 case CS5:
270 ubrlcr = UBRLCR_WRDLEN5;
271 break;
272 case CS6:
273 ubrlcr = UBRLCR_WRDLEN6;
274 break;
275 case CS7:
276 ubrlcr = UBRLCR_WRDLEN7;
277 break;
278 case CS8:
279 default:
280 ubrlcr = UBRLCR_WRDLEN8;
281 break;
282 }
283
284 if (termios->c_cflag & CSTOPB)
285 ubrlcr |= UBRLCR_XSTOP;
286
287 if (termios->c_cflag & PARENB) {
288 ubrlcr |= UBRLCR_PRTEN;
289 if (!(termios->c_cflag & PARODD))
290 ubrlcr |= UBRLCR_EVENPRT;
291 }
292
293 /* Enable FIFO */
294 ubrlcr |= UBRLCR_FIFOEN;
295
296 /* Set read status mask */
297 port->read_status_mask = UARTDR_OVERR;
298 if (termios->c_iflag & INPCK)
299 port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;
300
301 /* Set status ignore mask */
302 port->ignore_status_mask = 0;
303 if (!(termios->c_cflag & CREAD))
304 port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR |
305 UARTDR_FRMERR;
306
307 uart_update_timeout(port, termios->c_cflag, baud);
308
309 writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET);
310}
311
312static const char *uart_clps711x_type(struct uart_port *port)
313{
314 return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL;
315}
316
317static void uart_clps711x_config_port(struct uart_port *port, int flags)
318{
319 if (flags & UART_CONFIG_TYPE)
320 port->type = PORT_CLPS711X;
321}
322
323static void uart_clps711x_nop_void(struct uart_port *port)
324{
325}
326
327static int uart_clps711x_nop_int(struct uart_port *port)
328{
329 return 0;
330}
331
332static const struct uart_ops uart_clps711x_ops = {
333 .tx_empty = uart_clps711x_tx_empty,
334 .set_mctrl = uart_clps711x_set_mctrl,
335 .get_mctrl = uart_clps711x_get_mctrl,
336 .stop_tx = uart_clps711x_stop_tx,
337 .start_tx = uart_clps711x_start_tx,
338 .stop_rx = uart_clps711x_nop_void,
339 .break_ctl = uart_clps711x_break_ctl,
340 .set_ldisc = uart_clps711x_set_ldisc,
341 .startup = uart_clps711x_startup,
342 .shutdown = uart_clps711x_shutdown,
343 .set_termios = uart_clps711x_set_termios,
344 .type = uart_clps711x_type,
345 .config_port = uart_clps711x_config_port,
346 .release_port = uart_clps711x_nop_void,
347 .request_port = uart_clps711x_nop_int,
348};
349
350#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
351static void uart_clps711x_console_putchar(struct uart_port *port, unsigned char ch)
352{
353 struct clps711x_port *s = dev_get_drvdata(port->dev);
354 u32 sysflg = 0;
355
356 /* Wait for FIFO is not full */
357 do {
358 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
359 } while (sysflg & SYSFLG_UTXFF);
360
361 writew(ch, port->membase + UARTDR_OFFSET);
362}
363
364static void uart_clps711x_console_write(struct console *co, const char *c,
365 unsigned n)
366{
367 struct uart_port *port = clps711x_uart.state[co->index].uart_port;
368 struct clps711x_port *s = dev_get_drvdata(port->dev);
369 u32 sysflg = 0;
370
371 uart_console_write(port, c, n, uart_clps711x_console_putchar);
372
373 /* Wait for transmitter to become empty */
374 do {
375 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
376 } while (sysflg & SYSFLG_UBUSY);
377}
378
379static int uart_clps711x_console_setup(struct console *co, char *options)
380{
381 int baud = 38400, bits = 8, parity = 'n', flow = 'n';
382 int ret, index = co->index;
383 struct clps711x_port *s;
384 struct uart_port *port;
385 unsigned int quot;
386 u32 ubrlcr;
387
388 if (index < 0 || index >= UART_CLPS711X_NR)
389 return -EINVAL;
390
391 port = clps711x_uart.state[index].uart_port;
392 if (!port)
393 return -ENODEV;
394
395 s = dev_get_drvdata(port->dev);
396
397 if (!options) {
398 u32 syscon = 0;
399
400 regmap_read(s->syscon, SYSCON_OFFSET, &syscon);
401 if (syscon & SYSCON_UARTEN) {
402 ubrlcr = readl(port->membase + UBRLCR_OFFSET);
403
404 if (ubrlcr & UBRLCR_PRTEN) {
405 if (ubrlcr & UBRLCR_EVENPRT)
406 parity = 'e';
407 else
408 parity = 'o';
409 }
410
411 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
412 bits = 7;
413
414 quot = ubrlcr & UBRLCR_BAUD_MASK;
415 baud = port->uartclk / (16 * (quot + 1));
416 }
417 } else
418 uart_parse_options(options, &baud, &parity, &bits, &flow);
419
420 ret = uart_set_options(port, co, baud, parity, bits, flow);
421 if (ret)
422 return ret;
423
424 return regmap_update_bits(s->syscon, SYSCON_OFFSET,
425 SYSCON_UARTEN, SYSCON_UARTEN);
426}
427
428static struct console clps711x_console = {
429 .name = UART_CLPS711X_DEVNAME,
430 .device = uart_console_device,
431 .write = uart_clps711x_console_write,
432 .setup = uart_clps711x_console_setup,
433 .flags = CON_PRINTBUFFER,
434 .index = -1,
435};
436#endif
437
438static int uart_clps711x_probe(struct platform_device *pdev)
439{
440 struct device_node *np = pdev->dev.of_node;
441 struct clps711x_port *s;
442 struct resource *res;
443 struct clk *uart_clk;
444 int irq, ret;
445
446 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
447 if (!s)
448 return -ENOMEM;
449
450 uart_clk = devm_clk_get(&pdev->dev, NULL);
451 if (IS_ERR(uart_clk))
452 return PTR_ERR(uart_clk);
453
454 s->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
455 if (IS_ERR(s->port.membase))
456 return PTR_ERR(s->port.membase);
457
458 irq = platform_get_irq(pdev, 0);
459 if (irq < 0)
460 return irq;
461 s->port.irq = irq;
462
463 s->rx_irq = platform_get_irq(pdev, 1);
464 if (s->rx_irq < 0)
465 return s->rx_irq;
466
467 s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon");
468 if (IS_ERR(s->syscon))
469 return PTR_ERR(s->syscon);
470
471 s->port.line = of_alias_get_id(np, "serial");
472 s->port.dev = &pdev->dev;
473 s->port.iotype = UPIO_MEM32;
474 s->port.mapbase = res->start;
475 s->port.type = PORT_CLPS711X;
476 s->port.fifosize = 16;
477 s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CLPS711X_CONSOLE);
478 s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
479 s->port.uartclk = clk_get_rate(uart_clk);
480 s->port.ops = &uart_clps711x_ops;
481
482 platform_set_drvdata(pdev, s);
483
484 s->gpios = mctrl_gpio_init_noauto(&pdev->dev, 0);
485 if (IS_ERR(s->gpios))
486 return PTR_ERR(s->gpios);
487
488 ret = uart_add_one_port(&clps711x_uart, &s->port);
489 if (ret)
490 return ret;
491
492 /* Disable port */
493 if (!uart_console(&s->port))
494 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
495
496 s->tx_enabled = 1;
497
498 ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0,
499 dev_name(&pdev->dev), &s->port);
500 if (ret) {
501 uart_remove_one_port(&clps711x_uart, &s->port);
502 return ret;
503 }
504
505 ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0,
506 dev_name(&pdev->dev), &s->port);
507 if (ret)
508 uart_remove_one_port(&clps711x_uart, &s->port);
509
510 return ret;
511}
512
513static void uart_clps711x_remove(struct platform_device *pdev)
514{
515 struct clps711x_port *s = platform_get_drvdata(pdev);
516
517 uart_remove_one_port(&clps711x_uart, &s->port);
518}
519
520static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = {
521 { .compatible = "cirrus,ep7209-uart", },
522 { }
523};
524MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids);
525
526static struct platform_driver clps711x_uart_platform = {
527 .driver = {
528 .name = "clps711x-uart",
529 .of_match_table = of_match_ptr(clps711x_uart_dt_ids),
530 },
531 .probe = uart_clps711x_probe,
532 .remove_new = uart_clps711x_remove,
533};
534
535static int __init uart_clps711x_init(void)
536{
537 int ret;
538
539#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
540 clps711x_uart.cons = &clps711x_console;
541 clps711x_console.data = &clps711x_uart;
542#endif
543
544 ret = uart_register_driver(&clps711x_uart);
545 if (ret)
546 return ret;
547
548 return platform_driver_register(&clps711x_uart_platform);
549}
550module_init(uart_clps711x_init);
551
552static void __exit uart_clps711x_exit(void)
553{
554 platform_driver_unregister(&clps711x_uart_platform);
555 uart_unregister_driver(&clps711x_uart);
556}
557module_exit(uart_clps711x_exit);
558
559MODULE_AUTHOR("Deep Blue Solutions Ltd");
560MODULE_DESCRIPTION("CLPS711X serial driver");
561MODULE_LICENSE("GPL");
1/*
2 * Driver for CLPS711x serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#if defined(CONFIG_SERIAL_CLPS711X_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16#define SUPPORT_SYSRQ
17#endif
18
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/console.h>
22#include <linux/serial_core.h>
23#include <linux/serial.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/ioport.h>
29#include <linux/of.h>
30#include <linux/platform_device.h>
31#include <linux/regmap.h>
32
33#include <linux/mfd/syscon.h>
34#include <linux/mfd/syscon/clps711x.h>
35
36#define UART_CLPS711X_DEVNAME "ttyCL"
37#define UART_CLPS711X_NR 2
38#define UART_CLPS711X_MAJOR 204
39#define UART_CLPS711X_MINOR 40
40
41#define UARTDR_OFFSET (0x00)
42#define UBRLCR_OFFSET (0x40)
43
44#define UARTDR_FRMERR (1 << 8)
45#define UARTDR_PARERR (1 << 9)
46#define UARTDR_OVERR (1 << 10)
47
48#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
49#define UBRLCR_BREAK (1 << 12)
50#define UBRLCR_PRTEN (1 << 13)
51#define UBRLCR_EVENPRT (1 << 14)
52#define UBRLCR_XSTOP (1 << 15)
53#define UBRLCR_FIFOEN (1 << 16)
54#define UBRLCR_WRDLEN5 (0 << 17)
55#define UBRLCR_WRDLEN6 (1 << 17)
56#define UBRLCR_WRDLEN7 (2 << 17)
57#define UBRLCR_WRDLEN8 (3 << 17)
58#define UBRLCR_WRDLEN_MASK (3 << 17)
59
60struct clps711x_port {
61 struct uart_port port;
62 unsigned int tx_enabled;
63 int rx_irq;
64 struct regmap *syscon;
65 bool use_ms;
66};
67
68static struct uart_driver clps711x_uart = {
69 .owner = THIS_MODULE,
70 .driver_name = UART_CLPS711X_DEVNAME,
71 .dev_name = UART_CLPS711X_DEVNAME,
72 .major = UART_CLPS711X_MAJOR,
73 .minor = UART_CLPS711X_MINOR,
74 .nr = UART_CLPS711X_NR,
75};
76
77static void uart_clps711x_stop_tx(struct uart_port *port)
78{
79 struct clps711x_port *s = dev_get_drvdata(port->dev);
80
81 if (s->tx_enabled) {
82 disable_irq(port->irq);
83 s->tx_enabled = 0;
84 }
85}
86
87static void uart_clps711x_start_tx(struct uart_port *port)
88{
89 struct clps711x_port *s = dev_get_drvdata(port->dev);
90
91 if (!s->tx_enabled) {
92 s->tx_enabled = 1;
93 enable_irq(port->irq);
94 }
95}
96
97static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id)
98{
99 struct uart_port *port = dev_id;
100 struct clps711x_port *s = dev_get_drvdata(port->dev);
101 unsigned int status, flg;
102 u16 ch;
103
104 for (;;) {
105 u32 sysflg = 0;
106
107 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
108 if (sysflg & SYSFLG_URXFE)
109 break;
110
111 ch = readw(port->membase + UARTDR_OFFSET);
112 status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR);
113 ch &= 0xff;
114
115 port->icount.rx++;
116 flg = TTY_NORMAL;
117
118 if (unlikely(status)) {
119 if (status & UARTDR_PARERR)
120 port->icount.parity++;
121 else if (status & UARTDR_FRMERR)
122 port->icount.frame++;
123 else if (status & UARTDR_OVERR)
124 port->icount.overrun++;
125
126 status &= port->read_status_mask;
127
128 if (status & UARTDR_PARERR)
129 flg = TTY_PARITY;
130 else if (status & UARTDR_FRMERR)
131 flg = TTY_FRAME;
132 else if (status & UARTDR_OVERR)
133 flg = TTY_OVERRUN;
134 }
135
136 if (uart_handle_sysrq_char(port, ch))
137 continue;
138
139 if (status & port->ignore_status_mask)
140 continue;
141
142 uart_insert_char(port, status, UARTDR_OVERR, ch, flg);
143 }
144
145 tty_flip_buffer_push(&port->state->port);
146
147 return IRQ_HANDLED;
148}
149
150static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id)
151{
152 struct uart_port *port = dev_id;
153 struct clps711x_port *s = dev_get_drvdata(port->dev);
154 struct circ_buf *xmit = &port->state->xmit;
155
156 if (port->x_char) {
157 writew(port->x_char, port->membase + UARTDR_OFFSET);
158 port->icount.tx++;
159 port->x_char = 0;
160 return IRQ_HANDLED;
161 }
162
163 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
164 if (s->tx_enabled) {
165 disable_irq_nosync(port->irq);
166 s->tx_enabled = 0;
167 }
168 return IRQ_HANDLED;
169 }
170
171 while (!uart_circ_empty(xmit)) {
172 u32 sysflg = 0;
173
174 writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET);
175 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
176 port->icount.tx++;
177
178 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
179 if (sysflg & SYSFLG_UTXFF)
180 break;
181 }
182
183 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
184 uart_write_wakeup(port);
185
186 return IRQ_HANDLED;
187}
188
189static unsigned int uart_clps711x_tx_empty(struct uart_port *port)
190{
191 struct clps711x_port *s = dev_get_drvdata(port->dev);
192 u32 sysflg = 0;
193
194 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
195
196 return (sysflg & SYSFLG_UBUSY) ? 0 : TIOCSER_TEMT;
197}
198
199static unsigned int uart_clps711x_get_mctrl(struct uart_port *port)
200{
201 struct clps711x_port *s = dev_get_drvdata(port->dev);
202 unsigned int result = 0;
203
204 if (s->use_ms) {
205 u32 sysflg = 0;
206
207 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
208 if (sysflg & SYSFLG1_DCD)
209 result |= TIOCM_CAR;
210 if (sysflg & SYSFLG1_DSR)
211 result |= TIOCM_DSR;
212 if (sysflg & SYSFLG1_CTS)
213 result |= TIOCM_CTS;
214 } else
215 result = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
216
217 return result;
218}
219
220static void uart_clps711x_set_mctrl(struct uart_port *port, unsigned int mctrl)
221{
222 /* Do nothing */
223}
224
225static void uart_clps711x_break_ctl(struct uart_port *port, int break_state)
226{
227 unsigned int ubrlcr;
228
229 ubrlcr = readl(port->membase + UBRLCR_OFFSET);
230 if (break_state)
231 ubrlcr |= UBRLCR_BREAK;
232 else
233 ubrlcr &= ~UBRLCR_BREAK;
234 writel(ubrlcr, port->membase + UBRLCR_OFFSET);
235}
236
237static void uart_clps711x_set_ldisc(struct uart_port *port, int ld)
238{
239 if (!port->line) {
240 struct clps711x_port *s = dev_get_drvdata(port->dev);
241
242 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON1_SIREN,
243 (ld == N_IRDA) ? SYSCON1_SIREN : 0);
244 }
245}
246
247static int uart_clps711x_startup(struct uart_port *port)
248{
249 struct clps711x_port *s = dev_get_drvdata(port->dev);
250
251 /* Disable break */
252 writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK,
253 port->membase + UBRLCR_OFFSET);
254
255 /* Enable the port */
256 return regmap_update_bits(s->syscon, SYSCON_OFFSET,
257 SYSCON_UARTEN, SYSCON_UARTEN);
258}
259
260static void uart_clps711x_shutdown(struct uart_port *port)
261{
262 struct clps711x_port *s = dev_get_drvdata(port->dev);
263
264 /* Disable the port */
265 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
266}
267
268static void uart_clps711x_set_termios(struct uart_port *port,
269 struct ktermios *termios,
270 struct ktermios *old)
271{
272 u32 ubrlcr;
273 unsigned int baud, quot;
274
275 /* Mask termios capabilities we don't support */
276 termios->c_cflag &= ~CMSPAR;
277 termios->c_iflag &= ~(BRKINT | IGNBRK);
278
279 /* Ask the core to calculate the divisor for us */
280 baud = uart_get_baud_rate(port, termios, old, port->uartclk / 4096,
281 port->uartclk / 16);
282 quot = uart_get_divisor(port, baud);
283
284 switch (termios->c_cflag & CSIZE) {
285 case CS5:
286 ubrlcr = UBRLCR_WRDLEN5;
287 break;
288 case CS6:
289 ubrlcr = UBRLCR_WRDLEN6;
290 break;
291 case CS7:
292 ubrlcr = UBRLCR_WRDLEN7;
293 break;
294 case CS8:
295 default:
296 ubrlcr = UBRLCR_WRDLEN8;
297 break;
298 }
299
300 if (termios->c_cflag & CSTOPB)
301 ubrlcr |= UBRLCR_XSTOP;
302
303 if (termios->c_cflag & PARENB) {
304 ubrlcr |= UBRLCR_PRTEN;
305 if (!(termios->c_cflag & PARODD))
306 ubrlcr |= UBRLCR_EVENPRT;
307 }
308
309 /* Enable FIFO */
310 ubrlcr |= UBRLCR_FIFOEN;
311
312 /* Set read status mask */
313 port->read_status_mask = UARTDR_OVERR;
314 if (termios->c_iflag & INPCK)
315 port->read_status_mask |= UARTDR_PARERR | UARTDR_FRMERR;
316
317 /* Set status ignore mask */
318 port->ignore_status_mask = 0;
319 if (!(termios->c_cflag & CREAD))
320 port->ignore_status_mask |= UARTDR_OVERR | UARTDR_PARERR |
321 UARTDR_FRMERR;
322
323 uart_update_timeout(port, termios->c_cflag, baud);
324
325 writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET);
326}
327
328static const char *uart_clps711x_type(struct uart_port *port)
329{
330 return (port->type == PORT_CLPS711X) ? "CLPS711X" : NULL;
331}
332
333static void uart_clps711x_config_port(struct uart_port *port, int flags)
334{
335 if (flags & UART_CONFIG_TYPE)
336 port->type = PORT_CLPS711X;
337}
338
339static void uart_clps711x_nop_void(struct uart_port *port)
340{
341}
342
343static int uart_clps711x_nop_int(struct uart_port *port)
344{
345 return 0;
346}
347
348static const struct uart_ops uart_clps711x_ops = {
349 .tx_empty = uart_clps711x_tx_empty,
350 .set_mctrl = uart_clps711x_set_mctrl,
351 .get_mctrl = uart_clps711x_get_mctrl,
352 .stop_tx = uart_clps711x_stop_tx,
353 .start_tx = uart_clps711x_start_tx,
354 .stop_rx = uart_clps711x_nop_void,
355 .enable_ms = uart_clps711x_nop_void,
356 .break_ctl = uart_clps711x_break_ctl,
357 .set_ldisc = uart_clps711x_set_ldisc,
358 .startup = uart_clps711x_startup,
359 .shutdown = uart_clps711x_shutdown,
360 .set_termios = uart_clps711x_set_termios,
361 .type = uart_clps711x_type,
362 .config_port = uart_clps711x_config_port,
363 .release_port = uart_clps711x_nop_void,
364 .request_port = uart_clps711x_nop_int,
365};
366
367#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
368static void uart_clps711x_console_putchar(struct uart_port *port, int ch)
369{
370 struct clps711x_port *s = dev_get_drvdata(port->dev);
371 u32 sysflg = 0;
372
373 /* Wait for FIFO is not full */
374 do {
375 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
376 } while (sysflg & SYSFLG_UTXFF);
377
378 writew(ch, port->membase + UARTDR_OFFSET);
379}
380
381static void uart_clps711x_console_write(struct console *co, const char *c,
382 unsigned n)
383{
384 struct uart_port *port = clps711x_uart.state[co->index].uart_port;
385 struct clps711x_port *s = dev_get_drvdata(port->dev);
386 u32 sysflg = 0;
387
388 uart_console_write(port, c, n, uart_clps711x_console_putchar);
389
390 /* Wait for transmitter to become empty */
391 do {
392 regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg);
393 } while (sysflg & SYSFLG_UBUSY);
394}
395
396static int uart_clps711x_console_setup(struct console *co, char *options)
397{
398 int baud = 38400, bits = 8, parity = 'n', flow = 'n';
399 int ret, index = co->index;
400 struct clps711x_port *s;
401 struct uart_port *port;
402 unsigned int quot;
403 u32 ubrlcr;
404
405 if (index < 0 || index >= UART_CLPS711X_NR)
406 return -EINVAL;
407
408 port = clps711x_uart.state[index].uart_port;
409 if (!port)
410 return -ENODEV;
411
412 s = dev_get_drvdata(port->dev);
413
414 if (!options) {
415 u32 syscon = 0;
416
417 regmap_read(s->syscon, SYSCON_OFFSET, &syscon);
418 if (syscon & SYSCON_UARTEN) {
419 ubrlcr = readl(port->membase + UBRLCR_OFFSET);
420
421 if (ubrlcr & UBRLCR_PRTEN) {
422 if (ubrlcr & UBRLCR_EVENPRT)
423 parity = 'e';
424 else
425 parity = 'o';
426 }
427
428 if ((ubrlcr & UBRLCR_WRDLEN_MASK) == UBRLCR_WRDLEN7)
429 bits = 7;
430
431 quot = ubrlcr & UBRLCR_BAUD_MASK;
432 baud = port->uartclk / (16 * (quot + 1));
433 }
434 } else
435 uart_parse_options(options, &baud, &parity, &bits, &flow);
436
437 ret = uart_set_options(port, co, baud, parity, bits, flow);
438 if (ret)
439 return ret;
440
441 return regmap_update_bits(s->syscon, SYSCON_OFFSET,
442 SYSCON_UARTEN, SYSCON_UARTEN);
443}
444
445static struct console clps711x_console = {
446 .name = UART_CLPS711X_DEVNAME,
447 .device = uart_console_device,
448 .write = uart_clps711x_console_write,
449 .setup = uart_clps711x_console_setup,
450 .flags = CON_PRINTBUFFER,
451 .index = -1,
452};
453#endif
454
455static int uart_clps711x_probe(struct platform_device *pdev)
456{
457 struct device_node *np = pdev->dev.of_node;
458 int ret, index = np ? of_alias_get_id(np, "serial") : pdev->id;
459 struct clps711x_port *s;
460 struct resource *res;
461 struct clk *uart_clk;
462
463 if (index < 0 || index >= UART_CLPS711X_NR)
464 return -EINVAL;
465
466 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
467 if (!s)
468 return -ENOMEM;
469
470 uart_clk = devm_clk_get(&pdev->dev, NULL);
471 if (IS_ERR(uart_clk))
472 return PTR_ERR(uart_clk);
473
474 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
475 s->port.membase = devm_ioremap_resource(&pdev->dev, res);
476 if (IS_ERR(s->port.membase))
477 return PTR_ERR(s->port.membase);
478
479 s->port.irq = platform_get_irq(pdev, 0);
480 if (IS_ERR_VALUE(s->port.irq))
481 return s->port.irq;
482
483 s->rx_irq = platform_get_irq(pdev, 1);
484 if (IS_ERR_VALUE(s->rx_irq))
485 return s->rx_irq;
486
487 if (!np) {
488 char syscon_name[9];
489
490 sprintf(syscon_name, "syscon.%i", index + 1);
491 s->syscon = syscon_regmap_lookup_by_pdevname(syscon_name);
492 if (IS_ERR(s->syscon))
493 return PTR_ERR(s->syscon);
494
495 s->use_ms = !index;
496 } else {
497 s->syscon = syscon_regmap_lookup_by_phandle(np, "syscon");
498 if (IS_ERR(s->syscon))
499 return PTR_ERR(s->syscon);
500
501 if (!index)
502 s->use_ms = of_property_read_bool(np, "uart-use-ms");
503 }
504
505 s->port.line = index;
506 s->port.dev = &pdev->dev;
507 s->port.iotype = UPIO_MEM32;
508 s->port.mapbase = res->start;
509 s->port.type = PORT_CLPS711X;
510 s->port.fifosize = 16;
511 s->port.flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
512 s->port.uartclk = clk_get_rate(uart_clk);
513 s->port.ops = &uart_clps711x_ops;
514
515 platform_set_drvdata(pdev, s);
516
517 ret = uart_add_one_port(&clps711x_uart, &s->port);
518 if (ret)
519 return ret;
520
521 /* Disable port */
522 if (!uart_console(&s->port))
523 regmap_update_bits(s->syscon, SYSCON_OFFSET, SYSCON_UARTEN, 0);
524
525 s->tx_enabled = 1;
526
527 ret = devm_request_irq(&pdev->dev, s->port.irq, uart_clps711x_int_tx, 0,
528 dev_name(&pdev->dev), &s->port);
529 if (ret) {
530 uart_remove_one_port(&clps711x_uart, &s->port);
531 return ret;
532 }
533
534 ret = devm_request_irq(&pdev->dev, s->rx_irq, uart_clps711x_int_rx, 0,
535 dev_name(&pdev->dev), &s->port);
536 if (ret)
537 uart_remove_one_port(&clps711x_uart, &s->port);
538
539 return ret;
540}
541
542static int uart_clps711x_remove(struct platform_device *pdev)
543{
544 struct clps711x_port *s = platform_get_drvdata(pdev);
545
546 return uart_remove_one_port(&clps711x_uart, &s->port);
547}
548
549static const struct of_device_id __maybe_unused clps711x_uart_dt_ids[] = {
550 { .compatible = "cirrus,clps711x-uart", },
551 { }
552};
553MODULE_DEVICE_TABLE(of, clps711x_uart_dt_ids);
554
555static struct platform_driver clps711x_uart_platform = {
556 .driver = {
557 .name = "clps711x-uart",
558 .owner = THIS_MODULE,
559 .of_match_table = of_match_ptr(clps711x_uart_dt_ids),
560 },
561 .probe = uart_clps711x_probe,
562 .remove = uart_clps711x_remove,
563};
564
565static int __init uart_clps711x_init(void)
566{
567 int ret;
568
569#ifdef CONFIG_SERIAL_CLPS711X_CONSOLE
570 clps711x_uart.cons = &clps711x_console;
571 clps711x_console.data = &clps711x_uart;
572#endif
573
574 ret = uart_register_driver(&clps711x_uart);
575 if (ret)
576 return ret;
577
578 return platform_driver_register(&clps711x_uart_platform);
579}
580module_init(uart_clps711x_init);
581
582static void __exit uart_clps711x_exit(void)
583{
584 platform_driver_unregister(&clps711x_uart_platform);
585 uart_unregister_driver(&clps711x_uart);
586}
587module_exit(uart_clps711x_exit);
588
589MODULE_AUTHOR("Deep Blue Solutions Ltd");
590MODULE_DESCRIPTION("CLPS711X serial driver");
591MODULE_LICENSE("GPL");