1/*
  2 * Copyright (c) 2006 Ben Dooks
  3 * Copyright 2006-2009 Simtec Electronics
  4 *	Ben Dooks <ben@simtec.co.uk>
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 *
 10*/
 11
 12#include <linux/spinlock.h>
 13#include <linux/workqueue.h>
 14#include <linux/interrupt.h>
 15#include <linux/delay.h>
 16#include <linux/errno.h>
 17#include <linux/err.h>
 18#include <linux/clk.h>
 19#include <linux/platform_device.h>
 20#include <linux/gpio.h>
 21#include <linux/io.h>
 22#include <linux/slab.h>
 23
 24#include <linux/spi/spi.h>
 25#include <linux/spi/spi_bitbang.h>
 26#include <linux/spi/s3c24xx.h>
 27#include <linux/module.h>
 28
 29#include <plat/regs-spi.h>
 30
 31#include <asm/fiq.h>
 32
 33#include "spi-s3c24xx-fiq.h"
 34
 35/**
 36 * s3c24xx_spi_devstate - per device data
 37 * @hz: Last frequency calculated for @sppre field.
 38 * @mode: Last mode setting for the @spcon field.
 39 * @spcon: Value to write to the SPCON register.
 40 * @sppre: Value to write to the SPPRE register.
 41 */
 42struct s3c24xx_spi_devstate {
 43	unsigned int	hz;
 44	unsigned int	mode;
 45	u8		spcon;
 46	u8		sppre;
 47};
 48
 49enum spi_fiq_mode {
 50	FIQ_MODE_NONE	= 0,
 51	FIQ_MODE_TX	= 1,
 52	FIQ_MODE_RX	= 2,
 53	FIQ_MODE_TXRX	= 3,
 54};
 55
 56struct s3c24xx_spi {
 57	/* bitbang has to be first */
 58	struct spi_bitbang	 bitbang;
 59	struct completion	 done;
 60
 61	void __iomem		*regs;
 62	int			 irq;
 63	int			 len;
 64	int			 count;
 65
 66	struct fiq_handler	 fiq_handler;
 67	enum spi_fiq_mode	 fiq_mode;
 68	unsigned char		 fiq_inuse;
 69	unsigned char		 fiq_claimed;
 70
 71	void			(*set_cs)(struct s3c2410_spi_info *spi,
 72					  int cs, int pol);
 73
 74	/* data buffers */
 75	const unsigned char	*tx;
 76	unsigned char		*rx;
 77
 78	struct clk		*clk;
 79	struct spi_master	*master;
 80	struct spi_device	*curdev;
 81	struct device		*dev;
 82	struct s3c2410_spi_info *pdata;
 83};
 84
 85#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
 86#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
 87
 88static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
 89{
 90	return spi_master_get_devdata(sdev->master);
 91}
 92
 93static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
 94{
 95	gpio_set_value(spi->pin_cs, pol);
 96}
 97
 98static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
 99{
100	struct s3c24xx_spi_devstate *cs = spi->controller_state;
101	struct s3c24xx_spi *hw = to_hw(spi);
102	unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
103
104	/* change the chipselect state and the state of the spi engine clock */
105
106	switch (value) {
107	case BITBANG_CS_INACTIVE:
108		hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
109		writeb(cs->spcon, hw->regs + S3C2410_SPCON);
110		break;
111
112	case BITBANG_CS_ACTIVE:
113		writeb(cs->spcon | S3C2410_SPCON_ENSCK,
114		       hw->regs + S3C2410_SPCON);
115		hw->set_cs(hw->pdata, spi->chip_select, cspol);
116		break;
117	}
118}
119
120static int s3c24xx_spi_update_state(struct spi_device *spi,
121				    struct spi_transfer *t)
122{
123	struct s3c24xx_spi *hw = to_hw(spi);
124	struct s3c24xx_spi_devstate *cs = spi->controller_state;
125	unsigned int hz;
126	unsigned int div;
127	unsigned long clk;
128
129	hz  = t ? t->speed_hz : spi->max_speed_hz;
130
131	if (!hz)
132		hz = spi->max_speed_hz;
133
134	if (spi->mode != cs->mode) {
135		u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
136
137		if (spi->mode & SPI_CPHA)
138			spcon |= S3C2410_SPCON_CPHA_FMTB;
139
140		if (spi->mode & SPI_CPOL)
141			spcon |= S3C2410_SPCON_CPOL_HIGH;
142
143		cs->mode = spi->mode;
144		cs->spcon = spcon;
145	}
146
147	if (cs->hz != hz) {
148		clk = clk_get_rate(hw->clk);
149		div = DIV_ROUND_UP(clk, hz * 2) - 1;
150
151		if (div > 255)
152			div = 255;
153
154		dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
155			div, hz, clk / (2 * (div + 1)));
156
157		cs->hz = hz;
158		cs->sppre = div;
159	}
160
161	return 0;
162}
163
164static int s3c24xx_spi_setupxfer(struct spi_device *spi,
165				 struct spi_transfer *t)
166{
167	struct s3c24xx_spi_devstate *cs = spi->controller_state;
168	struct s3c24xx_spi *hw = to_hw(spi);
169	int ret;
170
171	ret = s3c24xx_spi_update_state(spi, t);
172	if (!ret)
173		writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
174
175	return ret;
176}
177
178static int s3c24xx_spi_setup(struct spi_device *spi)
179{
180	struct s3c24xx_spi_devstate *cs = spi->controller_state;
181	struct s3c24xx_spi *hw = to_hw(spi);
182	int ret;
183
184	/* allocate settings on the first call */
185	if (!cs) {
186		cs = kzalloc(sizeof(struct s3c24xx_spi_devstate), GFP_KERNEL);
187		if (!cs) {
188			dev_err(&spi->dev, "no memory for controller state\n");
189			return -ENOMEM;
190		}
191
192		cs->spcon = SPCON_DEFAULT;
193		cs->hz = -1;
194		spi->controller_state = cs;
195	}
196
197	/* initialise the state from the device */
198	ret = s3c24xx_spi_update_state(spi, NULL);
199	if (ret)
200		return ret;
201
202	spin_lock(&hw->bitbang.lock);
203	if (!hw->bitbang.busy) {
204		hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
205		/* need to ndelay for 0.5 clocktick ? */
206	}
207	spin_unlock(&hw->bitbang.lock);
208
209	return 0;
210}
211
212static void s3c24xx_spi_cleanup(struct spi_device *spi)
213{
214	kfree(spi->controller_state);
215}
216
217static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
218{
219	return hw->tx ? hw->tx[count] : 0;
220}
221
222#ifdef CONFIG_SPI_S3C24XX_FIQ
223/* Support for FIQ based pseudo-DMA to improve the transfer speed.
224 *
225 * This code uses the assembly helper in spi_s3c24xx_spi.S which is
226 * used by the FIQ core to move data between main memory and the peripheral
227 * block. Since this is code running on the processor, there is no problem
228 * with cache coherency of the buffers, so we can use any buffer we like.
229 */
230
231/**
232 * struct spi_fiq_code - FIQ code and header
233 * @length: The length of the code fragment, excluding this header.
234 * @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
235 * @data: The code itself to install as a FIQ handler.
236 */
237struct spi_fiq_code {
238	u32	length;
239	u32	ack_offset;
240	u8	data[0];
241};
242
243extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
244extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
245extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
246
247/**
248 * ack_bit - turn IRQ into IRQ acknowledgement bit
249 * @irq: The interrupt number
250 *
251 * Returns the bit to write to the interrupt acknowledge register.
252 */
253static inline u32 ack_bit(unsigned int irq)
254{
255	return 1 << (irq - IRQ_EINT0);
256}
257
258/**
259 * s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
260 * @hw: The hardware state.
261 *
262 * Claim the FIQ handler (only one can be active at any one time) and
263 * then setup the correct transfer code for this transfer.
264 *
265 * This call updates all the necessary state information if successful,
266 * so the caller does not need to do anything more than start the transfer
267 * as normal, since the IRQ will have been re-routed to the FIQ handler.
268*/
269static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
270{
271	struct pt_regs regs;
272	enum spi_fiq_mode mode;
273	struct spi_fiq_code *code;
274	int ret;
275
276	if (!hw->fiq_claimed) {
277		/* try and claim fiq if we haven't got it, and if not
278		 * then return and simply use another transfer method */
279
280		ret = claim_fiq(&hw->fiq_handler);
281		if (ret)
282			return;
283	}
284
285	if (hw->tx && !hw->rx)
286		mode = FIQ_MODE_TX;
287	else if (hw->rx && !hw->tx)
288		mode = FIQ_MODE_RX;
289	else
290		mode = FIQ_MODE_TXRX;
291
292	regs.uregs[fiq_rspi] = (long)hw->regs;
293	regs.uregs[fiq_rrx]  = (long)hw->rx;
294	regs.uregs[fiq_rtx]  = (long)hw->tx + 1;
295	regs.uregs[fiq_rcount] = hw->len - 1;
296	regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
297
298	set_fiq_regs(&regs);
299
300	if (hw->fiq_mode != mode) {
301		u32 *ack_ptr;
302
303		hw->fiq_mode = mode;
304
305		switch (mode) {
306		case FIQ_MODE_TX:
307			code = &s3c24xx_spi_fiq_tx;
308			break;
309		case FIQ_MODE_RX:
310			code = &s3c24xx_spi_fiq_rx;
311			break;
312		case FIQ_MODE_TXRX:
313			code = &s3c24xx_spi_fiq_txrx;
314			break;
315		default:
316			code = NULL;
317		}
318
319		BUG_ON(!code);
320
321		ack_ptr = (u32 *)&code->data[code->ack_offset];
322		*ack_ptr = ack_bit(hw->irq);
323
324		set_fiq_handler(&code->data, code->length);
325	}
326
327	s3c24xx_set_fiq(hw->irq, true);
328
329	hw->fiq_mode = mode;
330	hw->fiq_inuse = 1;
331}
332
333/**
334 * s3c24xx_spi_fiqop - FIQ core code callback
335 * @pw: Data registered with the handler
336 * @release: Whether this is a release or a return.
337 *
338 * Called by the FIQ code when another module wants to use the FIQ, so
339 * return whether we are currently using this or not and then update our
340 * internal state.
341 */
342static int s3c24xx_spi_fiqop(void *pw, int release)
343{
344	struct s3c24xx_spi *hw = pw;
345	int ret = 0;
346
347	if (release) {
348		if (hw->fiq_inuse)
349			ret = -EBUSY;
350
351		/* note, we do not need to unroute the FIQ, as the FIQ
352		 * vector code de-routes it to signal the end of transfer */
353
354		hw->fiq_mode = FIQ_MODE_NONE;
355		hw->fiq_claimed = 0;
356	} else {
357		hw->fiq_claimed = 1;
358	}
359
360	return ret;
361}
362
363/**
364 * s3c24xx_spi_initfiq - setup the information for the FIQ core
365 * @hw: The hardware state.
366 *
367 * Setup the fiq_handler block to pass to the FIQ core.
368 */
369static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
370{
371	hw->fiq_handler.dev_id = hw;
372	hw->fiq_handler.name = dev_name(hw->dev);
373	hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
374}
375
376/**
377 * s3c24xx_spi_usefiq - return if we should be using FIQ.
378 * @hw: The hardware state.
379 *
380 * Return true if the platform data specifies whether this channel is
381 * allowed to use the FIQ.
382 */
383static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
384{
385	return hw->pdata->use_fiq;
386}
387
388/**
389 * s3c24xx_spi_usingfiq - return if channel is using FIQ
390 * @spi: The hardware state.
391 *
392 * Return whether the channel is currently using the FIQ (separate from
393 * whether the FIQ is claimed).
394 */
395static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
396{
397	return spi->fiq_inuse;
398}
399#else
400
401static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
402static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
403static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
404static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
405
406#endif /* CONFIG_SPI_S3C24XX_FIQ */
407
408static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
409{
410	struct s3c24xx_spi *hw = to_hw(spi);
411
412	hw->tx = t->tx_buf;
413	hw->rx = t->rx_buf;
414	hw->len = t->len;
415	hw->count = 0;
416
417	init_completion(&hw->done);
418
419	hw->fiq_inuse = 0;
420	if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
421		s3c24xx_spi_tryfiq(hw);
422
423	/* send the first byte */
424	writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
425
426	wait_for_completion(&hw->done);
427	return hw->count;
428}
429
430static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
431{
432	struct s3c24xx_spi *hw = dev;
433	unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
434	unsigned int count = hw->count;
435
436	if (spsta & S3C2410_SPSTA_DCOL) {
437		dev_dbg(hw->dev, "data-collision\n");
438		complete(&hw->done);
439		goto irq_done;
440	}
441
442	if (!(spsta & S3C2410_SPSTA_READY)) {
443		dev_dbg(hw->dev, "spi not ready for tx?\n");
444		complete(&hw->done);
445		goto irq_done;
446	}
447
448	if (!s3c24xx_spi_usingfiq(hw)) {
449		hw->count++;
450
451		if (hw->rx)
452			hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
453
454		count++;
455
456		if (count < hw->len)
457			writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
458		else
459			complete(&hw->done);
460	} else {
461		hw->count = hw->len;
462		hw->fiq_inuse = 0;
463
464		if (hw->rx)
465			hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
466
467		complete(&hw->done);
468	}
469
470 irq_done:
471	return IRQ_HANDLED;
472}
473
474static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
475{
476	/* for the moment, permanently enable the clock */
477
478	clk_enable(hw->clk);
479
480	/* program defaults into the registers */
481
482	writeb(0xff, hw->regs + S3C2410_SPPRE);
483	writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
484	writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
485
486	if (hw->pdata) {
487		if (hw->set_cs == s3c24xx_spi_gpiocs)
488			gpio_direction_output(hw->pdata->pin_cs, 1);
489
490		if (hw->pdata->gpio_setup)
491			hw->pdata->gpio_setup(hw->pdata, 1);
492	}
493}
494
495static int s3c24xx_spi_probe(struct platform_device *pdev)
496{
497	struct s3c2410_spi_info *pdata;
498	struct s3c24xx_spi *hw;
499	struct spi_master *master;
500	struct resource *res;
501	int err = 0;
502
503	master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
504	if (master == NULL) {
505		dev_err(&pdev->dev, "No memory for spi_master\n");
506		return -ENOMEM;
507	}
508
509	hw = spi_master_get_devdata(master);
510	memset(hw, 0, sizeof(struct s3c24xx_spi));
511
512	hw->master = master;
513	hw->pdata = pdata = dev_get_platdata(&pdev->dev);
514	hw->dev = &pdev->dev;
515
516	if (pdata == NULL) {
517		dev_err(&pdev->dev, "No platform data supplied\n");
518		err = -ENOENT;
519		goto err_no_pdata;
520	}
521
522	platform_set_drvdata(pdev, hw);
523	init_completion(&hw->done);
524
525	/* initialise fiq handler */
526
527	s3c24xx_spi_initfiq(hw);
528
529	/* setup the master state. */
530
531	/* the spi->mode bits understood by this driver: */
532	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
533
534	master->num_chipselect = hw->pdata->num_cs;
535	master->bus_num = pdata->bus_num;
536	master->bits_per_word_mask = SPI_BPW_MASK(8);
537
538	/* setup the state for the bitbang driver */
539
540	hw->bitbang.master         = hw->master;
541	hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
542	hw->bitbang.chipselect     = s3c24xx_spi_chipsel;
543	hw->bitbang.txrx_bufs      = s3c24xx_spi_txrx;
544
545	hw->master->setup  = s3c24xx_spi_setup;
546	hw->master->cleanup = s3c24xx_spi_cleanup;
547
548	dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
549
550	/* find and map our resources */
551	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
552	hw->regs = devm_ioremap_resource(&pdev->dev, res);
553	if (IS_ERR(hw->regs)) {
554		err = PTR_ERR(hw->regs);
555		goto err_no_pdata;
556	}
557
558	hw->irq = platform_get_irq(pdev, 0);
559	if (hw->irq < 0) {
560		dev_err(&pdev->dev, "No IRQ specified\n");
561		err = -ENOENT;
562		goto err_no_pdata;
563	}
564
565	err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
566				pdev->name, hw);
567	if (err) {
568		dev_err(&pdev->dev, "Cannot claim IRQ\n");
569		goto err_no_pdata;
570	}
571
572	hw->clk = devm_clk_get(&pdev->dev, "spi");
573	if (IS_ERR(hw->clk)) {
574		dev_err(&pdev->dev, "No clock for device\n");
575		err = PTR_ERR(hw->clk);
576		goto err_no_pdata;
577	}
578
579	/* setup any gpio we can */
580
581	if (!pdata->set_cs) {
582		if (pdata->pin_cs < 0) {
583			dev_err(&pdev->dev, "No chipselect pin\n");
584			err = -EINVAL;
585			goto err_register;
586		}
587
588		err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
589					dev_name(&pdev->dev));
590		if (err) {
591			dev_err(&pdev->dev, "Failed to get gpio for cs\n");
592			goto err_register;
593		}
594
595		hw->set_cs = s3c24xx_spi_gpiocs;
596		gpio_direction_output(pdata->pin_cs, 1);
597	} else
598		hw->set_cs = pdata->set_cs;
599
600	s3c24xx_spi_initialsetup(hw);
601
602	/* register our spi controller */
603
604	err = spi_bitbang_start(&hw->bitbang);
605	if (err) {
606		dev_err(&pdev->dev, "Failed to register SPI master\n");
607		goto err_register;
608	}
609
610	return 0;
611
612 err_register:
613	clk_disable(hw->clk);
614
615 err_no_pdata:
616	spi_master_put(hw->master);
617	return err;
618}
619
620static int s3c24xx_spi_remove(struct platform_device *dev)
621{
622	struct s3c24xx_spi *hw = platform_get_drvdata(dev);
623
624	spi_bitbang_stop(&hw->bitbang);
625	clk_disable(hw->clk);
626	spi_master_put(hw->master);
627	return 0;
628}
629
630
631#ifdef CONFIG_PM
632
633static int s3c24xx_spi_suspend(struct device *dev)
634{
635	struct s3c24xx_spi *hw = dev_get_drvdata(dev);
636	int ret;
637
638	ret = spi_master_suspend(hw->master);
639	if (ret)
640		return ret;
641
642	if (hw->pdata && hw->pdata->gpio_setup)
643		hw->pdata->gpio_setup(hw->pdata, 0);
644
645	clk_disable(hw->clk);
646	return 0;
647}
648
649static int s3c24xx_spi_resume(struct device *dev)
650{
651	struct s3c24xx_spi *hw = dev_get_drvdata(dev);
652
653	s3c24xx_spi_initialsetup(hw);
654	return spi_master_resume(hw->master);
655}
656
657static const struct dev_pm_ops s3c24xx_spi_pmops = {
658	.suspend	= s3c24xx_spi_suspend,
659	.resume		= s3c24xx_spi_resume,
660};
661
662#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
663#else
664#define S3C24XX_SPI_PMOPS NULL
665#endif /* CONFIG_PM */
666
667MODULE_ALIAS("platform:s3c2410-spi");
668static struct platform_driver s3c24xx_spi_driver = {
669	.probe		= s3c24xx_spi_probe,
670	.remove		= s3c24xx_spi_remove,
671	.driver		= {
672		.name	= "s3c2410-spi",
673		.owner	= THIS_MODULE,
674		.pm	= S3C24XX_SPI_PMOPS,
675	},
676};
677module_platform_driver(s3c24xx_spi_driver);
678
679MODULE_DESCRIPTION("S3C24XX SPI Driver");
680MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
681MODULE_LICENSE("GPL");