1// SPDX-License-Identifier: GPL-2.0
  2//
  3// CS42L43 SPI Controller Driver
  4//
  5// Copyright (C) 2022-2023 Cirrus Logic, Inc. and
  6//                         Cirrus Logic International Semiconductor Ltd.
  7
  8#include <linux/bits.h>
  9#include <linux/bitfield.h>
 10#include <linux/device.h>
 11#include <linux/errno.h>
 12#include <linux/mfd/cs42l43.h>
 13#include <linux/mfd/cs42l43-regs.h>
 14#include <linux/module.h>
 15#include <linux/platform_device.h>
 16#include <linux/pm_runtime.h>
 17#include <linux/regmap.h>
 18#include <linux/spi/spi.h>
 19#include <linux/units.h>
 20
 21#define CS42L43_FIFO_SIZE		16
 22#define CS42L43_SPI_ROOT_HZ		(40 * HZ_PER_MHZ)
 23#define CS42L43_SPI_MAX_LENGTH		65532
 24
 25enum cs42l43_spi_cmd {
 26	CS42L43_WRITE,
 27	CS42L43_READ
 28};
 29
 30struct cs42l43_spi {
 31	struct device *dev;
 32	struct regmap *regmap;
 33	struct spi_controller *ctlr;
 34};
 35
 36static const unsigned int cs42l43_clock_divs[] = {
 37	2, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
 38};
 39
 40static int cs42l43_spi_tx(struct regmap *regmap, const u8 *buf, unsigned int len)
 41{
 42	const u8 *end = buf + len;
 43	u32 val = 0;
 44	int ret;
 45
 46	while (buf < end) {
 47		const u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
 48
 49		while (buf < block) {
 50			const u8 *word = min(buf + sizeof(u32), block);
 51			int pad = (buf + sizeof(u32)) - word;
 52
 53			while (buf < word) {
 54				val >>= BITS_PER_BYTE;
 55				val |= FIELD_PREP(GENMASK(31, 24), *buf);
 56
 57				buf++;
 58			}
 59
 60			val >>= pad * BITS_PER_BYTE;
 61
 62			regmap_write(regmap, CS42L43_TX_DATA, val);
 63		}
 64
 65		regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_TX_DONE_MASK);
 66
 67		ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
 68					       val, (val & CS42L43_SPI_TX_REQUEST_MASK),
 69					       1000, 5000);
 70		if (ret)
 71			return ret;
 72	}
 73
 74	return 0;
 75}
 76
 77static int cs42l43_spi_rx(struct regmap *regmap, u8 *buf, unsigned int len)
 78{
 79	u8 *end = buf + len;
 80	u32 val;
 81	int ret;
 82
 83	while (buf < end) {
 84		u8 *block = min(buf + CS42L43_FIFO_SIZE, end);
 85
 86		ret = regmap_read_poll_timeout(regmap, CS42L43_TRAN_STATUS1,
 87					       val, (val & CS42L43_SPI_RX_REQUEST_MASK),
 88					       1000, 5000);
 89		if (ret)
 90			return ret;
 91
 92		while (buf < block) {
 93			u8 *word = min(buf + sizeof(u32), block);
 94
 95			ret = regmap_read(regmap, CS42L43_RX_DATA, &val);
 96			if (ret)
 97				return ret;
 98
 99			while (buf < word) {
100				*buf = FIELD_GET(GENMASK(7, 0), val);
101
102				val >>= BITS_PER_BYTE;
103				buf++;
104			}
105		}
106
107		regmap_write(regmap, CS42L43_TRAN_CONFIG8, CS42L43_SPI_RX_DONE_MASK);
108	}
109
110	return 0;
111}
112
113static int cs42l43_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
114				struct spi_transfer *tfr)
115{
116	struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
117	int i, ret = -EINVAL;
118
119	for (i = 0; i < ARRAY_SIZE(cs42l43_clock_divs); i++) {
120		if (CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[i] <= tfr->speed_hz)
121			break;
122	}
123
124	if (i == ARRAY_SIZE(cs42l43_clock_divs))
125		return -EINVAL;
126
127	regmap_write(priv->regmap, CS42L43_SPI_CLK_CONFIG1, i);
128
129	if (tfr->tx_buf) {
130		regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_WRITE);
131		regmap_write(priv->regmap, CS42L43_TRAN_CONFIG4, tfr->len - 1);
132	} else if (tfr->rx_buf) {
133		regmap_write(priv->regmap, CS42L43_TRAN_CONFIG3, CS42L43_READ);
134		regmap_write(priv->regmap, CS42L43_TRAN_CONFIG5, tfr->len - 1);
135	}
136
137	regmap_write(priv->regmap, CS42L43_TRAN_CONFIG1, CS42L43_SPI_START_MASK);
138
139	if (tfr->tx_buf)
140		ret = cs42l43_spi_tx(priv->regmap, (const u8 *)tfr->tx_buf, tfr->len);
141	else if (tfr->rx_buf)
142		ret = cs42l43_spi_rx(priv->regmap, (u8 *)tfr->rx_buf, tfr->len);
143
144	return ret;
145}
146
147static void cs42l43_set_cs(struct spi_device *spi, bool is_high)
148{
149	struct cs42l43_spi *priv = spi_controller_get_devdata(spi->controller);
150
151	regmap_write(priv->regmap, CS42L43_SPI_CONFIG2, !is_high);
152}
153
154static int cs42l43_prepare_message(struct spi_controller *ctlr, struct spi_message *msg)
155{
156	struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
157	struct spi_device *spi = msg->spi;
158	unsigned int spi_config1 = 0;
159
160	/* select another internal CS, which doesn't exist, so CS 0 is not used */
161	if (spi_get_csgpiod(spi, 0))
162		spi_config1 |= 1 << CS42L43_SPI_SS_SEL_SHIFT;
163	if (spi->mode & SPI_CPOL)
164		spi_config1 |= CS42L43_SPI_CPOL_MASK;
165	if (spi->mode & SPI_CPHA)
166		spi_config1 |= CS42L43_SPI_CPHA_MASK;
167	if (spi->mode & SPI_3WIRE)
168		spi_config1 |= CS42L43_SPI_THREE_WIRE_MASK;
169
170	regmap_write(priv->regmap, CS42L43_SPI_CONFIG1, spi_config1);
171
172	return 0;
173}
174
175static int cs42l43_prepare_transfer_hardware(struct spi_controller *ctlr)
176{
177	struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
178	int ret;
179
180	ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, CS42L43_SPI_MSTR_EN_MASK);
181	if (ret)
182		dev_err(priv->dev, "Failed to enable SPI controller: %d\n", ret);
183
184	return ret;
185}
186
187static int cs42l43_unprepare_transfer_hardware(struct spi_controller *ctlr)
188{
189	struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
190	int ret;
191
192	ret = regmap_write(priv->regmap, CS42L43_BLOCK_EN2, 0);
193	if (ret)
194		dev_err(priv->dev, "Failed to disable SPI controller: %d\n", ret);
195
196	return ret;
197}
198
199static size_t cs42l43_spi_max_length(struct spi_device *spi)
200{
201	return CS42L43_SPI_MAX_LENGTH;
202}
203
204static int cs42l43_spi_probe(struct platform_device *pdev)
205{
206	struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
207	struct cs42l43_spi *priv;
208	struct fwnode_handle *fwnode = dev_fwnode(cs42l43->dev);
209	int ret;
210
211	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
212	if (!priv)
213		return -ENOMEM;
214
215	priv->ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*priv->ctlr));
216	if (!priv->ctlr)
217		return -ENOMEM;
218
219	spi_controller_set_devdata(priv->ctlr, priv);
220
221	priv->dev = &pdev->dev;
222	priv->regmap = cs42l43->regmap;
223
224	priv->ctlr->prepare_message = cs42l43_prepare_message;
225	priv->ctlr->prepare_transfer_hardware = cs42l43_prepare_transfer_hardware;
226	priv->ctlr->unprepare_transfer_hardware = cs42l43_unprepare_transfer_hardware;
227	priv->ctlr->transfer_one = cs42l43_transfer_one;
228	priv->ctlr->set_cs = cs42l43_set_cs;
229	priv->ctlr->max_transfer_size = cs42l43_spi_max_length;
230
231	if (is_of_node(fwnode))
232		fwnode = fwnode_get_named_child_node(fwnode, "spi");
233
234	device_set_node(&priv->ctlr->dev, fwnode);
235
236	priv->ctlr->mode_bits = SPI_3WIRE | SPI_MODE_X_MASK;
237	priv->ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
238	priv->ctlr->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
239					 SPI_BPW_MASK(32);
240	priv->ctlr->min_speed_hz = CS42L43_SPI_ROOT_HZ /
241				   cs42l43_clock_divs[ARRAY_SIZE(cs42l43_clock_divs) - 1];
242	priv->ctlr->max_speed_hz = CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[0];
243	priv->ctlr->use_gpio_descriptors = true;
244	priv->ctlr->auto_runtime_pm = true;
245
246	ret = devm_pm_runtime_enable(priv->dev);
247	if (ret)
248		return ret;
249
250	pm_runtime_idle(priv->dev);
251
252	regmap_write(priv->regmap, CS42L43_TRAN_CONFIG6, CS42L43_FIFO_SIZE - 1);
253	regmap_write(priv->regmap, CS42L43_TRAN_CONFIG7, CS42L43_FIFO_SIZE - 1);
254
255	// Disable Watchdog timer and enable stall
256	regmap_write(priv->regmap, CS42L43_SPI_CONFIG3, 0);
257	regmap_write(priv->regmap, CS42L43_SPI_CONFIG4, CS42L43_SPI_STALL_ENA_MASK);
258
259	ret = devm_spi_register_controller(priv->dev, priv->ctlr);
260	if (ret) {
261		dev_err(priv->dev, "Failed to register SPI controller: %d\n", ret);
262	}
263
264	return ret;
265}
266
267static const struct platform_device_id cs42l43_spi_id_table[] = {
268	{ "cs42l43-spi", },
269	{}
270};
271MODULE_DEVICE_TABLE(platform, cs42l43_spi_id_table);
272
273static struct platform_driver cs42l43_spi_driver = {
274	.driver = {
275		.name	= "cs42l43-spi",
276	},
277	.probe		= cs42l43_spi_probe,
278	.id_table	= cs42l43_spi_id_table,
279};
280module_platform_driver(cs42l43_spi_driver);
281
282MODULE_DESCRIPTION("CS42L43 SPI Driver");
283MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
284MODULE_AUTHOR("Maciej Strozek <mstrozek@opensource.cirrus.com>");
285MODULE_LICENSE("GPL");