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1/*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/gpio.h>
16#include <linux/slab.h>
17#include <linux/io.h>
18#include <linux/ioport.h>
19#include <linux/irq.h>
20#include <linux/errno.h>
21#include <linux/interrupt.h>
22#include <linux/platform_device.h>
23#include <linux/dma-mapping.h>
24#include <linux/spi/spi.h>
25#include <linux/workqueue.h>
26
27#include <asm/dma.h>
28#include <asm/portmux.h>
29#include <asm/bfin5xx_spi.h>
30#include <asm/cacheflush.h>
31
32#define DRV_NAME "bfin-spi"
33#define DRV_AUTHOR "Bryan Wu, Luke Yang"
34#define DRV_DESC "Blackfin on-chip SPI Controller Driver"
35#define DRV_VERSION "1.0"
36
37MODULE_AUTHOR(DRV_AUTHOR);
38MODULE_DESCRIPTION(DRV_DESC);
39MODULE_LICENSE("GPL");
40
41#define START_STATE ((void *)0)
42#define RUNNING_STATE ((void *)1)
43#define DONE_STATE ((void *)2)
44#define ERROR_STATE ((void *)-1)
45
46struct bfin_spi_master_data;
47
48struct bfin_spi_transfer_ops {
49 void (*write) (struct bfin_spi_master_data *);
50 void (*read) (struct bfin_spi_master_data *);
51 void (*duplex) (struct bfin_spi_master_data *);
52};
53
54struct bfin_spi_master_data {
55 /* Driver model hookup */
56 struct platform_device *pdev;
57
58 /* SPI framework hookup */
59 struct spi_master *master;
60
61 /* Regs base of SPI controller */
62 struct bfin_spi_regs __iomem *regs;
63
64 /* Pin request list */
65 u16 *pin_req;
66
67 /* BFIN hookup */
68 struct bfin5xx_spi_master *master_info;
69
70 /* Driver message queue */
71 struct workqueue_struct *workqueue;
72 struct work_struct pump_messages;
73 spinlock_t lock;
74 struct list_head queue;
75 int busy;
76 bool running;
77
78 /* Message Transfer pump */
79 struct tasklet_struct pump_transfers;
80
81 /* Current message transfer state info */
82 struct spi_message *cur_msg;
83 struct spi_transfer *cur_transfer;
84 struct bfin_spi_slave_data *cur_chip;
85 size_t len_in_bytes;
86 size_t len;
87 void *tx;
88 void *tx_end;
89 void *rx;
90 void *rx_end;
91
92 /* DMA stuffs */
93 int dma_channel;
94 int dma_mapped;
95 int dma_requested;
96 dma_addr_t rx_dma;
97 dma_addr_t tx_dma;
98
99 int irq_requested;
100 int spi_irq;
101
102 size_t rx_map_len;
103 size_t tx_map_len;
104 u8 n_bytes;
105 u16 ctrl_reg;
106 u16 flag_reg;
107
108 int cs_change;
109 const struct bfin_spi_transfer_ops *ops;
110};
111
112struct bfin_spi_slave_data {
113 u16 ctl_reg;
114 u16 baud;
115 u16 flag;
116
117 u8 chip_select_num;
118 u8 enable_dma;
119 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
120 u32 cs_gpio;
121 u16 idle_tx_val;
122 u8 pio_interrupt; /* use spi data irq */
123 const struct bfin_spi_transfer_ops *ops;
124};
125
126static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
127{
128 bfin_write_or(&drv_data->regs->ctl, BIT_CTL_ENABLE);
129}
130
131static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
132{
133 bfin_write_and(&drv_data->regs->ctl, ~BIT_CTL_ENABLE);
134}
135
136/* Caculate the SPI_BAUD register value based on input HZ */
137static u16 hz_to_spi_baud(u32 speed_hz)
138{
139 u_long sclk = get_sclk();
140 u16 spi_baud = (sclk / (2 * speed_hz));
141
142 if ((sclk % (2 * speed_hz)) > 0)
143 spi_baud++;
144
145 if (spi_baud < MIN_SPI_BAUD_VAL)
146 spi_baud = MIN_SPI_BAUD_VAL;
147
148 return spi_baud;
149}
150
151static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
152{
153 unsigned long limit = loops_per_jiffy << 1;
154
155 /* wait for stop and clear stat */
156 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF) && --limit)
157 cpu_relax();
158
159 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
160
161 return limit;
162}
163
164/* Chip select operation functions for cs_change flag */
165static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
166{
167 if (likely(chip->chip_select_num < MAX_CTRL_CS))
168 bfin_write_and(&drv_data->regs->flg, ~chip->flag);
169 else
170 gpio_set_value(chip->cs_gpio, 0);
171}
172
173static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
174 struct bfin_spi_slave_data *chip)
175{
176 if (likely(chip->chip_select_num < MAX_CTRL_CS))
177 bfin_write_or(&drv_data->regs->flg, chip->flag);
178 else
179 gpio_set_value(chip->cs_gpio, 1);
180
181 /* Move delay here for consistency */
182 if (chip->cs_chg_udelay)
183 udelay(chip->cs_chg_udelay);
184}
185
186/* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
187static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
188 struct bfin_spi_slave_data *chip)
189{
190 if (chip->chip_select_num < MAX_CTRL_CS)
191 bfin_write_or(&drv_data->regs->flg, chip->flag >> 8);
192}
193
194static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
195 struct bfin_spi_slave_data *chip)
196{
197 if (chip->chip_select_num < MAX_CTRL_CS)
198 bfin_write_and(&drv_data->regs->flg, ~(chip->flag >> 8));
199}
200
201/* stop controller and re-config current chip*/
202static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
203{
204 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
205
206 /* Clear status and disable clock */
207 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
208 bfin_spi_disable(drv_data);
209 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
210
211 SSYNC();
212
213 /* Load the registers */
214 bfin_write(&drv_data->regs->ctl, chip->ctl_reg);
215 bfin_write(&drv_data->regs->baud, chip->baud);
216
217 bfin_spi_enable(drv_data);
218 bfin_spi_cs_active(drv_data, chip);
219}
220
221/* used to kick off transfer in rx mode and read unwanted RX data */
222static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
223{
224 (void) bfin_read(&drv_data->regs->rdbr);
225}
226
227static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
228{
229 /* clear RXS (we check for RXS inside the loop) */
230 bfin_spi_dummy_read(drv_data);
231
232 while (drv_data->tx < drv_data->tx_end) {
233 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
234 /* wait until transfer finished.
235 checking SPIF or TXS may not guarantee transfer completion */
236 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
237 cpu_relax();
238 /* discard RX data and clear RXS */
239 bfin_spi_dummy_read(drv_data);
240 }
241}
242
243static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
244{
245 u16 tx_val = drv_data->cur_chip->idle_tx_val;
246
247 /* discard old RX data and clear RXS */
248 bfin_spi_dummy_read(drv_data);
249
250 while (drv_data->rx < drv_data->rx_end) {
251 bfin_write(&drv_data->regs->tdbr, tx_val);
252 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
253 cpu_relax();
254 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
255 }
256}
257
258static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
259{
260 /* discard old RX data and clear RXS */
261 bfin_spi_dummy_read(drv_data);
262
263 while (drv_data->rx < drv_data->rx_end) {
264 bfin_write(&drv_data->regs->tdbr, (*(u8 *) (drv_data->tx++)));
265 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
266 cpu_relax();
267 *(u8 *) (drv_data->rx++) = bfin_read(&drv_data->regs->rdbr);
268 }
269}
270
271static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
272 .write = bfin_spi_u8_writer,
273 .read = bfin_spi_u8_reader,
274 .duplex = bfin_spi_u8_duplex,
275};
276
277static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
278{
279 /* clear RXS (we check for RXS inside the loop) */
280 bfin_spi_dummy_read(drv_data);
281
282 while (drv_data->tx < drv_data->tx_end) {
283 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
284 drv_data->tx += 2;
285 /* wait until transfer finished.
286 checking SPIF or TXS may not guarantee transfer completion */
287 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
288 cpu_relax();
289 /* discard RX data and clear RXS */
290 bfin_spi_dummy_read(drv_data);
291 }
292}
293
294static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
295{
296 u16 tx_val = drv_data->cur_chip->idle_tx_val;
297
298 /* discard old RX data and clear RXS */
299 bfin_spi_dummy_read(drv_data);
300
301 while (drv_data->rx < drv_data->rx_end) {
302 bfin_write(&drv_data->regs->tdbr, tx_val);
303 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
304 cpu_relax();
305 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
306 drv_data->rx += 2;
307 }
308}
309
310static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
311{
312 /* discard old RX data and clear RXS */
313 bfin_spi_dummy_read(drv_data);
314
315 while (drv_data->rx < drv_data->rx_end) {
316 bfin_write(&drv_data->regs->tdbr, (*(u16 *) (drv_data->tx)));
317 drv_data->tx += 2;
318 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
319 cpu_relax();
320 *(u16 *) (drv_data->rx) = bfin_read(&drv_data->regs->rdbr);
321 drv_data->rx += 2;
322 }
323}
324
325static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
326 .write = bfin_spi_u16_writer,
327 .read = bfin_spi_u16_reader,
328 .duplex = bfin_spi_u16_duplex,
329};
330
331/* test if there is more transfer to be done */
332static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
333{
334 struct spi_message *msg = drv_data->cur_msg;
335 struct spi_transfer *trans = drv_data->cur_transfer;
336
337 /* Move to next transfer */
338 if (trans->transfer_list.next != &msg->transfers) {
339 drv_data->cur_transfer =
340 list_entry(trans->transfer_list.next,
341 struct spi_transfer, transfer_list);
342 return RUNNING_STATE;
343 } else
344 return DONE_STATE;
345}
346
347/*
348 * caller already set message->status;
349 * dma and pio irqs are blocked give finished message back
350 */
351static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
352{
353 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
354 unsigned long flags;
355 struct spi_message *msg;
356
357 spin_lock_irqsave(&drv_data->lock, flags);
358 msg = drv_data->cur_msg;
359 drv_data->cur_msg = NULL;
360 drv_data->cur_transfer = NULL;
361 drv_data->cur_chip = NULL;
362 queue_work(drv_data->workqueue, &drv_data->pump_messages);
363 spin_unlock_irqrestore(&drv_data->lock, flags);
364
365 msg->state = NULL;
366
367 if (!drv_data->cs_change)
368 bfin_spi_cs_deactive(drv_data, chip);
369
370 /* Not stop spi in autobuffer mode */
371 if (drv_data->tx_dma != 0xFFFF)
372 bfin_spi_disable(drv_data);
373
374 if (msg->complete)
375 msg->complete(msg->context);
376}
377
378/* spi data irq handler */
379static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
380{
381 struct bfin_spi_master_data *drv_data = dev_id;
382 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
383 struct spi_message *msg = drv_data->cur_msg;
384 int n_bytes = drv_data->n_bytes;
385 int loop = 0;
386
387 /* wait until transfer finished. */
388 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_RXS))
389 cpu_relax();
390
391 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
392 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
393 /* last read */
394 if (drv_data->rx) {
395 dev_dbg(&drv_data->pdev->dev, "last read\n");
396 if (!(n_bytes % 2)) {
397 u16 *buf = (u16 *)drv_data->rx;
398 for (loop = 0; loop < n_bytes / 2; loop++)
399 *buf++ = bfin_read(&drv_data->regs->rdbr);
400 } else {
401 u8 *buf = (u8 *)drv_data->rx;
402 for (loop = 0; loop < n_bytes; loop++)
403 *buf++ = bfin_read(&drv_data->regs->rdbr);
404 }
405 drv_data->rx += n_bytes;
406 }
407
408 msg->actual_length += drv_data->len_in_bytes;
409 if (drv_data->cs_change)
410 bfin_spi_cs_deactive(drv_data, chip);
411 /* Move to next transfer */
412 msg->state = bfin_spi_next_transfer(drv_data);
413
414 disable_irq_nosync(drv_data->spi_irq);
415
416 /* Schedule transfer tasklet */
417 tasklet_schedule(&drv_data->pump_transfers);
418 return IRQ_HANDLED;
419 }
420
421 if (drv_data->rx && drv_data->tx) {
422 /* duplex */
423 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
424 if (!(n_bytes % 2)) {
425 u16 *buf = (u16 *)drv_data->rx;
426 u16 *buf2 = (u16 *)drv_data->tx;
427 for (loop = 0; loop < n_bytes / 2; loop++) {
428 *buf++ = bfin_read(&drv_data->regs->rdbr);
429 bfin_write(&drv_data->regs->tdbr, *buf2++);
430 }
431 } else {
432 u8 *buf = (u8 *)drv_data->rx;
433 u8 *buf2 = (u8 *)drv_data->tx;
434 for (loop = 0; loop < n_bytes; loop++) {
435 *buf++ = bfin_read(&drv_data->regs->rdbr);
436 bfin_write(&drv_data->regs->tdbr, *buf2++);
437 }
438 }
439 } else if (drv_data->rx) {
440 /* read */
441 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
442 if (!(n_bytes % 2)) {
443 u16 *buf = (u16 *)drv_data->rx;
444 for (loop = 0; loop < n_bytes / 2; loop++) {
445 *buf++ = bfin_read(&drv_data->regs->rdbr);
446 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
447 }
448 } else {
449 u8 *buf = (u8 *)drv_data->rx;
450 for (loop = 0; loop < n_bytes; loop++) {
451 *buf++ = bfin_read(&drv_data->regs->rdbr);
452 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
453 }
454 }
455 } else if (drv_data->tx) {
456 /* write */
457 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
458 if (!(n_bytes % 2)) {
459 u16 *buf = (u16 *)drv_data->tx;
460 for (loop = 0; loop < n_bytes / 2; loop++) {
461 bfin_read(&drv_data->regs->rdbr);
462 bfin_write(&drv_data->regs->tdbr, *buf++);
463 }
464 } else {
465 u8 *buf = (u8 *)drv_data->tx;
466 for (loop = 0; loop < n_bytes; loop++) {
467 bfin_read(&drv_data->regs->rdbr);
468 bfin_write(&drv_data->regs->tdbr, *buf++);
469 }
470 }
471 }
472
473 if (drv_data->tx)
474 drv_data->tx += n_bytes;
475 if (drv_data->rx)
476 drv_data->rx += n_bytes;
477
478 return IRQ_HANDLED;
479}
480
481static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
482{
483 struct bfin_spi_master_data *drv_data = dev_id;
484 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
485 struct spi_message *msg = drv_data->cur_msg;
486 unsigned long timeout;
487 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
488 u16 spistat = bfin_read(&drv_data->regs->stat);
489
490 dev_dbg(&drv_data->pdev->dev,
491 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
492 dmastat, spistat);
493
494 if (drv_data->rx != NULL) {
495 u16 cr = bfin_read(&drv_data->regs->ctl);
496 /* discard old RX data and clear RXS */
497 bfin_spi_dummy_read(drv_data);
498 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_ENABLE); /* Disable SPI */
499 bfin_write(&drv_data->regs->ctl, cr & ~BIT_CTL_TIMOD); /* Restore State */
500 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR); /* Clear Status */
501 }
502
503 clear_dma_irqstat(drv_data->dma_channel);
504
505 /*
506 * wait for the last transaction shifted out. HRM states:
507 * at this point there may still be data in the SPI DMA FIFO waiting
508 * to be transmitted ... software needs to poll TXS in the SPI_STAT
509 * register until it goes low for 2 successive reads
510 */
511 if (drv_data->tx != NULL) {
512 while ((bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS) ||
513 (bfin_read(&drv_data->regs->stat) & BIT_STAT_TXS))
514 cpu_relax();
515 }
516
517 dev_dbg(&drv_data->pdev->dev,
518 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
519 dmastat, bfin_read(&drv_data->regs->stat));
520
521 timeout = jiffies + HZ;
522 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
523 if (!time_before(jiffies, timeout)) {
524 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF\n");
525 break;
526 } else
527 cpu_relax();
528
529 if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
530 msg->state = ERROR_STATE;
531 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
532 } else {
533 msg->actual_length += drv_data->len_in_bytes;
534
535 if (drv_data->cs_change)
536 bfin_spi_cs_deactive(drv_data, chip);
537
538 /* Move to next transfer */
539 msg->state = bfin_spi_next_transfer(drv_data);
540 }
541
542 /* Schedule transfer tasklet */
543 tasklet_schedule(&drv_data->pump_transfers);
544
545 /* free the irq handler before next transfer */
546 dev_dbg(&drv_data->pdev->dev,
547 "disable dma channel irq%d\n",
548 drv_data->dma_channel);
549 dma_disable_irq_nosync(drv_data->dma_channel);
550
551 return IRQ_HANDLED;
552}
553
554static void bfin_spi_pump_transfers(unsigned long data)
555{
556 struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
557 struct spi_message *message = NULL;
558 struct spi_transfer *transfer = NULL;
559 struct spi_transfer *previous = NULL;
560 struct bfin_spi_slave_data *chip = NULL;
561 unsigned int bits_per_word;
562 u16 cr, cr_width, dma_width, dma_config;
563 u32 tranf_success = 1;
564 u8 full_duplex = 0;
565
566 /* Get current state information */
567 message = drv_data->cur_msg;
568 transfer = drv_data->cur_transfer;
569 chip = drv_data->cur_chip;
570
571 /*
572 * if msg is error or done, report it back using complete() callback
573 */
574
575 /* Handle for abort */
576 if (message->state == ERROR_STATE) {
577 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
578 message->status = -EIO;
579 bfin_spi_giveback(drv_data);
580 return;
581 }
582
583 /* Handle end of message */
584 if (message->state == DONE_STATE) {
585 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
586 message->status = 0;
587 bfin_spi_flush(drv_data);
588 bfin_spi_giveback(drv_data);
589 return;
590 }
591
592 /* Delay if requested at end of transfer */
593 if (message->state == RUNNING_STATE) {
594 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
595 previous = list_entry(transfer->transfer_list.prev,
596 struct spi_transfer, transfer_list);
597 if (previous->delay_usecs)
598 udelay(previous->delay_usecs);
599 }
600
601 /* Flush any existing transfers that may be sitting in the hardware */
602 if (bfin_spi_flush(drv_data) == 0) {
603 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
604 message->status = -EIO;
605 bfin_spi_giveback(drv_data);
606 return;
607 }
608
609 if (transfer->len == 0) {
610 /* Move to next transfer of this msg */
611 message->state = bfin_spi_next_transfer(drv_data);
612 /* Schedule next transfer tasklet */
613 tasklet_schedule(&drv_data->pump_transfers);
614 return;
615 }
616
617 if (transfer->tx_buf != NULL) {
618 drv_data->tx = (void *)transfer->tx_buf;
619 drv_data->tx_end = drv_data->tx + transfer->len;
620 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
621 transfer->tx_buf, drv_data->tx_end);
622 } else {
623 drv_data->tx = NULL;
624 }
625
626 if (transfer->rx_buf != NULL) {
627 full_duplex = transfer->tx_buf != NULL;
628 drv_data->rx = transfer->rx_buf;
629 drv_data->rx_end = drv_data->rx + transfer->len;
630 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
631 transfer->rx_buf, drv_data->rx_end);
632 } else {
633 drv_data->rx = NULL;
634 }
635
636 drv_data->rx_dma = transfer->rx_dma;
637 drv_data->tx_dma = transfer->tx_dma;
638 drv_data->len_in_bytes = transfer->len;
639 drv_data->cs_change = transfer->cs_change;
640
641 /* Bits per word setup */
642 bits_per_word = transfer->bits_per_word;
643 if (bits_per_word == 16) {
644 drv_data->n_bytes = bits_per_word/8;
645 drv_data->len = (transfer->len) >> 1;
646 cr_width = BIT_CTL_WORDSIZE;
647 drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
648 } else if (bits_per_word == 8) {
649 drv_data->n_bytes = bits_per_word/8;
650 drv_data->len = transfer->len;
651 cr_width = 0;
652 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
653 }
654 cr = bfin_read(&drv_data->regs->ctl) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
655 cr |= cr_width;
656 bfin_write(&drv_data->regs->ctl, cr);
657
658 dev_dbg(&drv_data->pdev->dev,
659 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
660 drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
661
662 message->state = RUNNING_STATE;
663 dma_config = 0;
664
665 /* Speed setup (surely valid because already checked) */
666 if (transfer->speed_hz)
667 bfin_write(&drv_data->regs->baud, hz_to_spi_baud(transfer->speed_hz));
668 else
669 bfin_write(&drv_data->regs->baud, chip->baud);
670
671 bfin_write(&drv_data->regs->stat, BIT_STAT_CLR);
672 bfin_spi_cs_active(drv_data, chip);
673
674 dev_dbg(&drv_data->pdev->dev,
675 "now pumping a transfer: width is %d, len is %d\n",
676 cr_width, transfer->len);
677
678 /*
679 * Try to map dma buffer and do a dma transfer. If successful use,
680 * different way to r/w according to the enable_dma settings and if
681 * we are not doing a full duplex transfer (since the hardware does
682 * not support full duplex DMA transfers).
683 */
684 if (!full_duplex && drv_data->cur_chip->enable_dma
685 && drv_data->len > 6) {
686
687 unsigned long dma_start_addr, flags;
688
689 disable_dma(drv_data->dma_channel);
690 clear_dma_irqstat(drv_data->dma_channel);
691
692 /* config dma channel */
693 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
694 set_dma_x_count(drv_data->dma_channel, drv_data->len);
695 if (cr_width == BIT_CTL_WORDSIZE) {
696 set_dma_x_modify(drv_data->dma_channel, 2);
697 dma_width = WDSIZE_16;
698 } else {
699 set_dma_x_modify(drv_data->dma_channel, 1);
700 dma_width = WDSIZE_8;
701 }
702
703 /* poll for SPI completion before start */
704 while (!(bfin_read(&drv_data->regs->stat) & BIT_STAT_SPIF))
705 cpu_relax();
706
707 /* dirty hack for autobuffer DMA mode */
708 if (drv_data->tx_dma == 0xFFFF) {
709 dev_dbg(&drv_data->pdev->dev,
710 "doing autobuffer DMA out.\n");
711
712 /* no irq in autobuffer mode */
713 dma_config =
714 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
715 set_dma_config(drv_data->dma_channel, dma_config);
716 set_dma_start_addr(drv_data->dma_channel,
717 (unsigned long)drv_data->tx);
718 enable_dma(drv_data->dma_channel);
719
720 /* start SPI transfer */
721 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TIMOD_DMA_TX);
722
723 /* just return here, there can only be one transfer
724 * in this mode
725 */
726 message->status = 0;
727 bfin_spi_giveback(drv_data);
728 return;
729 }
730
731 /* In dma mode, rx or tx must be NULL in one transfer */
732 dma_config = (RESTART | dma_width | DI_EN);
733 if (drv_data->rx != NULL) {
734 /* set transfer mode, and enable SPI */
735 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
736 drv_data->rx, drv_data->len_in_bytes);
737
738 /* invalidate caches, if needed */
739 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
740 invalidate_dcache_range((unsigned long) drv_data->rx,
741 (unsigned long) (drv_data->rx +
742 drv_data->len_in_bytes));
743
744 dma_config |= WNR;
745 dma_start_addr = (unsigned long)drv_data->rx;
746 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
747
748 } else if (drv_data->tx != NULL) {
749 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
750
751 /* flush caches, if needed */
752 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
753 flush_dcache_range((unsigned long) drv_data->tx,
754 (unsigned long) (drv_data->tx +
755 drv_data->len_in_bytes));
756
757 dma_start_addr = (unsigned long)drv_data->tx;
758 cr |= BIT_CTL_TIMOD_DMA_TX;
759
760 } else
761 BUG();
762
763 /* oh man, here there be monsters ... and i dont mean the
764 * fluffy cute ones from pixar, i mean the kind that'll eat
765 * your data, kick your dog, and love it all. do *not* try
766 * and change these lines unless you (1) heavily test DMA
767 * with SPI flashes on a loaded system (e.g. ping floods),
768 * (2) know just how broken the DMA engine interaction with
769 * the SPI peripheral is, and (3) have someone else to blame
770 * when you screw it all up anyways.
771 */
772 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
773 set_dma_config(drv_data->dma_channel, dma_config);
774 local_irq_save(flags);
775 SSYNC();
776 bfin_write(&drv_data->regs->ctl, cr);
777 enable_dma(drv_data->dma_channel);
778 dma_enable_irq(drv_data->dma_channel);
779 local_irq_restore(flags);
780
781 return;
782 }
783
784 /*
785 * We always use SPI_WRITE mode (transfer starts with TDBR write).
786 * SPI_READ mode (transfer starts with RDBR read) seems to have
787 * problems with setting up the output value in TDBR prior to the
788 * start of the transfer.
789 */
790 bfin_write(&drv_data->regs->ctl, cr | BIT_CTL_TXMOD);
791
792 if (chip->pio_interrupt) {
793 /* SPI irq should have been disabled by now */
794
795 /* discard old RX data and clear RXS */
796 bfin_spi_dummy_read(drv_data);
797
798 /* start transfer */
799 if (drv_data->tx == NULL)
800 bfin_write(&drv_data->regs->tdbr, chip->idle_tx_val);
801 else {
802 int loop;
803 if (bits_per_word == 16) {
804 u16 *buf = (u16 *)drv_data->tx;
805 for (loop = 0; loop < bits_per_word / 16;
806 loop++) {
807 bfin_write(&drv_data->regs->tdbr, *buf++);
808 }
809 } else if (bits_per_word == 8) {
810 u8 *buf = (u8 *)drv_data->tx;
811 for (loop = 0; loop < bits_per_word / 8; loop++)
812 bfin_write(&drv_data->regs->tdbr, *buf++);
813 }
814
815 drv_data->tx += drv_data->n_bytes;
816 }
817
818 /* once TDBR is empty, interrupt is triggered */
819 enable_irq(drv_data->spi_irq);
820 return;
821 }
822
823 /* IO mode */
824 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
825
826 if (full_duplex) {
827 /* full duplex mode */
828 BUG_ON((drv_data->tx_end - drv_data->tx) !=
829 (drv_data->rx_end - drv_data->rx));
830 dev_dbg(&drv_data->pdev->dev,
831 "IO duplex: cr is 0x%x\n", cr);
832
833 drv_data->ops->duplex(drv_data);
834
835 if (drv_data->tx != drv_data->tx_end)
836 tranf_success = 0;
837 } else if (drv_data->tx != NULL) {
838 /* write only half duplex */
839 dev_dbg(&drv_data->pdev->dev,
840 "IO write: cr is 0x%x\n", cr);
841
842 drv_data->ops->write(drv_data);
843
844 if (drv_data->tx != drv_data->tx_end)
845 tranf_success = 0;
846 } else if (drv_data->rx != NULL) {
847 /* read only half duplex */
848 dev_dbg(&drv_data->pdev->dev,
849 "IO read: cr is 0x%x\n", cr);
850
851 drv_data->ops->read(drv_data);
852 if (drv_data->rx != drv_data->rx_end)
853 tranf_success = 0;
854 }
855
856 if (!tranf_success) {
857 dev_dbg(&drv_data->pdev->dev,
858 "IO write error!\n");
859 message->state = ERROR_STATE;
860 } else {
861 /* Update total byte transferred */
862 message->actual_length += drv_data->len_in_bytes;
863 /* Move to next transfer of this msg */
864 message->state = bfin_spi_next_transfer(drv_data);
865 if (drv_data->cs_change && message->state != DONE_STATE) {
866 bfin_spi_flush(drv_data);
867 bfin_spi_cs_deactive(drv_data, chip);
868 }
869 }
870
871 /* Schedule next transfer tasklet */
872 tasklet_schedule(&drv_data->pump_transfers);
873}
874
875/* pop a msg from queue and kick off real transfer */
876static void bfin_spi_pump_messages(struct work_struct *work)
877{
878 struct bfin_spi_master_data *drv_data;
879 unsigned long flags;
880
881 drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
882
883 /* Lock queue and check for queue work */
884 spin_lock_irqsave(&drv_data->lock, flags);
885 if (list_empty(&drv_data->queue) || !drv_data->running) {
886 /* pumper kicked off but no work to do */
887 drv_data->busy = 0;
888 spin_unlock_irqrestore(&drv_data->lock, flags);
889 return;
890 }
891
892 /* Make sure we are not already running a message */
893 if (drv_data->cur_msg) {
894 spin_unlock_irqrestore(&drv_data->lock, flags);
895 return;
896 }
897
898 /* Extract head of queue */
899 drv_data->cur_msg = list_entry(drv_data->queue.next,
900 struct spi_message, queue);
901
902 /* Setup the SSP using the per chip configuration */
903 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
904 bfin_spi_restore_state(drv_data);
905
906 list_del_init(&drv_data->cur_msg->queue);
907
908 /* Initial message state */
909 drv_data->cur_msg->state = START_STATE;
910 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
911 struct spi_transfer, transfer_list);
912
913 dev_dbg(&drv_data->pdev->dev,
914 "got a message to pump, state is set to: baud "
915 "%d, flag 0x%x, ctl 0x%x\n",
916 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
917 drv_data->cur_chip->ctl_reg);
918
919 dev_dbg(&drv_data->pdev->dev,
920 "the first transfer len is %d\n",
921 drv_data->cur_transfer->len);
922
923 /* Mark as busy and launch transfers */
924 tasklet_schedule(&drv_data->pump_transfers);
925
926 drv_data->busy = 1;
927 spin_unlock_irqrestore(&drv_data->lock, flags);
928}
929
930/*
931 * got a msg to transfer, queue it in drv_data->queue.
932 * And kick off message pumper
933 */
934static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
935{
936 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
937 unsigned long flags;
938
939 spin_lock_irqsave(&drv_data->lock, flags);
940
941 if (!drv_data->running) {
942 spin_unlock_irqrestore(&drv_data->lock, flags);
943 return -ESHUTDOWN;
944 }
945
946 msg->actual_length = 0;
947 msg->status = -EINPROGRESS;
948 msg->state = START_STATE;
949
950 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
951 list_add_tail(&msg->queue, &drv_data->queue);
952
953 if (drv_data->running && !drv_data->busy)
954 queue_work(drv_data->workqueue, &drv_data->pump_messages);
955
956 spin_unlock_irqrestore(&drv_data->lock, flags);
957
958 return 0;
959}
960
961#define MAX_SPI_SSEL 7
962
963static const u16 ssel[][MAX_SPI_SSEL] = {
964 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
965 P_SPI0_SSEL4, P_SPI0_SSEL5,
966 P_SPI0_SSEL6, P_SPI0_SSEL7},
967
968 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
969 P_SPI1_SSEL4, P_SPI1_SSEL5,
970 P_SPI1_SSEL6, P_SPI1_SSEL7},
971
972 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
973 P_SPI2_SSEL4, P_SPI2_SSEL5,
974 P_SPI2_SSEL6, P_SPI2_SSEL7},
975};
976
977/* setup for devices (may be called multiple times -- not just first setup) */
978static int bfin_spi_setup(struct spi_device *spi)
979{
980 struct bfin5xx_spi_chip *chip_info;
981 struct bfin_spi_slave_data *chip = NULL;
982 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
983 u16 bfin_ctl_reg;
984 int ret = -EINVAL;
985
986 /* Only alloc (or use chip_info) on first setup */
987 chip_info = NULL;
988 chip = spi_get_ctldata(spi);
989 if (chip == NULL) {
990 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
991 if (!chip) {
992 dev_err(&spi->dev, "cannot allocate chip data\n");
993 ret = -ENOMEM;
994 goto error;
995 }
996
997 chip->enable_dma = 0;
998 chip_info = spi->controller_data;
999 }
1000
1001 /* Let people set non-standard bits directly */
1002 bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
1003 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
1004
1005 /* chip_info isn't always needed */
1006 if (chip_info) {
1007 /* Make sure people stop trying to set fields via ctl_reg
1008 * when they should actually be using common SPI framework.
1009 * Currently we let through: WOM EMISO PSSE GM SZ.
1010 * Not sure if a user actually needs/uses any of these,
1011 * but let's assume (for now) they do.
1012 */
1013 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1014 dev_err(&spi->dev,
1015 "do not set bits in ctl_reg that the SPI framework manages\n");
1016 goto error;
1017 }
1018 chip->enable_dma = chip_info->enable_dma != 0
1019 && drv_data->master_info->enable_dma;
1020 chip->ctl_reg = chip_info->ctl_reg;
1021 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1022 chip->idle_tx_val = chip_info->idle_tx_val;
1023 chip->pio_interrupt = chip_info->pio_interrupt;
1024 } else {
1025 /* force a default base state */
1026 chip->ctl_reg &= bfin_ctl_reg;
1027 }
1028
1029 /* translate common spi framework into our register */
1030 if (spi->mode & SPI_CPOL)
1031 chip->ctl_reg |= BIT_CTL_CPOL;
1032 if (spi->mode & SPI_CPHA)
1033 chip->ctl_reg |= BIT_CTL_CPHA;
1034 if (spi->mode & SPI_LSB_FIRST)
1035 chip->ctl_reg |= BIT_CTL_LSBF;
1036 /* we dont support running in slave mode (yet?) */
1037 chip->ctl_reg |= BIT_CTL_MASTER;
1038
1039 /*
1040 * Notice: for blackfin, the speed_hz is the value of register
1041 * SPI_BAUD, not the real baudrate
1042 */
1043 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1044 chip->chip_select_num = spi->chip_select;
1045 if (chip->chip_select_num < MAX_CTRL_CS) {
1046 if (!(spi->mode & SPI_CPHA))
1047 dev_warn(&spi->dev,
1048 "Warning: SPI CPHA not set: Slave Select not under software control!\n"
1049 "See Documentation/blackfin/bfin-spi-notes.txt\n");
1050
1051 chip->flag = (1 << spi->chip_select) << 8;
1052 } else
1053 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1054
1055 if (chip->enable_dma && chip->pio_interrupt) {
1056 dev_err(&spi->dev,
1057 "enable_dma is set, do not set pio_interrupt\n");
1058 goto error;
1059 }
1060 /*
1061 * if any one SPI chip is registered and wants DMA, request the
1062 * DMA channel for it
1063 */
1064 if (chip->enable_dma && !drv_data->dma_requested) {
1065 /* register dma irq handler */
1066 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1067 if (ret) {
1068 dev_err(&spi->dev,
1069 "Unable to request BlackFin SPI DMA channel\n");
1070 goto error;
1071 }
1072 drv_data->dma_requested = 1;
1073
1074 ret = set_dma_callback(drv_data->dma_channel,
1075 bfin_spi_dma_irq_handler, drv_data);
1076 if (ret) {
1077 dev_err(&spi->dev, "Unable to set dma callback\n");
1078 goto error;
1079 }
1080 dma_disable_irq(drv_data->dma_channel);
1081 }
1082
1083 if (chip->pio_interrupt && !drv_data->irq_requested) {
1084 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1085 0, "BFIN_SPI", drv_data);
1086 if (ret) {
1087 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1088 goto error;
1089 }
1090 drv_data->irq_requested = 1;
1091 /* we use write mode, spi irq has to be disabled here */
1092 disable_irq(drv_data->spi_irq);
1093 }
1094
1095 if (chip->chip_select_num >= MAX_CTRL_CS) {
1096 /* Only request on first setup */
1097 if (spi_get_ctldata(spi) == NULL) {
1098 ret = gpio_request(chip->cs_gpio, spi->modalias);
1099 if (ret) {
1100 dev_err(&spi->dev, "gpio_request() error\n");
1101 goto pin_error;
1102 }
1103 gpio_direction_output(chip->cs_gpio, 1);
1104 }
1105 }
1106
1107 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1108 spi->modalias, spi->bits_per_word, chip->enable_dma);
1109 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1110 chip->ctl_reg, chip->flag);
1111
1112 spi_set_ctldata(spi, chip);
1113
1114 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1115 if (chip->chip_select_num < MAX_CTRL_CS) {
1116 ret = peripheral_request(ssel[spi->master->bus_num]
1117 [chip->chip_select_num-1], spi->modalias);
1118 if (ret) {
1119 dev_err(&spi->dev, "peripheral_request() error\n");
1120 goto pin_error;
1121 }
1122 }
1123
1124 bfin_spi_cs_enable(drv_data, chip);
1125 bfin_spi_cs_deactive(drv_data, chip);
1126
1127 return 0;
1128
1129 pin_error:
1130 if (chip->chip_select_num >= MAX_CTRL_CS)
1131 gpio_free(chip->cs_gpio);
1132 else
1133 peripheral_free(ssel[spi->master->bus_num]
1134 [chip->chip_select_num - 1]);
1135 error:
1136 if (chip) {
1137 if (drv_data->dma_requested)
1138 free_dma(drv_data->dma_channel);
1139 drv_data->dma_requested = 0;
1140
1141 kfree(chip);
1142 /* prevent free 'chip' twice */
1143 spi_set_ctldata(spi, NULL);
1144 }
1145
1146 return ret;
1147}
1148
1149/*
1150 * callback for spi framework.
1151 * clean driver specific data
1152 */
1153static void bfin_spi_cleanup(struct spi_device *spi)
1154{
1155 struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
1156 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1157
1158 if (!chip)
1159 return;
1160
1161 if (chip->chip_select_num < MAX_CTRL_CS) {
1162 peripheral_free(ssel[spi->master->bus_num]
1163 [chip->chip_select_num-1]);
1164 bfin_spi_cs_disable(drv_data, chip);
1165 } else
1166 gpio_free(chip->cs_gpio);
1167
1168 kfree(chip);
1169 /* prevent free 'chip' twice */
1170 spi_set_ctldata(spi, NULL);
1171}
1172
1173static int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
1174{
1175 INIT_LIST_HEAD(&drv_data->queue);
1176 spin_lock_init(&drv_data->lock);
1177
1178 drv_data->running = false;
1179 drv_data->busy = 0;
1180
1181 /* init transfer tasklet */
1182 tasklet_init(&drv_data->pump_transfers,
1183 bfin_spi_pump_transfers, (unsigned long)drv_data);
1184
1185 /* init messages workqueue */
1186 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1187 drv_data->workqueue = create_singlethread_workqueue(
1188 dev_name(drv_data->master->dev.parent));
1189 if (drv_data->workqueue == NULL)
1190 return -EBUSY;
1191
1192 return 0;
1193}
1194
1195static int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
1196{
1197 unsigned long flags;
1198
1199 spin_lock_irqsave(&drv_data->lock, flags);
1200
1201 if (drv_data->running || drv_data->busy) {
1202 spin_unlock_irqrestore(&drv_data->lock, flags);
1203 return -EBUSY;
1204 }
1205
1206 drv_data->running = true;
1207 drv_data->cur_msg = NULL;
1208 drv_data->cur_transfer = NULL;
1209 drv_data->cur_chip = NULL;
1210 spin_unlock_irqrestore(&drv_data->lock, flags);
1211
1212 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1213
1214 return 0;
1215}
1216
1217static int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
1218{
1219 unsigned long flags;
1220 unsigned limit = 500;
1221 int status = 0;
1222
1223 spin_lock_irqsave(&drv_data->lock, flags);
1224
1225 /*
1226 * This is a bit lame, but is optimized for the common execution path.
1227 * A wait_queue on the drv_data->busy could be used, but then the common
1228 * execution path (pump_messages) would be required to call wake_up or
1229 * friends on every SPI message. Do this instead
1230 */
1231 drv_data->running = false;
1232 while ((!list_empty(&drv_data->queue) || drv_data->busy) && limit--) {
1233 spin_unlock_irqrestore(&drv_data->lock, flags);
1234 msleep(10);
1235 spin_lock_irqsave(&drv_data->lock, flags);
1236 }
1237
1238 if (!list_empty(&drv_data->queue) || drv_data->busy)
1239 status = -EBUSY;
1240
1241 spin_unlock_irqrestore(&drv_data->lock, flags);
1242
1243 return status;
1244}
1245
1246static int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
1247{
1248 int status;
1249
1250 status = bfin_spi_stop_queue(drv_data);
1251 if (status != 0)
1252 return status;
1253
1254 destroy_workqueue(drv_data->workqueue);
1255
1256 return 0;
1257}
1258
1259static int bfin_spi_probe(struct platform_device *pdev)
1260{
1261 struct device *dev = &pdev->dev;
1262 struct bfin5xx_spi_master *platform_info;
1263 struct spi_master *master;
1264 struct bfin_spi_master_data *drv_data;
1265 struct resource *res;
1266 int status = 0;
1267
1268 platform_info = dev_get_platdata(dev);
1269
1270 /* Allocate master with space for drv_data */
1271 master = spi_alloc_master(dev, sizeof(*drv_data));
1272 if (!master) {
1273 dev_err(&pdev->dev, "can not alloc spi_master\n");
1274 return -ENOMEM;
1275 }
1276
1277 drv_data = spi_master_get_devdata(master);
1278 drv_data->master = master;
1279 drv_data->master_info = platform_info;
1280 drv_data->pdev = pdev;
1281 drv_data->pin_req = platform_info->pin_req;
1282
1283 /* the spi->mode bits supported by this driver: */
1284 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1285 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
1286 master->bus_num = pdev->id;
1287 master->num_chipselect = platform_info->num_chipselect;
1288 master->cleanup = bfin_spi_cleanup;
1289 master->setup = bfin_spi_setup;
1290 master->transfer = bfin_spi_transfer;
1291
1292 /* Find and map our resources */
1293 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1294 if (res == NULL) {
1295 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1296 status = -ENOENT;
1297 goto out_error_get_res;
1298 }
1299
1300 drv_data->regs = ioremap(res->start, resource_size(res));
1301 if (drv_data->regs == NULL) {
1302 dev_err(dev, "Cannot map IO\n");
1303 status = -ENXIO;
1304 goto out_error_ioremap;
1305 }
1306
1307 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1308 if (res == NULL) {
1309 dev_err(dev, "No DMA channel specified\n");
1310 status = -ENOENT;
1311 goto out_error_free_io;
1312 }
1313 drv_data->dma_channel = res->start;
1314
1315 drv_data->spi_irq = platform_get_irq(pdev, 0);
1316 if (drv_data->spi_irq < 0) {
1317 dev_err(dev, "No spi pio irq specified\n");
1318 status = -ENOENT;
1319 goto out_error_free_io;
1320 }
1321
1322 /* Initial and start queue */
1323 status = bfin_spi_init_queue(drv_data);
1324 if (status != 0) {
1325 dev_err(dev, "problem initializing queue\n");
1326 goto out_error_queue_alloc;
1327 }
1328
1329 status = bfin_spi_start_queue(drv_data);
1330 if (status != 0) {
1331 dev_err(dev, "problem starting queue\n");
1332 goto out_error_queue_alloc;
1333 }
1334
1335 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1336 if (status != 0) {
1337 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1338 goto out_error_queue_alloc;
1339 }
1340
1341 /* Reset SPI registers. If these registers were used by the boot loader,
1342 * the sky may fall on your head if you enable the dma controller.
1343 */
1344 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1345 bfin_write(&drv_data->regs->flg, 0xFF00);
1346
1347 /* Register with the SPI framework */
1348 platform_set_drvdata(pdev, drv_data);
1349 status = spi_register_master(master);
1350 if (status != 0) {
1351 dev_err(dev, "problem registering spi master\n");
1352 goto out_error_queue_alloc;
1353 }
1354
1355 dev_info(dev, "%s, Version %s, regs@%p, dma channel@%d\n",
1356 DRV_DESC, DRV_VERSION, drv_data->regs,
1357 drv_data->dma_channel);
1358 return status;
1359
1360out_error_queue_alloc:
1361 bfin_spi_destroy_queue(drv_data);
1362out_error_free_io:
1363 iounmap(drv_data->regs);
1364out_error_ioremap:
1365out_error_get_res:
1366 spi_master_put(master);
1367
1368 return status;
1369}
1370
1371/* stop hardware and remove the driver */
1372static int bfin_spi_remove(struct platform_device *pdev)
1373{
1374 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1375 int status = 0;
1376
1377 if (!drv_data)
1378 return 0;
1379
1380 /* Remove the queue */
1381 status = bfin_spi_destroy_queue(drv_data);
1382 if (status != 0)
1383 return status;
1384
1385 /* Disable the SSP at the peripheral and SOC level */
1386 bfin_spi_disable(drv_data);
1387
1388 /* Release DMA */
1389 if (drv_data->master_info->enable_dma) {
1390 if (dma_channel_active(drv_data->dma_channel))
1391 free_dma(drv_data->dma_channel);
1392 }
1393
1394 if (drv_data->irq_requested) {
1395 free_irq(drv_data->spi_irq, drv_data);
1396 drv_data->irq_requested = 0;
1397 }
1398
1399 /* Disconnect from the SPI framework */
1400 spi_unregister_master(drv_data->master);
1401
1402 peripheral_free_list(drv_data->pin_req);
1403
1404 return 0;
1405}
1406
1407#ifdef CONFIG_PM_SLEEP
1408static int bfin_spi_suspend(struct device *dev)
1409{
1410 struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev);
1411 int status = 0;
1412
1413 status = bfin_spi_stop_queue(drv_data);
1414 if (status != 0)
1415 return status;
1416
1417 drv_data->ctrl_reg = bfin_read(&drv_data->regs->ctl);
1418 drv_data->flag_reg = bfin_read(&drv_data->regs->flg);
1419
1420 /*
1421 * reset SPI_CTL and SPI_FLG registers
1422 */
1423 bfin_write(&drv_data->regs->ctl, BIT_CTL_CPHA | BIT_CTL_MASTER);
1424 bfin_write(&drv_data->regs->flg, 0xFF00);
1425
1426 return 0;
1427}
1428
1429static int bfin_spi_resume(struct device *dev)
1430{
1431 struct bfin_spi_master_data *drv_data = dev_get_drvdata(dev);
1432 int status = 0;
1433
1434 bfin_write(&drv_data->regs->ctl, drv_data->ctrl_reg);
1435 bfin_write(&drv_data->regs->flg, drv_data->flag_reg);
1436
1437 /* Start the queue running */
1438 status = bfin_spi_start_queue(drv_data);
1439 if (status != 0) {
1440 dev_err(dev, "problem starting queue (%d)\n", status);
1441 return status;
1442 }
1443
1444 return 0;
1445}
1446
1447static SIMPLE_DEV_PM_OPS(bfin_spi_pm_ops, bfin_spi_suspend, bfin_spi_resume);
1448
1449#define BFIN_SPI_PM_OPS (&bfin_spi_pm_ops)
1450#else
1451#define BFIN_SPI_PM_OPS NULL
1452#endif
1453
1454MODULE_ALIAS("platform:bfin-spi");
1455static struct platform_driver bfin_spi_driver = {
1456 .driver = {
1457 .name = DRV_NAME,
1458 .owner = THIS_MODULE,
1459 .pm = BFIN_SPI_PM_OPS,
1460 },
1461 .probe = bfin_spi_probe,
1462 .remove = bfin_spi_remove,
1463};
1464
1465static int __init bfin_spi_init(void)
1466{
1467 return platform_driver_register(&bfin_spi_driver);
1468}
1469subsys_initcall(bfin_spi_init);
1470
1471static void __exit bfin_spi_exit(void)
1472{
1473 platform_driver_unregister(&bfin_spi_driver);
1474}
1475module_exit(bfin_spi_exit);