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1/*
2 * Pinctrl Driver for ADI GPIO2 controller
3 *
4 * Copyright 2007-2013 Analog Devices Inc.
5 *
6 * Licensed under the GPLv2 or later
7 */
8
9#include <linux/bitops.h>
10#include <linux/delay.h>
11#include <linux/module.h>
12#include <linux/err.h>
13#include <linux/debugfs.h>
14#include <linux/seq_file.h>
15#include <linux/irq.h>
16#include <linux/platform_data/pinctrl-adi2.h>
17#include <linux/irqdomain.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/pinctrl/consumer.h>
22#include <linux/pinctrl/machine.h>
23#include <linux/syscore_ops.h>
24#include <linux/gpio.h>
25#include <asm/portmux.h>
26#include "pinctrl-adi2.h"
27#include "core.h"
28
29/*
30According to the BF54x HRM, pint means "pin interrupt".
31http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf
32
33ADSP-BF54x processor Blackfin processors have four SIC interrupt chan-
34nels dedicated to pin interrupt purposes. These channels are managed by
35four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx
36block can sense to up to 32 pins. While PINT0 and PINT1 can sense the
37pins of port A and port B, PINT2 and PINT3 manage all the pins from port
38C to port J as shown in Figure 9-2.
39
40n BF54x HRM:
41The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and
42upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi-
43plexers shown in Figure 9-3. Lower half units of eight pins can be
44forwarded to either byte 0 or byte 2 of either associated PINTx block.
45Upper half units can be forwarded to either byte 1 or byte 3 of the pin
46interrupt blocks, without further restrictions.
47
48All MMR registers in the pin interrupt module are 32 bits wide. To simply the
49mapping logic, this driver only maps a 16-bit gpio port to the upper or lower
5016 bits of a PINTx block. You can find the Figure 9-3 on page 583.
51
52Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map
53to one PINT device. Two in "struct gpio_pint" are used to ease the PINT
54interrupt handler.
55
56The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ
57domain pointer in domain[0]. The IRQ domain pointer of the other bank is set
58to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out
59the current domain pointer according to whether the interrupt request mask
60is in lower 16 bits (domain[0]) or upper 16bits (domain[1]).
61
62A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO
63port devices can be mapped to the same PINT device.
64
65*/
66
67static LIST_HEAD(adi_pint_list);
68static LIST_HEAD(adi_gpio_port_list);
69
70#define DRIVER_NAME "pinctrl-adi2"
71
72#define PINT_HI_OFFSET 16
73
74/**
75 * struct gpio_port_saved - GPIO port registers that should be saved between
76 * power suspend and resume operations.
77 *
78 * @fer: PORTx_FER register
79 * @data: PORTx_DATA register
80 * @dir: PORTx_DIR register
81 * @inen: PORTx_INEN register
82 * @mux: PORTx_MUX register
83 */
84struct gpio_port_saved {
85 u16 fer;
86 u16 data;
87 u16 dir;
88 u16 inen;
89 u32 mux;
90};
91
92/*
93 * struct gpio_pint_saved - PINT registers saved in PM operations
94 *
95 * @assign: ASSIGN register
96 * @edge_set: EDGE_SET register
97 * @invert_set: INVERT_SET register
98 */
99struct gpio_pint_saved {
100 u32 assign;
101 u32 edge_set;
102 u32 invert_set;
103};
104
105/**
106 * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO
107 * banks can be mapped into one Pin interrupt controller.
108 *
109 * @node: All gpio_pint instances are added to a global list.
110 * @base: PINT device register base address
111 * @irq: IRQ of the PINT device, it is the parent IRQ of all
112 * GPIO IRQs mapping to this device.
113 * @domain: [0] irq domain of the gpio port, whose hardware interrupts are
114 * mapping to the low 16-bit of the pint registers.
115 * [1] irq domain of the gpio port, whose hardware interrupts are
116 * mapping to the high 16-bit of the pint registers.
117 * @regs: address pointer to the PINT device
118 * @map_count: No more than 2 GPIO banks can be mapped to this PINT device.
119 * @lock: This lock make sure the irq_chip operations to one PINT device
120 * for different GPIO interrrupts are atomic.
121 * @pint_map_port: Set up the mapping between one PINT device and
122 * multiple GPIO banks.
123 */
124struct gpio_pint {
125 struct list_head node;
126 void __iomem *base;
127 int irq;
128 struct irq_domain *domain[2];
129 struct gpio_pint_regs *regs;
130 struct gpio_pint_saved saved_data;
131 int map_count;
132 spinlock_t lock;
133
134 int (*pint_map_port)(struct gpio_pint *pint, bool assign,
135 u8 map, struct irq_domain *domain);
136};
137
138/**
139 * ADI pin controller
140 *
141 * @dev: a pointer back to containing device
142 * @pctl: the pinctrl device
143 * @soc: SoC data for this specific chip
144 */
145struct adi_pinctrl {
146 struct device *dev;
147 struct pinctrl_dev *pctl;
148 const struct adi_pinctrl_soc_data *soc;
149};
150
151/**
152 * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped
153 * into one pin interrupt controller.
154 *
155 * @node: All gpio_port instances are added to a list.
156 * @base: GPIO bank device register base address
157 * @irq_base: base IRQ of the GPIO bank device
158 * @width: PIN number of the GPIO bank device
159 * @regs: address pointer to the GPIO bank device
160 * @saved_data: registers that should be saved between PM operations.
161 * @dev: device structure of this GPIO bank
162 * @pint: GPIO PINT device that this GPIO bank mapped to
163 * @pint_map: GIOP bank mapping code in PINT device
164 * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A
165 * GPIO bank can be mapped into either low 16 bits[0] or high 16
166 * bits[1] of each PINT register.
167 * @lock: This lock make sure the irq_chip operations to one PINT device
168 * for different GPIO interrrupts are atomic.
169 * @chip: abstract a GPIO controller
170 * @domain: The irq domain owned by the GPIO port.
171 * @rsvmap: Reservation map array for each pin in the GPIO bank
172 */
173struct gpio_port {
174 struct list_head node;
175 void __iomem *base;
176 int irq_base;
177 unsigned int width;
178 struct gpio_port_t *regs;
179 struct gpio_port_saved saved_data;
180 struct device *dev;
181
182 struct gpio_pint *pint;
183 u8 pint_map;
184 bool pint_assign;
185
186 spinlock_t lock;
187 struct gpio_chip chip;
188 struct irq_domain *domain;
189};
190
191static inline u8 pin_to_offset(struct pinctrl_gpio_range *range, unsigned pin)
192{
193 return pin - range->pin_base;
194}
195
196static inline u32 hwirq_to_pintbit(struct gpio_port *port, int hwirq)
197{
198 return port->pint_assign ? BIT(hwirq) << PINT_HI_OFFSET : BIT(hwirq);
199}
200
201static struct gpio_pint *find_gpio_pint(unsigned id)
202{
203 struct gpio_pint *pint;
204 int i = 0;
205
206 list_for_each_entry(pint, &adi_pint_list, node) {
207 if (id == i)
208 return pint;
209 i++;
210 }
211
212 return NULL;
213}
214
215static inline void port_setup(struct gpio_port *port, unsigned offset,
216 bool use_for_gpio)
217{
218 struct gpio_port_t *regs = port->regs;
219
220 if (use_for_gpio)
221 writew(readw(®s->port_fer) & ~BIT(offset),
222 ®s->port_fer);
223 else
224 writew(readw(®s->port_fer) | BIT(offset), ®s->port_fer);
225}
226
227static inline void portmux_setup(struct gpio_port *port, unsigned offset,
228 unsigned short function)
229{
230 struct gpio_port_t *regs = port->regs;
231 u32 pmux;
232
233 pmux = readl(®s->port_mux);
234
235 /* The function field of each pin has 2 consecutive bits in
236 * the mux register.
237 */
238 pmux &= ~(0x3 << (2 * offset));
239 pmux |= (function & 0x3) << (2 * offset);
240
241 writel(pmux, ®s->port_mux);
242}
243
244static inline u16 get_portmux(struct gpio_port *port, unsigned offset)
245{
246 struct gpio_port_t *regs = port->regs;
247 u32 pmux = readl(®s->port_mux);
248
249 /* The function field of each pin has 2 consecutive bits in
250 * the mux register.
251 */
252 return pmux >> (2 * offset) & 0x3;
253}
254
255static void adi_gpio_ack_irq(struct irq_data *d)
256{
257 unsigned long flags;
258 struct gpio_port *port = irq_data_get_irq_chip_data(d);
259 struct gpio_pint_regs *regs = port->pint->regs;
260 unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
261
262 spin_lock_irqsave(&port->lock, flags);
263 spin_lock(&port->pint->lock);
264
265 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
266 if (readl(®s->invert_set) & pintbit)
267 writel(pintbit, ®s->invert_clear);
268 else
269 writel(pintbit, ®s->invert_set);
270 }
271
272 writel(pintbit, ®s->request);
273
274 spin_unlock(&port->pint->lock);
275 spin_unlock_irqrestore(&port->lock, flags);
276}
277
278static void adi_gpio_mask_ack_irq(struct irq_data *d)
279{
280 unsigned long flags;
281 struct gpio_port *port = irq_data_get_irq_chip_data(d);
282 struct gpio_pint_regs *regs = port->pint->regs;
283 unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
284
285 spin_lock_irqsave(&port->lock, flags);
286 spin_lock(&port->pint->lock);
287
288 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
289 if (readl(®s->invert_set) & pintbit)
290 writel(pintbit, ®s->invert_clear);
291 else
292 writel(pintbit, ®s->invert_set);
293 }
294
295 writel(pintbit, ®s->request);
296 writel(pintbit, ®s->mask_clear);
297
298 spin_unlock(&port->pint->lock);
299 spin_unlock_irqrestore(&port->lock, flags);
300}
301
302static void adi_gpio_mask_irq(struct irq_data *d)
303{
304 unsigned long flags;
305 struct gpio_port *port = irq_data_get_irq_chip_data(d);
306 struct gpio_pint_regs *regs = port->pint->regs;
307
308 spin_lock_irqsave(&port->lock, flags);
309 spin_lock(&port->pint->lock);
310
311 writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear);
312
313 spin_unlock(&port->pint->lock);
314 spin_unlock_irqrestore(&port->lock, flags);
315}
316
317static void adi_gpio_unmask_irq(struct irq_data *d)
318{
319 unsigned long flags;
320 struct gpio_port *port = irq_data_get_irq_chip_data(d);
321 struct gpio_pint_regs *regs = port->pint->regs;
322
323 spin_lock_irqsave(&port->lock, flags);
324 spin_lock(&port->pint->lock);
325
326 writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set);
327
328 spin_unlock(&port->pint->lock);
329 spin_unlock_irqrestore(&port->lock, flags);
330}
331
332static unsigned int adi_gpio_irq_startup(struct irq_data *d)
333{
334 unsigned long flags;
335 struct gpio_port *port = irq_data_get_irq_chip_data(d);
336 struct gpio_pint_regs *regs;
337
338 if (!port) {
339 pr_err("GPIO IRQ %d :Not exist\n", d->irq);
340 /* FIXME: negative return code will be ignored */
341 return -ENODEV;
342 }
343
344 regs = port->pint->regs;
345
346 spin_lock_irqsave(&port->lock, flags);
347 spin_lock(&port->pint->lock);
348
349 port_setup(port, d->hwirq, true);
350 writew(BIT(d->hwirq), &port->regs->dir_clear);
351 writew(readw(&port->regs->inen) | BIT(d->hwirq), &port->regs->inen);
352
353 writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_set);
354
355 spin_unlock(&port->pint->lock);
356 spin_unlock_irqrestore(&port->lock, flags);
357
358 return 0;
359}
360
361static void adi_gpio_irq_shutdown(struct irq_data *d)
362{
363 unsigned long flags;
364 struct gpio_port *port = irq_data_get_irq_chip_data(d);
365 struct gpio_pint_regs *regs = port->pint->regs;
366
367 spin_lock_irqsave(&port->lock, flags);
368 spin_lock(&port->pint->lock);
369
370 writel(hwirq_to_pintbit(port, d->hwirq), ®s->mask_clear);
371
372 spin_unlock(&port->pint->lock);
373 spin_unlock_irqrestore(&port->lock, flags);
374}
375
376static int adi_gpio_irq_type(struct irq_data *d, unsigned int type)
377{
378 unsigned long flags;
379 struct gpio_port *port = irq_data_get_irq_chip_data(d);
380 struct gpio_pint_regs *pint_regs;
381 unsigned pintmask;
382 unsigned int irq = d->irq;
383 int ret = 0;
384 char buf[16];
385
386 if (!port) {
387 pr_err("GPIO IRQ %d :Not exist\n", d->irq);
388 return -ENODEV;
389 }
390
391 pint_regs = port->pint->regs;
392
393 pintmask = hwirq_to_pintbit(port, d->hwirq);
394
395 spin_lock_irqsave(&port->lock, flags);
396 spin_lock(&port->pint->lock);
397
398 /* In case of interrupt autodetect, set irq type to edge sensitive. */
399 if (type == IRQ_TYPE_PROBE)
400 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
401
402 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
403 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
404 snprintf(buf, 16, "gpio-irq%d", irq);
405 port_setup(port, d->hwirq, true);
406 } else
407 goto out;
408
409 /* The GPIO interrupt is triggered only when its input value
410 * transfer from 0 to 1. So, invert the input value if the
411 * irq type is low or falling
412 */
413 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
414 writel(pintmask, &pint_regs->invert_set);
415 else
416 writel(pintmask, &pint_regs->invert_clear);
417
418 /* In edge sensitive case, if the input value of the requested irq
419 * is already 1, invert it.
420 */
421 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
422 if (gpio_get_value(port->chip.base + d->hwirq))
423 writel(pintmask, &pint_regs->invert_set);
424 else
425 writel(pintmask, &pint_regs->invert_clear);
426 }
427
428 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
429 writel(pintmask, &pint_regs->edge_set);
430 __irq_set_handler_locked(irq, handle_edge_irq);
431 } else {
432 writel(pintmask, &pint_regs->edge_clear);
433 __irq_set_handler_locked(irq, handle_level_irq);
434 }
435
436out:
437 spin_unlock(&port->pint->lock);
438 spin_unlock_irqrestore(&port->lock, flags);
439
440 return ret;
441}
442
443#ifdef CONFIG_PM
444static int adi_gpio_set_wake(struct irq_data *d, unsigned int state)
445{
446 struct gpio_port *port = irq_data_get_irq_chip_data(d);
447
448 if (!port || !port->pint || port->pint->irq != d->irq)
449 return -EINVAL;
450
451#ifndef SEC_GCTL
452 adi_internal_set_wake(port->pint->irq, state);
453#endif
454
455 return 0;
456}
457
458static int adi_pint_suspend(void)
459{
460 struct gpio_pint *pint;
461
462 list_for_each_entry(pint, &adi_pint_list, node) {
463 writel(0xffffffff, &pint->regs->mask_clear);
464 pint->saved_data.assign = readl(&pint->regs->assign);
465 pint->saved_data.edge_set = readl(&pint->regs->edge_set);
466 pint->saved_data.invert_set = readl(&pint->regs->invert_set);
467 }
468
469 return 0;
470}
471
472static void adi_pint_resume(void)
473{
474 struct gpio_pint *pint;
475
476 list_for_each_entry(pint, &adi_pint_list, node) {
477 writel(pint->saved_data.assign, &pint->regs->assign);
478 writel(pint->saved_data.edge_set, &pint->regs->edge_set);
479 writel(pint->saved_data.invert_set, &pint->regs->invert_set);
480 }
481}
482
483static int adi_gpio_suspend(void)
484{
485 struct gpio_port *port;
486
487 list_for_each_entry(port, &adi_gpio_port_list, node) {
488 port->saved_data.fer = readw(&port->regs->port_fer);
489 port->saved_data.mux = readl(&port->regs->port_mux);
490 port->saved_data.data = readw(&port->regs->data);
491 port->saved_data.inen = readw(&port->regs->inen);
492 port->saved_data.dir = readw(&port->regs->dir_set);
493 }
494
495 return adi_pint_suspend();
496}
497
498static void adi_gpio_resume(void)
499{
500 struct gpio_port *port;
501
502 adi_pint_resume();
503
504 list_for_each_entry(port, &adi_gpio_port_list, node) {
505 writel(port->saved_data.mux, &port->regs->port_mux);
506 writew(port->saved_data.fer, &port->regs->port_fer);
507 writew(port->saved_data.inen, &port->regs->inen);
508 writew(port->saved_data.data & port->saved_data.dir,
509 &port->regs->data_set);
510 writew(port->saved_data.dir, &port->regs->dir_set);
511 }
512
513}
514
515static struct syscore_ops gpio_pm_syscore_ops = {
516 .suspend = adi_gpio_suspend,
517 .resume = adi_gpio_resume,
518};
519#else /* CONFIG_PM */
520#define adi_gpio_set_wake NULL
521#endif /* CONFIG_PM */
522
523#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
524static inline void preflow_handler(struct irq_desc *desc)
525{
526 if (desc->preflow_handler)
527 desc->preflow_handler(&desc->irq_data);
528}
529#else
530static inline void preflow_handler(struct irq_desc *desc) { }
531#endif
532
533static void adi_gpio_handle_pint_irq(unsigned int inta_irq,
534 struct irq_desc *desc)
535{
536 u32 request;
537 u32 level_mask, hwirq;
538 bool umask = false;
539 struct gpio_pint *pint = irq_desc_get_handler_data(desc);
540 struct irq_chip *chip = irq_desc_get_chip(desc);
541 struct gpio_pint_regs *regs = pint->regs;
542 struct irq_domain *domain;
543
544 preflow_handler(desc);
545 chained_irq_enter(chip, desc);
546
547 request = readl(®s->request);
548 level_mask = readl(®s->edge_set) & request;
549
550 hwirq = 0;
551 domain = pint->domain[0];
552 while (request) {
553 /* domain pointer need to be changed only once at IRQ 16 when
554 * we go through IRQ requests from bit 0 to bit 31.
555 */
556 if (hwirq == PINT_HI_OFFSET)
557 domain = pint->domain[1];
558
559 if (request & 1) {
560 if (level_mask & BIT(hwirq)) {
561 umask = true;
562 chained_irq_exit(chip, desc);
563 }
564 generic_handle_irq(irq_find_mapping(domain,
565 hwirq % PINT_HI_OFFSET));
566 }
567
568 hwirq++;
569 request >>= 1;
570 }
571
572 if (!umask)
573 chained_irq_exit(chip, desc);
574}
575
576static struct irq_chip adi_gpio_irqchip = {
577 .name = "GPIO",
578 .irq_ack = adi_gpio_ack_irq,
579 .irq_mask = adi_gpio_mask_irq,
580 .irq_mask_ack = adi_gpio_mask_ack_irq,
581 .irq_unmask = adi_gpio_unmask_irq,
582 .irq_disable = adi_gpio_mask_irq,
583 .irq_enable = adi_gpio_unmask_irq,
584 .irq_set_type = adi_gpio_irq_type,
585 .irq_startup = adi_gpio_irq_startup,
586 .irq_shutdown = adi_gpio_irq_shutdown,
587 .irq_set_wake = adi_gpio_set_wake,
588};
589
590static int adi_get_groups_count(struct pinctrl_dev *pctldev)
591{
592 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
593
594 return pinctrl->soc->ngroups;
595}
596
597static const char *adi_get_group_name(struct pinctrl_dev *pctldev,
598 unsigned selector)
599{
600 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
601
602 return pinctrl->soc->groups[selector].name;
603}
604
605static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
606 const unsigned **pins,
607 unsigned *num_pins)
608{
609 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
610
611 *pins = pinctrl->soc->groups[selector].pins;
612 *num_pins = pinctrl->soc->groups[selector].num;
613 return 0;
614}
615
616static struct pinctrl_ops adi_pctrl_ops = {
617 .get_groups_count = adi_get_groups_count,
618 .get_group_name = adi_get_group_name,
619 .get_group_pins = adi_get_group_pins,
620};
621
622static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id,
623 unsigned group_id)
624{
625 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
626 struct gpio_port *port;
627 struct pinctrl_gpio_range *range;
628 unsigned long flags;
629 unsigned short *mux, pin;
630
631 mux = (unsigned short *)pinctrl->soc->groups[group_id].mux;
632
633 while (*mux) {
634 pin = P_IDENT(*mux);
635
636 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
637 if (range == NULL) /* should not happen */
638 return -ENODEV;
639
640 port = container_of(range->gc, struct gpio_port, chip);
641
642 spin_lock_irqsave(&port->lock, flags);
643
644 portmux_setup(port, pin_to_offset(range, pin),
645 P_FUNCT2MUX(*mux));
646 port_setup(port, pin_to_offset(range, pin), false);
647 mux++;
648
649 spin_unlock_irqrestore(&port->lock, flags);
650 }
651
652 return 0;
653}
654
655static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned func_id,
656 unsigned group_id)
657{
658 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
659 struct gpio_port *port;
660 struct pinctrl_gpio_range *range;
661 unsigned long flags;
662 unsigned short *mux, pin;
663
664 mux = (unsigned short *)pinctrl->soc->groups[group_id].mux;
665
666 while (*mux) {
667 pin = P_IDENT(*mux);
668
669 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
670 if (range == NULL) /* should not happen */
671 return;
672
673 port = container_of(range->gc, struct gpio_port, chip);
674
675 spin_lock_irqsave(&port->lock, flags);
676
677 port_setup(port, pin_to_offset(range, pin), true);
678 mux++;
679
680 spin_unlock_irqrestore(&port->lock, flags);
681 }
682}
683
684static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
685{
686 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
687
688 return pinctrl->soc->nfunctions;
689}
690
691static const char *adi_pinmux_get_func_name(struct pinctrl_dev *pctldev,
692 unsigned selector)
693{
694 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
695
696 return pinctrl->soc->functions[selector].name;
697}
698
699static int adi_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
700 const char * const **groups,
701 unsigned * const num_groups)
702{
703 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
704
705 *groups = pinctrl->soc->functions[selector].groups;
706 *num_groups = pinctrl->soc->functions[selector].num_groups;
707 return 0;
708}
709
710static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
711 struct pinctrl_gpio_range *range, unsigned pin)
712{
713 struct gpio_port *port;
714 unsigned long flags;
715 u8 offset;
716
717 port = container_of(range->gc, struct gpio_port, chip);
718 offset = pin_to_offset(range, pin);
719
720 spin_lock_irqsave(&port->lock, flags);
721
722 port_setup(port, offset, true);
723
724 spin_unlock_irqrestore(&port->lock, flags);
725
726 return 0;
727}
728
729static struct pinmux_ops adi_pinmux_ops = {
730 .enable = adi_pinmux_enable,
731 .disable = adi_pinmux_disable,
732 .get_functions_count = adi_pinmux_get_funcs_count,
733 .get_function_name = adi_pinmux_get_func_name,
734 .get_function_groups = adi_pinmux_get_groups,
735 .gpio_request_enable = adi_pinmux_request_gpio,
736};
737
738
739static struct pinctrl_desc adi_pinmux_desc = {
740 .name = DRIVER_NAME,
741 .pctlops = &adi_pctrl_ops,
742 .pmxops = &adi_pinmux_ops,
743 .owner = THIS_MODULE,
744};
745
746static int adi_gpio_request(struct gpio_chip *chip, unsigned offset)
747{
748 return pinctrl_request_gpio(chip->base + offset);
749}
750
751static void adi_gpio_free(struct gpio_chip *chip, unsigned offset)
752{
753 pinctrl_free_gpio(chip->base + offset);
754}
755
756static int adi_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
757{
758 struct gpio_port *port;
759 unsigned long flags;
760
761 port = container_of(chip, struct gpio_port, chip);
762
763 spin_lock_irqsave(&port->lock, flags);
764
765 writew(BIT(offset), &port->regs->dir_clear);
766 writew(readw(&port->regs->inen) | BIT(offset), &port->regs->inen);
767
768 spin_unlock_irqrestore(&port->lock, flags);
769
770 return 0;
771}
772
773static void adi_gpio_set_value(struct gpio_chip *chip, unsigned offset,
774 int value)
775{
776 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
777 struct gpio_port_t *regs = port->regs;
778 unsigned long flags;
779
780 spin_lock_irqsave(&port->lock, flags);
781
782 if (value)
783 writew(BIT(offset), ®s->data_set);
784 else
785 writew(BIT(offset), ®s->data_clear);
786
787 spin_unlock_irqrestore(&port->lock, flags);
788}
789
790static int adi_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
791 int value)
792{
793 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
794 struct gpio_port_t *regs = port->regs;
795 unsigned long flags;
796
797 spin_lock_irqsave(&port->lock, flags);
798
799 writew(readw(®s->inen) & ~BIT(offset), ®s->inen);
800 if (value)
801 writew(BIT(offset), ®s->data_set);
802 else
803 writew(BIT(offset), ®s->data_clear);
804 writew(BIT(offset), ®s->dir_set);
805
806 spin_unlock_irqrestore(&port->lock, flags);
807
808 return 0;
809}
810
811static int adi_gpio_get_value(struct gpio_chip *chip, unsigned offset)
812{
813 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
814 struct gpio_port_t *regs = port->regs;
815 unsigned long flags;
816 int ret;
817
818 spin_lock_irqsave(&port->lock, flags);
819
820 ret = !!(readw(®s->data) & BIT(offset));
821
822 spin_unlock_irqrestore(&port->lock, flags);
823
824 return ret;
825}
826
827static int adi_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
828{
829 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
830
831 if (port->irq_base >= 0)
832 return irq_find_mapping(port->domain, offset);
833 else
834 return irq_create_mapping(port->domain, offset);
835}
836
837static int adi_pint_map_port(struct gpio_pint *pint, bool assign, u8 map,
838 struct irq_domain *domain)
839{
840 struct gpio_pint_regs *regs = pint->regs;
841 u32 map_mask;
842
843 if (pint->map_count > 1)
844 return -EINVAL;
845
846 pint->map_count++;
847
848 /* The map_mask of each gpio port is a 16-bit duplicate
849 * of the 8-bit map. It can be set to either high 16 bits or low
850 * 16 bits of the pint assignment register.
851 */
852 map_mask = (map << 8) | map;
853 if (assign) {
854 map_mask <<= PINT_HI_OFFSET;
855 writel((readl(®s->assign) & 0xFFFF) | map_mask,
856 ®s->assign);
857 } else
858 writel((readl(®s->assign) & 0xFFFF0000) | map_mask,
859 ®s->assign);
860
861 pint->domain[assign] = domain;
862
863 return 0;
864}
865
866static int adi_gpio_pint_probe(struct platform_device *pdev)
867{
868 struct device *dev = &pdev->dev;
869 struct resource *res;
870 struct gpio_pint *pint;
871
872 pint = devm_kzalloc(dev, sizeof(struct gpio_pint), GFP_KERNEL);
873 if (!pint) {
874 dev_err(dev, "Memory alloc failed\n");
875 return -ENOMEM;
876 }
877
878 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
879 pint->base = devm_ioremap_resource(dev, res);
880 if (IS_ERR(pint->base))
881 return PTR_ERR(pint->base);
882
883 pint->regs = (struct gpio_pint_regs *)pint->base;
884
885 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
886 if (!res) {
887 dev_err(dev, "Invalid IRQ resource\n");
888 return -ENODEV;
889 }
890
891 spin_lock_init(&pint->lock);
892
893 pint->irq = res->start;
894 pint->pint_map_port = adi_pint_map_port;
895 platform_set_drvdata(pdev, pint);
896
897 irq_set_chained_handler(pint->irq, adi_gpio_handle_pint_irq);
898 irq_set_handler_data(pint->irq, pint);
899
900 list_add_tail(&pint->node, &adi_pint_list);
901
902 return 0;
903}
904
905static int adi_gpio_pint_remove(struct platform_device *pdev)
906{
907 struct gpio_pint *pint = platform_get_drvdata(pdev);
908
909 list_del(&pint->node);
910 irq_set_handler(pint->irq, handle_simple_irq);
911
912 return 0;
913}
914
915static int adi_gpio_irq_map(struct irq_domain *d, unsigned int irq,
916 irq_hw_number_t hwirq)
917{
918 struct gpio_port *port = d->host_data;
919
920 if (!port)
921 return -EINVAL;
922
923 irq_set_chip_data(irq, port);
924 irq_set_chip_and_handler(irq, &adi_gpio_irqchip,
925 handle_level_irq);
926
927 return 0;
928}
929
930const struct irq_domain_ops adi_gpio_irq_domain_ops = {
931 .map = adi_gpio_irq_map,
932 .xlate = irq_domain_xlate_onecell,
933};
934
935static int adi_gpio_init_int(struct gpio_port *port)
936{
937 struct device_node *node = port->dev->of_node;
938 struct gpio_pint *pint = port->pint;
939 int ret;
940
941 port->domain = irq_domain_add_linear(node, port->width,
942 &adi_gpio_irq_domain_ops, port);
943 if (!port->domain) {
944 dev_err(port->dev, "Failed to create irqdomain\n");
945 return -ENOSYS;
946 }
947
948 /* According to BF54x and BF60x HRM, pin interrupt devices are not
949 * part of the GPIO port device. in GPIO interrupt mode, the GPIO
950 * pins of multiple port devices can be routed into one pin interrupt
951 * device. The mapping can be configured by setting pint assignment
952 * register with the mapping value of different GPIO port. This is
953 * done via function pint_map_port().
954 */
955 ret = pint->pint_map_port(port->pint, port->pint_assign,
956 port->pint_map, port->domain);
957 if (ret)
958 return ret;
959
960 if (port->irq_base >= 0) {
961 ret = irq_create_strict_mappings(port->domain, port->irq_base,
962 0, port->width);
963 if (ret) {
964 dev_err(port->dev, "Couldn't associate to domain\n");
965 return ret;
966 }
967 }
968
969 return 0;
970}
971
972#define DEVNAME_SIZE 16
973
974static int adi_gpio_probe(struct platform_device *pdev)
975{
976 struct device *dev = &pdev->dev;
977 const struct adi_pinctrl_gpio_platform_data *pdata;
978 struct resource *res;
979 struct gpio_port *port;
980 char pinctrl_devname[DEVNAME_SIZE];
981 static int gpio;
982 int ret = 0, ret1;
983
984 pdata = dev->platform_data;
985 if (!pdata)
986 return -EINVAL;
987
988 port = devm_kzalloc(dev, sizeof(struct gpio_port), GFP_KERNEL);
989 if (!port) {
990 dev_err(dev, "Memory alloc failed\n");
991 return -ENOMEM;
992 }
993
994 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
995 port->base = devm_ioremap_resource(dev, res);
996 if (IS_ERR(port->base))
997 return PTR_ERR(port->base);
998
999 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1000 if (!res)
1001 port->irq_base = -1;
1002 else
1003 port->irq_base = res->start;
1004
1005 port->width = pdata->port_width;
1006 port->dev = dev;
1007 port->regs = (struct gpio_port_t *)port->base;
1008 port->pint_assign = pdata->pint_assign;
1009 port->pint_map = pdata->pint_map;
1010
1011 port->pint = find_gpio_pint(pdata->pint_id);
1012 if (port->pint) {
1013 ret = adi_gpio_init_int(port);
1014 if (ret)
1015 return ret;
1016 }
1017
1018 spin_lock_init(&port->lock);
1019
1020 platform_set_drvdata(pdev, port);
1021
1022 port->chip.label = "adi-gpio";
1023 port->chip.direction_input = adi_gpio_direction_input;
1024 port->chip.get = adi_gpio_get_value;
1025 port->chip.direction_output = adi_gpio_direction_output;
1026 port->chip.set = adi_gpio_set_value;
1027 port->chip.request = adi_gpio_request;
1028 port->chip.free = adi_gpio_free;
1029 port->chip.to_irq = adi_gpio_to_irq;
1030 if (pdata->port_gpio_base > 0)
1031 port->chip.base = pdata->port_gpio_base;
1032 else
1033 port->chip.base = gpio;
1034 port->chip.ngpio = port->width;
1035 gpio = port->chip.base + port->width;
1036
1037 ret = gpiochip_add(&port->chip);
1038 if (ret) {
1039 dev_err(&pdev->dev, "Fail to add GPIO chip.\n");
1040 goto out_remove_domain;
1041 }
1042
1043 /* Add gpio pin range */
1044 snprintf(pinctrl_devname, DEVNAME_SIZE, "pinctrl-adi2.%d",
1045 pdata->pinctrl_id);
1046 pinctrl_devname[DEVNAME_SIZE - 1] = 0;
1047 ret = gpiochip_add_pin_range(&port->chip, pinctrl_devname,
1048 0, pdata->port_pin_base, port->width);
1049 if (ret) {
1050 dev_err(&pdev->dev, "Fail to add pin range to %s.\n",
1051 pinctrl_devname);
1052 goto out_remove_gpiochip;
1053 }
1054
1055 list_add_tail(&port->node, &adi_gpio_port_list);
1056
1057 return 0;
1058
1059out_remove_gpiochip:
1060 ret1 = gpiochip_remove(&port->chip);
1061out_remove_domain:
1062 if (port->pint)
1063 irq_domain_remove(port->domain);
1064
1065 return ret;
1066}
1067
1068static int adi_gpio_remove(struct platform_device *pdev)
1069{
1070 struct gpio_port *port = platform_get_drvdata(pdev);
1071 int ret;
1072 u8 offset;
1073
1074 list_del(&port->node);
1075 gpiochip_remove_pin_ranges(&port->chip);
1076 ret = gpiochip_remove(&port->chip);
1077 if (port->pint) {
1078 for (offset = 0; offset < port->width; offset++)
1079 irq_dispose_mapping(irq_find_mapping(port->domain,
1080 offset));
1081 irq_domain_remove(port->domain);
1082 }
1083
1084 return ret;
1085}
1086
1087static int adi_pinctrl_probe(struct platform_device *pdev)
1088{
1089 struct adi_pinctrl *pinctrl;
1090
1091 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1092 if (!pinctrl)
1093 return -ENOMEM;
1094
1095 pinctrl->dev = &pdev->dev;
1096
1097 adi_pinctrl_soc_init(&pinctrl->soc);
1098
1099 adi_pinmux_desc.pins = pinctrl->soc->pins;
1100 adi_pinmux_desc.npins = pinctrl->soc->npins;
1101
1102 /* Now register the pin controller and all pins it handles */
1103 pinctrl->pctl = pinctrl_register(&adi_pinmux_desc, &pdev->dev, pinctrl);
1104 if (!pinctrl->pctl) {
1105 dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n");
1106 return -EINVAL;
1107 }
1108
1109 platform_set_drvdata(pdev, pinctrl);
1110
1111 return 0;
1112}
1113
1114static int adi_pinctrl_remove(struct platform_device *pdev)
1115{
1116 struct adi_pinctrl *pinctrl = platform_get_drvdata(pdev);
1117
1118 pinctrl_unregister(pinctrl->pctl);
1119
1120 return 0;
1121}
1122
1123static struct platform_driver adi_pinctrl_driver = {
1124 .probe = adi_pinctrl_probe,
1125 .remove = adi_pinctrl_remove,
1126 .driver = {
1127 .name = DRIVER_NAME,
1128 },
1129};
1130
1131static struct platform_driver adi_gpio_pint_driver = {
1132 .probe = adi_gpio_pint_probe,
1133 .remove = adi_gpio_pint_remove,
1134 .driver = {
1135 .name = "adi-gpio-pint",
1136 },
1137};
1138
1139static struct platform_driver adi_gpio_driver = {
1140 .probe = adi_gpio_probe,
1141 .remove = adi_gpio_remove,
1142 .driver = {
1143 .name = "adi-gpio",
1144 },
1145};
1146
1147static int __init adi_pinctrl_setup(void)
1148{
1149 int ret;
1150
1151 ret = platform_driver_register(&adi_pinctrl_driver);
1152 if (ret)
1153 return ret;
1154
1155 ret = platform_driver_register(&adi_gpio_pint_driver);
1156 if (ret)
1157 goto pint_error;
1158
1159 ret = platform_driver_register(&adi_gpio_driver);
1160 if (ret)
1161 goto gpio_error;
1162
1163#ifdef CONFIG_PM
1164 register_syscore_ops(&gpio_pm_syscore_ops);
1165#endif
1166 return ret;
1167gpio_error:
1168 platform_driver_unregister(&adi_gpio_pint_driver);
1169pint_error:
1170 platform_driver_unregister(&adi_pinctrl_driver);
1171
1172 return ret;
1173}
1174arch_initcall(adi_pinctrl_setup);
1175
1176MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
1177MODULE_DESCRIPTION("ADI gpio2 pin control driver");
1178MODULE_LICENSE("GPL");