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1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * Contact Information:
15 * wlanfae <wlanfae@realtek.com>
16 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
17 * Hsinchu 300, Taiwan.
18 *
19 * Larry Finger <Larry.Finger@lwfinger.net>
20 *
21 *****************************************************************************/
22
23#ifndef __RTL8723BE_DM_H__
24#define __RTL8723BE_DM_H__
25
26#define MAIN_ANT 0
27#define AUX_ANT 1
28#define MAIN_ANT_CG_TRX 1
29#define AUX_ANT_CG_TRX 0
30#define MAIN_ANT_CGCS_RX 0
31#define AUX_ANT_CGCS_RX 1
32
33#define TXSCALE_TABLE_SIZE 30
34
35/*RF REG LIST*/
36#define DM_REG_RF_MODE_11N 0x00
37#define DM_REG_RF_0B_11N 0x0B
38#define DM_REG_CHNBW_11N 0x18
39#define DM_REG_T_METER_11N 0x24
40#define DM_REG_RF_25_11N 0x25
41#define DM_REG_RF_26_11N 0x26
42#define DM_REG_RF_27_11N 0x27
43#define DM_REG_RF_2B_11N 0x2B
44#define DM_REG_RF_2C_11N 0x2C
45#define DM_REG_RXRF_A3_11N 0x3C
46#define DM_REG_T_METER_92D_11N 0x42
47#define DM_REG_T_METER_88E_11N 0x42
48
49/*BB REG LIST*/
50/*PAGE 8 */
51#define DM_REG_BB_CTRL_11N 0x800
52#define DM_REG_RF_PIN_11N 0x804
53#define DM_REG_PSD_CTRL_11N 0x808
54#define DM_REG_TX_ANT_CTRL_11N 0x80C
55#define DM_REG_BB_PWR_SAV5_11N 0x818
56#define DM_REG_CCK_RPT_FORMAT_11N 0x824
57#define DM_REG_RX_DEFUALT_A_11N 0x858
58#define DM_REG_RX_DEFUALT_B_11N 0x85A
59#define DM_REG_BB_PWR_SAV3_11N 0x85C
60#define DM_REG_ANTSEL_CTRL_11N 0x860
61#define DM_REG_RX_ANT_CTRL_11N 0x864
62#define DM_REG_PIN_CTRL_11N 0x870
63#define DM_REG_BB_PWR_SAV1_11N 0x874
64#define DM_REG_ANTSEL_PATH_11N 0x878
65#define DM_REG_BB_3WIRE_11N 0x88C
66#define DM_REG_SC_CNT_11N 0x8C4
67#define DM_REG_PSD_DATA_11N 0x8B4
68/*PAGE 9*/
69#define DM_REG_ANT_MAPPING1_11N 0x914
70#define DM_REG_ANT_MAPPING2_11N 0x918
71/*PAGE A*/
72#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA00
73#define DM_REG_CCK_CCA_11N 0xA0A
74#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
75#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA10
76#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA14
77#define DM_REG_CCK_FILTER_PARA1_11N 0xA22
78#define DM_REG_CCK_FILTER_PARA2_11N 0xA23
79#define DM_REG_CCK_FILTER_PARA3_11N 0xA24
80#define DM_REG_CCK_FILTER_PARA4_11N 0xA25
81#define DM_REG_CCK_FILTER_PARA5_11N 0xA26
82#define DM_REG_CCK_FILTER_PARA6_11N 0xA27
83#define DM_REG_CCK_FILTER_PARA7_11N 0xA28
84#define DM_REG_CCK_FILTER_PARA8_11N 0xA29
85#define DM_REG_CCK_FA_RST_11N 0xA2C
86#define DM_REG_CCK_FA_MSB_11N 0xA58
87#define DM_REG_CCK_FA_LSB_11N 0xA5C
88#define DM_REG_CCK_CCA_CNT_11N 0xA60
89#define DM_REG_BB_PWR_SAV4_11N 0xA74
90/*PAGE B */
91#define DM_REG_LNA_SWITCH_11N 0xB2C
92#define DM_REG_PATH_SWITCH_11N 0xB30
93#define DM_REG_RSSI_CTRL_11N 0xB38
94#define DM_REG_CONFIG_ANTA_11N 0xB68
95#define DM_REG_RSSI_BT_11N 0xB9C
96/*PAGE C */
97#define DM_REG_OFDM_FA_HOLDC_11N 0xC00
98#define DM_REG_RX_PATH_11N 0xC04
99#define DM_REG_TRMUX_11N 0xC08
100#define DM_REG_OFDM_FA_RSTC_11N 0xC0C
101#define DM_REG_RXIQI_MATRIX_11N 0xC14
102#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
103#define DM_REG_IGI_A_11N 0xC50
104#define DM_REG_ANTDIV_PARA2_11N 0xC54
105#define DM_REG_IGI_B_11N 0xC58
106#define DM_REG_ANTDIV_PARA3_11N 0xC5C
107#define DM_REG_BB_PWR_SAV2_11N 0xC70
108#define DM_REG_RX_OFF_11N 0xC7C
109#define DM_REG_TXIQK_MATRIXA_11N 0xC80
110#define DM_REG_TXIQK_MATRIXB_11N 0xC88
111#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
112#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
113#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
114#define DM_REG_ANTDIV_PARA1_11N 0xCA4
115#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0
116/*PAGE D */
117#define DM_REG_OFDM_FA_RSTD_11N 0xD00
118#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0
119#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4
120#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8
121/*PAGE E */
122#define DM_REG_TXAGC_A_6_18_11N 0xE00
123#define DM_REG_TXAGC_A_24_54_11N 0xE04
124#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08
125#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10
126#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14
127#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18
128#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C
129#define DM_REG_FPGA0_IQK_11N 0xE28
130#define DM_REG_TXIQK_TONE_A_11N 0xE30
131#define DM_REG_RXIQK_TONE_A_11N 0xE34
132#define DM_REG_TXIQK_PI_A_11N 0xE38
133#define DM_REG_RXIQK_PI_A_11N 0xE3C
134#define DM_REG_TXIQK_11N 0xE40
135#define DM_REG_RXIQK_11N 0xE44
136#define DM_REG_IQK_AGC_PTS_11N 0xE48
137#define DM_REG_IQK_AGC_RSP_11N 0xE4C
138#define DM_REG_BLUETOOTH_11N 0xE6C
139#define DM_REG_RX_WAIT_CCA_11N 0xE70
140#define DM_REG_TX_CCK_RFON_11N 0xE74
141#define DM_REG_TX_CCK_BBON_11N 0xE78
142#define DM_REG_OFDM_RFON_11N 0xE7C
143#define DM_REG_OFDM_BBON_11N 0xE80
144#define DM_REG_TX2RX_11N 0xE84
145#define DM_REG_TX2TX_11N 0xE88
146#define DM_REG_RX_CCK_11N 0xE8C
147#define DM_REG_RX_OFDM_11N 0xED0
148#define DM_REG_RX_WAIT_RIFS_11N 0xED4
149#define DM_REG_RX2RX_11N 0xED8
150#define DM_REG_STANDBY_11N 0xEDC
151#define DM_REG_SLEEP_11N 0xEE0
152#define DM_REG_PMPD_ANAEN_11N 0xEEC
153
154/*MAC REG LIST*/
155#define DM_REG_BB_RST_11N 0x02
156#define DM_REG_ANTSEL_PIN_11N 0x4C
157#define DM_REG_EARLY_MODE_11N 0x4D0
158#define DM_REG_RSSI_MONITOR_11N 0x4FE
159#define DM_REG_EDCA_VO_11N 0x500
160#define DM_REG_EDCA_VI_11N 0x504
161#define DM_REG_EDCA_BE_11N 0x508
162#define DM_REG_EDCA_BK_11N 0x50C
163#define DM_REG_TXPAUSE_11N 0x522
164#define DM_REG_RESP_TX_11N 0x6D8
165#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0
166#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4
167
168/*DIG Related*/
169#define DM_BIT_IGI_11N 0x0000007F
170
171#define HAL_DM_DIG_DISABLE BIT(0)
172#define HAL_DM_HIPWR_DISABLE BIT(1)
173
174#define OFDM_TABLE_LENGTH 43
175#define CCK_TABLE_LENGTH 33
176
177#define OFDM_TABLE_SIZE 37
178#define CCK_TABLE_SIZE 33
179
180#define BW_AUTO_SWITCH_HIGH_LOW 25
181#define BW_AUTO_SWITCH_LOW_HIGH 30
182
183#define DM_DIG_THRESH_HIGH 40
184#define DM_DIG_THRESH_LOW 35
185
186#define DM_FALSEALARM_THRESH_LOW 400
187#define DM_FALSEALARM_THRESH_HIGH 1000
188
189#define DM_DIG_MAX 0x3e
190#define DM_DIG_MIN 0x1e
191
192#define DM_DIG_MAX_AP 0x32
193#define DM_DIG_MIN_AP 0x20
194
195#define DM_DIG_FA_UPPER 0x3e
196#define DM_DIG_FA_LOWER 0x1e
197#define DM_DIG_FA_TH0 0x200
198#define DM_DIG_FA_TH1 0x300
199#define DM_DIG_FA_TH2 0x400
200
201#define DM_DIG_BACKOFF_MAX 12
202#define DM_DIG_BACKOFF_MIN -4
203#define DM_DIG_BACKOFF_DEFAULT 10
204
205#define RXPATHSELECTION_DIFF_TH 18
206
207#define DM_RATR_STA_INIT 0
208#define DM_RATR_STA_HIGH 1
209#define DM_RATR_STA_MIDDLE 2
210#define DM_RATR_STA_LOW 3
211
212#define CTS2SELF_THVAL 30
213#define REGC38_TH 20
214
215#define TXHIGHPWRLEVEL_NORMAL 0
216#define TXHIGHPWRLEVEL_LEVEL1 1
217#define TXHIGHPWRLEVEL_LEVEL2 2
218#define TXHIGHPWRLEVEL_BT1 3
219#define TXHIGHPWRLEVEL_BT2 4
220
221#define DM_TYPE_BYFW 0
222#define DM_TYPE_BYDRIVER 1
223
224#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
225#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
226#define TXPWRTRACK_MAX_IDX 6
227
228/* Dynamic ATC switch */
229#define ATC_STATUS_OFF 0x0 /* enable */
230#define ATC_STATUS_ON 0x1 /* disable */
231#define CFO_THRESHOLD_XTAL 10 /* kHz */
232#define CFO_THRESHOLD_ATC 80 /* kHz */
233
234enum FAT_STATE {
235 FAT_NORMAL_STATE = 0,
236 FAT_TRAINING_STATE = 1,
237};
238
239enum tag_dynamic_init_gain_operation_type_definition {
240 DIG_TYPE_THRESH_HIGH = 0,
241 DIG_TYPE_THRESH_LOW = 1,
242 DIG_TYPE_BACKOFF = 2,
243 DIG_TYPE_RX_GAIN_MIN = 3,
244 DIG_TYPE_RX_GAIN_MAX = 4,
245 DIG_TYPE_ENABLE = 5,
246 DIG_TYPE_DISABLE = 6,
247 DIG_OP_TYPE_MAX
248};
249
250enum dm_1r_cca_e {
251 CCA_1R = 0,
252 CCA_2R = 1,
253 CCA_MAX = 2,
254};
255
256enum dm_rf_e {
257 RF_SAVE = 0,
258 RF_NORMAL = 1,
259 RF_MAX = 2,
260};
261
262enum dm_sw_ant_switch_e {
263 ANS_ANTENNA_B = 1,
264 ANS_ANTENNA_A = 2,
265 ANS_ANTENNA_MAX = 3,
266};
267
268enum dm_dig_ext_port_alg_e {
269 DIG_EXT_PORT_STAGE_0 = 0,
270 DIG_EXT_PORT_STAGE_1 = 1,
271 DIG_EXT_PORT_STAGE_2 = 2,
272 DIG_EXT_PORT_STAGE_3 = 3,
273 DIG_EXT_PORT_STAGE_MAX = 4,
274};
275
276enum dm_dig_connect_e {
277 DIG_STA_DISCONNECT = 0,
278 DIG_STA_CONNECT = 1,
279 DIG_STA_BEFORE_CONNECT = 2,
280 DIG_MULTISTA_DISCONNECT = 3,
281 DIG_MULTISTA_CONNECT = 4,
282 DIG_CONNECT_MAX
283};
284
285enum pwr_track_control_method {
286 BBSWING,
287 TXAGC
288};
289
290#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
291#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
292#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
293#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
294#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
295
296void rtl8723be_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw, u8 *pdesc,
297 u32 mac_id);
298void rtl8723be_dm_ant_sel_statistics(struct ieee80211_hw *hw, u8 antsel_tr_mux,
299 u32 mac_id, u32 rx_pwdb_all);
300void rtl8723be_dm_fast_antenna_trainning_callback(unsigned long data);
301void rtl8723be_dm_init(struct ieee80211_hw *hw);
302void rtl8723be_dm_watchdog(struct ieee80211_hw *hw);
303void rtl8723be_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);
304void rtl8723be_dm_check_txpower_tracking(struct ieee80211_hw *hw);
305void rtl8723be_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
306void rtl8723be_dm_txpower_track_adjust(struct ieee80211_hw *hw, u8 type,
307 u8 *pdirection, u32 *poutwrite_val);
308void rtl8723be_dm_init_edca_turbo(struct ieee80211_hw *hw);
309
310#endif