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1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_PHY_COMMON_H__
31#define __RTL92C_PHY_COMMON_H__
32
33#define MAX_PRECMD_CNT 16
34#define MAX_RFDEPENDCMD_CNT 16
35#define MAX_POSTCMD_CNT 16
36
37#define MAX_DOZE_WAITING_TIMES_9x 64
38
39#define RT_CANNOT_IO(hw) false
40#define HIGHPOWER_RADIOA_ARRAYLEN 22
41
42#define MAX_TOLERANCE 5
43
44#define APK_BB_REG_NUM 5
45#define APK_AFE_REG_NUM 16
46#define APK_CURVE_REG_NUM 4
47#define PATH_NUM 2
48
49#define LOOP_LIMIT 5
50#define MAX_STALL_TIME 50
51#define AntennaDiversityValue 0x80
52#define MAX_TXPWR_IDX_NMODE_92S 63
53#define Reset_Cnt_Limit 3
54
55#define IQK_ADDA_REG_NUM 16
56#define IQK_MAC_REG_NUM 4
57
58#define IQK_DELAY_TIME 1
59#define RF90_PATH_MAX 2
60
61#define CT_OFFSET_MAC_ADDR 0X16
62
63#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
64#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
65#define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66
66#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
67#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
68
69#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
70#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
71
72#define CT_OFFSET_CHANNEL_PLAH 0x75
73#define CT_OFFSET_THERMAL_METER 0x78
74#define CT_OFFSET_RF_OPTION 0x79
75#define CT_OFFSET_VERSION 0x7E
76#define CT_OFFSET_CUSTOMER_ID 0x7F
77
78#define RTL92C_MAX_PATH_NUM 2
79#define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
80
81enum swchnlcmd_id {
82 CMDID_END,
83 CMDID_SET_TXPOWEROWER_LEVEL,
84 CMDID_BBREGWRITE10,
85 CMDID_WRITEPORT_ULONG,
86 CMDID_WRITEPORT_USHORT,
87 CMDID_WRITEPORT_UCHAR,
88 CMDID_RF_WRITEREG,
89};
90
91struct swchnlcmd {
92 enum swchnlcmd_id cmdid;
93 u32 para1;
94 u32 para2;
95 u32 msdelay;
96};
97
98enum hw90_block_e {
99 HW90_BLOCK_MAC = 0,
100 HW90_BLOCK_PHY0 = 1,
101 HW90_BLOCK_PHY1 = 2,
102 HW90_BLOCK_RF = 3,
103 HW90_BLOCK_MAXIMUM = 4,
104};
105
106enum baseband_config_type {
107 BASEBAND_CONFIG_PHY_REG = 0,
108 BASEBAND_CONFIG_AGC_TAB = 1,
109};
110
111enum ra_offset_area {
112 RA_OFFSET_LEGACY_OFDM1,
113 RA_OFFSET_LEGACY_OFDM2,
114 RA_OFFSET_HT_OFDM1,
115 RA_OFFSET_HT_OFDM2,
116 RA_OFFSET_HT_OFDM3,
117 RA_OFFSET_HT_OFDM4,
118 RA_OFFSET_HT_CCK,
119};
120
121enum antenna_path {
122 ANTENNA_NONE,
123 ANTENNA_D,
124 ANTENNA_C,
125 ANTENNA_CD,
126 ANTENNA_B,
127 ANTENNA_BD,
128 ANTENNA_BC,
129 ANTENNA_BCD,
130 ANTENNA_A,
131 ANTENNA_AD,
132 ANTENNA_AC,
133 ANTENNA_ACD,
134 ANTENNA_AB,
135 ANTENNA_ABD,
136 ANTENNA_ABC,
137 ANTENNA_ABCD
138};
139
140struct r_antenna_select_ofdm {
141 u32 r_tx_antenna:4;
142 u32 r_ant_l:4;
143 u32 r_ant_non_ht:4;
144 u32 r_ant_ht1:4;
145 u32 r_ant_ht2:4;
146 u32 r_ant_ht_s1:4;
147 u32 r_ant_non_ht_s1:4;
148 u32 ofdm_txsc:2;
149 u32 reserved:2;
150};
151
152struct r_antenna_select_cck {
153 u8 r_cckrx_enable_2:2;
154 u8 r_cckrx_enable:2;
155 u8 r_ccktx_enable:4;
156};
157
158struct efuse_contents {
159 u8 mac_addr[ETH_ALEN];
160 u8 cck_tx_power_idx[6];
161 u8 ht40_1s_tx_power_idx[6];
162 u8 ht40_2s_tx_power_idx_diff[3];
163 u8 ht20_tx_power_idx_diff[3];
164 u8 ofdm_tx_power_idx_diff[3];
165 u8 ht40_max_power_offset[3];
166 u8 ht20_max_power_offset[3];
167 u8 channel_plan;
168 u8 thermal_meter;
169 u8 rf_option[5];
170 u8 version;
171 u8 oem_id;
172 u8 regulatory;
173};
174
175struct tx_power_struct {
176 u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
177 u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
178 u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
179 u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
180 u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
181 u8 legacy_ht_txpowerdiff;
182 u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
183 u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
184 u8 pwrgroup_cnt;
185 u32 mcs_original_offset[4][16];
186};
187
188u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw,
189 u32 regaddr, u32 bitmask);
190void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
191 u32 regaddr, u32 bitmask, u32 data);
192u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
193 enum radio_path rfpath, u32 regaddr,
194 u32 bitmask);
195bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
196bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
197bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
198bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
199 enum radio_path rfpath);
200void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
201void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw,
202 long *powerlevel);
203void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
204bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
205 long power_indbm);
206void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
207 enum nl80211_channel_type ch_type);
208void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
209u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
210void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
211void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw,
212 u16 beaconinterval);
213void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
214void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
215void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
216bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
217 enum radio_path rfpath);
218bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
219 u32 rfpath);
220bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
221 enum rf_pwrstate rfpwr_state);
222void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
223void rtl92c_phy_set_io(struct ieee80211_hw *hw);
224void rtl92c_bb_block_on(struct ieee80211_hw *hw);
225u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
226long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
227 enum wireless_mode wirelessmode,
228 u8 txpwridx);
229u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
230 enum wireless_mode wirelessmode,
231 long power_indbm);
232void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
233void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
234bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
235 u8 channel, u8 *stage, u8 *step,
236 u32 *delay);
237u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw);
238u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
239 enum radio_path rfpath, u32 offset);
240void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
241 enum radio_path rfpath, u32 offset,
242 u32 data);
243u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
244 enum radio_path rfpath, u32 offset);
245void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
246 enum radio_path rfpath, u32 offset,
247 u32 data);
248bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
249void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
250 u32 regaddr, u32 bitmask,
251 u32 data);
252bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
253
254#endif