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1/*
2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
6
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
15
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
20
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
25
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, see <http://www.gnu.org/licenses/>.
28 */
29
30/*
31 Module: rt2800lib
32 Abstract: rt2800 generic device routines.
33 */
34
35#include <linux/crc-ccitt.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/slab.h>
39
40#include "rt2x00.h"
41#include "rt2800lib.h"
42#include "rt2800.h"
43
44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2800_register_read and rt2800_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 * The _lock versions must be used if you already hold the csr_mutex
57 */
58#define WAIT_FOR_BBP(__dev, __reg) \
59 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
60#define WAIT_FOR_RFCSR(__dev, __reg) \
61 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
62#define WAIT_FOR_RF(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
64#define WAIT_FOR_MCU(__dev, __reg) \
65 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
66 H2M_MAILBOX_CSR_OWNER, (__reg))
67
68static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
69{
70 /* check for rt2872 on SoC */
71 if (!rt2x00_is_soc(rt2x00dev) ||
72 !rt2x00_rt(rt2x00dev, RT2872))
73 return false;
74
75 /* we know for sure that these rf chipsets are used on rt305x boards */
76 if (rt2x00_rf(rt2x00dev, RF3020) ||
77 rt2x00_rf(rt2x00dev, RF3021) ||
78 rt2x00_rf(rt2x00dev, RF3022))
79 return true;
80
81 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
82 return false;
83}
84
85static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 const unsigned int word, const u8 value)
87{
88 u32 reg;
89
90 mutex_lock(&rt2x00dev->csr_mutex);
91
92 /*
93 * Wait until the BBP becomes available, afterwards we
94 * can safely write the new data into the register.
95 */
96 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
97 reg = 0;
98 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value);
99 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
100 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
101 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0);
102 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
103
104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
105 }
106
107 mutex_unlock(&rt2x00dev->csr_mutex);
108}
109
110static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
111 const unsigned int word, u8 *value)
112{
113 u32 reg;
114
115 mutex_lock(&rt2x00dev->csr_mutex);
116
117 /*
118 * Wait until the BBP becomes available, afterwards we
119 * can safely write the read request into the register.
120 * After the data has been written, we wait until hardware
121 * returns the correct value, if at any time the register
122 * doesn't become available in time, reg will be 0xffffffff
123 * which means we return 0xff to the caller.
124 */
125 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
126 reg = 0;
127 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
128 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
129 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1);
130 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
131
132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
133
134 WAIT_FOR_BBP(rt2x00dev, ®);
135 }
136
137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
138
139 mutex_unlock(&rt2x00dev->csr_mutex);
140}
141
142static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
143 const unsigned int word, const u8 value)
144{
145 u32 reg;
146
147 mutex_lock(&rt2x00dev->csr_mutex);
148
149 /*
150 * Wait until the RFCSR becomes available, afterwards we
151 * can safely write the new data into the register.
152 */
153 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
154 reg = 0;
155 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value);
156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
157 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1);
158 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
159
160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
161 }
162
163 mutex_unlock(&rt2x00dev->csr_mutex);
164}
165
166static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
167 const unsigned int word, u8 *value)
168{
169 u32 reg;
170
171 mutex_lock(&rt2x00dev->csr_mutex);
172
173 /*
174 * Wait until the RFCSR becomes available, afterwards we
175 * can safely write the read request into the register.
176 * After the data has been written, we wait until hardware
177 * returns the correct value, if at any time the register
178 * doesn't become available in time, reg will be 0xffffffff
179 * which means we return 0xff to the caller.
180 */
181 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
182 reg = 0;
183 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
184 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0);
185 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
186
187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
188
189 WAIT_FOR_RFCSR(rt2x00dev, ®);
190 }
191
192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
193
194 mutex_unlock(&rt2x00dev->csr_mutex);
195}
196
197static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
198 const unsigned int word, const u32 value)
199{
200 u32 reg;
201
202 mutex_lock(&rt2x00dev->csr_mutex);
203
204 /*
205 * Wait until the RF becomes available, afterwards we
206 * can safely write the new data into the register.
207 */
208 if (WAIT_FOR_RF(rt2x00dev, ®)) {
209 reg = 0;
210 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value);
211 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0);
212 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0);
213 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1);
214
215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
216 rt2x00_rf_write(rt2x00dev, word, value);
217 }
218
219 mutex_unlock(&rt2x00dev->csr_mutex);
220}
221
222static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
223 [EEPROM_CHIP_ID] = 0x0000,
224 [EEPROM_VERSION] = 0x0001,
225 [EEPROM_MAC_ADDR_0] = 0x0002,
226 [EEPROM_MAC_ADDR_1] = 0x0003,
227 [EEPROM_MAC_ADDR_2] = 0x0004,
228 [EEPROM_NIC_CONF0] = 0x001a,
229 [EEPROM_NIC_CONF1] = 0x001b,
230 [EEPROM_FREQ] = 0x001d,
231 [EEPROM_LED_AG_CONF] = 0x001e,
232 [EEPROM_LED_ACT_CONF] = 0x001f,
233 [EEPROM_LED_POLARITY] = 0x0020,
234 [EEPROM_NIC_CONF2] = 0x0021,
235 [EEPROM_LNA] = 0x0022,
236 [EEPROM_RSSI_BG] = 0x0023,
237 [EEPROM_RSSI_BG2] = 0x0024,
238 [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
239 [EEPROM_RSSI_A] = 0x0025,
240 [EEPROM_RSSI_A2] = 0x0026,
241 [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
242 [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
243 [EEPROM_TXPOWER_DELTA] = 0x0028,
244 [EEPROM_TXPOWER_BG1] = 0x0029,
245 [EEPROM_TXPOWER_BG2] = 0x0030,
246 [EEPROM_TSSI_BOUND_BG1] = 0x0037,
247 [EEPROM_TSSI_BOUND_BG2] = 0x0038,
248 [EEPROM_TSSI_BOUND_BG3] = 0x0039,
249 [EEPROM_TSSI_BOUND_BG4] = 0x003a,
250 [EEPROM_TSSI_BOUND_BG5] = 0x003b,
251 [EEPROM_TXPOWER_A1] = 0x003c,
252 [EEPROM_TXPOWER_A2] = 0x0053,
253 [EEPROM_TSSI_BOUND_A1] = 0x006a,
254 [EEPROM_TSSI_BOUND_A2] = 0x006b,
255 [EEPROM_TSSI_BOUND_A3] = 0x006c,
256 [EEPROM_TSSI_BOUND_A4] = 0x006d,
257 [EEPROM_TSSI_BOUND_A5] = 0x006e,
258 [EEPROM_TXPOWER_BYRATE] = 0x006f,
259 [EEPROM_BBP_START] = 0x0078,
260};
261
262static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
263 [EEPROM_CHIP_ID] = 0x0000,
264 [EEPROM_VERSION] = 0x0001,
265 [EEPROM_MAC_ADDR_0] = 0x0002,
266 [EEPROM_MAC_ADDR_1] = 0x0003,
267 [EEPROM_MAC_ADDR_2] = 0x0004,
268 [EEPROM_NIC_CONF0] = 0x001a,
269 [EEPROM_NIC_CONF1] = 0x001b,
270 [EEPROM_NIC_CONF2] = 0x001c,
271 [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
272 [EEPROM_FREQ] = 0x0022,
273 [EEPROM_LED_AG_CONF] = 0x0023,
274 [EEPROM_LED_ACT_CONF] = 0x0024,
275 [EEPROM_LED_POLARITY] = 0x0025,
276 [EEPROM_LNA] = 0x0026,
277 [EEPROM_EXT_LNA2] = 0x0027,
278 [EEPROM_RSSI_BG] = 0x0028,
279 [EEPROM_RSSI_BG2] = 0x0029,
280 [EEPROM_RSSI_A] = 0x002a,
281 [EEPROM_RSSI_A2] = 0x002b,
282 [EEPROM_TXPOWER_BG1] = 0x0030,
283 [EEPROM_TXPOWER_BG2] = 0x0037,
284 [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
285 [EEPROM_TSSI_BOUND_BG1] = 0x0045,
286 [EEPROM_TSSI_BOUND_BG2] = 0x0046,
287 [EEPROM_TSSI_BOUND_BG3] = 0x0047,
288 [EEPROM_TSSI_BOUND_BG4] = 0x0048,
289 [EEPROM_TSSI_BOUND_BG5] = 0x0049,
290 [EEPROM_TXPOWER_A1] = 0x004b,
291 [EEPROM_TXPOWER_A2] = 0x0065,
292 [EEPROM_EXT_TXPOWER_A3] = 0x007f,
293 [EEPROM_TSSI_BOUND_A1] = 0x009a,
294 [EEPROM_TSSI_BOUND_A2] = 0x009b,
295 [EEPROM_TSSI_BOUND_A3] = 0x009c,
296 [EEPROM_TSSI_BOUND_A4] = 0x009d,
297 [EEPROM_TSSI_BOUND_A5] = 0x009e,
298 [EEPROM_TXPOWER_BYRATE] = 0x00a0,
299};
300
301static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
302 const enum rt2800_eeprom_word word)
303{
304 const unsigned int *map;
305 unsigned int index;
306
307 if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
308 "%s: invalid EEPROM word %d\n",
309 wiphy_name(rt2x00dev->hw->wiphy), word))
310 return 0;
311
312 if (rt2x00_rt(rt2x00dev, RT3593))
313 map = rt2800_eeprom_map_ext;
314 else
315 map = rt2800_eeprom_map;
316
317 index = map[word];
318
319 /* Index 0 is valid only for EEPROM_CHIP_ID.
320 * Otherwise it means that the offset of the
321 * given word is not initialized in the map,
322 * or that the field is not usable on the
323 * actual chipset.
324 */
325 WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
326 "%s: invalid access of EEPROM word %d\n",
327 wiphy_name(rt2x00dev->hw->wiphy), word);
328
329 return index;
330}
331
332static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
333 const enum rt2800_eeprom_word word)
334{
335 unsigned int index;
336
337 index = rt2800_eeprom_word_index(rt2x00dev, word);
338 return rt2x00_eeprom_addr(rt2x00dev, index);
339}
340
341static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
342 const enum rt2800_eeprom_word word, u16 *data)
343{
344 unsigned int index;
345
346 index = rt2800_eeprom_word_index(rt2x00dev, word);
347 rt2x00_eeprom_read(rt2x00dev, index, data);
348}
349
350static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
351 const enum rt2800_eeprom_word word, u16 data)
352{
353 unsigned int index;
354
355 index = rt2800_eeprom_word_index(rt2x00dev, word);
356 rt2x00_eeprom_write(rt2x00dev, index, data);
357}
358
359static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
360 const enum rt2800_eeprom_word array,
361 unsigned int offset,
362 u16 *data)
363{
364 unsigned int index;
365
366 index = rt2800_eeprom_word_index(rt2x00dev, array);
367 rt2x00_eeprom_read(rt2x00dev, index + offset, data);
368}
369
370static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
371{
372 u32 reg;
373 int i, count;
374
375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®);
376 if (rt2x00_get_field32(reg, WLAN_EN))
377 return 0;
378
379 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
380 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1);
381 rt2x00_set_field32(®, WLAN_CLK_EN, 0);
382 rt2x00_set_field32(®, WLAN_EN, 1);
383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
384
385 udelay(REGISTER_BUSY_DELAY);
386
387 count = 0;
388 do {
389 /*
390 * Check PLL_LD & XTAL_RDY.
391 */
392 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
393 rt2800_register_read(rt2x00dev, CMB_CTRL, ®);
394 if (rt2x00_get_field32(reg, PLL_LD) &&
395 rt2x00_get_field32(reg, XTAL_RDY))
396 break;
397 udelay(REGISTER_BUSY_DELAY);
398 }
399
400 if (i >= REGISTER_BUSY_COUNT) {
401
402 if (count >= 10)
403 return -EIO;
404
405 rt2800_register_write(rt2x00dev, 0x58, 0x018);
406 udelay(REGISTER_BUSY_DELAY);
407 rt2800_register_write(rt2x00dev, 0x58, 0x418);
408 udelay(REGISTER_BUSY_DELAY);
409 rt2800_register_write(rt2x00dev, 0x58, 0x618);
410 udelay(REGISTER_BUSY_DELAY);
411 count++;
412 } else {
413 count = 0;
414 }
415
416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®);
417 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0);
418 rt2x00_set_field32(®, WLAN_CLK_EN, 1);
419 rt2x00_set_field32(®, WLAN_RESET, 1);
420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
421 udelay(10);
422 rt2x00_set_field32(®, WLAN_RESET, 0);
423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
424 udelay(10);
425 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
426 } while (count != 0);
427
428 return 0;
429}
430
431void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
432 const u8 command, const u8 token,
433 const u8 arg0, const u8 arg1)
434{
435 u32 reg;
436
437 /*
438 * SOC devices don't support MCU requests.
439 */
440 if (rt2x00_is_soc(rt2x00dev))
441 return;
442
443 mutex_lock(&rt2x00dev->csr_mutex);
444
445 /*
446 * Wait until the MCU becomes available, afterwards we
447 * can safely write the new data into the register.
448 */
449 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
450 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
451 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
452 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
453 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
455
456 reg = 0;
457 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
459 }
460
461 mutex_unlock(&rt2x00dev->csr_mutex);
462}
463EXPORT_SYMBOL_GPL(rt2800_mcu_request);
464
465int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
466{
467 unsigned int i = 0;
468 u32 reg;
469
470 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
471 rt2800_register_read(rt2x00dev, MAC_CSR0, ®);
472 if (reg && reg != ~0)
473 return 0;
474 msleep(1);
475 }
476
477 rt2x00_err(rt2x00dev, "Unstable hardware\n");
478 return -EBUSY;
479}
480EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
481
482int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
483{
484 unsigned int i;
485 u32 reg;
486
487 /*
488 * Some devices are really slow to respond here. Wait a whole second
489 * before timing out.
490 */
491 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
495 return 0;
496
497 msleep(10);
498 }
499
500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
501 return -EACCES;
502}
503EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
504
505void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
506{
507 u32 reg;
508
509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
510 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
511 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
512 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
513 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
514 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
516}
517EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
518
519void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
520 unsigned short *txwi_size,
521 unsigned short *rxwi_size)
522{
523 switch (rt2x00dev->chip.rt) {
524 case RT3593:
525 *txwi_size = TXWI_DESC_SIZE_4WORDS;
526 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
527 break;
528
529 case RT5592:
530 *txwi_size = TXWI_DESC_SIZE_5WORDS;
531 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
532 break;
533
534 default:
535 *txwi_size = TXWI_DESC_SIZE_4WORDS;
536 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
537 break;
538 }
539}
540EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
541
542static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
543{
544 u16 fw_crc;
545 u16 crc;
546
547 /*
548 * The last 2 bytes in the firmware array are the crc checksum itself,
549 * this means that we should never pass those 2 bytes to the crc
550 * algorithm.
551 */
552 fw_crc = (data[len - 2] << 8 | data[len - 1]);
553
554 /*
555 * Use the crc ccitt algorithm.
556 * This will return the same value as the legacy driver which
557 * used bit ordering reversion on the both the firmware bytes
558 * before input input as well as on the final output.
559 * Obviously using crc ccitt directly is much more efficient.
560 */
561 crc = crc_ccitt(~0, data, len - 2);
562
563 /*
564 * There is a small difference between the crc-itu-t + bitrev and
565 * the crc-ccitt crc calculation. In the latter method the 2 bytes
566 * will be swapped, use swab16 to convert the crc to the correct
567 * value.
568 */
569 crc = swab16(crc);
570
571 return fw_crc == crc;
572}
573
574int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
575 const u8 *data, const size_t len)
576{
577 size_t offset = 0;
578 size_t fw_len;
579 bool multiple;
580
581 /*
582 * PCI(e) & SOC devices require firmware with a length
583 * of 8kb. USB devices require firmware files with a length
584 * of 4kb. Certain USB chipsets however require different firmware,
585 * which Ralink only provides attached to the original firmware
586 * file. Thus for USB devices, firmware files have a length
587 * which is a multiple of 4kb. The firmware for rt3290 chip also
588 * have a length which is a multiple of 4kb.
589 */
590 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
591 fw_len = 4096;
592 else
593 fw_len = 8192;
594
595 multiple = true;
596 /*
597 * Validate the firmware length
598 */
599 if (len != fw_len && (!multiple || (len % fw_len) != 0))
600 return FW_BAD_LENGTH;
601
602 /*
603 * Check if the chipset requires one of the upper parts
604 * of the firmware.
605 */
606 if (rt2x00_is_usb(rt2x00dev) &&
607 !rt2x00_rt(rt2x00dev, RT2860) &&
608 !rt2x00_rt(rt2x00dev, RT2872) &&
609 !rt2x00_rt(rt2x00dev, RT3070) &&
610 ((len / fw_len) == 1))
611 return FW_BAD_VERSION;
612
613 /*
614 * 8kb firmware files must be checked as if it were
615 * 2 separate firmware files.
616 */
617 while (offset < len) {
618 if (!rt2800_check_firmware_crc(data + offset, fw_len))
619 return FW_BAD_CRC;
620
621 offset += fw_len;
622 }
623
624 return FW_OK;
625}
626EXPORT_SYMBOL_GPL(rt2800_check_firmware);
627
628int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
629 const u8 *data, const size_t len)
630{
631 unsigned int i;
632 u32 reg;
633 int retval;
634
635 if (rt2x00_rt(rt2x00dev, RT3290)) {
636 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
637 if (retval)
638 return -EBUSY;
639 }
640
641 /*
642 * If driver doesn't wake up firmware here,
643 * rt2800_load_firmware will hang forever when interface is up again.
644 */
645 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
646
647 /*
648 * Wait for stable hardware.
649 */
650 if (rt2800_wait_csr_ready(rt2x00dev))
651 return -EBUSY;
652
653 if (rt2x00_is_pci(rt2x00dev)) {
654 if (rt2x00_rt(rt2x00dev, RT3290) ||
655 rt2x00_rt(rt2x00dev, RT3572) ||
656 rt2x00_rt(rt2x00dev, RT5390) ||
657 rt2x00_rt(rt2x00dev, RT5392)) {
658 rt2800_register_read(rt2x00dev, AUX_CTRL, ®);
659 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
660 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
662 }
663 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
664 }
665
666 rt2800_disable_wpdma(rt2x00dev);
667
668 /*
669 * Write firmware to the device.
670 */
671 rt2800_drv_write_firmware(rt2x00dev, data, len);
672
673 /*
674 * Wait for device to stabilize.
675 */
676 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®);
678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
679 break;
680 msleep(1);
681 }
682
683 if (i == REGISTER_BUSY_COUNT) {
684 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
685 return -EBUSY;
686 }
687
688 /*
689 * Disable DMA, will be reenabled later when enabling
690 * the radio.
691 */
692 rt2800_disable_wpdma(rt2x00dev);
693
694 /*
695 * Initialize firmware.
696 */
697 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
698 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
699 if (rt2x00_is_usb(rt2x00dev)) {
700 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
701 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
702 }
703 msleep(1);
704
705 return 0;
706}
707EXPORT_SYMBOL_GPL(rt2800_load_firmware);
708
709void rt2800_write_tx_data(struct queue_entry *entry,
710 struct txentry_desc *txdesc)
711{
712 __le32 *txwi = rt2800_drv_get_txwi(entry);
713 u32 word;
714 int i;
715
716 /*
717 * Initialize TX Info descriptor
718 */
719 rt2x00_desc_read(txwi, 0, &word);
720 rt2x00_set_field32(&word, TXWI_W0_FRAG,
721 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
722 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
723 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
724 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
725 rt2x00_set_field32(&word, TXWI_W0_TS,
726 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
727 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
728 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
729 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
730 txdesc->u.ht.mpdu_density);
731 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
732 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
733 rt2x00_set_field32(&word, TXWI_W0_BW,
734 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
735 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
736 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
737 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
738 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
739 rt2x00_desc_write(txwi, 0, word);
740
741 rt2x00_desc_read(txwi, 1, &word);
742 rt2x00_set_field32(&word, TXWI_W1_ACK,
743 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
744 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
745 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
746 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
747 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
748 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
749 txdesc->key_idx : txdesc->u.ht.wcid);
750 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
751 txdesc->length);
752 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
753 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
754 rt2x00_desc_write(txwi, 1, word);
755
756 /*
757 * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
758 * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
759 * When TXD_W3_WIV is set to 1 it will use the IV data
760 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
761 * crypto entry in the registers should be used to encrypt the frame.
762 *
763 * Nulify all remaining words as well, we don't know how to program them.
764 */
765 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
766 _rt2x00_desc_write(txwi, i, 0);
767}
768EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
769
770static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
771{
772 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
773 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
774 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
775 u16 eeprom;
776 u8 offset0;
777 u8 offset1;
778 u8 offset2;
779
780 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
781 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
782 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
783 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
784 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
785 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
786 } else {
787 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
788 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
789 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
790 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
791 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
792 }
793
794 /*
795 * Convert the value from the descriptor into the RSSI value
796 * If the value in the descriptor is 0, it is considered invalid
797 * and the default (extremely low) rssi value is assumed
798 */
799 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
800 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
801 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
802
803 /*
804 * mac80211 only accepts a single RSSI value. Calculating the
805 * average doesn't deliver a fair answer either since -60:-60 would
806 * be considered equally good as -50:-70 while the second is the one
807 * which gives less energy...
808 */
809 rssi0 = max(rssi0, rssi1);
810 return (int)max(rssi0, rssi2);
811}
812
813void rt2800_process_rxwi(struct queue_entry *entry,
814 struct rxdone_entry_desc *rxdesc)
815{
816 __le32 *rxwi = (__le32 *) entry->skb->data;
817 u32 word;
818
819 rt2x00_desc_read(rxwi, 0, &word);
820
821 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
822 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
823
824 rt2x00_desc_read(rxwi, 1, &word);
825
826 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
827 rxdesc->flags |= RX_FLAG_SHORT_GI;
828
829 if (rt2x00_get_field32(word, RXWI_W1_BW))
830 rxdesc->flags |= RX_FLAG_40MHZ;
831
832 /*
833 * Detect RX rate, always use MCS as signal type.
834 */
835 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
836 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
837 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
838
839 /*
840 * Mask of 0x8 bit to remove the short preamble flag.
841 */
842 if (rxdesc->rate_mode == RATE_MODE_CCK)
843 rxdesc->signal &= ~0x8;
844
845 rt2x00_desc_read(rxwi, 2, &word);
846
847 /*
848 * Convert descriptor AGC value to RSSI value.
849 */
850 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
851 /*
852 * Remove RXWI descriptor from start of the buffer.
853 */
854 skb_pull(entry->skb, entry->queue->winfo_size);
855}
856EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
857
858void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
859{
860 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
861 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
862 struct txdone_entry_desc txdesc;
863 u32 word;
864 u16 mcs, real_mcs;
865 int aggr, ampdu;
866
867 /*
868 * Obtain the status about this packet.
869 */
870 txdesc.flags = 0;
871 rt2x00_desc_read(txwi, 0, &word);
872
873 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
874 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
875
876 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
877 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
878
879 /*
880 * If a frame was meant to be sent as a single non-aggregated MPDU
881 * but ended up in an aggregate the used tx rate doesn't correlate
882 * with the one specified in the TXWI as the whole aggregate is sent
883 * with the same rate.
884 *
885 * For example: two frames are sent to rt2x00, the first one sets
886 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
887 * and requests MCS15. If the hw aggregates both frames into one
888 * AMDPU the tx status for both frames will contain MCS7 although
889 * the frame was sent successfully.
890 *
891 * Hence, replace the requested rate with the real tx rate to not
892 * confuse the rate control algortihm by providing clearly wrong
893 * data.
894 */
895 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
896 skbdesc->tx_rate_idx = real_mcs;
897 mcs = real_mcs;
898 }
899
900 if (aggr == 1 || ampdu == 1)
901 __set_bit(TXDONE_AMPDU, &txdesc.flags);
902
903 /*
904 * Ralink has a retry mechanism using a global fallback
905 * table. We setup this fallback table to try the immediate
906 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
907 * always contains the MCS used for the last transmission, be
908 * it successful or not.
909 */
910 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
911 /*
912 * Transmission succeeded. The number of retries is
913 * mcs - real_mcs
914 */
915 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
916 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
917 } else {
918 /*
919 * Transmission failed. The number of retries is
920 * always 7 in this case (for a total number of 8
921 * frames sent).
922 */
923 __set_bit(TXDONE_FAILURE, &txdesc.flags);
924 txdesc.retry = rt2x00dev->long_retry;
925 }
926
927 /*
928 * the frame was retried at least once
929 * -> hw used fallback rates
930 */
931 if (txdesc.retry)
932 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
933
934 rt2x00lib_txdone(entry, &txdesc);
935}
936EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
937
938static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
939 unsigned int index)
940{
941 return HW_BEACON_BASE(index);
942}
943
944static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
945 unsigned int index)
946{
947 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
948}
949
950void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
951{
952 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
953 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
954 unsigned int beacon_base;
955 unsigned int padding_len;
956 u32 orig_reg, reg;
957 const int txwi_desc_size = entry->queue->winfo_size;
958
959 /*
960 * Disable beaconing while we are reloading the beacon data,
961 * otherwise we might be sending out invalid data.
962 */
963 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
964 orig_reg = reg;
965 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
966 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
967
968 /*
969 * Add space for the TXWI in front of the skb.
970 */
971 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
972
973 /*
974 * Register descriptor details in skb frame descriptor.
975 */
976 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
977 skbdesc->desc = entry->skb->data;
978 skbdesc->desc_len = txwi_desc_size;
979
980 /*
981 * Add the TXWI for the beacon to the skb.
982 */
983 rt2800_write_tx_data(entry, txdesc);
984
985 /*
986 * Dump beacon to userspace through debugfs.
987 */
988 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
989
990 /*
991 * Write entire beacon with TXWI and padding to register.
992 */
993 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
994 if (padding_len && skb_pad(entry->skb, padding_len)) {
995 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
996 /* skb freed by skb_pad() on failure */
997 entry->skb = NULL;
998 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
999 return;
1000 }
1001
1002 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1003
1004 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1005 entry->skb->len + padding_len);
1006
1007 /*
1008 * Enable beaconing again.
1009 */
1010 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
1011 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1012
1013 /*
1014 * Clean up beacon skb.
1015 */
1016 dev_kfree_skb_any(entry->skb);
1017 entry->skb = NULL;
1018}
1019EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1020
1021static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1022 unsigned int index)
1023{
1024 int i;
1025 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1026 unsigned int beacon_base;
1027
1028 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1029
1030 /*
1031 * For the Beacon base registers we only need to clear
1032 * the whole TXWI which (when set to 0) will invalidate
1033 * the entire beacon.
1034 */
1035 for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1036 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1037}
1038
1039void rt2800_clear_beacon(struct queue_entry *entry)
1040{
1041 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1042 u32 reg;
1043
1044 /*
1045 * Disable beaconing while we are reloading the beacon data,
1046 * otherwise we might be sending out invalid data.
1047 */
1048 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1049 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
1050 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1051
1052 /*
1053 * Clear beacon.
1054 */
1055 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1056
1057 /*
1058 * Enabled beaconing again.
1059 */
1060 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
1061 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1062}
1063EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1064
1065#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1066const struct rt2x00debug rt2800_rt2x00debug = {
1067 .owner = THIS_MODULE,
1068 .csr = {
1069 .read = rt2800_register_read,
1070 .write = rt2800_register_write,
1071 .flags = RT2X00DEBUGFS_OFFSET,
1072 .word_base = CSR_REG_BASE,
1073 .word_size = sizeof(u32),
1074 .word_count = CSR_REG_SIZE / sizeof(u32),
1075 },
1076 .eeprom = {
1077 /* NOTE: The local EEPROM access functions can't
1078 * be used here, use the generic versions instead.
1079 */
1080 .read = rt2x00_eeprom_read,
1081 .write = rt2x00_eeprom_write,
1082 .word_base = EEPROM_BASE,
1083 .word_size = sizeof(u16),
1084 .word_count = EEPROM_SIZE / sizeof(u16),
1085 },
1086 .bbp = {
1087 .read = rt2800_bbp_read,
1088 .write = rt2800_bbp_write,
1089 .word_base = BBP_BASE,
1090 .word_size = sizeof(u8),
1091 .word_count = BBP_SIZE / sizeof(u8),
1092 },
1093 .rf = {
1094 .read = rt2x00_rf_read,
1095 .write = rt2800_rf_write,
1096 .word_base = RF_BASE,
1097 .word_size = sizeof(u32),
1098 .word_count = RF_SIZE / sizeof(u32),
1099 },
1100 .rfcsr = {
1101 .read = rt2800_rfcsr_read,
1102 .write = rt2800_rfcsr_write,
1103 .word_base = RFCSR_BASE,
1104 .word_size = sizeof(u8),
1105 .word_count = RFCSR_SIZE / sizeof(u8),
1106 },
1107};
1108EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1109#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1110
1111int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1112{
1113 u32 reg;
1114
1115 if (rt2x00_rt(rt2x00dev, RT3290)) {
1116 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®);
1117 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1118 } else {
1119 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®);
1120 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1121 }
1122}
1123EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1124
1125#ifdef CONFIG_RT2X00_LIB_LEDS
1126static void rt2800_brightness_set(struct led_classdev *led_cdev,
1127 enum led_brightness brightness)
1128{
1129 struct rt2x00_led *led =
1130 container_of(led_cdev, struct rt2x00_led, led_dev);
1131 unsigned int enabled = brightness != LED_OFF;
1132 unsigned int bg_mode =
1133 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
1134 unsigned int polarity =
1135 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1136 EEPROM_FREQ_LED_POLARITY);
1137 unsigned int ledmode =
1138 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1139 EEPROM_FREQ_LED_MODE);
1140 u32 reg;
1141
1142 /* Check for SoC (SOC devices don't support MCU requests) */
1143 if (rt2x00_is_soc(led->rt2x00dev)) {
1144 rt2800_register_read(led->rt2x00dev, LED_CFG, ®);
1145
1146 /* Set LED Polarity */
1147 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity);
1148
1149 /* Set LED Mode */
1150 if (led->type == LED_TYPE_RADIO) {
1151 rt2x00_set_field32(®, LED_CFG_G_LED_MODE,
1152 enabled ? 3 : 0);
1153 } else if (led->type == LED_TYPE_ASSOC) {
1154 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE,
1155 enabled ? 3 : 0);
1156 } else if (led->type == LED_TYPE_QUALITY) {
1157 rt2x00_set_field32(®, LED_CFG_R_LED_MODE,
1158 enabled ? 3 : 0);
1159 }
1160
1161 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1162
1163 } else {
1164 if (led->type == LED_TYPE_RADIO) {
1165 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1166 enabled ? 0x20 : 0);
1167 } else if (led->type == LED_TYPE_ASSOC) {
1168 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1169 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1170 } else if (led->type == LED_TYPE_QUALITY) {
1171 /*
1172 * The brightness is divided into 6 levels (0 - 5),
1173 * The specs tell us the following levels:
1174 * 0, 1 ,3, 7, 15, 31
1175 * to determine the level in a simple way we can simply
1176 * work with bitshifting:
1177 * (1 << level) - 1
1178 */
1179 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1180 (1 << brightness / (LED_FULL / 6)) - 1,
1181 polarity);
1182 }
1183 }
1184}
1185
1186static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1187 struct rt2x00_led *led, enum led_type type)
1188{
1189 led->rt2x00dev = rt2x00dev;
1190 led->type = type;
1191 led->led_dev.brightness_set = rt2800_brightness_set;
1192 led->flags = LED_INITIALIZED;
1193}
1194#endif /* CONFIG_RT2X00_LIB_LEDS */
1195
1196/*
1197 * Configuration handlers.
1198 */
1199static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1200 const u8 *address,
1201 int wcid)
1202{
1203 struct mac_wcid_entry wcid_entry;
1204 u32 offset;
1205
1206 offset = MAC_WCID_ENTRY(wcid);
1207
1208 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1209 if (address)
1210 memcpy(wcid_entry.mac, address, ETH_ALEN);
1211
1212 rt2800_register_multiwrite(rt2x00dev, offset,
1213 &wcid_entry, sizeof(wcid_entry));
1214}
1215
1216static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1217{
1218 u32 offset;
1219 offset = MAC_WCID_ATTR_ENTRY(wcid);
1220 rt2800_register_write(rt2x00dev, offset, 0);
1221}
1222
1223static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1224 int wcid, u32 bssidx)
1225{
1226 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1227 u32 reg;
1228
1229 /*
1230 * The BSS Idx numbers is split in a main value of 3 bits,
1231 * and a extended field for adding one additional bit to the value.
1232 */
1233 rt2800_register_read(rt2x00dev, offset, ®);
1234 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1235 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1236 (bssidx & 0x8) >> 3);
1237 rt2800_register_write(rt2x00dev, offset, reg);
1238}
1239
1240static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1241 struct rt2x00lib_crypto *crypto,
1242 struct ieee80211_key_conf *key)
1243{
1244 struct mac_iveiv_entry iveiv_entry;
1245 u32 offset;
1246 u32 reg;
1247
1248 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1249
1250 if (crypto->cmd == SET_KEY) {
1251 rt2800_register_read(rt2x00dev, offset, ®);
1252 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB,
1253 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1254 /*
1255 * Both the cipher as the BSS Idx numbers are split in a main
1256 * value of 3 bits, and a extended field for adding one additional
1257 * bit to the value.
1258 */
1259 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER,
1260 (crypto->cipher & 0x7));
1261 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1262 (crypto->cipher & 0x8) >> 3);
1263 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1264 rt2800_register_write(rt2x00dev, offset, reg);
1265 } else {
1266 /* Delete the cipher without touching the bssidx */
1267 rt2800_register_read(rt2x00dev, offset, ®);
1268 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1269 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1270 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1271 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1272 rt2800_register_write(rt2x00dev, offset, reg);
1273 }
1274
1275 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1276
1277 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1278 if ((crypto->cipher == CIPHER_TKIP) ||
1279 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1280 (crypto->cipher == CIPHER_AES))
1281 iveiv_entry.iv[3] |= 0x20;
1282 iveiv_entry.iv[3] |= key->keyidx << 6;
1283 rt2800_register_multiwrite(rt2x00dev, offset,
1284 &iveiv_entry, sizeof(iveiv_entry));
1285}
1286
1287int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1288 struct rt2x00lib_crypto *crypto,
1289 struct ieee80211_key_conf *key)
1290{
1291 struct hw_key_entry key_entry;
1292 struct rt2x00_field32 field;
1293 u32 offset;
1294 u32 reg;
1295
1296 if (crypto->cmd == SET_KEY) {
1297 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1298
1299 memcpy(key_entry.key, crypto->key,
1300 sizeof(key_entry.key));
1301 memcpy(key_entry.tx_mic, crypto->tx_mic,
1302 sizeof(key_entry.tx_mic));
1303 memcpy(key_entry.rx_mic, crypto->rx_mic,
1304 sizeof(key_entry.rx_mic));
1305
1306 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1307 rt2800_register_multiwrite(rt2x00dev, offset,
1308 &key_entry, sizeof(key_entry));
1309 }
1310
1311 /*
1312 * The cipher types are stored over multiple registers
1313 * starting with SHARED_KEY_MODE_BASE each word will have
1314 * 32 bits and contains the cipher types for 2 bssidx each.
1315 * Using the correct defines correctly will cause overhead,
1316 * so just calculate the correct offset.
1317 */
1318 field.bit_offset = 4 * (key->hw_key_idx % 8);
1319 field.bit_mask = 0x7 << field.bit_offset;
1320
1321 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1322
1323 rt2800_register_read(rt2x00dev, offset, ®);
1324 rt2x00_set_field32(®, field,
1325 (crypto->cmd == SET_KEY) * crypto->cipher);
1326 rt2800_register_write(rt2x00dev, offset, reg);
1327
1328 /*
1329 * Update WCID information
1330 */
1331 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1332 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1333 crypto->bssidx);
1334 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1335
1336 return 0;
1337}
1338EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1339
1340static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1341{
1342 struct mac_wcid_entry wcid_entry;
1343 int idx;
1344 u32 offset;
1345
1346 /*
1347 * Search for the first free WCID entry and return the corresponding
1348 * index.
1349 *
1350 * Make sure the WCID starts _after_ the last possible shared key
1351 * entry (>32).
1352 *
1353 * Since parts of the pairwise key table might be shared with
1354 * the beacon frame buffers 6 & 7 we should only write into the
1355 * first 222 entries.
1356 */
1357 for (idx = 33; idx <= 222; idx++) {
1358 offset = MAC_WCID_ENTRY(idx);
1359 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1360 sizeof(wcid_entry));
1361 if (is_broadcast_ether_addr(wcid_entry.mac))
1362 return idx;
1363 }
1364
1365 /*
1366 * Use -1 to indicate that we don't have any more space in the WCID
1367 * table.
1368 */
1369 return -1;
1370}
1371
1372int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1373 struct rt2x00lib_crypto *crypto,
1374 struct ieee80211_key_conf *key)
1375{
1376 struct hw_key_entry key_entry;
1377 u32 offset;
1378
1379 if (crypto->cmd == SET_KEY) {
1380 /*
1381 * Allow key configuration only for STAs that are
1382 * known by the hw.
1383 */
1384 if (crypto->wcid < 0)
1385 return -ENOSPC;
1386 key->hw_key_idx = crypto->wcid;
1387
1388 memcpy(key_entry.key, crypto->key,
1389 sizeof(key_entry.key));
1390 memcpy(key_entry.tx_mic, crypto->tx_mic,
1391 sizeof(key_entry.tx_mic));
1392 memcpy(key_entry.rx_mic, crypto->rx_mic,
1393 sizeof(key_entry.rx_mic));
1394
1395 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1396 rt2800_register_multiwrite(rt2x00dev, offset,
1397 &key_entry, sizeof(key_entry));
1398 }
1399
1400 /*
1401 * Update WCID information
1402 */
1403 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1404
1405 return 0;
1406}
1407EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1408
1409int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1410 struct ieee80211_sta *sta)
1411{
1412 int wcid;
1413 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1414
1415 /*
1416 * Find next free WCID.
1417 */
1418 wcid = rt2800_find_wcid(rt2x00dev);
1419
1420 /*
1421 * Store selected wcid even if it is invalid so that we can
1422 * later decide if the STA is uploaded into the hw.
1423 */
1424 sta_priv->wcid = wcid;
1425
1426 /*
1427 * No space left in the device, however, we can still communicate
1428 * with the STA -> No error.
1429 */
1430 if (wcid < 0)
1431 return 0;
1432
1433 /*
1434 * Clean up WCID attributes and write STA address to the device.
1435 */
1436 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1437 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1438 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1439 rt2x00lib_get_bssidx(rt2x00dev, vif));
1440 return 0;
1441}
1442EXPORT_SYMBOL_GPL(rt2800_sta_add);
1443
1444int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1445{
1446 /*
1447 * Remove WCID entry, no need to clean the attributes as they will
1448 * get renewed when the WCID is reused.
1449 */
1450 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1451
1452 return 0;
1453}
1454EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1455
1456void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1457 const unsigned int filter_flags)
1458{
1459 u32 reg;
1460
1461 /*
1462 * Start configuration steps.
1463 * Note that the version error will always be dropped
1464 * and broadcast frames will always be accepted since
1465 * there is no filter for it at this time.
1466 */
1467 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®);
1468 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR,
1469 !(filter_flags & FIF_FCSFAIL));
1470 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR,
1471 !(filter_flags & FIF_PLCPFAIL));
1472 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME,
1473 !(filter_flags & FIF_PROMISC_IN_BSS));
1474 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1475 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1476 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST,
1477 !(filter_flags & FIF_ALLMULTI));
1478 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0);
1479 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1480 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK,
1481 !(filter_flags & FIF_CONTROL));
1482 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END,
1483 !(filter_flags & FIF_CONTROL));
1484 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK,
1485 !(filter_flags & FIF_CONTROL));
1486 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS,
1487 !(filter_flags & FIF_CONTROL));
1488 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS,
1489 !(filter_flags & FIF_CONTROL));
1490 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL,
1491 !(filter_flags & FIF_PSPOLL));
1492 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0);
1493 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR,
1494 !(filter_flags & FIF_CONTROL));
1495 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL,
1496 !(filter_flags & FIF_CONTROL));
1497 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1498}
1499EXPORT_SYMBOL_GPL(rt2800_config_filter);
1500
1501void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1502 struct rt2x00intf_conf *conf, const unsigned int flags)
1503{
1504 u32 reg;
1505 bool update_bssid = false;
1506
1507 if (flags & CONFIG_UPDATE_TYPE) {
1508 /*
1509 * Enable synchronisation.
1510 */
1511 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1512 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1513 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1514
1515 if (conf->sync == TSF_SYNC_AP_NONE) {
1516 /*
1517 * Tune beacon queue transmit parameters for AP mode
1518 */
1519 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®);
1520 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1521 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1522 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1523 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1524 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1525 } else {
1526 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®);
1527 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1528 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1529 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1530 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1531 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1532 }
1533 }
1534
1535 if (flags & CONFIG_UPDATE_MAC) {
1536 if (flags & CONFIG_UPDATE_TYPE &&
1537 conf->sync == TSF_SYNC_AP_NONE) {
1538 /*
1539 * The BSSID register has to be set to our own mac
1540 * address in AP mode.
1541 */
1542 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1543 update_bssid = true;
1544 }
1545
1546 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1547 reg = le32_to_cpu(conf->mac[1]);
1548 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1549 conf->mac[1] = cpu_to_le32(reg);
1550 }
1551
1552 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1553 conf->mac, sizeof(conf->mac));
1554 }
1555
1556 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1557 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1558 reg = le32_to_cpu(conf->bssid[1]);
1559 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1560 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1561 conf->bssid[1] = cpu_to_le32(reg);
1562 }
1563
1564 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1565 conf->bssid, sizeof(conf->bssid));
1566 }
1567}
1568EXPORT_SYMBOL_GPL(rt2800_config_intf);
1569
1570static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1571 struct rt2x00lib_erp *erp)
1572{
1573 bool any_sta_nongf = !!(erp->ht_opmode &
1574 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1575 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1576 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1577 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1578 u32 reg;
1579
1580 /* default protection rate for HT20: OFDM 24M */
1581 mm20_rate = gf20_rate = 0x4004;
1582
1583 /* default protection rate for HT40: duplicate OFDM 24M */
1584 mm40_rate = gf40_rate = 0x4084;
1585
1586 switch (protection) {
1587 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1588 /*
1589 * All STAs in this BSS are HT20/40 but there might be
1590 * STAs not supporting greenfield mode.
1591 * => Disable protection for HT transmissions.
1592 */
1593 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1594
1595 break;
1596 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1597 /*
1598 * All STAs in this BSS are HT20 or HT20/40 but there
1599 * might be STAs not supporting greenfield mode.
1600 * => Protect all HT40 transmissions.
1601 */
1602 mm20_mode = gf20_mode = 0;
1603 mm40_mode = gf40_mode = 2;
1604
1605 break;
1606 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1607 /*
1608 * Nonmember protection:
1609 * According to 802.11n we _should_ protect all
1610 * HT transmissions (but we don't have to).
1611 *
1612 * But if cts_protection is enabled we _shall_ protect
1613 * all HT transmissions using a CCK rate.
1614 *
1615 * And if any station is non GF we _shall_ protect
1616 * GF transmissions.
1617 *
1618 * We decide to protect everything
1619 * -> fall through to mixed mode.
1620 */
1621 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1622 /*
1623 * Legacy STAs are present
1624 * => Protect all HT transmissions.
1625 */
1626 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1627
1628 /*
1629 * If erp protection is needed we have to protect HT
1630 * transmissions with CCK 11M long preamble.
1631 */
1632 if (erp->cts_protection) {
1633 /* don't duplicate RTS/CTS in CCK mode */
1634 mm20_rate = mm40_rate = 0x0003;
1635 gf20_rate = gf40_rate = 0x0003;
1636 }
1637 break;
1638 }
1639
1640 /* check for STAs not supporting greenfield mode */
1641 if (any_sta_nongf)
1642 gf20_mode = gf40_mode = 2;
1643
1644 /* Update HT protection config */
1645 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
1646 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1647 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1648 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1649
1650 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
1651 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1652 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1653 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1654
1655 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
1656 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1657 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1658 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1659
1660 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
1661 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1662 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1663 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1664}
1665
1666void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1667 u32 changed)
1668{
1669 u32 reg;
1670
1671 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1672 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
1673 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY,
1674 !!erp->short_preamble);
1675 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE,
1676 !!erp->short_preamble);
1677 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1678 }
1679
1680 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1681 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
1682 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL,
1683 erp->cts_protection ? 2 : 0);
1684 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1685 }
1686
1687 if (changed & BSS_CHANGED_BASIC_RATES) {
1688 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1689 erp->basic_rates);
1690 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1691 }
1692
1693 if (changed & BSS_CHANGED_ERP_SLOT) {
1694 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®);
1695 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME,
1696 erp->slot_time);
1697 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1698
1699 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®);
1700 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs);
1701 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1702 }
1703
1704 if (changed & BSS_CHANGED_BEACON_INT) {
1705 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1706 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
1707 erp->beacon_int * 16);
1708 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1709 }
1710
1711 if (changed & BSS_CHANGED_HT)
1712 rt2800_config_ht_opmode(rt2x00dev, erp);
1713}
1714EXPORT_SYMBOL_GPL(rt2800_config_erp);
1715
1716static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1717{
1718 u32 reg;
1719 u16 eeprom;
1720 u8 led_ctrl, led_g_mode, led_r_mode;
1721
1722 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
1723 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1724 rt2x00_set_field32(®, GPIO_SWITCH_0, 1);
1725 rt2x00_set_field32(®, GPIO_SWITCH_1, 1);
1726 } else {
1727 rt2x00_set_field32(®, GPIO_SWITCH_0, 0);
1728 rt2x00_set_field32(®, GPIO_SWITCH_1, 0);
1729 }
1730 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1731
1732 rt2800_register_read(rt2x00dev, LED_CFG, ®);
1733 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1734 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1735 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1736 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1737 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1738 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1739 if (led_ctrl == 0 || led_ctrl > 0x40) {
1740 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode);
1741 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode);
1742 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1743 } else {
1744 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1745 (led_g_mode << 2) | led_r_mode, 1);
1746 }
1747 }
1748}
1749
1750static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1751 enum antenna ant)
1752{
1753 u32 reg;
1754 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1755 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1756
1757 if (rt2x00_is_pci(rt2x00dev)) {
1758 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®);
1759 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1760 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1761 } else if (rt2x00_is_usb(rt2x00dev))
1762 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1763 eesk_pin, 0);
1764
1765 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®);
1766 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0);
1767 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3);
1768 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1769}
1770
1771void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1772{
1773 u8 r1;
1774 u8 r3;
1775 u16 eeprom;
1776
1777 rt2800_bbp_read(rt2x00dev, 1, &r1);
1778 rt2800_bbp_read(rt2x00dev, 3, &r3);
1779
1780 if (rt2x00_rt(rt2x00dev, RT3572) &&
1781 rt2x00_has_cap_bt_coexist(rt2x00dev))
1782 rt2800_config_3572bt_ant(rt2x00dev);
1783
1784 /*
1785 * Configure the TX antenna.
1786 */
1787 switch (ant->tx_chain_num) {
1788 case 1:
1789 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1790 break;
1791 case 2:
1792 if (rt2x00_rt(rt2x00dev, RT3572) &&
1793 rt2x00_has_cap_bt_coexist(rt2x00dev))
1794 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1795 else
1796 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1797 break;
1798 case 3:
1799 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1800 break;
1801 }
1802
1803 /*
1804 * Configure the RX antenna.
1805 */
1806 switch (ant->rx_chain_num) {
1807 case 1:
1808 if (rt2x00_rt(rt2x00dev, RT3070) ||
1809 rt2x00_rt(rt2x00dev, RT3090) ||
1810 rt2x00_rt(rt2x00dev, RT3352) ||
1811 rt2x00_rt(rt2x00dev, RT3390)) {
1812 rt2800_eeprom_read(rt2x00dev,
1813 EEPROM_NIC_CONF1, &eeprom);
1814 if (rt2x00_get_field16(eeprom,
1815 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1816 rt2800_set_ant_diversity(rt2x00dev,
1817 rt2x00dev->default_ant.rx);
1818 }
1819 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1820 break;
1821 case 2:
1822 if (rt2x00_rt(rt2x00dev, RT3572) &&
1823 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
1824 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1825 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1826 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1827 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1828 } else {
1829 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1830 }
1831 break;
1832 case 3:
1833 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1834 break;
1835 }
1836
1837 rt2800_bbp_write(rt2x00dev, 3, r3);
1838 rt2800_bbp_write(rt2x00dev, 1, r1);
1839
1840 if (rt2x00_rt(rt2x00dev, RT3593)) {
1841 if (ant->rx_chain_num == 1)
1842 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1843 else
1844 rt2800_bbp_write(rt2x00dev, 86, 0x46);
1845 }
1846}
1847EXPORT_SYMBOL_GPL(rt2800_config_ant);
1848
1849static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1850 struct rt2x00lib_conf *libconf)
1851{
1852 u16 eeprom;
1853 short lna_gain;
1854
1855 if (libconf->rf.channel <= 14) {
1856 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1857 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1858 } else if (libconf->rf.channel <= 64) {
1859 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1860 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1861 } else if (libconf->rf.channel <= 128) {
1862 if (rt2x00_rt(rt2x00dev, RT3593)) {
1863 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1864 lna_gain = rt2x00_get_field16(eeprom,
1865 EEPROM_EXT_LNA2_A1);
1866 } else {
1867 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1868 lna_gain = rt2x00_get_field16(eeprom,
1869 EEPROM_RSSI_BG2_LNA_A1);
1870 }
1871 } else {
1872 if (rt2x00_rt(rt2x00dev, RT3593)) {
1873 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
1874 lna_gain = rt2x00_get_field16(eeprom,
1875 EEPROM_EXT_LNA2_A2);
1876 } else {
1877 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1878 lna_gain = rt2x00_get_field16(eeprom,
1879 EEPROM_RSSI_A2_LNA_A2);
1880 }
1881 }
1882
1883 rt2x00dev->lna_gain = lna_gain;
1884}
1885
1886#define FREQ_OFFSET_BOUND 0x5f
1887
1888static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
1889{
1890 u8 freq_offset, prev_freq_offset;
1891 u8 rfcsr, prev_rfcsr;
1892
1893 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
1894 freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
1895
1896 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1897 prev_rfcsr = rfcsr;
1898
1899 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
1900 if (rfcsr == prev_rfcsr)
1901 return;
1902
1903 if (rt2x00_is_usb(rt2x00dev)) {
1904 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
1905 freq_offset, prev_rfcsr);
1906 return;
1907 }
1908
1909 prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
1910 while (prev_freq_offset != freq_offset) {
1911 if (prev_freq_offset < freq_offset)
1912 prev_freq_offset++;
1913 else
1914 prev_freq_offset--;
1915
1916 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
1917 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1918
1919 usleep_range(1000, 1500);
1920 }
1921}
1922
1923static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1924 struct ieee80211_conf *conf,
1925 struct rf_channel *rf,
1926 struct channel_info *info)
1927{
1928 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1929
1930 if (rt2x00dev->default_ant.tx_chain_num == 1)
1931 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1932
1933 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1934 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1935 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1936 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1937 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1938
1939 if (rf->channel > 14) {
1940 /*
1941 * When TX power is below 0, we should increase it by 7 to
1942 * make it a positive value (Minimum value is -7).
1943 * However this means that values between 0 and 7 have
1944 * double meaning, and we should set a 7DBm boost flag.
1945 */
1946 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1947 (info->default_power1 >= 0));
1948
1949 if (info->default_power1 < 0)
1950 info->default_power1 += 7;
1951
1952 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1953
1954 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1955 (info->default_power2 >= 0));
1956
1957 if (info->default_power2 < 0)
1958 info->default_power2 += 7;
1959
1960 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1961 } else {
1962 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1963 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1964 }
1965
1966 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1967
1968 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1969 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1970 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1971 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1972
1973 udelay(200);
1974
1975 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1976 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1977 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1978 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1979
1980 udelay(200);
1981
1982 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1983 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1984 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1985 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1986}
1987
1988static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1989 struct ieee80211_conf *conf,
1990 struct rf_channel *rf,
1991 struct channel_info *info)
1992{
1993 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1994 u8 rfcsr, calib_tx, calib_rx;
1995
1996 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1997
1998 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1999 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2000 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2001
2002 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2003 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2004 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2005
2006 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2007 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2008 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2009
2010 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2011 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2012 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2013
2014 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2015 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2016 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2017 rt2x00dev->default_ant.rx_chain_num <= 1);
2018 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2019 rt2x00dev->default_ant.rx_chain_num <= 2);
2020 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2021 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2022 rt2x00dev->default_ant.tx_chain_num <= 1);
2023 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2024 rt2x00dev->default_ant.tx_chain_num <= 2);
2025 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2026
2027 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2028 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2029 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2030
2031 if (rt2x00_rt(rt2x00dev, RT3390)) {
2032 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2033 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2034 } else {
2035 if (conf_is_ht40(conf)) {
2036 calib_tx = drv_data->calibration_bw40;
2037 calib_rx = drv_data->calibration_bw40;
2038 } else {
2039 calib_tx = drv_data->calibration_bw20;
2040 calib_rx = drv_data->calibration_bw20;
2041 }
2042 }
2043
2044 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
2045 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2046 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2047
2048 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
2049 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2050 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2051
2052 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2053 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2054 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2055
2056 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2057 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2058 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2059 msleep(1);
2060 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2061 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2062}
2063
2064static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2065 struct ieee80211_conf *conf,
2066 struct rf_channel *rf,
2067 struct channel_info *info)
2068{
2069 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2070 u8 rfcsr;
2071 u32 reg;
2072
2073 if (rf->channel <= 14) {
2074 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2075 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2076 } else {
2077 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2078 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2079 }
2080
2081 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2082 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2083
2084 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2085 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2086 if (rf->channel <= 14)
2087 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2088 else
2089 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2090 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2091
2092 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
2093 if (rf->channel <= 14)
2094 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2095 else
2096 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2097 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2098
2099 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2100 if (rf->channel <= 14) {
2101 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2102 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2103 info->default_power1);
2104 } else {
2105 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2106 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2107 (info->default_power1 & 0x3) |
2108 ((info->default_power1 & 0xC) << 1));
2109 }
2110 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2111
2112 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
2113 if (rf->channel <= 14) {
2114 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2115 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2116 info->default_power2);
2117 } else {
2118 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2119 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2120 (info->default_power2 & 0x3) |
2121 ((info->default_power2 & 0xC) << 1));
2122 }
2123 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2124
2125 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2126 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2127 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2128 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2129 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2130 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2131 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2132 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2133 if (rf->channel <= 14) {
2134 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2135 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2136 }
2137 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2138 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2139 } else {
2140 switch (rt2x00dev->default_ant.tx_chain_num) {
2141 case 1:
2142 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2143 case 2:
2144 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2145 break;
2146 }
2147
2148 switch (rt2x00dev->default_ant.rx_chain_num) {
2149 case 1:
2150 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2151 case 2:
2152 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2153 break;
2154 }
2155 }
2156 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2157
2158 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
2159 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2160 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2161
2162 if (conf_is_ht40(conf)) {
2163 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2164 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2165 } else {
2166 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2167 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2168 }
2169
2170 if (rf->channel <= 14) {
2171 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2172 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2173 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2174 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2175 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2176 rfcsr = 0x4c;
2177 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2178 drv_data->txmixer_gain_24g);
2179 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2180 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2181 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2182 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2183 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2184 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2185 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2186 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2187 } else {
2188 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2189 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2190 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2191 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2192 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2193 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2194 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2195 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2196 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2197 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2198 rfcsr = 0x7a;
2199 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2200 drv_data->txmixer_gain_5g);
2201 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2202 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2203 if (rf->channel <= 64) {
2204 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2205 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2206 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2207 } else if (rf->channel <= 128) {
2208 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2209 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2210 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2211 } else {
2212 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2213 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2214 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2215 }
2216 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2217 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2218 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2219 }
2220
2221 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®);
2222 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0);
2223 if (rf->channel <= 14)
2224 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1);
2225 else
2226 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0);
2227 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2228
2229 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2230 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2231 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2232}
2233
2234static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2235 struct ieee80211_conf *conf,
2236 struct rf_channel *rf,
2237 struct channel_info *info)
2238{
2239 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2240 u8 txrx_agc_fc;
2241 u8 txrx_h20m;
2242 u8 rfcsr;
2243 u8 bbp;
2244 const bool txbf_enabled = false; /* TODO */
2245
2246 /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2247 rt2800_bbp_read(rt2x00dev, 109, &bbp);
2248 rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2249 rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2250 rt2800_bbp_write(rt2x00dev, 109, bbp);
2251
2252 rt2800_bbp_read(rt2x00dev, 110, &bbp);
2253 rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2254 rt2800_bbp_write(rt2x00dev, 110, bbp);
2255
2256 if (rf->channel <= 14) {
2257 /* Restore BBP 25 & 26 for 2.4 GHz */
2258 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2259 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2260 } else {
2261 /* Hard code BBP 25 & 26 for 5GHz */
2262
2263 /* Enable IQ Phase correction */
2264 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2265 /* Setup IQ Phase correction value */
2266 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2267 }
2268
2269 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2270 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2271
2272 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2273 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2274 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2275
2276 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2277 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2278 if (rf->channel <= 14)
2279 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2280 else
2281 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2282 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2283
2284 rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
2285 if (rf->channel <= 14) {
2286 rfcsr = 0;
2287 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2288 info->default_power1 & 0x1f);
2289 } else {
2290 if (rt2x00_is_usb(rt2x00dev))
2291 rfcsr = 0x40;
2292
2293 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2294 ((info->default_power1 & 0x18) << 1) |
2295 (info->default_power1 & 7));
2296 }
2297 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2298
2299 rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
2300 if (rf->channel <= 14) {
2301 rfcsr = 0;
2302 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2303 info->default_power2 & 0x1f);
2304 } else {
2305 if (rt2x00_is_usb(rt2x00dev))
2306 rfcsr = 0x40;
2307
2308 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2309 ((info->default_power2 & 0x18) << 1) |
2310 (info->default_power2 & 7));
2311 }
2312 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2313
2314 rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
2315 if (rf->channel <= 14) {
2316 rfcsr = 0;
2317 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2318 info->default_power3 & 0x1f);
2319 } else {
2320 if (rt2x00_is_usb(rt2x00dev))
2321 rfcsr = 0x40;
2322
2323 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2324 ((info->default_power3 & 0x18) << 1) |
2325 (info->default_power3 & 7));
2326 }
2327 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2328
2329 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2330 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2331 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2332 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2333 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2334 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2335 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2336 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2337 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2338
2339 switch (rt2x00dev->default_ant.tx_chain_num) {
2340 case 3:
2341 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2342 /* fallthrough */
2343 case 2:
2344 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2345 /* fallthrough */
2346 case 1:
2347 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2348 break;
2349 }
2350
2351 switch (rt2x00dev->default_ant.rx_chain_num) {
2352 case 3:
2353 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2354 /* fallthrough */
2355 case 2:
2356 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2357 /* fallthrough */
2358 case 1:
2359 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2360 break;
2361 }
2362 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2363
2364 rt2800_adjust_freq_offset(rt2x00dev);
2365
2366 if (conf_is_ht40(conf)) {
2367 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2368 RFCSR24_TX_AGC_FC);
2369 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2370 RFCSR24_TX_H20M);
2371 } else {
2372 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2373 RFCSR24_TX_AGC_FC);
2374 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2375 RFCSR24_TX_H20M);
2376 }
2377
2378 /* NOTE: the reference driver does not writes the new value
2379 * back to RFCSR 32
2380 */
2381 rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
2382 rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2383
2384 if (rf->channel <= 14)
2385 rfcsr = 0xa0;
2386 else
2387 rfcsr = 0x80;
2388 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2389
2390 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2391 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2392 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2393 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2394
2395 /* Band selection */
2396 rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
2397 if (rf->channel <= 14)
2398 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2399 else
2400 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2401 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2402
2403 rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
2404 if (rf->channel <= 14)
2405 rfcsr = 0x3c;
2406 else
2407 rfcsr = 0x20;
2408 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2409
2410 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
2411 if (rf->channel <= 14)
2412 rfcsr = 0x1a;
2413 else
2414 rfcsr = 0x12;
2415 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2416
2417 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
2418 if (rf->channel >= 1 && rf->channel <= 14)
2419 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2420 else if (rf->channel >= 36 && rf->channel <= 64)
2421 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2422 else if (rf->channel >= 100 && rf->channel <= 128)
2423 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2424 else
2425 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2426 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2427
2428 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2429 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2430 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2431
2432 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2433
2434 if (rf->channel <= 14) {
2435 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2436 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2437 } else {
2438 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2439 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2440 }
2441
2442 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2443 rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2444 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2445
2446 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
2447 if (rf->channel <= 14) {
2448 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2449 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2450 } else {
2451 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2452 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2453 }
2454 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2455
2456 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2457 if (rf->channel <= 14)
2458 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2459 else
2460 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2461
2462 if (txbf_enabled)
2463 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2464
2465 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2466
2467 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2468 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2469 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2470
2471 rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
2472 if (rf->channel <= 14)
2473 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2474 else
2475 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2476 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2477
2478 if (rf->channel <= 14) {
2479 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2480 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2481 } else {
2482 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2483 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2484 }
2485
2486 /* Initiate VCO calibration */
2487 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2488 if (rf->channel <= 14) {
2489 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2490 } else {
2491 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2492 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2493 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2494 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2495 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2496 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2497 }
2498 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2499
2500 if (rf->channel >= 1 && rf->channel <= 14) {
2501 rfcsr = 0x23;
2502 if (txbf_enabled)
2503 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2504 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2505
2506 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2507 } else if (rf->channel >= 36 && rf->channel <= 64) {
2508 rfcsr = 0x36;
2509 if (txbf_enabled)
2510 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2511 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2512
2513 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2514 } else if (rf->channel >= 100 && rf->channel <= 128) {
2515 rfcsr = 0x32;
2516 if (txbf_enabled)
2517 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2518 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2519
2520 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2521 } else {
2522 rfcsr = 0x30;
2523 if (txbf_enabled)
2524 rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2525 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2526
2527 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2528 }
2529}
2530
2531#define POWER_BOUND 0x27
2532#define POWER_BOUND_5G 0x2b
2533
2534static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2535 struct ieee80211_conf *conf,
2536 struct rf_channel *rf,
2537 struct channel_info *info)
2538{
2539 u8 rfcsr;
2540
2541 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2542 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2543 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2544 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2545 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2546
2547 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2548 if (info->default_power1 > POWER_BOUND)
2549 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2550 else
2551 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2552 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2553
2554 rt2800_adjust_freq_offset(rt2x00dev);
2555
2556 if (rf->channel <= 14) {
2557 if (rf->channel == 6)
2558 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2559 else
2560 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2561
2562 if (rf->channel >= 1 && rf->channel <= 6)
2563 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2564 else if (rf->channel >= 7 && rf->channel <= 11)
2565 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2566 else if (rf->channel >= 12 && rf->channel <= 14)
2567 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2568 }
2569}
2570
2571static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2572 struct ieee80211_conf *conf,
2573 struct rf_channel *rf,
2574 struct channel_info *info)
2575{
2576 u8 rfcsr;
2577
2578 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2579 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2580
2581 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2582 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2583 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2584
2585 if (info->default_power1 > POWER_BOUND)
2586 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2587 else
2588 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2589
2590 if (info->default_power2 > POWER_BOUND)
2591 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2592 else
2593 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2594
2595 rt2800_adjust_freq_offset(rt2x00dev);
2596
2597 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2598 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2599 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2600
2601 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2602 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2603 else
2604 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2605
2606 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2607 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2608 else
2609 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2610
2611 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2612 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2613
2614 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2615
2616 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2617}
2618
2619static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2620 struct ieee80211_conf *conf,
2621 struct rf_channel *rf,
2622 struct channel_info *info)
2623{
2624 u8 rfcsr;
2625
2626 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2627 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2628 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2629 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2630 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2631
2632 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2633 if (info->default_power1 > POWER_BOUND)
2634 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2635 else
2636 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2637 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2638
2639 if (rt2x00_rt(rt2x00dev, RT5392)) {
2640 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2641 if (info->default_power2 > POWER_BOUND)
2642 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2643 else
2644 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2645 info->default_power2);
2646 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2647 }
2648
2649 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2650 if (rt2x00_rt(rt2x00dev, RT5392)) {
2651 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2652 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2653 }
2654 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2655 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2656 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2657 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2658 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2659
2660 rt2800_adjust_freq_offset(rt2x00dev);
2661
2662 if (rf->channel <= 14) {
2663 int idx = rf->channel-1;
2664
2665 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2666 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2667 /* r55/r59 value array of channel 1~14 */
2668 static const char r55_bt_rev[] = {0x83, 0x83,
2669 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2670 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2671 static const char r59_bt_rev[] = {0x0e, 0x0e,
2672 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2673 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2674
2675 rt2800_rfcsr_write(rt2x00dev, 55,
2676 r55_bt_rev[idx]);
2677 rt2800_rfcsr_write(rt2x00dev, 59,
2678 r59_bt_rev[idx]);
2679 } else {
2680 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2681 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2682 0x88, 0x88, 0x86, 0x85, 0x84};
2683
2684 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2685 }
2686 } else {
2687 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2688 static const char r55_nonbt_rev[] = {0x23, 0x23,
2689 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2690 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2691 static const char r59_nonbt_rev[] = {0x07, 0x07,
2692 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2693 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2694
2695 rt2800_rfcsr_write(rt2x00dev, 55,
2696 r55_nonbt_rev[idx]);
2697 rt2800_rfcsr_write(rt2x00dev, 59,
2698 r59_nonbt_rev[idx]);
2699 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2700 rt2x00_rt(rt2x00dev, RT5392)) {
2701 static const char r59_non_bt[] = {0x8f, 0x8f,
2702 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2703 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2704
2705 rt2800_rfcsr_write(rt2x00dev, 59,
2706 r59_non_bt[idx]);
2707 }
2708 }
2709 }
2710}
2711
2712static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2713 struct ieee80211_conf *conf,
2714 struct rf_channel *rf,
2715 struct channel_info *info)
2716{
2717 u8 rfcsr, ep_reg;
2718 u32 reg;
2719 int power_bound;
2720
2721 /* TODO */
2722 const bool is_11b = false;
2723 const bool is_type_ep = false;
2724
2725 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
2726 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL,
2727 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2728 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2729
2730 /* Order of values on rf_channel entry: N, K, mod, R */
2731 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2732
2733 rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
2734 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2735 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2736 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2737 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2738
2739 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2740 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2741 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2742 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2743
2744 if (rf->channel <= 14) {
2745 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2746 /* FIXME: RF11 owerwrite ? */
2747 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2748 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2749 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2750 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2751 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2752 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2753 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2754 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2755 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2756 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2757 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2758 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2759 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2760 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2761 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2762 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2763 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2764 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2765 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2766 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2767 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2768 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2769 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2770 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2771 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2772 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2773 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2774 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2775
2776 /* TODO RF27 <- tssi */
2777
2778 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2779 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2780 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2781
2782 if (is_11b) {
2783 /* CCK */
2784 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2785 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2786 if (is_type_ep)
2787 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2788 else
2789 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2790 } else {
2791 /* OFDM */
2792 if (is_type_ep)
2793 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2794 else
2795 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2796 }
2797
2798 power_bound = POWER_BOUND;
2799 ep_reg = 0x2;
2800 } else {
2801 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2802 /* FIMXE: RF11 overwrite */
2803 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2804 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2805 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2806 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
2807 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
2808 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
2809 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
2810 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
2811 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
2812 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
2813 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
2814 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
2815 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
2816 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
2817
2818 /* TODO RF27 <- tssi */
2819
2820 if (rf->channel >= 36 && rf->channel <= 64) {
2821
2822 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
2823 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
2824 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
2825 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
2826 if (rf->channel <= 50)
2827 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
2828 else if (rf->channel >= 52)
2829 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
2830 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
2831 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
2832 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
2833 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
2834 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
2835 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
2836 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
2837 if (rf->channel <= 50) {
2838 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
2839 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
2840 } else if (rf->channel >= 52) {
2841 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
2842 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2843 }
2844
2845 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2846 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
2847 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2848
2849 } else if (rf->channel >= 100 && rf->channel <= 165) {
2850
2851 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
2852 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2853 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2854 if (rf->channel <= 153) {
2855 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
2856 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
2857 } else if (rf->channel >= 155) {
2858 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
2859 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
2860 }
2861 if (rf->channel <= 138) {
2862 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
2863 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
2864 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
2865 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
2866 } else if (rf->channel >= 140) {
2867 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
2868 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
2869 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
2870 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
2871 }
2872 if (rf->channel <= 124)
2873 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
2874 else if (rf->channel >= 126)
2875 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
2876 if (rf->channel <= 138)
2877 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2878 else if (rf->channel >= 140)
2879 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
2880 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
2881 if (rf->channel <= 138)
2882 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
2883 else if (rf->channel >= 140)
2884 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
2885 if (rf->channel <= 128)
2886 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
2887 else if (rf->channel >= 130)
2888 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
2889 if (rf->channel <= 116)
2890 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
2891 else if (rf->channel >= 118)
2892 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
2893 if (rf->channel <= 138)
2894 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
2895 else if (rf->channel >= 140)
2896 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
2897 if (rf->channel <= 116)
2898 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
2899 else if (rf->channel >= 118)
2900 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
2901 }
2902
2903 power_bound = POWER_BOUND_5G;
2904 ep_reg = 0x3;
2905 }
2906
2907 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2908 if (info->default_power1 > power_bound)
2909 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
2910 else
2911 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2912 if (is_type_ep)
2913 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
2914 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2915
2916 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2917 if (info->default_power2 > power_bound)
2918 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
2919 else
2920 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
2921 if (is_type_ep)
2922 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
2923 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2924
2925 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2926 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2927 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2928
2929 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
2930 rt2x00dev->default_ant.tx_chain_num >= 1);
2931 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2932 rt2x00dev->default_ant.tx_chain_num == 2);
2933 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2934
2935 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
2936 rt2x00dev->default_ant.rx_chain_num >= 1);
2937 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2938 rt2x00dev->default_ant.rx_chain_num == 2);
2939 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2940
2941 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2942 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
2943
2944 if (conf_is_ht40(conf))
2945 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
2946 else
2947 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
2948
2949 if (!is_11b) {
2950 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
2951 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
2952 }
2953
2954 /* TODO proper frequency adjustment */
2955 rt2800_adjust_freq_offset(rt2x00dev);
2956
2957 /* TODO merge with others */
2958 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2959 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2960 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2961
2962 /* BBP settings */
2963 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2964 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2965 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2966
2967 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
2968 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
2969 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
2970 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
2971
2972 /* GLRT band configuration */
2973 rt2800_bbp_write(rt2x00dev, 195, 128);
2974 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
2975 rt2800_bbp_write(rt2x00dev, 195, 129);
2976 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
2977 rt2800_bbp_write(rt2x00dev, 195, 130);
2978 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
2979 rt2800_bbp_write(rt2x00dev, 195, 131);
2980 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
2981 rt2800_bbp_write(rt2x00dev, 195, 133);
2982 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
2983 rt2800_bbp_write(rt2x00dev, 195, 124);
2984 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
2985}
2986
2987static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
2988 const unsigned int word,
2989 const u8 value)
2990{
2991 u8 chain, reg;
2992
2993 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
2994 rt2800_bbp_read(rt2x00dev, 27, ®);
2995 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain);
2996 rt2800_bbp_write(rt2x00dev, 27, reg);
2997
2998 rt2800_bbp_write(rt2x00dev, word, value);
2999 }
3000}
3001
3002static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3003{
3004 u8 cal;
3005
3006 /* TX0 IQ Gain */
3007 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3008 if (channel <= 14)
3009 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3010 else if (channel >= 36 && channel <= 64)
3011 cal = rt2x00_eeprom_byte(rt2x00dev,
3012 EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3013 else if (channel >= 100 && channel <= 138)
3014 cal = rt2x00_eeprom_byte(rt2x00dev,
3015 EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3016 else if (channel >= 140 && channel <= 165)
3017 cal = rt2x00_eeprom_byte(rt2x00dev,
3018 EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3019 else
3020 cal = 0;
3021 rt2800_bbp_write(rt2x00dev, 159, cal);
3022
3023 /* TX0 IQ Phase */
3024 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3025 if (channel <= 14)
3026 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3027 else if (channel >= 36 && channel <= 64)
3028 cal = rt2x00_eeprom_byte(rt2x00dev,
3029 EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3030 else if (channel >= 100 && channel <= 138)
3031 cal = rt2x00_eeprom_byte(rt2x00dev,
3032 EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3033 else if (channel >= 140 && channel <= 165)
3034 cal = rt2x00_eeprom_byte(rt2x00dev,
3035 EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3036 else
3037 cal = 0;
3038 rt2800_bbp_write(rt2x00dev, 159, cal);
3039
3040 /* TX1 IQ Gain */
3041 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3042 if (channel <= 14)
3043 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3044 else if (channel >= 36 && channel <= 64)
3045 cal = rt2x00_eeprom_byte(rt2x00dev,
3046 EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3047 else if (channel >= 100 && channel <= 138)
3048 cal = rt2x00_eeprom_byte(rt2x00dev,
3049 EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3050 else if (channel >= 140 && channel <= 165)
3051 cal = rt2x00_eeprom_byte(rt2x00dev,
3052 EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3053 else
3054 cal = 0;
3055 rt2800_bbp_write(rt2x00dev, 159, cal);
3056
3057 /* TX1 IQ Phase */
3058 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3059 if (channel <= 14)
3060 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3061 else if (channel >= 36 && channel <= 64)
3062 cal = rt2x00_eeprom_byte(rt2x00dev,
3063 EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3064 else if (channel >= 100 && channel <= 138)
3065 cal = rt2x00_eeprom_byte(rt2x00dev,
3066 EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3067 else if (channel >= 140 && channel <= 165)
3068 cal = rt2x00_eeprom_byte(rt2x00dev,
3069 EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3070 else
3071 cal = 0;
3072 rt2800_bbp_write(rt2x00dev, 159, cal);
3073
3074 /* FIXME: possible RX0, RX1 callibration ? */
3075
3076 /* RF IQ compensation control */
3077 rt2800_bbp_write(rt2x00dev, 158, 0x04);
3078 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3079 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3080
3081 /* RF IQ imbalance compensation control */
3082 rt2800_bbp_write(rt2x00dev, 158, 0x03);
3083 cal = rt2x00_eeprom_byte(rt2x00dev,
3084 EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3085 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3086}
3087
3088static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3089 unsigned int channel,
3090 char txpower)
3091{
3092 if (rt2x00_rt(rt2x00dev, RT3593))
3093 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3094
3095 if (channel <= 14)
3096 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3097
3098 if (rt2x00_rt(rt2x00dev, RT3593))
3099 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3100 MAX_A_TXPOWER_3593);
3101 else
3102 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3103}
3104
3105static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3106 struct ieee80211_conf *conf,
3107 struct rf_channel *rf,
3108 struct channel_info *info)
3109{
3110 u32 reg;
3111 unsigned int tx_pin;
3112 u8 bbp, rfcsr;
3113
3114 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3115 info->default_power1);
3116 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3117 info->default_power2);
3118 if (rt2x00dev->default_ant.tx_chain_num > 2)
3119 info->default_power3 =
3120 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3121 info->default_power3);
3122
3123 switch (rt2x00dev->chip.rf) {
3124 case RF2020:
3125 case RF3020:
3126 case RF3021:
3127 case RF3022:
3128 case RF3320:
3129 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3130 break;
3131 case RF3052:
3132 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3133 break;
3134 case RF3053:
3135 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3136 break;
3137 case RF3290:
3138 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3139 break;
3140 case RF3322:
3141 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3142 break;
3143 case RF3070:
3144 case RF5360:
3145 case RF5370:
3146 case RF5372:
3147 case RF5390:
3148 case RF5392:
3149 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3150 break;
3151 case RF5592:
3152 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3153 break;
3154 default:
3155 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3156 }
3157
3158 if (rt2x00_rf(rt2x00dev, RF3070) ||
3159 rt2x00_rf(rt2x00dev, RF3290) ||
3160 rt2x00_rf(rt2x00dev, RF3322) ||
3161 rt2x00_rf(rt2x00dev, RF5360) ||
3162 rt2x00_rf(rt2x00dev, RF5370) ||
3163 rt2x00_rf(rt2x00dev, RF5372) ||
3164 rt2x00_rf(rt2x00dev, RF5390) ||
3165 rt2x00_rf(rt2x00dev, RF5392)) {
3166 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3167 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
3168 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
3169 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3170
3171 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
3172 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3173 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3174 }
3175
3176 /*
3177 * Change BBP settings
3178 */
3179 if (rt2x00_rt(rt2x00dev, RT3352)) {
3180 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3181 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3182 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3183 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3184 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3185 if (rf->channel > 14) {
3186 /* Disable CCK Packet detection on 5GHz */
3187 rt2800_bbp_write(rt2x00dev, 70, 0x00);
3188 } else {
3189 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3190 }
3191
3192 if (conf_is_ht40(conf))
3193 rt2800_bbp_write(rt2x00dev, 105, 0x04);
3194 else
3195 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3196
3197 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3198 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3199 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3200 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3201 } else {
3202 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3203 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3204 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3205 rt2800_bbp_write(rt2x00dev, 86, 0);
3206 }
3207
3208 if (rf->channel <= 14) {
3209 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3210 !rt2x00_rt(rt2x00dev, RT5392)) {
3211 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3212 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3213 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3214 } else {
3215 if (rt2x00_rt(rt2x00dev, RT3593))
3216 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3217 else
3218 rt2800_bbp_write(rt2x00dev, 82, 0x84);
3219 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3220 }
3221 if (rt2x00_rt(rt2x00dev, RT3593))
3222 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3223 }
3224
3225 } else {
3226 if (rt2x00_rt(rt2x00dev, RT3572))
3227 rt2800_bbp_write(rt2x00dev, 82, 0x94);
3228 else if (rt2x00_rt(rt2x00dev, RT3593))
3229 rt2800_bbp_write(rt2x00dev, 82, 0x82);
3230 else
3231 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3232
3233 if (rt2x00_rt(rt2x00dev, RT3593))
3234 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3235
3236 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
3237 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3238 else
3239 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3240 }
3241
3242 rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®);
3243 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3244 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14);
3245 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14);
3246 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3247
3248 if (rt2x00_rt(rt2x00dev, RT3572))
3249 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3250
3251 tx_pin = 0;
3252
3253 switch (rt2x00dev->default_ant.tx_chain_num) {
3254 case 3:
3255 /* Turn on tertiary PAs */
3256 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3257 rf->channel > 14);
3258 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3259 rf->channel <= 14);
3260 /* fall-through */
3261 case 2:
3262 /* Turn on secondary PAs */
3263 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3264 rf->channel > 14);
3265 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3266 rf->channel <= 14);
3267 /* fall-through */
3268 case 1:
3269 /* Turn on primary PAs */
3270 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3271 rf->channel > 14);
3272 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
3273 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3274 else
3275 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3276 rf->channel <= 14);
3277 break;
3278 }
3279
3280 switch (rt2x00dev->default_ant.rx_chain_num) {
3281 case 3:
3282 /* Turn on tertiary LNAs */
3283 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3284 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3285 /* fall-through */
3286 case 2:
3287 /* Turn on secondary LNAs */
3288 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3289 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3290 /* fall-through */
3291 case 1:
3292 /* Turn on primary LNAs */
3293 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3294 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3295 break;
3296 }
3297
3298 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3299 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3300
3301 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3302
3303 if (rt2x00_rt(rt2x00dev, RT3572)) {
3304 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3305
3306 /* AGC init */
3307 if (rf->channel <= 14)
3308 reg = 0x1c + (2 * rt2x00dev->lna_gain);
3309 else
3310 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3311
3312 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3313 }
3314
3315 if (rt2x00_rt(rt2x00dev, RT3593)) {
3316 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®);
3317
3318 /* Band selection */
3319 if (rt2x00_is_usb(rt2x00dev) ||
3320 rt2x00_is_pcie(rt2x00dev)) {
3321 /* GPIO #8 controls all paths */
3322 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0);
3323 if (rf->channel <= 14)
3324 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1);
3325 else
3326 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0);
3327 }
3328
3329 /* LNA PE control. */
3330 if (rt2x00_is_usb(rt2x00dev)) {
3331 /* GPIO #4 controls PE0 and PE1,
3332 * GPIO #7 controls PE2
3333 */
3334 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0);
3335 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0);
3336
3337 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1);
3338 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1);
3339 } else if (rt2x00_is_pcie(rt2x00dev)) {
3340 /* GPIO #4 controls PE0, PE1 and PE2 */
3341 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0);
3342 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1);
3343 }
3344
3345 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3346
3347 /* AGC init */
3348 if (rf->channel <= 14)
3349 reg = 0x1c + 2 * rt2x00dev->lna_gain;
3350 else
3351 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3352
3353 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3354
3355 usleep_range(1000, 1500);
3356 }
3357
3358 if (rt2x00_rt(rt2x00dev, RT5592)) {
3359 rt2800_bbp_write(rt2x00dev, 195, 141);
3360 rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
3361
3362 /* AGC init */
3363 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
3364 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3365
3366 rt2800_iq_calibrate(rt2x00dev, rf->channel);
3367 }
3368
3369 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3370 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3371 rt2800_bbp_write(rt2x00dev, 4, bbp);
3372
3373 rt2800_bbp_read(rt2x00dev, 3, &bbp);
3374 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3375 rt2800_bbp_write(rt2x00dev, 3, bbp);
3376
3377 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3378 if (conf_is_ht40(conf)) {
3379 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3380 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3381 rt2800_bbp_write(rt2x00dev, 73, 0x16);
3382 } else {
3383 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3384 rt2800_bbp_write(rt2x00dev, 70, 0x08);
3385 rt2800_bbp_write(rt2x00dev, 73, 0x11);
3386 }
3387 }
3388
3389 msleep(1);
3390
3391 /*
3392 * Clear channel statistic counters
3393 */
3394 rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®);
3395 rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®);
3396 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®);
3397
3398 /*
3399 * Clear update flag
3400 */
3401 if (rt2x00_rt(rt2x00dev, RT3352)) {
3402 rt2800_bbp_read(rt2x00dev, 49, &bbp);
3403 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3404 rt2800_bbp_write(rt2x00dev, 49, bbp);
3405 }
3406}
3407
3408static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3409{
3410 u8 tssi_bounds[9];
3411 u8 current_tssi;
3412 u16 eeprom;
3413 u8 step;
3414 int i;
3415
3416 /*
3417 * First check if temperature compensation is supported.
3418 */
3419 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3420 if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3421 return 0;
3422
3423 /*
3424 * Read TSSI boundaries for temperature compensation from
3425 * the EEPROM.
3426 *
3427 * Array idx 0 1 2 3 4 5 6 7 8
3428 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
3429 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3430 */
3431 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
3432 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
3433 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3434 EEPROM_TSSI_BOUND_BG1_MINUS4);
3435 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3436 EEPROM_TSSI_BOUND_BG1_MINUS3);
3437
3438 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
3439 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3440 EEPROM_TSSI_BOUND_BG2_MINUS2);
3441 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3442 EEPROM_TSSI_BOUND_BG2_MINUS1);
3443
3444 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
3445 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3446 EEPROM_TSSI_BOUND_BG3_REF);
3447 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3448 EEPROM_TSSI_BOUND_BG3_PLUS1);
3449
3450 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
3451 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3452 EEPROM_TSSI_BOUND_BG4_PLUS2);
3453 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3454 EEPROM_TSSI_BOUND_BG4_PLUS3);
3455
3456 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
3457 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3458 EEPROM_TSSI_BOUND_BG5_PLUS4);
3459
3460 step = rt2x00_get_field16(eeprom,
3461 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3462 } else {
3463 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
3464 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3465 EEPROM_TSSI_BOUND_A1_MINUS4);
3466 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3467 EEPROM_TSSI_BOUND_A1_MINUS3);
3468
3469 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
3470 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3471 EEPROM_TSSI_BOUND_A2_MINUS2);
3472 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3473 EEPROM_TSSI_BOUND_A2_MINUS1);
3474
3475 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
3476 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3477 EEPROM_TSSI_BOUND_A3_REF);
3478 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3479 EEPROM_TSSI_BOUND_A3_PLUS1);
3480
3481 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
3482 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3483 EEPROM_TSSI_BOUND_A4_PLUS2);
3484 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3485 EEPROM_TSSI_BOUND_A4_PLUS3);
3486
3487 rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
3488 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3489 EEPROM_TSSI_BOUND_A5_PLUS4);
3490
3491 step = rt2x00_get_field16(eeprom,
3492 EEPROM_TSSI_BOUND_A5_AGC_STEP);
3493 }
3494
3495 /*
3496 * Check if temperature compensation is supported.
3497 */
3498 if (tssi_bounds[4] == 0xff || step == 0xff)
3499 return 0;
3500
3501 /*
3502 * Read current TSSI (BBP 49).
3503 */
3504 rt2800_bbp_read(rt2x00dev, 49, ¤t_tssi);
3505
3506 /*
3507 * Compare TSSI value (BBP49) with the compensation boundaries
3508 * from the EEPROM and increase or decrease tx power.
3509 */
3510 for (i = 0; i <= 3; i++) {
3511 if (current_tssi > tssi_bounds[i])
3512 break;
3513 }
3514
3515 if (i == 4) {
3516 for (i = 8; i >= 5; i--) {
3517 if (current_tssi < tssi_bounds[i])
3518 break;
3519 }
3520 }
3521
3522 return (i - 4) * step;
3523}
3524
3525static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
3526 enum ieee80211_band band)
3527{
3528 u16 eeprom;
3529 u8 comp_en;
3530 u8 comp_type;
3531 int comp_value = 0;
3532
3533 rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
3534
3535 /*
3536 * HT40 compensation not required.
3537 */
3538 if (eeprom == 0xffff ||
3539 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3540 return 0;
3541
3542 if (band == IEEE80211_BAND_2GHZ) {
3543 comp_en = rt2x00_get_field16(eeprom,
3544 EEPROM_TXPOWER_DELTA_ENABLE_2G);
3545 if (comp_en) {
3546 comp_type = rt2x00_get_field16(eeprom,
3547 EEPROM_TXPOWER_DELTA_TYPE_2G);
3548 comp_value = rt2x00_get_field16(eeprom,
3549 EEPROM_TXPOWER_DELTA_VALUE_2G);
3550 if (!comp_type)
3551 comp_value = -comp_value;
3552 }
3553 } else {
3554 comp_en = rt2x00_get_field16(eeprom,
3555 EEPROM_TXPOWER_DELTA_ENABLE_5G);
3556 if (comp_en) {
3557 comp_type = rt2x00_get_field16(eeprom,
3558 EEPROM_TXPOWER_DELTA_TYPE_5G);
3559 comp_value = rt2x00_get_field16(eeprom,
3560 EEPROM_TXPOWER_DELTA_VALUE_5G);
3561 if (!comp_type)
3562 comp_value = -comp_value;
3563 }
3564 }
3565
3566 return comp_value;
3567}
3568
3569static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
3570 int power_level, int max_power)
3571{
3572 int delta;
3573
3574 if (rt2x00_has_cap_power_limit(rt2x00dev))
3575 return 0;
3576
3577 /*
3578 * XXX: We don't know the maximum transmit power of our hardware since
3579 * the EEPROM doesn't expose it. We only know that we are calibrated
3580 * to 100% tx power.
3581 *
3582 * Hence, we assume the regulatory limit that cfg80211 calulated for
3583 * the current channel is our maximum and if we are requested to lower
3584 * the value we just reduce our tx power accordingly.
3585 */
3586 delta = power_level - max_power;
3587 return min(delta, 0);
3588}
3589
3590static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
3591 enum ieee80211_band band, int power_level,
3592 u8 txpower, int delta)
3593{
3594 u16 eeprom;
3595 u8 criterion;
3596 u8 eirp_txpower;
3597 u8 eirp_txpower_criterion;
3598 u8 reg_limit;
3599
3600 if (rt2x00_rt(rt2x00dev, RT3593))
3601 return min_t(u8, txpower, 0xc);
3602
3603 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
3604 /*
3605 * Check if eirp txpower exceed txpower_limit.
3606 * We use OFDM 6M as criterion and its eirp txpower
3607 * is stored at EEPROM_EIRP_MAX_TX_POWER.
3608 * .11b data rate need add additional 4dbm
3609 * when calculating eirp txpower.
3610 */
3611 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3612 1, &eeprom);
3613 criterion = rt2x00_get_field16(eeprom,
3614 EEPROM_TXPOWER_BYRATE_RATE0);
3615
3616 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
3617 &eeprom);
3618
3619 if (band == IEEE80211_BAND_2GHZ)
3620 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3621 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
3622 else
3623 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
3624 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
3625
3626 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
3627 (is_rate_b ? 4 : 0) + delta;
3628
3629 reg_limit = (eirp_txpower > power_level) ?
3630 (eirp_txpower - power_level) : 0;
3631 } else
3632 reg_limit = 0;
3633
3634 txpower = max(0, txpower + delta - reg_limit);
3635 return min_t(u8, txpower, 0xc);
3636}
3637
3638
3639enum {
3640 TX_PWR_CFG_0_IDX,
3641 TX_PWR_CFG_1_IDX,
3642 TX_PWR_CFG_2_IDX,
3643 TX_PWR_CFG_3_IDX,
3644 TX_PWR_CFG_4_IDX,
3645 TX_PWR_CFG_5_IDX,
3646 TX_PWR_CFG_6_IDX,
3647 TX_PWR_CFG_7_IDX,
3648 TX_PWR_CFG_8_IDX,
3649 TX_PWR_CFG_9_IDX,
3650 TX_PWR_CFG_0_EXT_IDX,
3651 TX_PWR_CFG_1_EXT_IDX,
3652 TX_PWR_CFG_2_EXT_IDX,
3653 TX_PWR_CFG_3_EXT_IDX,
3654 TX_PWR_CFG_4_EXT_IDX,
3655 TX_PWR_CFG_IDX_COUNT,
3656};
3657
3658static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
3659 struct ieee80211_channel *chan,
3660 int power_level)
3661{
3662 u8 txpower;
3663 u16 eeprom;
3664 u32 regs[TX_PWR_CFG_IDX_COUNT];
3665 unsigned int offset;
3666 enum ieee80211_band band = chan->band;
3667 int delta;
3668 int i;
3669
3670 memset(regs, '\0', sizeof(regs));
3671
3672 /* TODO: adapt TX power reduction from the rt28xx code */
3673
3674 /* calculate temperature compensation delta */
3675 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
3676
3677 if (band == IEEE80211_BAND_5GHZ)
3678 offset = 16;
3679 else
3680 offset = 0;
3681
3682 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
3683 offset += 8;
3684
3685 /* read the next four txpower values */
3686 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3687 offset, &eeprom);
3688
3689 /* CCK 1MBS,2MBS */
3690 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3691 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3692 txpower, delta);
3693 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
3694 TX_PWR_CFG_0_CCK1_CH0, txpower);
3695 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
3696 TX_PWR_CFG_0_CCK1_CH1, txpower);
3697 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
3698 TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
3699
3700 /* CCK 5.5MBS,11MBS */
3701 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3702 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
3703 txpower, delta);
3704 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
3705 TX_PWR_CFG_0_CCK5_CH0, txpower);
3706 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
3707 TX_PWR_CFG_0_CCK5_CH1, txpower);
3708 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
3709 TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
3710
3711 /* OFDM 6MBS,9MBS */
3712 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3713 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3714 txpower, delta);
3715 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
3716 TX_PWR_CFG_0_OFDM6_CH0, txpower);
3717 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
3718 TX_PWR_CFG_0_OFDM6_CH1, txpower);
3719 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
3720 TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
3721
3722 /* OFDM 12MBS,18MBS */
3723 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3724 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3725 txpower, delta);
3726 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
3727 TX_PWR_CFG_0_OFDM12_CH0, txpower);
3728 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX],
3729 TX_PWR_CFG_0_OFDM12_CH1, txpower);
3730 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX],
3731 TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
3732
3733 /* read the next four txpower values */
3734 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3735 offset + 1, &eeprom);
3736
3737 /* OFDM 24MBS,36MBS */
3738 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3739 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3740 txpower, delta);
3741 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
3742 TX_PWR_CFG_1_OFDM24_CH0, txpower);
3743 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
3744 TX_PWR_CFG_1_OFDM24_CH1, txpower);
3745 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
3746 TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
3747
3748 /* OFDM 48MBS */
3749 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3750 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3751 txpower, delta);
3752 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
3753 TX_PWR_CFG_1_OFDM48_CH0, txpower);
3754 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
3755 TX_PWR_CFG_1_OFDM48_CH1, txpower);
3756 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
3757 TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
3758
3759 /* OFDM 54MBS */
3760 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3761 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3762 txpower, delta);
3763 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
3764 TX_PWR_CFG_7_OFDM54_CH0, txpower);
3765 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
3766 TX_PWR_CFG_7_OFDM54_CH1, txpower);
3767 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
3768 TX_PWR_CFG_7_OFDM54_CH2, txpower);
3769
3770 /* read the next four txpower values */
3771 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3772 offset + 2, &eeprom);
3773
3774 /* MCS 0,1 */
3775 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3776 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3777 txpower, delta);
3778 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
3779 TX_PWR_CFG_1_MCS0_CH0, txpower);
3780 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
3781 TX_PWR_CFG_1_MCS0_CH1, txpower);
3782 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
3783 TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
3784
3785 /* MCS 2,3 */
3786 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3787 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3788 txpower, delta);
3789 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
3790 TX_PWR_CFG_1_MCS2_CH0, txpower);
3791 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX],
3792 TX_PWR_CFG_1_MCS2_CH1, txpower);
3793 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX],
3794 TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
3795
3796 /* MCS 4,5 */
3797 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3798 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3799 txpower, delta);
3800 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
3801 TX_PWR_CFG_2_MCS4_CH0, txpower);
3802 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
3803 TX_PWR_CFG_2_MCS4_CH1, txpower);
3804 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
3805 TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
3806
3807 /* MCS 6 */
3808 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3809 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3810 txpower, delta);
3811 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
3812 TX_PWR_CFG_2_MCS6_CH0, txpower);
3813 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
3814 TX_PWR_CFG_2_MCS6_CH1, txpower);
3815 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
3816 TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
3817
3818 /* read the next four txpower values */
3819 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3820 offset + 3, &eeprom);
3821
3822 /* MCS 7 */
3823 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3824 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3825 txpower, delta);
3826 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
3827 TX_PWR_CFG_7_MCS7_CH0, txpower);
3828 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
3829 TX_PWR_CFG_7_MCS7_CH1, txpower);
3830 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX],
3831 TX_PWR_CFG_7_MCS7_CH2, txpower);
3832
3833 /* MCS 8,9 */
3834 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3835 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3836 txpower, delta);
3837 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
3838 TX_PWR_CFG_2_MCS8_CH0, txpower);
3839 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
3840 TX_PWR_CFG_2_MCS8_CH1, txpower);
3841 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
3842 TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
3843
3844 /* MCS 10,11 */
3845 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3846 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3847 txpower, delta);
3848 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
3849 TX_PWR_CFG_2_MCS10_CH0, txpower);
3850 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX],
3851 TX_PWR_CFG_2_MCS10_CH1, txpower);
3852 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX],
3853 TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
3854
3855 /* MCS 12,13 */
3856 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3857 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3858 txpower, delta);
3859 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
3860 TX_PWR_CFG_3_MCS12_CH0, txpower);
3861 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
3862 TX_PWR_CFG_3_MCS12_CH1, txpower);
3863 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
3864 TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
3865
3866 /* read the next four txpower values */
3867 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3868 offset + 4, &eeprom);
3869
3870 /* MCS 14 */
3871 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3872 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3873 txpower, delta);
3874 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
3875 TX_PWR_CFG_3_MCS14_CH0, txpower);
3876 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
3877 TX_PWR_CFG_3_MCS14_CH1, txpower);
3878 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
3879 TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
3880
3881 /* MCS 15 */
3882 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3883 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3884 txpower, delta);
3885 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
3886 TX_PWR_CFG_8_MCS15_CH0, txpower);
3887 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
3888 TX_PWR_CFG_8_MCS15_CH1, txpower);
3889 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
3890 TX_PWR_CFG_8_MCS15_CH2, txpower);
3891
3892 /* MCS 16,17 */
3893 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3894 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3895 txpower, delta);
3896 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
3897 TX_PWR_CFG_5_MCS16_CH0, txpower);
3898 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
3899 TX_PWR_CFG_5_MCS16_CH1, txpower);
3900 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
3901 TX_PWR_CFG_5_MCS16_CH2, txpower);
3902
3903 /* MCS 18,19 */
3904 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3905 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3906 txpower, delta);
3907 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
3908 TX_PWR_CFG_5_MCS18_CH0, txpower);
3909 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
3910 TX_PWR_CFG_5_MCS18_CH1, txpower);
3911 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX],
3912 TX_PWR_CFG_5_MCS18_CH2, txpower);
3913
3914 /* read the next four txpower values */
3915 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3916 offset + 5, &eeprom);
3917
3918 /* MCS 20,21 */
3919 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3920 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3921 txpower, delta);
3922 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
3923 TX_PWR_CFG_6_MCS20_CH0, txpower);
3924 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
3925 TX_PWR_CFG_6_MCS20_CH1, txpower);
3926 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
3927 TX_PWR_CFG_6_MCS20_CH2, txpower);
3928
3929 /* MCS 22 */
3930 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3931 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3932 txpower, delta);
3933 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
3934 TX_PWR_CFG_6_MCS22_CH0, txpower);
3935 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
3936 TX_PWR_CFG_6_MCS22_CH1, txpower);
3937 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX],
3938 TX_PWR_CFG_6_MCS22_CH2, txpower);
3939
3940 /* MCS 23 */
3941 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3942 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3943 txpower, delta);
3944 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
3945 TX_PWR_CFG_8_MCS23_CH0, txpower);
3946 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
3947 TX_PWR_CFG_8_MCS23_CH1, txpower);
3948 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX],
3949 TX_PWR_CFG_8_MCS23_CH2, txpower);
3950
3951 /* read the next four txpower values */
3952 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3953 offset + 6, &eeprom);
3954
3955 /* STBC, MCS 0,1 */
3956 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
3957 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3958 txpower, delta);
3959 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
3960 TX_PWR_CFG_3_STBC0_CH0, txpower);
3961 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
3962 TX_PWR_CFG_3_STBC0_CH1, txpower);
3963 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
3964 TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
3965
3966 /* STBC, MCS 2,3 */
3967 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
3968 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3969 txpower, delta);
3970 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
3971 TX_PWR_CFG_3_STBC2_CH0, txpower);
3972 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX],
3973 TX_PWR_CFG_3_STBC2_CH1, txpower);
3974 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX],
3975 TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
3976
3977 /* STBC, MCS 4,5 */
3978 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
3979 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3980 txpower, delta);
3981 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
3982 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
3983 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
3984 txpower);
3985
3986 /* STBC, MCS 6 */
3987 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
3988 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
3989 txpower, delta);
3990 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
3991 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
3992 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
3993 txpower);
3994
3995 /* read the next four txpower values */
3996 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
3997 offset + 7, &eeprom);
3998
3999 /* STBC, MCS 7 */
4000 txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4001 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4002 txpower, delta);
4003 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX],
4004 TX_PWR_CFG_9_STBC7_CH0, txpower);
4005 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX],
4006 TX_PWR_CFG_9_STBC7_CH1, txpower);
4007 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX],
4008 TX_PWR_CFG_9_STBC7_CH2, txpower);
4009
4010 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4011 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4012 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4013 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4014 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4015 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4016 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4017 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4018 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4019 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4020
4021 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4022 regs[TX_PWR_CFG_0_EXT_IDX]);
4023 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4024 regs[TX_PWR_CFG_1_EXT_IDX]);
4025 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4026 regs[TX_PWR_CFG_2_EXT_IDX]);
4027 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4028 regs[TX_PWR_CFG_3_EXT_IDX]);
4029 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4030 regs[TX_PWR_CFG_4_EXT_IDX]);
4031
4032 for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4033 rt2x00_dbg(rt2x00dev,
4034 "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4035 (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
4036 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4037 '4' : '2',
4038 (i > TX_PWR_CFG_9_IDX) ?
4039 (i - TX_PWR_CFG_9_IDX - 1) : i,
4040 (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4041 (unsigned long) regs[i]);
4042}
4043
4044/*
4045 * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4046 * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4047 * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4048 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4049 * Reference per rate transmit power values are located in the EEPROM at
4050 * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4051 * current conditions (i.e. band, bandwidth, temperature, user settings).
4052 */
4053static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4054 struct ieee80211_channel *chan,
4055 int power_level)
4056{
4057 u8 txpower, r1;
4058 u16 eeprom;
4059 u32 reg, offset;
4060 int i, is_rate_b, delta, power_ctrl;
4061 enum ieee80211_band band = chan->band;
4062
4063 /*
4064 * Calculate HT40 compensation. For 40MHz we need to add or subtract
4065 * value read from EEPROM (different for 2GHz and for 5GHz).
4066 */
4067 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4068
4069 /*
4070 * Calculate temperature compensation. Depends on measurement of current
4071 * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4072 * to temperature or maybe other factors) is smaller or bigger than
4073 * expected. We adjust it, based on TSSI reference and boundaries values
4074 * provided in EEPROM.
4075 */
4076 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4077
4078 /*
4079 * Decrease power according to user settings, on devices with unknown
4080 * maximum tx power. For other devices we take user power_level into
4081 * consideration on rt2800_compensate_txpower().
4082 */
4083 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4084 chan->max_power);
4085
4086 /*
4087 * BBP_R1 controls TX power for all rates, it allow to set the following
4088 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4089 *
4090 * TODO: we do not use +6 dBm option to do not increase power beyond
4091 * regulatory limit, however this could be utilized for devices with
4092 * CAPABILITY_POWER_LIMIT.
4093 *
4094 * TODO: add different temperature compensation code for RT3290 & RT5390
4095 * to allow to use BBP_R1 for those chips.
4096 */
4097 if (!rt2x00_rt(rt2x00dev, RT3290) &&
4098 !rt2x00_rt(rt2x00dev, RT5390)) {
4099 rt2800_bbp_read(rt2x00dev, 1, &r1);
4100 if (delta <= -12) {
4101 power_ctrl = 2;
4102 delta += 12;
4103 } else if (delta <= -6) {
4104 power_ctrl = 1;
4105 delta += 6;
4106 } else {
4107 power_ctrl = 0;
4108 }
4109 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4110 rt2800_bbp_write(rt2x00dev, 1, r1);
4111 }
4112
4113 offset = TX_PWR_CFG_0;
4114
4115 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4116 /* just to be safe */
4117 if (offset > TX_PWR_CFG_4)
4118 break;
4119
4120 rt2800_register_read(rt2x00dev, offset, ®);
4121
4122 /* read the next four txpower values */
4123 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4124 i, &eeprom);
4125
4126 is_rate_b = i ? 0 : 1;
4127 /*
4128 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4129 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4130 * TX_PWR_CFG_4: unknown
4131 */
4132 txpower = rt2x00_get_field16(eeprom,
4133 EEPROM_TXPOWER_BYRATE_RATE0);
4134 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4135 power_level, txpower, delta);
4136 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower);
4137
4138 /*
4139 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4140 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4141 * TX_PWR_CFG_4: unknown
4142 */
4143 txpower = rt2x00_get_field16(eeprom,
4144 EEPROM_TXPOWER_BYRATE_RATE1);
4145 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4146 power_level, txpower, delta);
4147 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower);
4148
4149 /*
4150 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4151 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
4152 * TX_PWR_CFG_4: unknown
4153 */
4154 txpower = rt2x00_get_field16(eeprom,
4155 EEPROM_TXPOWER_BYRATE_RATE2);
4156 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4157 power_level, txpower, delta);
4158 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower);
4159
4160 /*
4161 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4162 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
4163 * TX_PWR_CFG_4: unknown
4164 */
4165 txpower = rt2x00_get_field16(eeprom,
4166 EEPROM_TXPOWER_BYRATE_RATE3);
4167 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4168 power_level, txpower, delta);
4169 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower);
4170
4171 /* read the next four txpower values */
4172 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4173 i + 1, &eeprom);
4174
4175 is_rate_b = 0;
4176 /*
4177 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4178 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4179 * TX_PWR_CFG_4: unknown
4180 */
4181 txpower = rt2x00_get_field16(eeprom,
4182 EEPROM_TXPOWER_BYRATE_RATE0);
4183 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4184 power_level, txpower, delta);
4185 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower);
4186
4187 /*
4188 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4189 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4190 * TX_PWR_CFG_4: unknown
4191 */
4192 txpower = rt2x00_get_field16(eeprom,
4193 EEPROM_TXPOWER_BYRATE_RATE1);
4194 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4195 power_level, txpower, delta);
4196 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower);
4197
4198 /*
4199 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4200 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4201 * TX_PWR_CFG_4: unknown
4202 */
4203 txpower = rt2x00_get_field16(eeprom,
4204 EEPROM_TXPOWER_BYRATE_RATE2);
4205 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4206 power_level, txpower, delta);
4207 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower);
4208
4209 /*
4210 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4211 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4212 * TX_PWR_CFG_4: unknown
4213 */
4214 txpower = rt2x00_get_field16(eeprom,
4215 EEPROM_TXPOWER_BYRATE_RATE3);
4216 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4217 power_level, txpower, delta);
4218 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower);
4219
4220 rt2800_register_write(rt2x00dev, offset, reg);
4221
4222 /* next TX_PWR_CFG register */
4223 offset += 4;
4224 }
4225}
4226
4227static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4228 struct ieee80211_channel *chan,
4229 int power_level)
4230{
4231 if (rt2x00_rt(rt2x00dev, RT3593))
4232 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4233 else
4234 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4235}
4236
4237void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4238{
4239 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4240 rt2x00dev->tx_power);
4241}
4242EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4243
4244void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4245{
4246 u32 tx_pin;
4247 u8 rfcsr;
4248
4249 /*
4250 * A voltage-controlled oscillator(VCO) is an electronic oscillator
4251 * designed to be controlled in oscillation frequency by a voltage
4252 * input. Maybe the temperature will affect the frequency of
4253 * oscillation to be shifted. The VCO calibration will be called
4254 * periodically to adjust the frequency to be precision.
4255 */
4256
4257 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4258 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4259 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4260
4261 switch (rt2x00dev->chip.rf) {
4262 case RF2020:
4263 case RF3020:
4264 case RF3021:
4265 case RF3022:
4266 case RF3320:
4267 case RF3052:
4268 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
4269 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4270 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4271 break;
4272 case RF3053:
4273 case RF3070:
4274 case RF3290:
4275 case RF5360:
4276 case RF5370:
4277 case RF5372:
4278 case RF5390:
4279 case RF5392:
4280 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
4281 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4282 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4283 break;
4284 default:
4285 return;
4286 }
4287
4288 mdelay(1);
4289
4290 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
4291 if (rt2x00dev->rf_channel <= 14) {
4292 switch (rt2x00dev->default_ant.tx_chain_num) {
4293 case 3:
4294 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4295 /* fall through */
4296 case 2:
4297 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4298 /* fall through */
4299 case 1:
4300 default:
4301 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4302 break;
4303 }
4304 } else {
4305 switch (rt2x00dev->default_ant.tx_chain_num) {
4306 case 3:
4307 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4308 /* fall through */
4309 case 2:
4310 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4311 /* fall through */
4312 case 1:
4313 default:
4314 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4315 break;
4316 }
4317 }
4318 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4319
4320}
4321EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4322
4323static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4324 struct rt2x00lib_conf *libconf)
4325{
4326 u32 reg;
4327
4328 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®);
4329 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT,
4330 libconf->conf->short_frame_max_tx_count);
4331 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT,
4332 libconf->conf->long_frame_max_tx_count);
4333 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4334}
4335
4336static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
4337 struct rt2x00lib_conf *libconf)
4338{
4339 enum dev_state state =
4340 (libconf->conf->flags & IEEE80211_CONF_PS) ?
4341 STATE_SLEEP : STATE_AWAKE;
4342 u32 reg;
4343
4344 if (state == STATE_SLEEP) {
4345 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
4346
4347 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
4348 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
4349 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
4350 libconf->conf->listen_interval - 1);
4351 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1);
4352 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4353
4354 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4355 } else {
4356 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
4357 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
4358 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
4359 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0);
4360 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
4361
4362 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
4363 }
4364}
4365
4366void rt2800_config(struct rt2x00_dev *rt2x00dev,
4367 struct rt2x00lib_conf *libconf,
4368 const unsigned int flags)
4369{
4370 /* Always recalculate LNA gain before changing configuration */
4371 rt2800_config_lna_gain(rt2x00dev, libconf);
4372
4373 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
4374 rt2800_config_channel(rt2x00dev, libconf->conf,
4375 &libconf->rf, &libconf->channel);
4376 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4377 libconf->conf->power_level);
4378 }
4379 if (flags & IEEE80211_CONF_CHANGE_POWER)
4380 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
4381 libconf->conf->power_level);
4382 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
4383 rt2800_config_retry_limit(rt2x00dev, libconf);
4384 if (flags & IEEE80211_CONF_CHANGE_PS)
4385 rt2800_config_ps(rt2x00dev, libconf);
4386}
4387EXPORT_SYMBOL_GPL(rt2800_config);
4388
4389/*
4390 * Link tuning
4391 */
4392void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4393{
4394 u32 reg;
4395
4396 /*
4397 * Update FCS error count from register.
4398 */
4399 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®);
4400 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
4401}
4402EXPORT_SYMBOL_GPL(rt2800_link_stats);
4403
4404static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
4405{
4406 u8 vgc;
4407
4408 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
4409 if (rt2x00_rt(rt2x00dev, RT3070) ||
4410 rt2x00_rt(rt2x00dev, RT3071) ||
4411 rt2x00_rt(rt2x00dev, RT3090) ||
4412 rt2x00_rt(rt2x00dev, RT3290) ||
4413 rt2x00_rt(rt2x00dev, RT3390) ||
4414 rt2x00_rt(rt2x00dev, RT3572) ||
4415 rt2x00_rt(rt2x00dev, RT3593) ||
4416 rt2x00_rt(rt2x00dev, RT5390) ||
4417 rt2x00_rt(rt2x00dev, RT5392) ||
4418 rt2x00_rt(rt2x00dev, RT5592))
4419 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
4420 else
4421 vgc = 0x2e + rt2x00dev->lna_gain;
4422 } else { /* 5GHZ band */
4423 if (rt2x00_rt(rt2x00dev, RT3593))
4424 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
4425 else if (rt2x00_rt(rt2x00dev, RT5592))
4426 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
4427 else {
4428 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4429 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
4430 else
4431 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
4432 }
4433 }
4434
4435 return vgc;
4436}
4437
4438static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
4439 struct link_qual *qual, u8 vgc_level)
4440{
4441 if (qual->vgc_level != vgc_level) {
4442 if (rt2x00_rt(rt2x00dev, RT3572) ||
4443 rt2x00_rt(rt2x00dev, RT3593)) {
4444 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
4445 vgc_level);
4446 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
4447 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
4448 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
4449 } else {
4450 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
4451 }
4452
4453 qual->vgc_level = vgc_level;
4454 qual->vgc_level_reg = vgc_level;
4455 }
4456}
4457
4458void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
4459{
4460 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
4461}
4462EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
4463
4464void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
4465 const u32 count)
4466{
4467 u8 vgc;
4468
4469 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
4470 return;
4471
4472 /* When RSSI is better than a certain threshold, increase VGC
4473 * with a chip specific value in order to improve the balance
4474 * between sensibility and noise isolation.
4475 */
4476
4477 vgc = rt2800_get_default_vgc(rt2x00dev);
4478
4479 switch (rt2x00dev->chip.rt) {
4480 case RT3572:
4481 case RT3593:
4482 if (qual->rssi > -65) {
4483 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
4484 vgc += 0x20;
4485 else
4486 vgc += 0x10;
4487 }
4488 break;
4489
4490 case RT5592:
4491 if (qual->rssi > -65)
4492 vgc += 0x20;
4493 break;
4494
4495 default:
4496 if (qual->rssi > -80)
4497 vgc += 0x10;
4498 break;
4499 }
4500
4501 rt2800_set_vgc(rt2x00dev, qual, vgc);
4502}
4503EXPORT_SYMBOL_GPL(rt2800_link_tuner);
4504
4505/*
4506 * Initialization functions.
4507 */
4508static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
4509{
4510 u32 reg;
4511 u16 eeprom;
4512 unsigned int i;
4513 int ret;
4514
4515 rt2800_disable_wpdma(rt2x00dev);
4516
4517 ret = rt2800_drv_init_registers(rt2x00dev);
4518 if (ret)
4519 return ret;
4520
4521 rt2800_register_read(rt2x00dev, BCN_OFFSET0, ®);
4522 rt2x00_set_field32(®, BCN_OFFSET0_BCN0,
4523 rt2800_get_beacon_offset(rt2x00dev, 0));
4524 rt2x00_set_field32(®, BCN_OFFSET0_BCN1,
4525 rt2800_get_beacon_offset(rt2x00dev, 1));
4526 rt2x00_set_field32(®, BCN_OFFSET0_BCN2,
4527 rt2800_get_beacon_offset(rt2x00dev, 2));
4528 rt2x00_set_field32(®, BCN_OFFSET0_BCN3,
4529 rt2800_get_beacon_offset(rt2x00dev, 3));
4530 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
4531
4532 rt2800_register_read(rt2x00dev, BCN_OFFSET1, ®);
4533 rt2x00_set_field32(®, BCN_OFFSET1_BCN4,
4534 rt2800_get_beacon_offset(rt2x00dev, 4));
4535 rt2x00_set_field32(®, BCN_OFFSET1_BCN5,
4536 rt2800_get_beacon_offset(rt2x00dev, 5));
4537 rt2x00_set_field32(®, BCN_OFFSET1_BCN6,
4538 rt2800_get_beacon_offset(rt2x00dev, 6));
4539 rt2x00_set_field32(®, BCN_OFFSET1_BCN7,
4540 rt2800_get_beacon_offset(rt2x00dev, 7));
4541 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
4542
4543 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
4544 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
4545
4546 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
4547
4548 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
4549 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
4550 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
4551 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0);
4552 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
4553 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
4554 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
4555 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
4556
4557 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
4558
4559 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®);
4560 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9);
4561 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
4562 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
4563
4564 if (rt2x00_rt(rt2x00dev, RT3290)) {
4565 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®);
4566 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
4567 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1);
4568 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
4569 }
4570
4571 rt2800_register_read(rt2x00dev, CMB_CTRL, ®);
4572 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
4573 rt2x00_set_field32(®, LDO0_EN, 1);
4574 rt2x00_set_field32(®, LDO_BGSEL, 3);
4575 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
4576 }
4577
4578 rt2800_register_read(rt2x00dev, OSC_CTRL, ®);
4579 rt2x00_set_field32(®, OSC_ROSC_EN, 1);
4580 rt2x00_set_field32(®, OSC_CAL_REQ, 1);
4581 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27);
4582 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
4583
4584 rt2800_register_read(rt2x00dev, COEX_CFG0, ®);
4585 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e);
4586 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
4587
4588 rt2800_register_read(rt2x00dev, COEX_CFG2, ®);
4589 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00);
4590 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17);
4591 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93);
4592 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f);
4593 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
4594
4595 rt2800_register_read(rt2x00dev, PLL_CTRL, ®);
4596 rt2x00_set_field32(®, PLL_CONTROL, 1);
4597 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
4598 }
4599
4600 if (rt2x00_rt(rt2x00dev, RT3071) ||
4601 rt2x00_rt(rt2x00dev, RT3090) ||
4602 rt2x00_rt(rt2x00dev, RT3290) ||
4603 rt2x00_rt(rt2x00dev, RT3390)) {
4604
4605 if (rt2x00_rt(rt2x00dev, RT3290))
4606 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4607 0x00000404);
4608 else
4609 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
4610 0x00000400);
4611
4612 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4613 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4614 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4615 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4616 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4617 &eeprom);
4618 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4619 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4620 0x0000002c);
4621 else
4622 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4623 0x0000000f);
4624 } else {
4625 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4626 }
4627 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
4628 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4629
4630 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4631 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4632 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
4633 } else {
4634 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4635 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4636 }
4637 } else if (rt2800_is_305x_soc(rt2x00dev)) {
4638 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4639 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4640 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
4641 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4642 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4643 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4644 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4645 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4646 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
4647 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4648 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4649 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
4650 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
4651 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
4652 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
4653 &eeprom);
4654 if (rt2x00_get_field16(eeprom,
4655 EEPROM_NIC_CONF1_DAC_TEST))
4656 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4657 0x0000001f);
4658 else
4659 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4660 0x0000000f);
4661 } else {
4662 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
4663 0x00000000);
4664 }
4665 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
4666 rt2x00_rt(rt2x00dev, RT5392) ||
4667 rt2x00_rt(rt2x00dev, RT5592)) {
4668 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
4669 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4670 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
4671 } else {
4672 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
4673 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
4674 }
4675
4676 rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®);
4677 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
4678 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0);
4679 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
4680 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0);
4681 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0);
4682 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1);
4683 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0);
4684 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0);
4685 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
4686
4687 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®);
4688 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
4689 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
4690 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
4691 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
4692
4693 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®);
4694 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
4695 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
4696 rt2x00_rt(rt2x00dev, RT2883) ||
4697 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
4698 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2);
4699 else
4700 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1);
4701 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0);
4702 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0);
4703 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
4704
4705 rt2800_register_read(rt2x00dev, LED_CFG, ®);
4706 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70);
4707 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30);
4708 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3);
4709 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3);
4710 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3);
4711 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3);
4712 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1);
4713 rt2800_register_write(rt2x00dev, LED_CFG, reg);
4714
4715 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
4716
4717 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®);
4718 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
4719 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
4720 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000);
4721 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
4722 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0);
4723 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
4724 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4725
4726 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
4727 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1);
4728 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
4729 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0);
4730 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0);
4731 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1);
4732 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
4733 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
4734 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
4735
4736 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
4737 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3);
4738 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0);
4739 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
4740 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4741 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4742 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4743 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4744 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4745 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4746 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1);
4747 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4748
4749 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
4750 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3);
4751 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0);
4752 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
4753 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4754 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4755 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4756 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4757 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4758 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4759 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1);
4760 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4761
4762 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
4763 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
4764 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0);
4765 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4766 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4767 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4768 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4769 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4770 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4771 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4772 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0);
4773 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4774
4775 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
4776 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
4777 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0);
4778 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4779 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4780 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4781 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4782 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4783 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4784 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4785 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0);
4786 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4787
4788 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
4789 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
4790 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0);
4791 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
4792 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4793 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4794 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4795 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
4796 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4797 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
4798 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0);
4799 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4800
4801 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
4802 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
4803 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0);
4804 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
4805 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
4806 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
4807 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
4808 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
4809 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
4810 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
4811 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0);
4812 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4813
4814 if (rt2x00_is_usb(rt2x00dev)) {
4815 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
4816
4817 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
4818 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
4819 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
4820 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
4821 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
4822 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
4823 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
4824 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
4825 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
4826 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
4827 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4828 }
4829
4830 /*
4831 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
4832 * although it is reserved.
4833 */
4834 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®);
4835 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
4836 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
4837 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
4838 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
4839 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
4840 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
4841 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
4842 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
4843 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
4844 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0);
4845 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
4846
4847 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
4848 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
4849
4850 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
4851 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
4852 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES,
4853 IEEE80211_MAX_RTS_THRESHOLD);
4854 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0);
4855 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4856
4857 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
4858
4859 /*
4860 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
4861 * time should be set to 16. However, the original Ralink driver uses
4862 * 16 for both and indeed using a value of 10 for CCK SIFS results in
4863 * connection problems with 11g + CTS protection. Hence, use the same
4864 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
4865 */
4866 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®);
4867 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
4868 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
4869 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
4870 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314);
4871 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
4872 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
4873
4874 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
4875
4876 /*
4877 * ASIC will keep garbage value after boot, clear encryption keys.
4878 */
4879 for (i = 0; i < 4; i++)
4880 rt2800_register_write(rt2x00dev,
4881 SHARED_KEY_MODE_ENTRY(i), 0);
4882
4883 for (i = 0; i < 256; i++) {
4884 rt2800_config_wcid(rt2x00dev, NULL, i);
4885 rt2800_delete_wcid_attr(rt2x00dev, i);
4886 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
4887 }
4888
4889 /*
4890 * Clear all beacons
4891 */
4892 for (i = 0; i < 8; i++)
4893 rt2800_clear_beacon_register(rt2x00dev, i);
4894
4895 if (rt2x00_is_usb(rt2x00dev)) {
4896 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®);
4897 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30);
4898 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4899 } else if (rt2x00_is_pcie(rt2x00dev)) {
4900 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®);
4901 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125);
4902 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
4903 }
4904
4905 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®);
4906 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0);
4907 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0);
4908 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1);
4909 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2);
4910 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3);
4911 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4);
4912 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5);
4913 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6);
4914 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
4915
4916 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®);
4917 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8);
4918 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8);
4919 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9);
4920 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10);
4921 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11);
4922 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12);
4923 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13);
4924 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14);
4925 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
4926
4927 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®);
4928 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8);
4929 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8);
4930 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9);
4931 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10);
4932 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11);
4933 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12);
4934 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13);
4935 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14);
4936 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
4937
4938 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®);
4939 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0);
4940 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0);
4941 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1);
4942 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2);
4943 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
4944
4945 /*
4946 * Do not force the BA window size, we use the TXWI to set it
4947 */
4948 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®);
4949 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
4950 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
4951 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
4952
4953 /*
4954 * We must clear the error counters.
4955 * These registers are cleared on read,
4956 * so we may pass a useless variable to store the value.
4957 */
4958 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®);
4959 rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®);
4960 rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®);
4961 rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®);
4962 rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®);
4963 rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®);
4964
4965 /*
4966 * Setup leadtime for pre tbtt interrupt to 6ms
4967 */
4968 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®);
4969 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
4970 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
4971
4972 /*
4973 * Set up channel statistics timer
4974 */
4975 rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®);
4976 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1);
4977 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1);
4978 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1);
4979 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1);
4980 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1);
4981 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
4982
4983 return 0;
4984}
4985
4986static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
4987{
4988 unsigned int i;
4989 u32 reg;
4990
4991 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
4992 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®);
4993 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
4994 return 0;
4995
4996 udelay(REGISTER_BUSY_DELAY);
4997 }
4998
4999 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
5000 return -EACCES;
5001}
5002
5003static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5004{
5005 unsigned int i;
5006 u8 value;
5007
5008 /*
5009 * BBP was enabled after firmware was loaded,
5010 * but we need to reactivate it now.
5011 */
5012 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5013 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5014 msleep(1);
5015
5016 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5017 rt2800_bbp_read(rt2x00dev, 0, &value);
5018 if ((value != 0xff) && (value != 0x00))
5019 return 0;
5020 udelay(REGISTER_BUSY_DELAY);
5021 }
5022
5023 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
5024 return -EACCES;
5025}
5026
5027static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5028{
5029 u8 value;
5030
5031 rt2800_bbp_read(rt2x00dev, 4, &value);
5032 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5033 rt2800_bbp_write(rt2x00dev, 4, value);
5034}
5035
5036static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5037{
5038 rt2800_bbp_write(rt2x00dev, 142, 1);
5039 rt2800_bbp_write(rt2x00dev, 143, 57);
5040}
5041
5042static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5043{
5044 const u8 glrt_table[] = {
5045 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5046 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5047 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5048 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5049 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5050 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5051 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5052 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5053 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
5054 };
5055 int i;
5056
5057 for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5058 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5059 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5060 }
5061};
5062
5063static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
5064{
5065 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5066 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5067 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5068 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5069 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5070 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5071 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5072 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5073 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5074 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5075 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5076 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5077 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5078 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5079 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5080 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5081}
5082
5083static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5084{
5085 u16 eeprom;
5086 u8 value;
5087
5088 rt2800_bbp_read(rt2x00dev, 138, &value);
5089 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5090 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5091 value |= 0x20;
5092 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5093 value &= ~0x02;
5094 rt2800_bbp_write(rt2x00dev, 138, value);
5095}
5096
5097static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5098{
5099 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5100
5101 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5102 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5103
5104 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5105 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5106
5107 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5108
5109 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5110 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5111
5112 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5113
5114 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5115
5116 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5117
5118 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5119
5120 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5121
5122 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5123
5124 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5125
5126 rt2800_bbp_write(rt2x00dev, 105, 0x01);
5127
5128 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5129}
5130
5131static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5132{
5133 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5134 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5135
5136 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5137 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5138 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5139 } else {
5140 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5141 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5142 }
5143
5144 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5145
5146 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5147
5148 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5149
5150 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5151
5152 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5153 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5154 else
5155 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5156
5157 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5158
5159 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5160
5161 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5162
5163 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5164
5165 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5166
5167 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5168}
5169
5170static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5171{
5172 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5173 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5174
5175 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5176 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5177
5178 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5179
5180 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5181 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5182 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5183
5184 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5185
5186 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5187
5188 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5189
5190 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5191
5192 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5193
5194 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5195
5196 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5197 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5198 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5199 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5200 else
5201 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5202
5203 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5204
5205 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5206
5207 if (rt2x00_rt(rt2x00dev, RT3071) ||
5208 rt2x00_rt(rt2x00dev, RT3090))
5209 rt2800_disable_unused_dac_adc(rt2x00dev);
5210}
5211
5212static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5213{
5214 u8 value;
5215
5216 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5217
5218 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5219
5220 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5221 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5222
5223 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5224
5225 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5226 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5227 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5228 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5229
5230 rt2800_bbp_write(rt2x00dev, 77, 0x58);
5231
5232 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5233
5234 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5235 rt2800_bbp_write(rt2x00dev, 79, 0x18);
5236 rt2800_bbp_write(rt2x00dev, 80, 0x09);
5237 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5238
5239 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5240
5241 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5242
5243 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5244
5245 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5246
5247 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5248
5249 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5250
5251 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5252
5253 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5254
5255 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5256
5257 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5258
5259 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5260
5261 rt2800_bbp_write(rt2x00dev, 67, 0x24);
5262 rt2800_bbp_write(rt2x00dev, 143, 0x04);
5263 rt2800_bbp_write(rt2x00dev, 142, 0x99);
5264 rt2800_bbp_write(rt2x00dev, 150, 0x30);
5265 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5266 rt2800_bbp_write(rt2x00dev, 152, 0x20);
5267 rt2800_bbp_write(rt2x00dev, 153, 0x34);
5268 rt2800_bbp_write(rt2x00dev, 154, 0x40);
5269 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5270 rt2800_bbp_write(rt2x00dev, 253, 0x04);
5271
5272 rt2800_bbp_read(rt2x00dev, 47, &value);
5273 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5274 rt2800_bbp_write(rt2x00dev, 47, value);
5275
5276 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5277 rt2800_bbp_read(rt2x00dev, 3, &value);
5278 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5279 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5280 rt2800_bbp_write(rt2x00dev, 3, value);
5281}
5282
5283static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5284{
5285 rt2800_bbp_write(rt2x00dev, 3, 0x00);
5286 rt2800_bbp_write(rt2x00dev, 4, 0x50);
5287
5288 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5289
5290 rt2800_bbp_write(rt2x00dev, 47, 0x48);
5291
5292 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5293 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5294
5295 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5296
5297 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5298 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5299 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5300 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5301
5302 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5303
5304 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5305
5306 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5307 rt2800_bbp_write(rt2x00dev, 80, 0x08);
5308 rt2800_bbp_write(rt2x00dev, 81, 0x37);
5309
5310 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5311
5312 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5313
5314 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5315
5316 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5317
5318 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5319
5320 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5321
5322 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5323
5324 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5325
5326 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5327
5328 rt2800_bbp_write(rt2x00dev, 105, 0x34);
5329
5330 rt2800_bbp_write(rt2x00dev, 106, 0x05);
5331
5332 rt2800_bbp_write(rt2x00dev, 120, 0x50);
5333
5334 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5335
5336 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
5337 /* Set ITxBF timeout to 0x9c40=1000msec */
5338 rt2800_bbp_write(rt2x00dev, 179, 0x02);
5339 rt2800_bbp_write(rt2x00dev, 180, 0x00);
5340 rt2800_bbp_write(rt2x00dev, 182, 0x40);
5341 rt2800_bbp_write(rt2x00dev, 180, 0x01);
5342 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
5343 rt2800_bbp_write(rt2x00dev, 179, 0x00);
5344 /* Reprogram the inband interface to put right values in RXWI */
5345 rt2800_bbp_write(rt2x00dev, 142, 0x04);
5346 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
5347 rt2800_bbp_write(rt2x00dev, 142, 0x06);
5348 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
5349 rt2800_bbp_write(rt2x00dev, 142, 0x07);
5350 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
5351 rt2800_bbp_write(rt2x00dev, 142, 0x08);
5352 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
5353
5354 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
5355}
5356
5357static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
5358{
5359 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5360 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5361
5362 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5363 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5364
5365 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5366
5367 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5368 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5369 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5370
5371 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5372
5373 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5374
5375 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5376
5377 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5378
5379 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5380
5381 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5382
5383 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
5384 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5385 else
5386 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5387
5388 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5389
5390 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5391
5392 rt2800_disable_unused_dac_adc(rt2x00dev);
5393}
5394
5395static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
5396{
5397 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5398
5399 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5400 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5401
5402 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5403 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5404
5405 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5406
5407 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5408 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5409 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5410
5411 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5412
5413 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5414
5415 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5416
5417 rt2800_bbp_write(rt2x00dev, 86, 0x00);
5418
5419 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5420
5421 rt2800_bbp_write(rt2x00dev, 92, 0x00);
5422
5423 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5424
5425 rt2800_bbp_write(rt2x00dev, 105, 0x05);
5426
5427 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5428
5429 rt2800_disable_unused_dac_adc(rt2x00dev);
5430}
5431
5432static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
5433{
5434 rt2800_init_bbp_early(rt2x00dev);
5435
5436 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5437 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5438 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5439 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
5440
5441 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5442
5443 /* Enable DC filter */
5444 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
5445 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5446}
5447
5448static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
5449{
5450 int ant, div_mode;
5451 u16 eeprom;
5452 u8 value;
5453
5454 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5455
5456 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5457
5458 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5459 rt2800_bbp_write(rt2x00dev, 66, 0x38);
5460
5461 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5462
5463 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5464 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5465 rt2800_bbp_write(rt2x00dev, 75, 0x46);
5466 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5467
5468 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5469
5470 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5471
5472 rt2800_bbp_write(rt2x00dev, 79, 0x13);
5473 rt2800_bbp_write(rt2x00dev, 80, 0x05);
5474 rt2800_bbp_write(rt2x00dev, 81, 0x33);
5475
5476 rt2800_bbp_write(rt2x00dev, 82, 0x62);
5477
5478 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5479
5480 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5481
5482 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5483
5484 if (rt2x00_rt(rt2x00dev, RT5392))
5485 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5486
5487 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5488
5489 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5490
5491 if (rt2x00_rt(rt2x00dev, RT5392)) {
5492 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5493 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5494 }
5495
5496 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5497
5498 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5499
5500 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
5501
5502 if (rt2x00_rt(rt2x00dev, RT5390))
5503 rt2800_bbp_write(rt2x00dev, 106, 0x03);
5504 else if (rt2x00_rt(rt2x00dev, RT5392))
5505 rt2800_bbp_write(rt2x00dev, 106, 0x12);
5506 else
5507 WARN_ON(1);
5508
5509 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5510
5511 if (rt2x00_rt(rt2x00dev, RT5392)) {
5512 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
5513 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
5514 }
5515
5516 rt2800_disable_unused_dac_adc(rt2x00dev);
5517
5518 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5519 div_mode = rt2x00_get_field16(eeprom,
5520 EEPROM_NIC_CONF1_ANT_DIVERSITY);
5521 ant = (div_mode == 3) ? 1 : 0;
5522
5523 /* check if this is a Bluetooth combo card */
5524 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
5525 u32 reg;
5526
5527 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®);
5528 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0);
5529 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0);
5530 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0);
5531 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0);
5532 if (ant == 0)
5533 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1);
5534 else if (ant == 1)
5535 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1);
5536 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5537 }
5538
5539 /* This chip has hardware antenna diversity*/
5540 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
5541 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
5542 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
5543 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
5544 }
5545
5546 rt2800_bbp_read(rt2x00dev, 152, &value);
5547 if (ant == 0)
5548 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5549 else
5550 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5551 rt2800_bbp_write(rt2x00dev, 152, value);
5552
5553 rt2800_init_freq_calibration(rt2x00dev);
5554}
5555
5556static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
5557{
5558 int ant, div_mode;
5559 u16 eeprom;
5560 u8 value;
5561
5562 rt2800_init_bbp_early(rt2x00dev);
5563
5564 rt2800_bbp_read(rt2x00dev, 105, &value);
5565 rt2x00_set_field8(&value, BBP105_MLD,
5566 rt2x00dev->default_ant.rx_chain_num == 2);
5567 rt2800_bbp_write(rt2x00dev, 105, value);
5568
5569 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5570
5571 rt2800_bbp_write(rt2x00dev, 20, 0x06);
5572 rt2800_bbp_write(rt2x00dev, 31, 0x08);
5573 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5574 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
5575 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
5576 rt2800_bbp_write(rt2x00dev, 70, 0x05);
5577 rt2800_bbp_write(rt2x00dev, 73, 0x13);
5578 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
5579 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
5580 rt2800_bbp_write(rt2x00dev, 76, 0x28);
5581 rt2800_bbp_write(rt2x00dev, 77, 0x59);
5582 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
5583 rt2800_bbp_write(rt2x00dev, 86, 0x38);
5584 rt2800_bbp_write(rt2x00dev, 88, 0x90);
5585 rt2800_bbp_write(rt2x00dev, 91, 0x04);
5586 rt2800_bbp_write(rt2x00dev, 92, 0x02);
5587 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
5588 rt2800_bbp_write(rt2x00dev, 98, 0x12);
5589 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
5590 rt2800_bbp_write(rt2x00dev, 104, 0x92);
5591 /* FIXME BBP105 owerwrite */
5592 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
5593 rt2800_bbp_write(rt2x00dev, 106, 0x35);
5594 rt2800_bbp_write(rt2x00dev, 128, 0x12);
5595 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
5596 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
5597 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
5598
5599 /* Initialize GLRT (Generalized Likehood Radio Test) */
5600 rt2800_init_bbp_5592_glrt(rt2x00dev);
5601
5602 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5603
5604 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
5605 div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
5606 ant = (div_mode == 3) ? 1 : 0;
5607 rt2800_bbp_read(rt2x00dev, 152, &value);
5608 if (ant == 0) {
5609 /* Main antenna */
5610 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
5611 } else {
5612 /* Auxiliary antenna */
5613 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
5614 }
5615 rt2800_bbp_write(rt2x00dev, 152, value);
5616
5617 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
5618 rt2800_bbp_read(rt2x00dev, 254, &value);
5619 rt2x00_set_field8(&value, BBP254_BIT7, 1);
5620 rt2800_bbp_write(rt2x00dev, 254, value);
5621 }
5622
5623 rt2800_init_freq_calibration(rt2x00dev);
5624
5625 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5626 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
5627 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5628}
5629
5630static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
5631{
5632 unsigned int i;
5633 u16 eeprom;
5634 u8 reg_id;
5635 u8 value;
5636
5637 if (rt2800_is_305x_soc(rt2x00dev))
5638 rt2800_init_bbp_305x_soc(rt2x00dev);
5639
5640 switch (rt2x00dev->chip.rt) {
5641 case RT2860:
5642 case RT2872:
5643 case RT2883:
5644 rt2800_init_bbp_28xx(rt2x00dev);
5645 break;
5646 case RT3070:
5647 case RT3071:
5648 case RT3090:
5649 rt2800_init_bbp_30xx(rt2x00dev);
5650 break;
5651 case RT3290:
5652 rt2800_init_bbp_3290(rt2x00dev);
5653 break;
5654 case RT3352:
5655 rt2800_init_bbp_3352(rt2x00dev);
5656 break;
5657 case RT3390:
5658 rt2800_init_bbp_3390(rt2x00dev);
5659 break;
5660 case RT3572:
5661 rt2800_init_bbp_3572(rt2x00dev);
5662 break;
5663 case RT3593:
5664 rt2800_init_bbp_3593(rt2x00dev);
5665 return;
5666 case RT5390:
5667 case RT5392:
5668 rt2800_init_bbp_53xx(rt2x00dev);
5669 break;
5670 case RT5592:
5671 rt2800_init_bbp_5592(rt2x00dev);
5672 return;
5673 }
5674
5675 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
5676 rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
5677 &eeprom);
5678
5679 if (eeprom != 0xffff && eeprom != 0x0000) {
5680 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
5681 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
5682 rt2800_bbp_write(rt2x00dev, reg_id, value);
5683 }
5684 }
5685}
5686
5687static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
5688{
5689 u32 reg;
5690
5691 rt2800_register_read(rt2x00dev, OPT_14_CSR, ®);
5692 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1);
5693 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
5694}
5695
5696static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
5697 u8 filter_target)
5698{
5699 unsigned int i;
5700 u8 bbp;
5701 u8 rfcsr;
5702 u8 passband;
5703 u8 stopband;
5704 u8 overtuned = 0;
5705 u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
5706
5707 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5708
5709 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5710 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
5711 rt2800_bbp_write(rt2x00dev, 4, bbp);
5712
5713 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
5714 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
5715 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
5716
5717 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5718 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
5719 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5720
5721 /*
5722 * Set power & frequency of passband test tone
5723 */
5724 rt2800_bbp_write(rt2x00dev, 24, 0);
5725
5726 for (i = 0; i < 100; i++) {
5727 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5728 msleep(1);
5729
5730 rt2800_bbp_read(rt2x00dev, 55, &passband);
5731 if (passband)
5732 break;
5733 }
5734
5735 /*
5736 * Set power & frequency of stopband test tone
5737 */
5738 rt2800_bbp_write(rt2x00dev, 24, 0x06);
5739
5740 for (i = 0; i < 100; i++) {
5741 rt2800_bbp_write(rt2x00dev, 25, 0x90);
5742 msleep(1);
5743
5744 rt2800_bbp_read(rt2x00dev, 55, &stopband);
5745
5746 if ((passband - stopband) <= filter_target) {
5747 rfcsr24++;
5748 overtuned += ((passband - stopband) == filter_target);
5749 } else
5750 break;
5751
5752 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5753 }
5754
5755 rfcsr24 -= !!overtuned;
5756
5757 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
5758 return rfcsr24;
5759}
5760
5761static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
5762 const unsigned int rf_reg)
5763{
5764 u8 rfcsr;
5765
5766 rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
5767 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
5768 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5769 msleep(1);
5770 rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
5771 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
5772}
5773
5774static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
5775{
5776 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5777 u8 filter_tgt_bw20;
5778 u8 filter_tgt_bw40;
5779 u8 rfcsr, bbp;
5780
5781 /*
5782 * TODO: sync filter_tgt values with vendor driver
5783 */
5784 if (rt2x00_rt(rt2x00dev, RT3070)) {
5785 filter_tgt_bw20 = 0x16;
5786 filter_tgt_bw40 = 0x19;
5787 } else {
5788 filter_tgt_bw20 = 0x13;
5789 filter_tgt_bw40 = 0x15;
5790 }
5791
5792 drv_data->calibration_bw20 =
5793 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
5794 drv_data->calibration_bw40 =
5795 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
5796
5797 /*
5798 * Save BBP 25 & 26 values for later use in channel switching (for 3052)
5799 */
5800 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
5801 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
5802
5803 /*
5804 * Set back to initial state
5805 */
5806 rt2800_bbp_write(rt2x00dev, 24, 0);
5807
5808 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
5809 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
5810 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
5811
5812 /*
5813 * Set BBP back to BW20
5814 */
5815 rt2800_bbp_read(rt2x00dev, 4, &bbp);
5816 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
5817 rt2800_bbp_write(rt2x00dev, 4, bbp);
5818}
5819
5820static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
5821{
5822 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5823 u8 min_gain, rfcsr, bbp;
5824 u16 eeprom;
5825
5826 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
5827
5828 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
5829 if (rt2x00_rt(rt2x00dev, RT3070) ||
5830 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5831 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5832 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5833 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
5834 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
5835 }
5836
5837 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
5838 if (drv_data->txmixer_gain_24g >= min_gain) {
5839 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
5840 drv_data->txmixer_gain_24g);
5841 }
5842
5843 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
5844
5845 if (rt2x00_rt(rt2x00dev, RT3090)) {
5846 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5847 rt2800_bbp_read(rt2x00dev, 138, &bbp);
5848 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5849 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5850 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
5851 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5852 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
5853 rt2800_bbp_write(rt2x00dev, 138, bbp);
5854 }
5855
5856 if (rt2x00_rt(rt2x00dev, RT3070)) {
5857 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
5858 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
5859 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
5860 else
5861 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
5862 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
5863 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
5864 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
5865 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
5866 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
5867 rt2x00_rt(rt2x00dev, RT3090) ||
5868 rt2x00_rt(rt2x00dev, RT3390)) {
5869 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5870 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5871 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
5872 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
5873 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
5874 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
5875 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5876
5877 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
5878 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
5879 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
5880
5881 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
5882 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
5883 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
5884
5885 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
5886 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
5887 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
5888 }
5889}
5890
5891static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
5892{
5893 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5894 u8 rfcsr;
5895 u8 tx_gain;
5896
5897 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
5898 rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
5899 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
5900
5901 rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
5902 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
5903 RFCSR17_TXMIXER_GAIN);
5904 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
5905 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
5906
5907 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
5908 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
5909 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
5910
5911 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
5912 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
5913 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
5914
5915 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
5916 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
5917 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
5918 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
5919
5920 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
5921 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
5922 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
5923
5924 /* TODO: enable stream mode */
5925}
5926
5927static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
5928{
5929 u8 reg;
5930 u16 eeprom;
5931
5932 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
5933 rt2800_bbp_read(rt2x00dev, 138, ®);
5934 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5935 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5936 rt2x00_set_field8(®, BBP138_RX_ADC1, 0);
5937 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5938 rt2x00_set_field8(®, BBP138_TX_DAC1, 1);
5939 rt2800_bbp_write(rt2x00dev, 138, reg);
5940
5941 rt2800_rfcsr_read(rt2x00dev, 38, ®);
5942 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0);
5943 rt2800_rfcsr_write(rt2x00dev, 38, reg);
5944
5945 rt2800_rfcsr_read(rt2x00dev, 39, ®);
5946 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0);
5947 rt2800_rfcsr_write(rt2x00dev, 39, reg);
5948
5949 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5950
5951 rt2800_rfcsr_read(rt2x00dev, 30, ®);
5952 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2);
5953 rt2800_rfcsr_write(rt2x00dev, 30, reg);
5954}
5955
5956static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
5957{
5958 rt2800_rf_init_calibration(rt2x00dev, 30);
5959
5960 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
5961 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
5962 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
5963 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
5964 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
5965 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
5966 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
5967 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
5968 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
5969 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
5970 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
5971 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
5972 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
5973 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
5974 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
5975 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
5976 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
5977 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
5978 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
5979 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
5980 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
5981 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
5982 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
5983 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
5984 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
5985 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
5986 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
5987 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
5988 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
5989 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
5990 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
5991 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
5992}
5993
5994static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
5995{
5996 u8 rfcsr;
5997 u16 eeprom;
5998 u32 reg;
5999
6000 /* XXX vendor driver do this only for 3070 */
6001 rt2800_rf_init_calibration(rt2x00dev, 30);
6002
6003 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6004 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6005 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6006 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6007 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6008 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6009 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6010 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6011 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6012 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6013 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6014 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6015 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6016 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6017 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6018 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6019 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6020 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
6021 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
6022
6023 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6024 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
6025 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
6026 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6027 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6028 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6029 rt2x00_rt(rt2x00dev, RT3090)) {
6030 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6031
6032 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6033 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6034 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6035
6036 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
6037 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
6038 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6039 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
6040 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
6041 &eeprom);
6042 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6043 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6044 else
6045 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6046 }
6047 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6048
6049 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
6050 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
6051 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6052 }
6053
6054 rt2800_rx_filter_calibration(rt2x00dev);
6055
6056 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6057 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6058 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6059 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6060
6061 rt2800_led_open_drain_enable(rt2x00dev);
6062 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6063}
6064
6065static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
6066{
6067 u8 rfcsr;
6068
6069 rt2800_rf_init_calibration(rt2x00dev, 2);
6070
6071 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6072 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6073 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6074 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6075 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6076 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
6077 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6078 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6079 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6080 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6081 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6082 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
6083 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6084 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
6085 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6086 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6087 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6088 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6089 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6090 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6091 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6092 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
6093 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6094 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6095 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6096 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6097 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6098 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6099 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6100 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
6101 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6102 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6103 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6104 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6105 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6106 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
6107 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6108 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6109 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6110 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6111 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
6112 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6113 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6114 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
6115 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6116 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
6117
6118 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
6119 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
6120 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
6121
6122 rt2800_led_open_drain_enable(rt2x00dev);
6123 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6124}
6125
6126static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
6127{
6128 rt2800_rf_init_calibration(rt2x00dev, 30);
6129
6130 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
6131 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
6132 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
6133 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
6134 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
6135 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6136 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
6137 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6138 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6139 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6140 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
6141 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
6142 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
6143 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
6144 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
6145 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6146 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
6147 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
6148 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6149 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6150 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6151 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6152 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6153 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6154 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6155 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6156 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6157 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
6158 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
6159 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6160 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6161 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6162 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6163 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
6164 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
6165 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
6166 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
6167 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
6168 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
6169 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
6170 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
6171 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
6172 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
6173 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
6174 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
6175 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
6176 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
6177 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
6178 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
6179 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
6180 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
6181 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
6182 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
6183 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
6184 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
6185 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
6186 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
6187 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
6188 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
6189 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
6190 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
6191 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6192 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6193
6194 rt2800_rx_filter_calibration(rt2x00dev);
6195 rt2800_led_open_drain_enable(rt2x00dev);
6196 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6197}
6198
6199static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
6200{
6201 u32 reg;
6202
6203 rt2800_rf_init_calibration(rt2x00dev, 30);
6204
6205 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
6206 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
6207 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6208 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
6209 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6210 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
6211 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
6212 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
6213 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
6214 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
6215 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
6216 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6217 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
6218 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
6219 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6220 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6221 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
6222 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
6223 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
6224 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
6225 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
6226 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
6227 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6228 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
6229 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6230 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
6231 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6232 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6233 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
6234 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
6235 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
6236 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
6237
6238 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
6239 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
6240 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6241
6242 rt2800_rx_filter_calibration(rt2x00dev);
6243
6244 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
6245 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6246
6247 rt2800_led_open_drain_enable(rt2x00dev);
6248 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6249}
6250
6251static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
6252{
6253 u8 rfcsr;
6254 u32 reg;
6255
6256 rt2800_rf_init_calibration(rt2x00dev, 30);
6257
6258 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
6259 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
6260 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
6261 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
6262 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
6263 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
6264 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
6265 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
6266 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
6267 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
6268 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
6269 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
6270 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
6271 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
6272 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
6273 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
6274 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
6275 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
6276 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
6277 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
6278 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
6279 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6280 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
6281 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6282 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
6283 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
6284 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
6285 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6286 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
6287 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
6288 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
6289
6290 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
6291 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6292 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6293
6294 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
6295 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6296 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
6297 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6298 msleep(1);
6299 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
6300 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6301 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
6302 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6303
6304 rt2800_rx_filter_calibration(rt2x00dev);
6305 rt2800_led_open_drain_enable(rt2x00dev);
6306 rt2800_normal_mode_setup_3xxx(rt2x00dev);
6307}
6308
6309static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
6310{
6311 u8 bbp;
6312 bool txbf_enabled = false; /* FIXME */
6313
6314 rt2800_bbp_read(rt2x00dev, 105, &bbp);
6315 if (rt2x00dev->default_ant.rx_chain_num == 1)
6316 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
6317 else
6318 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
6319 rt2800_bbp_write(rt2x00dev, 105, bbp);
6320
6321 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6322
6323 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6324 rt2800_bbp_write(rt2x00dev, 82, 0x82);
6325 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6326 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6327 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6328 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6329 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6330 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6331
6332 if (txbf_enabled)
6333 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6334 else
6335 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6336
6337 /* SNR mapping */
6338 rt2800_bbp_write(rt2x00dev, 142, 6);
6339 rt2800_bbp_write(rt2x00dev, 143, 160);
6340 rt2800_bbp_write(rt2x00dev, 142, 7);
6341 rt2800_bbp_write(rt2x00dev, 143, 161);
6342 rt2800_bbp_write(rt2x00dev, 142, 8);
6343 rt2800_bbp_write(rt2x00dev, 143, 162);
6344
6345 /* ADC/DAC control */
6346 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6347
6348 /* RX AGC energy lower bound in log2 */
6349 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6350
6351 /* FIXME: BBP 105 owerwrite? */
6352 rt2800_bbp_write(rt2x00dev, 105, 0x04);
6353
6354}
6355
6356static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
6357{
6358 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6359 u32 reg;
6360 u8 rfcsr;
6361
6362 /* Disable GPIO #4 and #7 function for LAN PE control */
6363 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
6364 rt2x00_set_field32(®, GPIO_SWITCH_4, 0);
6365 rt2x00_set_field32(®, GPIO_SWITCH_7, 0);
6366 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6367
6368 /* Initialize default register values */
6369 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
6370 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
6371 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
6372 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
6373 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
6374 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
6375 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
6376 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
6377 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
6378 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
6379 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
6380 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6381 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6382 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6383 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
6384 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
6385 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
6386 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
6387 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
6388 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
6389 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
6390 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
6391 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
6392 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
6393 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
6394 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
6395 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
6396 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
6397 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
6398 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
6399 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
6400 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
6401
6402 /* Initiate calibration */
6403 /* TODO: use rt2800_rf_init_calibration ? */
6404 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
6405 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
6406 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
6407
6408 rt2800_adjust_freq_offset(rt2x00dev);
6409
6410 rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
6411 rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
6412 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
6413
6414 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
6415 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6416 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
6417 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6418 usleep_range(1000, 1500);
6419 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
6420 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6421 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6422
6423 /* Set initial values for RX filter calibration */
6424 drv_data->calibration_bw20 = 0x1f;
6425 drv_data->calibration_bw40 = 0x2f;
6426
6427 /* Save BBP 25 & 26 values for later use in channel switching */
6428 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
6429 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
6430
6431 rt2800_led_open_drain_enable(rt2x00dev);
6432 rt2800_normal_mode_setup_3593(rt2x00dev);
6433
6434 rt3593_post_bbp_init(rt2x00dev);
6435
6436 /* TODO: enable stream mode support */
6437}
6438
6439static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
6440{
6441 rt2800_rf_init_calibration(rt2x00dev, 2);
6442
6443 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
6444 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6445 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6446 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6447 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6448 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6449 else
6450 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
6451 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6452 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6453 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6454 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6455 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6456 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6457 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6458 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6459 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6460 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
6461
6462 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6463 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
6464 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6465 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
6466 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
6467 if (rt2x00_is_usb(rt2x00dev) &&
6468 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6469 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6470 else
6471 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
6472 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
6473 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6474 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6475 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6476
6477 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6478 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6479 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
6480 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
6481 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6482 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6483 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6484 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6485 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
6486 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6487
6488 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
6489 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6490 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
6491 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
6492 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6493 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6494 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6495 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6496 else
6497 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
6498 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
6499 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6500 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6501
6502 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
6503 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6504 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
6505 else
6506 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
6507 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
6508 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
6509 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
6510 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
6511 else
6512 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
6513 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
6514 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
6515 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
6516
6517 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6518 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
6519 if (rt2x00_is_usb(rt2x00dev))
6520 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
6521 else
6522 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
6523 } else {
6524 if (rt2x00_is_usb(rt2x00dev))
6525 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
6526 else
6527 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
6528 }
6529 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
6530 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
6531
6532 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6533
6534 rt2800_led_open_drain_enable(rt2x00dev);
6535}
6536
6537static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
6538{
6539 rt2800_rf_init_calibration(rt2x00dev, 2);
6540
6541 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
6542 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
6543 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6544 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
6545 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6546 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
6547 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
6548 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
6549 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
6550 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6551 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6552 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6553 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6554 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
6555 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
6556 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
6557 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
6558 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
6559 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
6560 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
6561 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6562 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
6563 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6564 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6565 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
6566 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
6567 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
6568 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6569 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6570 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6571 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
6572 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
6573 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
6574 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
6575 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
6576 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
6577 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
6578 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
6579 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
6580 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
6581 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
6582 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
6583 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
6584 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
6585 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
6586 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
6587 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
6588 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
6589 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
6590 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
6591 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
6592 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
6593 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
6594 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
6595 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
6596 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
6597 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
6598 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6599
6600 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6601
6602 rt2800_led_open_drain_enable(rt2x00dev);
6603}
6604
6605static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
6606{
6607 rt2800_rf_init_calibration(rt2x00dev, 30);
6608
6609 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
6610 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
6611 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
6612 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
6613 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
6614 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
6615 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
6616 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
6617 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
6618 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
6619 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
6620 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
6621 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
6622 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
6623 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
6624 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
6625 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
6626 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
6627 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
6628 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
6629 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
6630
6631 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
6632 msleep(1);
6633
6634 rt2800_adjust_freq_offset(rt2x00dev);
6635
6636 /* Enable DC filter */
6637 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6638 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6639
6640 rt2800_normal_mode_setup_5xxx(rt2x00dev);
6641
6642 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
6643 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6644
6645 rt2800_led_open_drain_enable(rt2x00dev);
6646}
6647
6648static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
6649{
6650 if (rt2800_is_305x_soc(rt2x00dev)) {
6651 rt2800_init_rfcsr_305x_soc(rt2x00dev);
6652 return;
6653 }
6654
6655 switch (rt2x00dev->chip.rt) {
6656 case RT3070:
6657 case RT3071:
6658 case RT3090:
6659 rt2800_init_rfcsr_30xx(rt2x00dev);
6660 break;
6661 case RT3290:
6662 rt2800_init_rfcsr_3290(rt2x00dev);
6663 break;
6664 case RT3352:
6665 rt2800_init_rfcsr_3352(rt2x00dev);
6666 break;
6667 case RT3390:
6668 rt2800_init_rfcsr_3390(rt2x00dev);
6669 break;
6670 case RT3572:
6671 rt2800_init_rfcsr_3572(rt2x00dev);
6672 break;
6673 case RT3593:
6674 rt2800_init_rfcsr_3593(rt2x00dev);
6675 break;
6676 case RT5390:
6677 rt2800_init_rfcsr_5390(rt2x00dev);
6678 break;
6679 case RT5392:
6680 rt2800_init_rfcsr_5392(rt2x00dev);
6681 break;
6682 case RT5592:
6683 rt2800_init_rfcsr_5592(rt2x00dev);
6684 break;
6685 }
6686}
6687
6688int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
6689{
6690 u32 reg;
6691 u16 word;
6692
6693 /*
6694 * Initialize MAC registers.
6695 */
6696 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
6697 rt2800_init_registers(rt2x00dev)))
6698 return -EIO;
6699
6700 /*
6701 * Wait BBP/RF to wake up.
6702 */
6703 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
6704 return -EIO;
6705
6706 /*
6707 * Send signal during boot time to initialize firmware.
6708 */
6709 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
6710 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
6711 if (rt2x00_is_usb(rt2x00dev))
6712 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
6713 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
6714 msleep(1);
6715
6716 /*
6717 * Make sure BBP is up and running.
6718 */
6719 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
6720 return -EIO;
6721
6722 /*
6723 * Initialize BBP/RF registers.
6724 */
6725 rt2800_init_bbp(rt2x00dev);
6726 rt2800_init_rfcsr(rt2x00dev);
6727
6728 if (rt2x00_is_usb(rt2x00dev) &&
6729 (rt2x00_rt(rt2x00dev, RT3070) ||
6730 rt2x00_rt(rt2x00dev, RT3071) ||
6731 rt2x00_rt(rt2x00dev, RT3572))) {
6732 udelay(200);
6733 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
6734 udelay(10);
6735 }
6736
6737 /*
6738 * Enable RX.
6739 */
6740 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
6741 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
6742 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
6743 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6744
6745 udelay(50);
6746
6747 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
6748 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
6749 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
6750 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
6751 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
6752 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6753
6754 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
6755 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
6756 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
6757 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6758
6759 /*
6760 * Initialize LED control
6761 */
6762 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
6763 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
6764 word & 0xff, (word >> 8) & 0xff);
6765
6766 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
6767 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
6768 word & 0xff, (word >> 8) & 0xff);
6769
6770 rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
6771 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
6772 word & 0xff, (word >> 8) & 0xff);
6773
6774 return 0;
6775}
6776EXPORT_SYMBOL_GPL(rt2800_enable_radio);
6777
6778void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
6779{
6780 u32 reg;
6781
6782 rt2800_disable_wpdma(rt2x00dev);
6783
6784 /* Wait for DMA, ignore error */
6785 rt2800_wait_wpdma_ready(rt2x00dev);
6786
6787 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
6788 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0);
6789 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
6790 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
6791}
6792EXPORT_SYMBOL_GPL(rt2800_disable_radio);
6793
6794int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
6795{
6796 u32 reg;
6797 u16 efuse_ctrl_reg;
6798
6799 if (rt2x00_rt(rt2x00dev, RT3290))
6800 efuse_ctrl_reg = EFUSE_CTRL_3290;
6801 else
6802 efuse_ctrl_reg = EFUSE_CTRL;
6803
6804 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, ®);
6805 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
6806}
6807EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
6808
6809static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
6810{
6811 u32 reg;
6812 u16 efuse_ctrl_reg;
6813 u16 efuse_data0_reg;
6814 u16 efuse_data1_reg;
6815 u16 efuse_data2_reg;
6816 u16 efuse_data3_reg;
6817
6818 if (rt2x00_rt(rt2x00dev, RT3290)) {
6819 efuse_ctrl_reg = EFUSE_CTRL_3290;
6820 efuse_data0_reg = EFUSE_DATA0_3290;
6821 efuse_data1_reg = EFUSE_DATA1_3290;
6822 efuse_data2_reg = EFUSE_DATA2_3290;
6823 efuse_data3_reg = EFUSE_DATA3_3290;
6824 } else {
6825 efuse_ctrl_reg = EFUSE_CTRL;
6826 efuse_data0_reg = EFUSE_DATA0;
6827 efuse_data1_reg = EFUSE_DATA1;
6828 efuse_data2_reg = EFUSE_DATA2;
6829 efuse_data3_reg = EFUSE_DATA3;
6830 }
6831 mutex_lock(&rt2x00dev->csr_mutex);
6832
6833 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, ®);
6834 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i);
6835 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0);
6836 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1);
6837 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
6838
6839 /* Wait until the EEPROM has been loaded */
6840 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®);
6841 /* Apparently the data is read from end to start */
6842 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, ®);
6843 /* The returned value is in CPU order, but eeprom is le */
6844 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
6845 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, ®);
6846 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
6847 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, ®);
6848 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
6849 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, ®);
6850 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
6851
6852 mutex_unlock(&rt2x00dev->csr_mutex);
6853}
6854
6855int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
6856{
6857 unsigned int i;
6858
6859 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
6860 rt2800_efuse_read(rt2x00dev, i);
6861
6862 return 0;
6863}
6864EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
6865
6866static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
6867{
6868 u16 word;
6869
6870 if (rt2x00_rt(rt2x00dev, RT3593))
6871 return 0;
6872
6873 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
6874 if ((word & 0x00ff) != 0x00ff)
6875 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
6876
6877 return 0;
6878}
6879
6880static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
6881{
6882 u16 word;
6883
6884 if (rt2x00_rt(rt2x00dev, RT3593))
6885 return 0;
6886
6887 rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
6888 if ((word & 0x00ff) != 0x00ff)
6889 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
6890
6891 return 0;
6892}
6893
6894static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
6895{
6896 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6897 u16 word;
6898 u8 *mac;
6899 u8 default_lna_gain;
6900 int retval;
6901
6902 /*
6903 * Read the EEPROM.
6904 */
6905 retval = rt2800_read_eeprom(rt2x00dev);
6906 if (retval)
6907 return retval;
6908
6909 /*
6910 * Start validation of the data that has been read.
6911 */
6912 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
6913 if (!is_valid_ether_addr(mac)) {
6914 eth_random_addr(mac);
6915 rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
6916 }
6917
6918 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
6919 if (word == 0xffff) {
6920 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6921 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
6922 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
6923 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6924 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
6925 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
6926 rt2x00_rt(rt2x00dev, RT2872)) {
6927 /*
6928 * There is a max of 2 RX streams for RT28x0 series
6929 */
6930 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
6931 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
6932 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
6933 }
6934
6935 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
6936 if (word == 0xffff) {
6937 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
6938 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
6939 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
6940 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
6941 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
6942 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
6943 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
6944 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
6945 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
6946 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
6947 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
6948 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
6949 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
6950 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
6951 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
6952 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
6953 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
6954 }
6955
6956 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
6957 if ((word & 0x00ff) == 0x00ff) {
6958 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
6959 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6960 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
6961 }
6962 if ((word & 0xff00) == 0xff00) {
6963 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
6964 LED_MODE_TXRX_ACTIVITY);
6965 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
6966 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
6967 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
6968 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
6969 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
6970 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
6971 }
6972
6973 /*
6974 * During the LNA validation we are going to use
6975 * lna0 as correct value. Note that EEPROM_LNA
6976 * is never validated.
6977 */
6978 rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
6979 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
6980
6981 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
6982 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
6983 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
6984 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
6985 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
6986 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
6987
6988 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
6989
6990 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
6991 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
6992 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
6993 if (!rt2x00_rt(rt2x00dev, RT3593)) {
6994 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
6995 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
6996 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
6997 default_lna_gain);
6998 }
6999 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
7000
7001 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
7002
7003 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
7004 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
7005 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
7006 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
7007 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
7008 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
7009
7010 rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
7011 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
7012 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
7013 if (!rt2x00_rt(rt2x00dev, RT3593)) {
7014 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
7015 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
7016 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
7017 default_lna_gain);
7018 }
7019 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
7020
7021 if (rt2x00_rt(rt2x00dev, RT3593)) {
7022 rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
7023 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
7024 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
7025 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7026 default_lna_gain);
7027 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
7028 rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
7029 rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
7030 default_lna_gain);
7031 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
7032 }
7033
7034 return 0;
7035}
7036
7037static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
7038{
7039 u16 value;
7040 u16 eeprom;
7041 u16 rf;
7042
7043 /*
7044 * Read EEPROM word for configuration.
7045 */
7046 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
7047
7048 /*
7049 * Identify RF chipset by EEPROM value
7050 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
7051 * RT53xx: defined in "EEPROM_CHIP_ID" field
7052 */
7053 if (rt2x00_rt(rt2x00dev, RT3290) ||
7054 rt2x00_rt(rt2x00dev, RT5390) ||
7055 rt2x00_rt(rt2x00dev, RT5392))
7056 rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
7057 else
7058 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
7059
7060 switch (rf) {
7061 case RF2820:
7062 case RF2850:
7063 case RF2720:
7064 case RF2750:
7065 case RF3020:
7066 case RF2020:
7067 case RF3021:
7068 case RF3022:
7069 case RF3052:
7070 case RF3053:
7071 case RF3070:
7072 case RF3290:
7073 case RF3320:
7074 case RF3322:
7075 case RF5360:
7076 case RF5370:
7077 case RF5372:
7078 case RF5390:
7079 case RF5392:
7080 case RF5592:
7081 break;
7082 default:
7083 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
7084 rf);
7085 return -ENODEV;
7086 }
7087
7088 rt2x00_set_rf(rt2x00dev, rf);
7089
7090 /*
7091 * Identify default antenna configuration.
7092 */
7093 rt2x00dev->default_ant.tx_chain_num =
7094 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
7095 rt2x00dev->default_ant.rx_chain_num =
7096 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
7097
7098 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
7099
7100 if (rt2x00_rt(rt2x00dev, RT3070) ||
7101 rt2x00_rt(rt2x00dev, RT3090) ||
7102 rt2x00_rt(rt2x00dev, RT3352) ||
7103 rt2x00_rt(rt2x00dev, RT3390)) {
7104 value = rt2x00_get_field16(eeprom,
7105 EEPROM_NIC_CONF1_ANT_DIVERSITY);
7106 switch (value) {
7107 case 0:
7108 case 1:
7109 case 2:
7110 rt2x00dev->default_ant.tx = ANTENNA_A;
7111 rt2x00dev->default_ant.rx = ANTENNA_A;
7112 break;
7113 case 3:
7114 rt2x00dev->default_ant.tx = ANTENNA_A;
7115 rt2x00dev->default_ant.rx = ANTENNA_B;
7116 break;
7117 }
7118 } else {
7119 rt2x00dev->default_ant.tx = ANTENNA_A;
7120 rt2x00dev->default_ant.rx = ANTENNA_A;
7121 }
7122
7123 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
7124 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
7125 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
7126 }
7127
7128 /*
7129 * Determine external LNA informations.
7130 */
7131 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
7132 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
7133 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
7134 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
7135
7136 /*
7137 * Detect if this device has an hardware controlled radio.
7138 */
7139 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
7140 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
7141
7142 /*
7143 * Detect if this device has Bluetooth co-existence.
7144 */
7145 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
7146 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
7147
7148 /*
7149 * Read frequency offset and RF programming sequence.
7150 */
7151 rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
7152 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
7153
7154 /*
7155 * Store led settings, for correct led behaviour.
7156 */
7157#ifdef CONFIG_RT2X00_LIB_LEDS
7158 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
7159 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
7160 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
7161
7162 rt2x00dev->led_mcu_reg = eeprom;
7163#endif /* CONFIG_RT2X00_LIB_LEDS */
7164
7165 /*
7166 * Check if support EIRP tx power limit feature.
7167 */
7168 rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
7169
7170 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
7171 EIRP_MAX_TX_POWER_LIMIT)
7172 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
7173
7174 return 0;
7175}
7176
7177/*
7178 * RF value list for rt28xx
7179 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
7180 */
7181static const struct rf_channel rf_vals[] = {
7182 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
7183 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
7184 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
7185 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
7186 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
7187 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
7188 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
7189 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
7190 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
7191 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
7192 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
7193 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
7194 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
7195 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
7196
7197 /* 802.11 UNI / HyperLan 2 */
7198 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
7199 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
7200 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
7201 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
7202 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
7203 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
7204 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
7205 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
7206 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
7207 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
7208 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
7209 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
7210
7211 /* 802.11 HyperLan 2 */
7212 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
7213 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
7214 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
7215 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
7216 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
7217 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
7218 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
7219 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
7220 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
7221 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
7222 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
7223 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
7224 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
7225 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
7226 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
7227 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
7228
7229 /* 802.11 UNII */
7230 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
7231 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
7232 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
7233 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
7234 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
7235 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
7236 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
7237 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
7238 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
7239 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
7240 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
7241
7242 /* 802.11 Japan */
7243 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
7244 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
7245 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
7246 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
7247 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
7248 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
7249 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
7250};
7251
7252/*
7253 * RF value list for rt3xxx
7254 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
7255 */
7256static const struct rf_channel rf_vals_3x[] = {
7257 {1, 241, 2, 2 },
7258 {2, 241, 2, 7 },
7259 {3, 242, 2, 2 },
7260 {4, 242, 2, 7 },
7261 {5, 243, 2, 2 },
7262 {6, 243, 2, 7 },
7263 {7, 244, 2, 2 },
7264 {8, 244, 2, 7 },
7265 {9, 245, 2, 2 },
7266 {10, 245, 2, 7 },
7267 {11, 246, 2, 2 },
7268 {12, 246, 2, 7 },
7269 {13, 247, 2, 2 },
7270 {14, 248, 2, 4 },
7271
7272 /* 802.11 UNI / HyperLan 2 */
7273 {36, 0x56, 0, 4},
7274 {38, 0x56, 0, 6},
7275 {40, 0x56, 0, 8},
7276 {44, 0x57, 0, 0},
7277 {46, 0x57, 0, 2},
7278 {48, 0x57, 0, 4},
7279 {52, 0x57, 0, 8},
7280 {54, 0x57, 0, 10},
7281 {56, 0x58, 0, 0},
7282 {60, 0x58, 0, 4},
7283 {62, 0x58, 0, 6},
7284 {64, 0x58, 0, 8},
7285
7286 /* 802.11 HyperLan 2 */
7287 {100, 0x5b, 0, 8},
7288 {102, 0x5b, 0, 10},
7289 {104, 0x5c, 0, 0},
7290 {108, 0x5c, 0, 4},
7291 {110, 0x5c, 0, 6},
7292 {112, 0x5c, 0, 8},
7293 {116, 0x5d, 0, 0},
7294 {118, 0x5d, 0, 2},
7295 {120, 0x5d, 0, 4},
7296 {124, 0x5d, 0, 8},
7297 {126, 0x5d, 0, 10},
7298 {128, 0x5e, 0, 0},
7299 {132, 0x5e, 0, 4},
7300 {134, 0x5e, 0, 6},
7301 {136, 0x5e, 0, 8},
7302 {140, 0x5f, 0, 0},
7303
7304 /* 802.11 UNII */
7305 {149, 0x5f, 0, 9},
7306 {151, 0x5f, 0, 11},
7307 {153, 0x60, 0, 1},
7308 {157, 0x60, 0, 5},
7309 {159, 0x60, 0, 7},
7310 {161, 0x60, 0, 9},
7311 {165, 0x61, 0, 1},
7312 {167, 0x61, 0, 3},
7313 {169, 0x61, 0, 5},
7314 {171, 0x61, 0, 7},
7315 {173, 0x61, 0, 9},
7316};
7317
7318static const struct rf_channel rf_vals_5592_xtal20[] = {
7319 /* Channel, N, K, mod, R */
7320 {1, 482, 4, 10, 3},
7321 {2, 483, 4, 10, 3},
7322 {3, 484, 4, 10, 3},
7323 {4, 485, 4, 10, 3},
7324 {5, 486, 4, 10, 3},
7325 {6, 487, 4, 10, 3},
7326 {7, 488, 4, 10, 3},
7327 {8, 489, 4, 10, 3},
7328 {9, 490, 4, 10, 3},
7329 {10, 491, 4, 10, 3},
7330 {11, 492, 4, 10, 3},
7331 {12, 493, 4, 10, 3},
7332 {13, 494, 4, 10, 3},
7333 {14, 496, 8, 10, 3},
7334 {36, 172, 8, 12, 1},
7335 {38, 173, 0, 12, 1},
7336 {40, 173, 4, 12, 1},
7337 {42, 173, 8, 12, 1},
7338 {44, 174, 0, 12, 1},
7339 {46, 174, 4, 12, 1},
7340 {48, 174, 8, 12, 1},
7341 {50, 175, 0, 12, 1},
7342 {52, 175, 4, 12, 1},
7343 {54, 175, 8, 12, 1},
7344 {56, 176, 0, 12, 1},
7345 {58, 176, 4, 12, 1},
7346 {60, 176, 8, 12, 1},
7347 {62, 177, 0, 12, 1},
7348 {64, 177, 4, 12, 1},
7349 {100, 183, 4, 12, 1},
7350 {102, 183, 8, 12, 1},
7351 {104, 184, 0, 12, 1},
7352 {106, 184, 4, 12, 1},
7353 {108, 184, 8, 12, 1},
7354 {110, 185, 0, 12, 1},
7355 {112, 185, 4, 12, 1},
7356 {114, 185, 8, 12, 1},
7357 {116, 186, 0, 12, 1},
7358 {118, 186, 4, 12, 1},
7359 {120, 186, 8, 12, 1},
7360 {122, 187, 0, 12, 1},
7361 {124, 187, 4, 12, 1},
7362 {126, 187, 8, 12, 1},
7363 {128, 188, 0, 12, 1},
7364 {130, 188, 4, 12, 1},
7365 {132, 188, 8, 12, 1},
7366 {134, 189, 0, 12, 1},
7367 {136, 189, 4, 12, 1},
7368 {138, 189, 8, 12, 1},
7369 {140, 190, 0, 12, 1},
7370 {149, 191, 6, 12, 1},
7371 {151, 191, 10, 12, 1},
7372 {153, 192, 2, 12, 1},
7373 {155, 192, 6, 12, 1},
7374 {157, 192, 10, 12, 1},
7375 {159, 193, 2, 12, 1},
7376 {161, 193, 6, 12, 1},
7377 {165, 194, 2, 12, 1},
7378 {184, 164, 0, 12, 1},
7379 {188, 164, 4, 12, 1},
7380 {192, 165, 8, 12, 1},
7381 {196, 166, 0, 12, 1},
7382};
7383
7384static const struct rf_channel rf_vals_5592_xtal40[] = {
7385 /* Channel, N, K, mod, R */
7386 {1, 241, 2, 10, 3},
7387 {2, 241, 7, 10, 3},
7388 {3, 242, 2, 10, 3},
7389 {4, 242, 7, 10, 3},
7390 {5, 243, 2, 10, 3},
7391 {6, 243, 7, 10, 3},
7392 {7, 244, 2, 10, 3},
7393 {8, 244, 7, 10, 3},
7394 {9, 245, 2, 10, 3},
7395 {10, 245, 7, 10, 3},
7396 {11, 246, 2, 10, 3},
7397 {12, 246, 7, 10, 3},
7398 {13, 247, 2, 10, 3},
7399 {14, 248, 4, 10, 3},
7400 {36, 86, 4, 12, 1},
7401 {38, 86, 6, 12, 1},
7402 {40, 86, 8, 12, 1},
7403 {42, 86, 10, 12, 1},
7404 {44, 87, 0, 12, 1},
7405 {46, 87, 2, 12, 1},
7406 {48, 87, 4, 12, 1},
7407 {50, 87, 6, 12, 1},
7408 {52, 87, 8, 12, 1},
7409 {54, 87, 10, 12, 1},
7410 {56, 88, 0, 12, 1},
7411 {58, 88, 2, 12, 1},
7412 {60, 88, 4, 12, 1},
7413 {62, 88, 6, 12, 1},
7414 {64, 88, 8, 12, 1},
7415 {100, 91, 8, 12, 1},
7416 {102, 91, 10, 12, 1},
7417 {104, 92, 0, 12, 1},
7418 {106, 92, 2, 12, 1},
7419 {108, 92, 4, 12, 1},
7420 {110, 92, 6, 12, 1},
7421 {112, 92, 8, 12, 1},
7422 {114, 92, 10, 12, 1},
7423 {116, 93, 0, 12, 1},
7424 {118, 93, 2, 12, 1},
7425 {120, 93, 4, 12, 1},
7426 {122, 93, 6, 12, 1},
7427 {124, 93, 8, 12, 1},
7428 {126, 93, 10, 12, 1},
7429 {128, 94, 0, 12, 1},
7430 {130, 94, 2, 12, 1},
7431 {132, 94, 4, 12, 1},
7432 {134, 94, 6, 12, 1},
7433 {136, 94, 8, 12, 1},
7434 {138, 94, 10, 12, 1},
7435 {140, 95, 0, 12, 1},
7436 {149, 95, 9, 12, 1},
7437 {151, 95, 11, 12, 1},
7438 {153, 96, 1, 12, 1},
7439 {155, 96, 3, 12, 1},
7440 {157, 96, 5, 12, 1},
7441 {159, 96, 7, 12, 1},
7442 {161, 96, 9, 12, 1},
7443 {165, 97, 1, 12, 1},
7444 {184, 82, 0, 12, 1},
7445 {188, 82, 4, 12, 1},
7446 {192, 82, 8, 12, 1},
7447 {196, 83, 0, 12, 1},
7448};
7449
7450static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
7451{
7452 struct hw_mode_spec *spec = &rt2x00dev->spec;
7453 struct channel_info *info;
7454 char *default_power1;
7455 char *default_power2;
7456 char *default_power3;
7457 unsigned int i;
7458 u32 reg;
7459
7460 /*
7461 * Disable powersaving as default.
7462 */
7463 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
7464
7465 /*
7466 * Initialize all hw fields.
7467 */
7468 rt2x00dev->hw->flags =
7469 IEEE80211_HW_SIGNAL_DBM |
7470 IEEE80211_HW_SUPPORTS_PS |
7471 IEEE80211_HW_PS_NULLFUNC_STACK |
7472 IEEE80211_HW_AMPDU_AGGREGATION |
7473 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
7474 IEEE80211_HW_SUPPORTS_HT_CCK_RATES;
7475
7476 /*
7477 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
7478 * unless we are capable of sending the buffered frames out after the
7479 * DTIM transmission using rt2x00lib_beacondone. This will send out
7480 * multicast and broadcast traffic immediately instead of buffering it
7481 * infinitly and thus dropping it after some time.
7482 */
7483 if (!rt2x00_is_usb(rt2x00dev))
7484 rt2x00dev->hw->flags |=
7485 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
7486
7487 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
7488 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
7489 rt2800_eeprom_addr(rt2x00dev,
7490 EEPROM_MAC_ADDR_0));
7491
7492 /*
7493 * As rt2800 has a global fallback table we cannot specify
7494 * more then one tx rate per frame but since the hw will
7495 * try several rates (based on the fallback table) we should
7496 * initialize max_report_rates to the maximum number of rates
7497 * we are going to try. Otherwise mac80211 will truncate our
7498 * reported tx rates and the rc algortihm will end up with
7499 * incorrect data.
7500 */
7501 rt2x00dev->hw->max_rates = 1;
7502 rt2x00dev->hw->max_report_rates = 7;
7503 rt2x00dev->hw->max_rate_tries = 1;
7504
7505 /*
7506 * Initialize hw_mode information.
7507 */
7508 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
7509
7510 switch (rt2x00dev->chip.rf) {
7511 case RF2720:
7512 case RF2820:
7513 spec->num_channels = 14;
7514 spec->channels = rf_vals;
7515 break;
7516
7517 case RF2750:
7518 case RF2850:
7519 spec->num_channels = ARRAY_SIZE(rf_vals);
7520 spec->channels = rf_vals;
7521 break;
7522
7523 case RF2020:
7524 case RF3020:
7525 case RF3021:
7526 case RF3022:
7527 case RF3070:
7528 case RF3290:
7529 case RF3320:
7530 case RF3322:
7531 case RF5360:
7532 case RF5370:
7533 case RF5372:
7534 case RF5390:
7535 case RF5392:
7536 spec->num_channels = 14;
7537 spec->channels = rf_vals_3x;
7538 break;
7539
7540 case RF3052:
7541 case RF3053:
7542 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
7543 spec->channels = rf_vals_3x;
7544 break;
7545
7546 case RF5592:
7547 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, ®);
7548 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
7549 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
7550 spec->channels = rf_vals_5592_xtal40;
7551 } else {
7552 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
7553 spec->channels = rf_vals_5592_xtal20;
7554 }
7555 break;
7556 }
7557
7558 if (WARN_ON_ONCE(!spec->channels))
7559 return -ENODEV;
7560
7561 spec->supported_bands = SUPPORT_BAND_2GHZ;
7562 if (spec->num_channels > 14)
7563 spec->supported_bands |= SUPPORT_BAND_5GHZ;
7564
7565 /*
7566 * Initialize HT information.
7567 */
7568 if (!rt2x00_rf(rt2x00dev, RF2020))
7569 spec->ht.ht_supported = true;
7570 else
7571 spec->ht.ht_supported = false;
7572
7573 spec->ht.cap =
7574 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
7575 IEEE80211_HT_CAP_GRN_FLD |
7576 IEEE80211_HT_CAP_SGI_20 |
7577 IEEE80211_HT_CAP_SGI_40;
7578
7579 if (rt2x00dev->default_ant.tx_chain_num >= 2)
7580 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
7581
7582 spec->ht.cap |= rt2x00dev->default_ant.rx_chain_num <<
7583 IEEE80211_HT_CAP_RX_STBC_SHIFT;
7584
7585 spec->ht.ampdu_factor = 3;
7586 spec->ht.ampdu_density = 4;
7587 spec->ht.mcs.tx_params =
7588 IEEE80211_HT_MCS_TX_DEFINED |
7589 IEEE80211_HT_MCS_TX_RX_DIFF |
7590 ((rt2x00dev->default_ant.tx_chain_num - 1) <<
7591 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
7592
7593 switch (rt2x00dev->default_ant.rx_chain_num) {
7594 case 3:
7595 spec->ht.mcs.rx_mask[2] = 0xff;
7596 case 2:
7597 spec->ht.mcs.rx_mask[1] = 0xff;
7598 case 1:
7599 spec->ht.mcs.rx_mask[0] = 0xff;
7600 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
7601 break;
7602 }
7603
7604 /*
7605 * Create channel information array
7606 */
7607 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
7608 if (!info)
7609 return -ENOMEM;
7610
7611 spec->channels_info = info;
7612
7613 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
7614 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
7615
7616 if (rt2x00dev->default_ant.tx_chain_num > 2)
7617 default_power3 = rt2800_eeprom_addr(rt2x00dev,
7618 EEPROM_EXT_TXPOWER_BG3);
7619 else
7620 default_power3 = NULL;
7621
7622 for (i = 0; i < 14; i++) {
7623 info[i].default_power1 = default_power1[i];
7624 info[i].default_power2 = default_power2[i];
7625 if (default_power3)
7626 info[i].default_power3 = default_power3[i];
7627 }
7628
7629 if (spec->num_channels > 14) {
7630 default_power1 = rt2800_eeprom_addr(rt2x00dev,
7631 EEPROM_TXPOWER_A1);
7632 default_power2 = rt2800_eeprom_addr(rt2x00dev,
7633 EEPROM_TXPOWER_A2);
7634
7635 if (rt2x00dev->default_ant.tx_chain_num > 2)
7636 default_power3 =
7637 rt2800_eeprom_addr(rt2x00dev,
7638 EEPROM_EXT_TXPOWER_A3);
7639 else
7640 default_power3 = NULL;
7641
7642 for (i = 14; i < spec->num_channels; i++) {
7643 info[i].default_power1 = default_power1[i - 14];
7644 info[i].default_power2 = default_power2[i - 14];
7645 if (default_power3)
7646 info[i].default_power3 = default_power3[i - 14];
7647 }
7648 }
7649
7650 switch (rt2x00dev->chip.rf) {
7651 case RF2020:
7652 case RF3020:
7653 case RF3021:
7654 case RF3022:
7655 case RF3320:
7656 case RF3052:
7657 case RF3053:
7658 case RF3070:
7659 case RF3290:
7660 case RF5360:
7661 case RF5370:
7662 case RF5372:
7663 case RF5390:
7664 case RF5392:
7665 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
7666 break;
7667 }
7668
7669 return 0;
7670}
7671
7672static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
7673{
7674 u32 reg;
7675 u32 rt;
7676 u32 rev;
7677
7678 if (rt2x00_rt(rt2x00dev, RT3290))
7679 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, ®);
7680 else
7681 rt2800_register_read(rt2x00dev, MAC_CSR0, ®);
7682
7683 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
7684 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
7685
7686 switch (rt) {
7687 case RT2860:
7688 case RT2872:
7689 case RT2883:
7690 case RT3070:
7691 case RT3071:
7692 case RT3090:
7693 case RT3290:
7694 case RT3352:
7695 case RT3390:
7696 case RT3572:
7697 case RT3593:
7698 case RT5390:
7699 case RT5392:
7700 case RT5592:
7701 break;
7702 default:
7703 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
7704 rt, rev);
7705 return -ENODEV;
7706 }
7707
7708 rt2x00_set_rt(rt2x00dev, rt, rev);
7709
7710 return 0;
7711}
7712
7713int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
7714{
7715 int retval;
7716 u32 reg;
7717
7718 retval = rt2800_probe_rt(rt2x00dev);
7719 if (retval)
7720 return retval;
7721
7722 /*
7723 * Allocate eeprom data.
7724 */
7725 retval = rt2800_validate_eeprom(rt2x00dev);
7726 if (retval)
7727 return retval;
7728
7729 retval = rt2800_init_eeprom(rt2x00dev);
7730 if (retval)
7731 return retval;
7732
7733 /*
7734 * Enable rfkill polling by setting GPIO direction of the
7735 * rfkill switch GPIO pin correctly.
7736 */
7737 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®);
7738 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1);
7739 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
7740
7741 /*
7742 * Initialize hw specifications.
7743 */
7744 retval = rt2800_probe_hw_mode(rt2x00dev);
7745 if (retval)
7746 return retval;
7747
7748 /*
7749 * Set device capabilities.
7750 */
7751 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
7752 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
7753 if (!rt2x00_is_usb(rt2x00dev))
7754 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
7755
7756 /*
7757 * Set device requirements.
7758 */
7759 if (!rt2x00_is_soc(rt2x00dev))
7760 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
7761 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
7762 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
7763 if (!rt2800_hwcrypt_disabled(rt2x00dev))
7764 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
7765 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
7766 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
7767 if (rt2x00_is_usb(rt2x00dev))
7768 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
7769 else {
7770 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
7771 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
7772 }
7773
7774 /*
7775 * Set the rssi offset.
7776 */
7777 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
7778
7779 return 0;
7780}
7781EXPORT_SYMBOL_GPL(rt2800_probe_hw);
7782
7783/*
7784 * IEEE80211 stack callback functions.
7785 */
7786void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
7787 u16 *iv16)
7788{
7789 struct rt2x00_dev *rt2x00dev = hw->priv;
7790 struct mac_iveiv_entry iveiv_entry;
7791 u32 offset;
7792
7793 offset = MAC_IVEIV_ENTRY(hw_key_idx);
7794 rt2800_register_multiread(rt2x00dev, offset,
7795 &iveiv_entry, sizeof(iveiv_entry));
7796
7797 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
7798 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
7799}
7800EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
7801
7802int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
7803{
7804 struct rt2x00_dev *rt2x00dev = hw->priv;
7805 u32 reg;
7806 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
7807
7808 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
7809 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value);
7810 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
7811
7812 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
7813 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled);
7814 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
7815
7816 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
7817 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled);
7818 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
7819
7820 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
7821 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled);
7822 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
7823
7824 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
7825 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled);
7826 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
7827
7828 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
7829 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled);
7830 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
7831
7832 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
7833 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled);
7834 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
7835
7836 return 0;
7837}
7838EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
7839
7840int rt2800_conf_tx(struct ieee80211_hw *hw,
7841 struct ieee80211_vif *vif, u16 queue_idx,
7842 const struct ieee80211_tx_queue_params *params)
7843{
7844 struct rt2x00_dev *rt2x00dev = hw->priv;
7845 struct data_queue *queue;
7846 struct rt2x00_field32 field;
7847 int retval;
7848 u32 reg;
7849 u32 offset;
7850
7851 /*
7852 * First pass the configuration through rt2x00lib, that will
7853 * update the queue settings and validate the input. After that
7854 * we are free to update the registers based on the value
7855 * in the queue parameter.
7856 */
7857 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
7858 if (retval)
7859 return retval;
7860
7861 /*
7862 * We only need to perform additional register initialization
7863 * for WMM queues/
7864 */
7865 if (queue_idx >= 4)
7866 return 0;
7867
7868 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
7869
7870 /* Update WMM TXOP register */
7871 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
7872 field.bit_offset = (queue_idx & 1) * 16;
7873 field.bit_mask = 0xffff << field.bit_offset;
7874
7875 rt2800_register_read(rt2x00dev, offset, ®);
7876 rt2x00_set_field32(®, field, queue->txop);
7877 rt2800_register_write(rt2x00dev, offset, reg);
7878
7879 /* Update WMM registers */
7880 field.bit_offset = queue_idx * 4;
7881 field.bit_mask = 0xf << field.bit_offset;
7882
7883 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®);
7884 rt2x00_set_field32(®, field, queue->aifs);
7885 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
7886
7887 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®);
7888 rt2x00_set_field32(®, field, queue->cw_min);
7889 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
7890
7891 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®);
7892 rt2x00_set_field32(®, field, queue->cw_max);
7893 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
7894
7895 /* Update EDCA registers */
7896 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
7897
7898 rt2800_register_read(rt2x00dev, offset, ®);
7899 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
7900 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
7901 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
7902 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);
7903 rt2800_register_write(rt2x00dev, offset, reg);
7904
7905 return 0;
7906}
7907EXPORT_SYMBOL_GPL(rt2800_conf_tx);
7908
7909u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
7910{
7911 struct rt2x00_dev *rt2x00dev = hw->priv;
7912 u64 tsf;
7913 u32 reg;
7914
7915 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®);
7916 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
7917 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®);
7918 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
7919
7920 return tsf;
7921}
7922EXPORT_SYMBOL_GPL(rt2800_get_tsf);
7923
7924int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
7925 enum ieee80211_ampdu_mlme_action action,
7926 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
7927 u8 buf_size)
7928{
7929 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
7930 int ret = 0;
7931
7932 /*
7933 * Don't allow aggregation for stations the hardware isn't aware
7934 * of because tx status reports for frames to an unknown station
7935 * always contain wcid=255 and thus we can't distinguish between
7936 * multiple stations which leads to unwanted situations when the
7937 * hw reorders frames due to aggregation.
7938 */
7939 if (sta_priv->wcid < 0)
7940 return 1;
7941
7942 switch (action) {
7943 case IEEE80211_AMPDU_RX_START:
7944 case IEEE80211_AMPDU_RX_STOP:
7945 /*
7946 * The hw itself takes care of setting up BlockAck mechanisms.
7947 * So, we only have to allow mac80211 to nagotiate a BlockAck
7948 * agreement. Once that is done, the hw will BlockAck incoming
7949 * AMPDUs without further setup.
7950 */
7951 break;
7952 case IEEE80211_AMPDU_TX_START:
7953 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7954 break;
7955 case IEEE80211_AMPDU_TX_STOP_CONT:
7956 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7957 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7958 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
7959 break;
7960 case IEEE80211_AMPDU_TX_OPERATIONAL:
7961 break;
7962 default:
7963 rt2x00_warn((struct rt2x00_dev *)hw->priv,
7964 "Unknown AMPDU action\n");
7965 }
7966
7967 return ret;
7968}
7969EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
7970
7971int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
7972 struct survey_info *survey)
7973{
7974 struct rt2x00_dev *rt2x00dev = hw->priv;
7975 struct ieee80211_conf *conf = &hw->conf;
7976 u32 idle, busy, busy_ext;
7977
7978 if (idx != 0)
7979 return -ENOENT;
7980
7981 survey->channel = conf->chandef.chan;
7982
7983 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
7984 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
7985 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
7986
7987 if (idle || busy) {
7988 survey->filled = SURVEY_INFO_CHANNEL_TIME |
7989 SURVEY_INFO_CHANNEL_TIME_BUSY |
7990 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
7991
7992 survey->channel_time = (idle + busy) / 1000;
7993 survey->channel_time_busy = busy / 1000;
7994 survey->channel_time_ext_busy = busy_ext / 1000;
7995 }
7996
7997 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
7998 survey->filled |= SURVEY_INFO_IN_USE;
7999
8000 return 0;
8001
8002}
8003EXPORT_SYMBOL_GPL(rt2800_get_survey);
8004
8005MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
8006MODULE_VERSION(DRV_VERSION);
8007MODULE_DESCRIPTION("Ralink RT2800 library");
8008MODULE_LICENSE("GPL");