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1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/etherdevice.h>
32#include <linux/sched.h>
33#include <linux/slab.h>
34#include <linux/types.h>
35#include <linux/lockdep.h>
36#include <linux/pci.h>
37#include <linux/dma-mapping.h>
38#include <linux/delay.h>
39#include <linux/skbuff.h>
40#include <net/mac80211.h>
41
42#include "common.h"
43
44int
45_il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
46{
47 const int interval = 10; /* microseconds */
48 int t = 0;
49
50 do {
51 if ((_il_rd(il, addr) & mask) == (bits & mask))
52 return t;
53 udelay(interval);
54 t += interval;
55 } while (t < timeout);
56
57 return -ETIMEDOUT;
58}
59EXPORT_SYMBOL(_il_poll_bit);
60
61void
62il_set_bit(struct il_priv *p, u32 r, u32 m)
63{
64 unsigned long reg_flags;
65
66 spin_lock_irqsave(&p->reg_lock, reg_flags);
67 _il_set_bit(p, r, m);
68 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
69}
70EXPORT_SYMBOL(il_set_bit);
71
72void
73il_clear_bit(struct il_priv *p, u32 r, u32 m)
74{
75 unsigned long reg_flags;
76
77 spin_lock_irqsave(&p->reg_lock, reg_flags);
78 _il_clear_bit(p, r, m);
79 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
80}
81EXPORT_SYMBOL(il_clear_bit);
82
83bool
84_il_grab_nic_access(struct il_priv *il)
85{
86 int ret;
87 u32 val;
88
89 /* this bit wakes up the NIC */
90 _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
91
92 /*
93 * These bits say the device is running, and should keep running for
94 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
95 * but they do not indicate that embedded SRAM is restored yet;
96 * 3945 and 4965 have volatile SRAM, and must save/restore contents
97 * to/from host DRAM when sleeping/waking for power-saving.
98 * Each direction takes approximately 1/4 millisecond; with this
99 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
100 * series of register accesses are expected (e.g. reading Event Log),
101 * to keep device from sleeping.
102 *
103 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
104 * SRAM is okay/restored. We don't check that here because this call
105 * is just for hardware register access; but GP1 MAC_SLEEP check is a
106 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
107 *
108 */
109 ret =
110 _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
111 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
112 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
113 if (unlikely(ret < 0)) {
114 val = _il_rd(il, CSR_GP_CNTRL);
115 WARN_ONCE(1, "Timeout waiting for ucode processor access "
116 "(CSR_GP_CNTRL 0x%08x)\n", val);
117 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
118 return false;
119 }
120
121 return true;
122}
123EXPORT_SYMBOL_GPL(_il_grab_nic_access);
124
125int
126il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
127{
128 const int interval = 10; /* microseconds */
129 int t = 0;
130
131 do {
132 if ((il_rd(il, addr) & mask) == mask)
133 return t;
134 udelay(interval);
135 t += interval;
136 } while (t < timeout);
137
138 return -ETIMEDOUT;
139}
140EXPORT_SYMBOL(il_poll_bit);
141
142u32
143il_rd_prph(struct il_priv *il, u32 reg)
144{
145 unsigned long reg_flags;
146 u32 val;
147
148 spin_lock_irqsave(&il->reg_lock, reg_flags);
149 _il_grab_nic_access(il);
150 val = _il_rd_prph(il, reg);
151 _il_release_nic_access(il);
152 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
153 return val;
154}
155EXPORT_SYMBOL(il_rd_prph);
156
157void
158il_wr_prph(struct il_priv *il, u32 addr, u32 val)
159{
160 unsigned long reg_flags;
161
162 spin_lock_irqsave(&il->reg_lock, reg_flags);
163 if (likely(_il_grab_nic_access(il))) {
164 _il_wr_prph(il, addr, val);
165 _il_release_nic_access(il);
166 }
167 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
168}
169EXPORT_SYMBOL(il_wr_prph);
170
171u32
172il_read_targ_mem(struct il_priv *il, u32 addr)
173{
174 unsigned long reg_flags;
175 u32 value;
176
177 spin_lock_irqsave(&il->reg_lock, reg_flags);
178 _il_grab_nic_access(il);
179
180 _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
181 value = _il_rd(il, HBUS_TARG_MEM_RDAT);
182
183 _il_release_nic_access(il);
184 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
185 return value;
186}
187EXPORT_SYMBOL(il_read_targ_mem);
188
189void
190il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
191{
192 unsigned long reg_flags;
193
194 spin_lock_irqsave(&il->reg_lock, reg_flags);
195 if (likely(_il_grab_nic_access(il))) {
196 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
197 _il_wr(il, HBUS_TARG_MEM_WDAT, val);
198 _il_release_nic_access(il);
199 }
200 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
201}
202EXPORT_SYMBOL(il_write_targ_mem);
203
204const char *
205il_get_cmd_string(u8 cmd)
206{
207 switch (cmd) {
208 IL_CMD(N_ALIVE);
209 IL_CMD(N_ERROR);
210 IL_CMD(C_RXON);
211 IL_CMD(C_RXON_ASSOC);
212 IL_CMD(C_QOS_PARAM);
213 IL_CMD(C_RXON_TIMING);
214 IL_CMD(C_ADD_STA);
215 IL_CMD(C_REM_STA);
216 IL_CMD(C_WEPKEY);
217 IL_CMD(N_3945_RX);
218 IL_CMD(C_TX);
219 IL_CMD(C_RATE_SCALE);
220 IL_CMD(C_LEDS);
221 IL_CMD(C_TX_LINK_QUALITY_CMD);
222 IL_CMD(C_CHANNEL_SWITCH);
223 IL_CMD(N_CHANNEL_SWITCH);
224 IL_CMD(C_SPECTRUM_MEASUREMENT);
225 IL_CMD(N_SPECTRUM_MEASUREMENT);
226 IL_CMD(C_POWER_TBL);
227 IL_CMD(N_PM_SLEEP);
228 IL_CMD(N_PM_DEBUG_STATS);
229 IL_CMD(C_SCAN);
230 IL_CMD(C_SCAN_ABORT);
231 IL_CMD(N_SCAN_START);
232 IL_CMD(N_SCAN_RESULTS);
233 IL_CMD(N_SCAN_COMPLETE);
234 IL_CMD(N_BEACON);
235 IL_CMD(C_TX_BEACON);
236 IL_CMD(C_TX_PWR_TBL);
237 IL_CMD(C_BT_CONFIG);
238 IL_CMD(C_STATS);
239 IL_CMD(N_STATS);
240 IL_CMD(N_CARD_STATE);
241 IL_CMD(N_MISSED_BEACONS);
242 IL_CMD(C_CT_KILL_CONFIG);
243 IL_CMD(C_SENSITIVITY);
244 IL_CMD(C_PHY_CALIBRATION);
245 IL_CMD(N_RX_PHY);
246 IL_CMD(N_RX_MPDU);
247 IL_CMD(N_RX);
248 IL_CMD(N_COMPRESSED_BA);
249 default:
250 return "UNKNOWN";
251
252 }
253}
254EXPORT_SYMBOL(il_get_cmd_string);
255
256#define HOST_COMPLETE_TIMEOUT (HZ / 2)
257
258static void
259il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
260 struct il_rx_pkt *pkt)
261{
262 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
263 IL_ERR("Bad return from %s (0x%08X)\n",
264 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
265 return;
266 }
267#ifdef CONFIG_IWLEGACY_DEBUG
268 switch (cmd->hdr.cmd) {
269 case C_TX_LINK_QUALITY_CMD:
270 case C_SENSITIVITY:
271 D_HC_DUMP("back from %s (0x%08X)\n",
272 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
273 break;
274 default:
275 D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
276 pkt->hdr.flags);
277 }
278#endif
279}
280
281static int
282il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
283{
284 int ret;
285
286 BUG_ON(!(cmd->flags & CMD_ASYNC));
287
288 /* An asynchronous command can not expect an SKB to be set. */
289 BUG_ON(cmd->flags & CMD_WANT_SKB);
290
291 /* Assign a generic callback if one is not provided */
292 if (!cmd->callback)
293 cmd->callback = il_generic_cmd_callback;
294
295 if (test_bit(S_EXIT_PENDING, &il->status))
296 return -EBUSY;
297
298 ret = il_enqueue_hcmd(il, cmd);
299 if (ret < 0) {
300 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
301 il_get_cmd_string(cmd->id), ret);
302 return ret;
303 }
304 return 0;
305}
306
307int
308il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
309{
310 int cmd_idx;
311 int ret;
312
313 lockdep_assert_held(&il->mutex);
314
315 BUG_ON(cmd->flags & CMD_ASYNC);
316
317 /* A synchronous command can not have a callback set. */
318 BUG_ON(cmd->callback);
319
320 D_INFO("Attempting to send sync command %s\n",
321 il_get_cmd_string(cmd->id));
322
323 set_bit(S_HCMD_ACTIVE, &il->status);
324 D_INFO("Setting HCMD_ACTIVE for command %s\n",
325 il_get_cmd_string(cmd->id));
326
327 cmd_idx = il_enqueue_hcmd(il, cmd);
328 if (cmd_idx < 0) {
329 ret = cmd_idx;
330 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
331 il_get_cmd_string(cmd->id), ret);
332 goto out;
333 }
334
335 ret = wait_event_timeout(il->wait_command_queue,
336 !test_bit(S_HCMD_ACTIVE, &il->status),
337 HOST_COMPLETE_TIMEOUT);
338 if (!ret) {
339 if (test_bit(S_HCMD_ACTIVE, &il->status)) {
340 IL_ERR("Error sending %s: time out after %dms.\n",
341 il_get_cmd_string(cmd->id),
342 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
343
344 clear_bit(S_HCMD_ACTIVE, &il->status);
345 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
346 il_get_cmd_string(cmd->id));
347 ret = -ETIMEDOUT;
348 goto cancel;
349 }
350 }
351
352 if (test_bit(S_RFKILL, &il->status)) {
353 IL_ERR("Command %s aborted: RF KILL Switch\n",
354 il_get_cmd_string(cmd->id));
355 ret = -ECANCELED;
356 goto fail;
357 }
358 if (test_bit(S_FW_ERROR, &il->status)) {
359 IL_ERR("Command %s failed: FW Error\n",
360 il_get_cmd_string(cmd->id));
361 ret = -EIO;
362 goto fail;
363 }
364 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
365 IL_ERR("Error: Response NULL in '%s'\n",
366 il_get_cmd_string(cmd->id));
367 ret = -EIO;
368 goto cancel;
369 }
370
371 ret = 0;
372 goto out;
373
374cancel:
375 if (cmd->flags & CMD_WANT_SKB) {
376 /*
377 * Cancel the CMD_WANT_SKB flag for the cmd in the
378 * TX cmd queue. Otherwise in case the cmd comes
379 * in later, it will possibly set an invalid
380 * address (cmd->meta.source).
381 */
382 il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
383 }
384fail:
385 if (cmd->reply_page) {
386 il_free_pages(il, cmd->reply_page);
387 cmd->reply_page = 0;
388 }
389out:
390 return ret;
391}
392EXPORT_SYMBOL(il_send_cmd_sync);
393
394int
395il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
396{
397 if (cmd->flags & CMD_ASYNC)
398 return il_send_cmd_async(il, cmd);
399
400 return il_send_cmd_sync(il, cmd);
401}
402EXPORT_SYMBOL(il_send_cmd);
403
404int
405il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
406{
407 struct il_host_cmd cmd = {
408 .id = id,
409 .len = len,
410 .data = data,
411 };
412
413 return il_send_cmd_sync(il, &cmd);
414}
415EXPORT_SYMBOL(il_send_cmd_pdu);
416
417int
418il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
419 void (*callback) (struct il_priv *il,
420 struct il_device_cmd *cmd,
421 struct il_rx_pkt *pkt))
422{
423 struct il_host_cmd cmd = {
424 .id = id,
425 .len = len,
426 .data = data,
427 };
428
429 cmd.flags |= CMD_ASYNC;
430 cmd.callback = callback;
431
432 return il_send_cmd_async(il, &cmd);
433}
434EXPORT_SYMBOL(il_send_cmd_pdu_async);
435
436/* default: IL_LED_BLINK(0) using blinking idx table */
437static int led_mode;
438module_param(led_mode, int, S_IRUGO);
439MODULE_PARM_DESC(led_mode,
440 "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
441
442/* Throughput OFF time(ms) ON time (ms)
443 * >300 25 25
444 * >200 to 300 40 40
445 * >100 to 200 55 55
446 * >70 to 100 65 65
447 * >50 to 70 75 75
448 * >20 to 50 85 85
449 * >10 to 20 95 95
450 * >5 to 10 110 110
451 * >1 to 5 130 130
452 * >0 to 1 167 167
453 * <=0 SOLID ON
454 */
455static const struct ieee80211_tpt_blink il_blink[] = {
456 {.throughput = 0, .blink_time = 334},
457 {.throughput = 1 * 1024 - 1, .blink_time = 260},
458 {.throughput = 5 * 1024 - 1, .blink_time = 220},
459 {.throughput = 10 * 1024 - 1, .blink_time = 190},
460 {.throughput = 20 * 1024 - 1, .blink_time = 170},
461 {.throughput = 50 * 1024 - 1, .blink_time = 150},
462 {.throughput = 70 * 1024 - 1, .blink_time = 130},
463 {.throughput = 100 * 1024 - 1, .blink_time = 110},
464 {.throughput = 200 * 1024 - 1, .blink_time = 80},
465 {.throughput = 300 * 1024 - 1, .blink_time = 50},
466};
467
468/*
469 * Adjust led blink rate to compensate on a MAC Clock difference on every HW
470 * Led blink rate analysis showed an average deviation of 0% on 3945,
471 * 5% on 4965 HW.
472 * Need to compensate on the led on/off time per HW according to the deviation
473 * to achieve the desired led frequency
474 * The calculation is: (100-averageDeviation)/100 * blinkTime
475 * For code efficiency the calculation will be:
476 * compensation = (100 - averageDeviation) * 64 / 100
477 * NewBlinkTime = (compensation * BlinkTime) / 64
478 */
479static inline u8
480il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
481{
482 if (!compensation) {
483 IL_ERR("undefined blink compensation: "
484 "use pre-defined blinking time\n");
485 return time;
486 }
487
488 return (u8) ((time * compensation) >> 6);
489}
490
491/* Set led pattern command */
492static int
493il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
494{
495 struct il_led_cmd led_cmd = {
496 .id = IL_LED_LINK,
497 .interval = IL_DEF_LED_INTRVL
498 };
499 int ret;
500
501 if (!test_bit(S_READY, &il->status))
502 return -EBUSY;
503
504 if (il->blink_on == on && il->blink_off == off)
505 return 0;
506
507 if (off == 0) {
508 /* led is SOLID_ON */
509 on = IL_LED_SOLID;
510 }
511
512 D_LED("Led blink time compensation=%u\n",
513 il->cfg->led_compensation);
514 led_cmd.on =
515 il_blink_compensation(il, on,
516 il->cfg->led_compensation);
517 led_cmd.off =
518 il_blink_compensation(il, off,
519 il->cfg->led_compensation);
520
521 ret = il->ops->send_led_cmd(il, &led_cmd);
522 if (!ret) {
523 il->blink_on = on;
524 il->blink_off = off;
525 }
526 return ret;
527}
528
529static void
530il_led_brightness_set(struct led_classdev *led_cdev,
531 enum led_brightness brightness)
532{
533 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
534 unsigned long on = 0;
535
536 if (brightness > 0)
537 on = IL_LED_SOLID;
538
539 il_led_cmd(il, on, 0);
540}
541
542static int
543il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
544 unsigned long *delay_off)
545{
546 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
547
548 return il_led_cmd(il, *delay_on, *delay_off);
549}
550
551void
552il_leds_init(struct il_priv *il)
553{
554 int mode = led_mode;
555 int ret;
556
557 if (mode == IL_LED_DEFAULT)
558 mode = il->cfg->led_mode;
559
560 il->led.name =
561 kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
562 il->led.brightness_set = il_led_brightness_set;
563 il->led.blink_set = il_led_blink_set;
564 il->led.max_brightness = 1;
565
566 switch (mode) {
567 case IL_LED_DEFAULT:
568 WARN_ON(1);
569 break;
570 case IL_LED_BLINK:
571 il->led.default_trigger =
572 ieee80211_create_tpt_led_trigger(il->hw,
573 IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
574 il_blink,
575 ARRAY_SIZE(il_blink));
576 break;
577 case IL_LED_RF_STATE:
578 il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
579 break;
580 }
581
582 ret = led_classdev_register(&il->pci_dev->dev, &il->led);
583 if (ret) {
584 kfree(il->led.name);
585 return;
586 }
587
588 il->led_registered = true;
589}
590EXPORT_SYMBOL(il_leds_init);
591
592void
593il_leds_exit(struct il_priv *il)
594{
595 if (!il->led_registered)
596 return;
597
598 led_classdev_unregister(&il->led);
599 kfree(il->led.name);
600}
601EXPORT_SYMBOL(il_leds_exit);
602
603/************************** EEPROM BANDS ****************************
604 *
605 * The il_eeprom_band definitions below provide the mapping from the
606 * EEPROM contents to the specific channel number supported for each
607 * band.
608 *
609 * For example, il_priv->eeprom.band_3_channels[4] from the band_3
610 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
611 * The specific geography and calibration information for that channel
612 * is contained in the eeprom map itself.
613 *
614 * During init, we copy the eeprom information and channel map
615 * information into il->channel_info_24/52 and il->channel_map_24/52
616 *
617 * channel_map_24/52 provides the idx in the channel_info array for a
618 * given channel. We have to have two separate maps as there is channel
619 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
620 * band_2
621 *
622 * A value of 0xff stored in the channel_map indicates that the channel
623 * is not supported by the hardware at all.
624 *
625 * A value of 0xfe in the channel_map indicates that the channel is not
626 * valid for Tx with the current hardware. This means that
627 * while the system can tune and receive on a given channel, it may not
628 * be able to associate or transmit any frames on that
629 * channel. There is no corresponding channel information for that
630 * entry.
631 *
632 *********************************************************************/
633
634/* 2.4 GHz */
635const u8 il_eeprom_band_1[14] = {
636 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
637};
638
639/* 5.2 GHz bands */
640static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
641 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
642};
643
644static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
645 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
646};
647
648static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
649 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
650};
651
652static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
653 145, 149, 153, 157, 161, 165
654};
655
656static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
657 1, 2, 3, 4, 5, 6, 7
658};
659
660static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
661 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
662};
663
664/******************************************************************************
665 *
666 * EEPROM related functions
667 *
668******************************************************************************/
669
670static int
671il_eeprom_verify_signature(struct il_priv *il)
672{
673 u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
674 int ret = 0;
675
676 D_EEPROM("EEPROM signature=0x%08x\n", gp);
677 switch (gp) {
678 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
679 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
680 break;
681 default:
682 IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
683 ret = -ENOENT;
684 break;
685 }
686 return ret;
687}
688
689const u8 *
690il_eeprom_query_addr(const struct il_priv *il, size_t offset)
691{
692 BUG_ON(offset >= il->cfg->eeprom_size);
693 return &il->eeprom[offset];
694}
695EXPORT_SYMBOL(il_eeprom_query_addr);
696
697u16
698il_eeprom_query16(const struct il_priv *il, size_t offset)
699{
700 if (!il->eeprom)
701 return 0;
702 return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
703}
704EXPORT_SYMBOL(il_eeprom_query16);
705
706/**
707 * il_eeprom_init - read EEPROM contents
708 *
709 * Load the EEPROM contents from adapter into il->eeprom
710 *
711 * NOTE: This routine uses the non-debug IO access functions.
712 */
713int
714il_eeprom_init(struct il_priv *il)
715{
716 __le16 *e;
717 u32 gp = _il_rd(il, CSR_EEPROM_GP);
718 int sz;
719 int ret;
720 u16 addr;
721
722 /* allocate eeprom */
723 sz = il->cfg->eeprom_size;
724 D_EEPROM("NVM size = %d\n", sz);
725 il->eeprom = kzalloc(sz, GFP_KERNEL);
726 if (!il->eeprom) {
727 ret = -ENOMEM;
728 goto alloc_err;
729 }
730 e = (__le16 *) il->eeprom;
731
732 il->ops->apm_init(il);
733
734 ret = il_eeprom_verify_signature(il);
735 if (ret < 0) {
736 IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
737 ret = -ENOENT;
738 goto err;
739 }
740
741 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
742 ret = il->ops->eeprom_acquire_semaphore(il);
743 if (ret < 0) {
744 IL_ERR("Failed to acquire EEPROM semaphore.\n");
745 ret = -ENOENT;
746 goto err;
747 }
748
749 /* eeprom is an array of 16bit values */
750 for (addr = 0; addr < sz; addr += sizeof(u16)) {
751 u32 r;
752
753 _il_wr(il, CSR_EEPROM_REG,
754 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
755
756 ret =
757 _il_poll_bit(il, CSR_EEPROM_REG,
758 CSR_EEPROM_REG_READ_VALID_MSK,
759 CSR_EEPROM_REG_READ_VALID_MSK,
760 IL_EEPROM_ACCESS_TIMEOUT);
761 if (ret < 0) {
762 IL_ERR("Time out reading EEPROM[%d]\n", addr);
763 goto done;
764 }
765 r = _il_rd(il, CSR_EEPROM_REG);
766 e[addr / 2] = cpu_to_le16(r >> 16);
767 }
768
769 D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
770 il_eeprom_query16(il, EEPROM_VERSION));
771
772 ret = 0;
773done:
774 il->ops->eeprom_release_semaphore(il);
775
776err:
777 if (ret)
778 il_eeprom_free(il);
779 /* Reset chip to save power until we load uCode during "up". */
780 il_apm_stop(il);
781alloc_err:
782 return ret;
783}
784EXPORT_SYMBOL(il_eeprom_init);
785
786void
787il_eeprom_free(struct il_priv *il)
788{
789 kfree(il->eeprom);
790 il->eeprom = NULL;
791}
792EXPORT_SYMBOL(il_eeprom_free);
793
794static void
795il_init_band_reference(const struct il_priv *il, int eep_band,
796 int *eeprom_ch_count,
797 const struct il_eeprom_channel **eeprom_ch_info,
798 const u8 **eeprom_ch_idx)
799{
800 u32 offset = il->cfg->regulatory_bands[eep_band - 1];
801
802 switch (eep_band) {
803 case 1: /* 2.4GHz band */
804 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
805 *eeprom_ch_info =
806 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
807 offset);
808 *eeprom_ch_idx = il_eeprom_band_1;
809 break;
810 case 2: /* 4.9GHz band */
811 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
812 *eeprom_ch_info =
813 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
814 offset);
815 *eeprom_ch_idx = il_eeprom_band_2;
816 break;
817 case 3: /* 5.2GHz band */
818 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
819 *eeprom_ch_info =
820 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
821 offset);
822 *eeprom_ch_idx = il_eeprom_band_3;
823 break;
824 case 4: /* 5.5GHz band */
825 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
826 *eeprom_ch_info =
827 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
828 offset);
829 *eeprom_ch_idx = il_eeprom_band_4;
830 break;
831 case 5: /* 5.7GHz band */
832 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
833 *eeprom_ch_info =
834 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
835 offset);
836 *eeprom_ch_idx = il_eeprom_band_5;
837 break;
838 case 6: /* 2.4GHz ht40 channels */
839 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
840 *eeprom_ch_info =
841 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
842 offset);
843 *eeprom_ch_idx = il_eeprom_band_6;
844 break;
845 case 7: /* 5 GHz ht40 channels */
846 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
847 *eeprom_ch_info =
848 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
849 offset);
850 *eeprom_ch_idx = il_eeprom_band_7;
851 break;
852 default:
853 BUG();
854 }
855}
856
857#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
858 ? # x " " : "")
859/**
860 * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
861 *
862 * Does not set up a command, or touch hardware.
863 */
864static int
865il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel,
866 const struct il_eeprom_channel *eeprom_ch,
867 u8 clear_ht40_extension_channel)
868{
869 struct il_channel_info *ch_info;
870
871 ch_info =
872 (struct il_channel_info *)il_get_channel_info(il, band, channel);
873
874 if (!il_is_channel_valid(ch_info))
875 return -1;
876
877 D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
878 " Ad-Hoc %ssupported\n", ch_info->channel,
879 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
880 CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
881 CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
882 CHECK_AND_PRINT(DFS), eeprom_ch->flags,
883 eeprom_ch->max_power_avg,
884 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
885 !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
886
887 ch_info->ht40_eeprom = *eeprom_ch;
888 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
889 ch_info->ht40_flags = eeprom_ch->flags;
890 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
891 ch_info->ht40_extension_channel &=
892 ~clear_ht40_extension_channel;
893
894 return 0;
895}
896
897#define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
898 ? # x " " : "")
899
900/**
901 * il_init_channel_map - Set up driver's info for all possible channels
902 */
903int
904il_init_channel_map(struct il_priv *il)
905{
906 int eeprom_ch_count = 0;
907 const u8 *eeprom_ch_idx = NULL;
908 const struct il_eeprom_channel *eeprom_ch_info = NULL;
909 int band, ch;
910 struct il_channel_info *ch_info;
911
912 if (il->channel_count) {
913 D_EEPROM("Channel map already initialized.\n");
914 return 0;
915 }
916
917 D_EEPROM("Initializing regulatory info from EEPROM\n");
918
919 il->channel_count =
920 ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
921 ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
922 ARRAY_SIZE(il_eeprom_band_5);
923
924 D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
925
926 il->channel_info =
927 kzalloc(sizeof(struct il_channel_info) * il->channel_count,
928 GFP_KERNEL);
929 if (!il->channel_info) {
930 IL_ERR("Could not allocate channel_info\n");
931 il->channel_count = 0;
932 return -ENOMEM;
933 }
934
935 ch_info = il->channel_info;
936
937 /* Loop through the 5 EEPROM bands adding them in order to the
938 * channel map we maintain (that contains additional information than
939 * what just in the EEPROM) */
940 for (band = 1; band <= 5; band++) {
941
942 il_init_band_reference(il, band, &eeprom_ch_count,
943 &eeprom_ch_info, &eeprom_ch_idx);
944
945 /* Loop through each band adding each of the channels */
946 for (ch = 0; ch < eeprom_ch_count; ch++) {
947 ch_info->channel = eeprom_ch_idx[ch];
948 ch_info->band =
949 (band ==
950 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
951
952 /* permanently store EEPROM's channel regulatory flags
953 * and max power in channel info database. */
954 ch_info->eeprom = eeprom_ch_info[ch];
955
956 /* Copy the run-time flags so they are there even on
957 * invalid channels */
958 ch_info->flags = eeprom_ch_info[ch].flags;
959 /* First write that ht40 is not enabled, and then enable
960 * one by one */
961 ch_info->ht40_extension_channel =
962 IEEE80211_CHAN_NO_HT40;
963
964 if (!(il_is_channel_valid(ch_info))) {
965 D_EEPROM("Ch. %d Flags %x [%sGHz] - "
966 "No traffic\n", ch_info->channel,
967 ch_info->flags,
968 il_is_channel_a_band(ch_info) ? "5.2" :
969 "2.4");
970 ch_info++;
971 continue;
972 }
973
974 /* Initialize regulatory-based run-time data */
975 ch_info->max_power_avg = ch_info->curr_txpow =
976 eeprom_ch_info[ch].max_power_avg;
977 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
978 ch_info->min_power = 0;
979
980 D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
981 " Ad-Hoc %ssupported\n", ch_info->channel,
982 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
983 CHECK_AND_PRINT_I(VALID),
984 CHECK_AND_PRINT_I(IBSS),
985 CHECK_AND_PRINT_I(ACTIVE),
986 CHECK_AND_PRINT_I(RADAR),
987 CHECK_AND_PRINT_I(WIDE),
988 CHECK_AND_PRINT_I(DFS),
989 eeprom_ch_info[ch].flags,
990 eeprom_ch_info[ch].max_power_avg,
991 ((eeprom_ch_info[ch].
992 flags & EEPROM_CHANNEL_IBSS) &&
993 !(eeprom_ch_info[ch].
994 flags & EEPROM_CHANNEL_RADAR)) ? "" :
995 "not ");
996
997 ch_info++;
998 }
999 }
1000
1001 /* Check if we do have HT40 channels */
1002 if (il->cfg->regulatory_bands[5] == EEPROM_REGULATORY_BAND_NO_HT40 &&
1003 il->cfg->regulatory_bands[6] == EEPROM_REGULATORY_BAND_NO_HT40)
1004 return 0;
1005
1006 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
1007 for (band = 6; band <= 7; band++) {
1008 enum ieee80211_band ieeeband;
1009
1010 il_init_band_reference(il, band, &eeprom_ch_count,
1011 &eeprom_ch_info, &eeprom_ch_idx);
1012
1013 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1014 ieeeband =
1015 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
1016
1017 /* Loop through each band adding each of the channels */
1018 for (ch = 0; ch < eeprom_ch_count; ch++) {
1019 /* Set up driver's info for lower half */
1020 il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
1021 &eeprom_ch_info[ch],
1022 IEEE80211_CHAN_NO_HT40PLUS);
1023
1024 /* Set up driver's info for upper half */
1025 il_mod_ht40_chan_info(il, ieeeband,
1026 eeprom_ch_idx[ch] + 4,
1027 &eeprom_ch_info[ch],
1028 IEEE80211_CHAN_NO_HT40MINUS);
1029 }
1030 }
1031
1032 return 0;
1033}
1034EXPORT_SYMBOL(il_init_channel_map);
1035
1036/*
1037 * il_free_channel_map - undo allocations in il_init_channel_map
1038 */
1039void
1040il_free_channel_map(struct il_priv *il)
1041{
1042 kfree(il->channel_info);
1043 il->channel_count = 0;
1044}
1045EXPORT_SYMBOL(il_free_channel_map);
1046
1047/**
1048 * il_get_channel_info - Find driver's ilate channel info
1049 *
1050 * Based on band and channel number.
1051 */
1052const struct il_channel_info *
1053il_get_channel_info(const struct il_priv *il, enum ieee80211_band band,
1054 u16 channel)
1055{
1056 int i;
1057
1058 switch (band) {
1059 case IEEE80211_BAND_5GHZ:
1060 for (i = 14; i < il->channel_count; i++) {
1061 if (il->channel_info[i].channel == channel)
1062 return &il->channel_info[i];
1063 }
1064 break;
1065 case IEEE80211_BAND_2GHZ:
1066 if (channel >= 1 && channel <= 14)
1067 return &il->channel_info[channel - 1];
1068 break;
1069 default:
1070 BUG();
1071 }
1072
1073 return NULL;
1074}
1075EXPORT_SYMBOL(il_get_channel_info);
1076
1077/*
1078 * Setting power level allows the card to go to sleep when not busy.
1079 *
1080 * We calculate a sleep command based on the required latency, which
1081 * we get from mac80211.
1082 */
1083
1084#define SLP_VEC(X0, X1, X2, X3, X4) { \
1085 cpu_to_le32(X0), \
1086 cpu_to_le32(X1), \
1087 cpu_to_le32(X2), \
1088 cpu_to_le32(X3), \
1089 cpu_to_le32(X4) \
1090}
1091
1092static void
1093il_build_powertable_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
1094{
1095 const __le32 interval[3][IL_POWER_VEC_SIZE] = {
1096 SLP_VEC(2, 2, 4, 6, 0xFF),
1097 SLP_VEC(2, 4, 7, 10, 10),
1098 SLP_VEC(4, 7, 10, 10, 0xFF)
1099 };
1100 int i, dtim_period, no_dtim;
1101 u32 max_sleep;
1102 bool skip;
1103
1104 memset(cmd, 0, sizeof(*cmd));
1105
1106 if (il->power_data.pci_pm)
1107 cmd->flags |= IL_POWER_PCI_PM_MSK;
1108
1109 /* if no Power Save, we are done */
1110 if (il->power_data.ps_disabled)
1111 return;
1112
1113 cmd->flags = IL_POWER_DRIVER_ALLOW_SLEEP_MSK;
1114 cmd->keep_alive_seconds = 0;
1115 cmd->debug_flags = 0;
1116 cmd->rx_data_timeout = cpu_to_le32(25 * 1024);
1117 cmd->tx_data_timeout = cpu_to_le32(25 * 1024);
1118 cmd->keep_alive_beacons = 0;
1119
1120 dtim_period = il->vif ? il->vif->bss_conf.dtim_period : 0;
1121
1122 if (dtim_period <= 2) {
1123 memcpy(cmd->sleep_interval, interval[0], sizeof(interval[0]));
1124 no_dtim = 2;
1125 } else if (dtim_period <= 10) {
1126 memcpy(cmd->sleep_interval, interval[1], sizeof(interval[1]));
1127 no_dtim = 2;
1128 } else {
1129 memcpy(cmd->sleep_interval, interval[2], sizeof(interval[2]));
1130 no_dtim = 0;
1131 }
1132
1133 if (dtim_period == 0) {
1134 dtim_period = 1;
1135 skip = false;
1136 } else {
1137 skip = !!no_dtim;
1138 }
1139
1140 if (skip) {
1141 __le32 tmp = cmd->sleep_interval[IL_POWER_VEC_SIZE - 1];
1142
1143 max_sleep = le32_to_cpu(tmp);
1144 if (max_sleep == 0xFF)
1145 max_sleep = dtim_period * (skip + 1);
1146 else if (max_sleep > dtim_period)
1147 max_sleep = (max_sleep / dtim_period) * dtim_period;
1148 cmd->flags |= IL_POWER_SLEEP_OVER_DTIM_MSK;
1149 } else {
1150 max_sleep = dtim_period;
1151 cmd->flags &= ~IL_POWER_SLEEP_OVER_DTIM_MSK;
1152 }
1153
1154 for (i = 0; i < IL_POWER_VEC_SIZE; i++)
1155 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1156 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
1157}
1158
1159static int
1160il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
1161{
1162 D_POWER("Sending power/sleep command\n");
1163 D_POWER("Flags value = 0x%08X\n", cmd->flags);
1164 D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1165 D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1166 D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1167 le32_to_cpu(cmd->sleep_interval[0]),
1168 le32_to_cpu(cmd->sleep_interval[1]),
1169 le32_to_cpu(cmd->sleep_interval[2]),
1170 le32_to_cpu(cmd->sleep_interval[3]),
1171 le32_to_cpu(cmd->sleep_interval[4]));
1172
1173 return il_send_cmd_pdu(il, C_POWER_TBL,
1174 sizeof(struct il_powertable_cmd), cmd);
1175}
1176
1177static int
1178il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
1179{
1180 int ret;
1181 bool update_chains;
1182
1183 lockdep_assert_held(&il->mutex);
1184
1185 /* Don't update the RX chain when chain noise calibration is running */
1186 update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
1187 il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
1188
1189 if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
1190 return 0;
1191
1192 if (!il_is_ready_rf(il))
1193 return -EIO;
1194
1195 /* scan complete use sleep_power_next, need to be updated */
1196 memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
1197 if (test_bit(S_SCANNING, &il->status) && !force) {
1198 D_INFO("Defer power set mode while scanning\n");
1199 return 0;
1200 }
1201
1202 if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
1203 set_bit(S_POWER_PMI, &il->status);
1204
1205 ret = il_set_power(il, cmd);
1206 if (!ret) {
1207 if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
1208 clear_bit(S_POWER_PMI, &il->status);
1209
1210 if (il->ops->update_chain_flags && update_chains)
1211 il->ops->update_chain_flags(il);
1212 else if (il->ops->update_chain_flags)
1213 D_POWER("Cannot update the power, chain noise "
1214 "calibration running: %d\n",
1215 il->chain_noise_data.state);
1216
1217 memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
1218 } else
1219 IL_ERR("set power fail, ret = %d", ret);
1220
1221 return ret;
1222}
1223
1224int
1225il_power_update_mode(struct il_priv *il, bool force)
1226{
1227 struct il_powertable_cmd cmd;
1228
1229 il_build_powertable_cmd(il, &cmd);
1230
1231 return il_power_set_mode(il, &cmd, force);
1232}
1233EXPORT_SYMBOL(il_power_update_mode);
1234
1235/* initialize to default */
1236void
1237il_power_initialize(struct il_priv *il)
1238{
1239 u16 lctl;
1240
1241 pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
1242 il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
1243
1244 il->power_data.debug_sleep_level_override = -1;
1245
1246 memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
1247}
1248EXPORT_SYMBOL(il_power_initialize);
1249
1250/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
1251 * sending probe req. This should be set long enough to hear probe responses
1252 * from more than one AP. */
1253#define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
1254#define IL_ACTIVE_DWELL_TIME_52 (20)
1255
1256#define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
1257#define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
1258
1259/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
1260 * Must be set longer than active dwell time.
1261 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
1262#define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
1263#define IL_PASSIVE_DWELL_TIME_52 (10)
1264#define IL_PASSIVE_DWELL_BASE (100)
1265#define IL_CHANNEL_TUNE_TIME 5
1266
1267static int
1268il_send_scan_abort(struct il_priv *il)
1269{
1270 int ret;
1271 struct il_rx_pkt *pkt;
1272 struct il_host_cmd cmd = {
1273 .id = C_SCAN_ABORT,
1274 .flags = CMD_WANT_SKB,
1275 };
1276
1277 /* Exit instantly with error when device is not ready
1278 * to receive scan abort command or it does not perform
1279 * hardware scan currently */
1280 if (!test_bit(S_READY, &il->status) ||
1281 !test_bit(S_GEO_CONFIGURED, &il->status) ||
1282 !test_bit(S_SCAN_HW, &il->status) ||
1283 test_bit(S_FW_ERROR, &il->status) ||
1284 test_bit(S_EXIT_PENDING, &il->status))
1285 return -EIO;
1286
1287 ret = il_send_cmd_sync(il, &cmd);
1288 if (ret)
1289 return ret;
1290
1291 pkt = (struct il_rx_pkt *)cmd.reply_page;
1292 if (pkt->u.status != CAN_ABORT_STATUS) {
1293 /* The scan abort will return 1 for success or
1294 * 2 for "failure". A failure condition can be
1295 * due to simply not being in an active scan which
1296 * can occur if we send the scan abort before we
1297 * the microcode has notified us that a scan is
1298 * completed. */
1299 D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
1300 ret = -EIO;
1301 }
1302
1303 il_free_pages(il, cmd.reply_page);
1304 return ret;
1305}
1306
1307static void
1308il_complete_scan(struct il_priv *il, bool aborted)
1309{
1310 /* check if scan was requested from mac80211 */
1311 if (il->scan_request) {
1312 D_SCAN("Complete scan in mac80211\n");
1313 ieee80211_scan_completed(il->hw, aborted);
1314 }
1315
1316 il->scan_vif = NULL;
1317 il->scan_request = NULL;
1318}
1319
1320void
1321il_force_scan_end(struct il_priv *il)
1322{
1323 lockdep_assert_held(&il->mutex);
1324
1325 if (!test_bit(S_SCANNING, &il->status)) {
1326 D_SCAN("Forcing scan end while not scanning\n");
1327 return;
1328 }
1329
1330 D_SCAN("Forcing scan end\n");
1331 clear_bit(S_SCANNING, &il->status);
1332 clear_bit(S_SCAN_HW, &il->status);
1333 clear_bit(S_SCAN_ABORTING, &il->status);
1334 il_complete_scan(il, true);
1335}
1336
1337static void
1338il_do_scan_abort(struct il_priv *il)
1339{
1340 int ret;
1341
1342 lockdep_assert_held(&il->mutex);
1343
1344 if (!test_bit(S_SCANNING, &il->status)) {
1345 D_SCAN("Not performing scan to abort\n");
1346 return;
1347 }
1348
1349 if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
1350 D_SCAN("Scan abort in progress\n");
1351 return;
1352 }
1353
1354 ret = il_send_scan_abort(il);
1355 if (ret) {
1356 D_SCAN("Send scan abort failed %d\n", ret);
1357 il_force_scan_end(il);
1358 } else
1359 D_SCAN("Successfully send scan abort\n");
1360}
1361
1362/**
1363 * il_scan_cancel - Cancel any currently executing HW scan
1364 */
1365int
1366il_scan_cancel(struct il_priv *il)
1367{
1368 D_SCAN("Queuing abort scan\n");
1369 queue_work(il->workqueue, &il->abort_scan);
1370 return 0;
1371}
1372EXPORT_SYMBOL(il_scan_cancel);
1373
1374/**
1375 * il_scan_cancel_timeout - Cancel any currently executing HW scan
1376 * @ms: amount of time to wait (in milliseconds) for scan to abort
1377 *
1378 */
1379int
1380il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
1381{
1382 unsigned long timeout = jiffies + msecs_to_jiffies(ms);
1383
1384 lockdep_assert_held(&il->mutex);
1385
1386 D_SCAN("Scan cancel timeout\n");
1387
1388 il_do_scan_abort(il);
1389
1390 while (time_before_eq(jiffies, timeout)) {
1391 if (!test_bit(S_SCAN_HW, &il->status))
1392 break;
1393 msleep(20);
1394 }
1395
1396 return test_bit(S_SCAN_HW, &il->status);
1397}
1398EXPORT_SYMBOL(il_scan_cancel_timeout);
1399
1400/* Service response to C_SCAN (0x80) */
1401static void
1402il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
1403{
1404#ifdef CONFIG_IWLEGACY_DEBUG
1405 struct il_rx_pkt *pkt = rxb_addr(rxb);
1406 struct il_scanreq_notification *notif =
1407 (struct il_scanreq_notification *)pkt->u.raw;
1408
1409 D_SCAN("Scan request status = 0x%x\n", notif->status);
1410#endif
1411}
1412
1413/* Service N_SCAN_START (0x82) */
1414static void
1415il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
1416{
1417 struct il_rx_pkt *pkt = rxb_addr(rxb);
1418 struct il_scanstart_notification *notif =
1419 (struct il_scanstart_notification *)pkt->u.raw;
1420 il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
1421 D_SCAN("Scan start: " "%d [802.11%s] "
1422 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
1423 notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
1424 le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
1425}
1426
1427/* Service N_SCAN_RESULTS (0x83) */
1428static void
1429il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
1430{
1431#ifdef CONFIG_IWLEGACY_DEBUG
1432 struct il_rx_pkt *pkt = rxb_addr(rxb);
1433 struct il_scanresults_notification *notif =
1434 (struct il_scanresults_notification *)pkt->u.raw;
1435
1436 D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
1437 "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
1438 le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
1439 le32_to_cpu(notif->stats[0]),
1440 le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
1441#endif
1442}
1443
1444/* Service N_SCAN_COMPLETE (0x84) */
1445static void
1446il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
1447{
1448
1449#ifdef CONFIG_IWLEGACY_DEBUG
1450 struct il_rx_pkt *pkt = rxb_addr(rxb);
1451 struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
1452#endif
1453
1454 D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
1455 scan_notif->scanned_channels, scan_notif->tsf_low,
1456 scan_notif->tsf_high, scan_notif->status);
1457
1458 /* The HW is no longer scanning */
1459 clear_bit(S_SCAN_HW, &il->status);
1460
1461 D_SCAN("Scan on %sGHz took %dms\n",
1462 (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
1463 jiffies_to_msecs(jiffies - il->scan_start));
1464
1465 queue_work(il->workqueue, &il->scan_completed);
1466}
1467
1468void
1469il_setup_rx_scan_handlers(struct il_priv *il)
1470{
1471 /* scan handlers */
1472 il->handlers[C_SCAN] = il_hdl_scan;
1473 il->handlers[N_SCAN_START] = il_hdl_scan_start;
1474 il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
1475 il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
1476}
1477EXPORT_SYMBOL(il_setup_rx_scan_handlers);
1478
1479u16
1480il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1481 u8 n_probes)
1482{
1483 if (band == IEEE80211_BAND_5GHZ)
1484 return IL_ACTIVE_DWELL_TIME_52 +
1485 IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
1486 else
1487 return IL_ACTIVE_DWELL_TIME_24 +
1488 IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
1489}
1490EXPORT_SYMBOL(il_get_active_dwell_time);
1491
1492u16
1493il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1494 struct ieee80211_vif *vif)
1495{
1496 u16 value;
1497
1498 u16 passive =
1499 (band ==
1500 IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
1501 IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
1502 IL_PASSIVE_DWELL_TIME_52;
1503
1504 if (il_is_any_associated(il)) {
1505 /*
1506 * If we're associated, we clamp the maximum passive
1507 * dwell time to be 98% of the smallest beacon interval
1508 * (minus 2 * channel tune time)
1509 */
1510 value = il->vif ? il->vif->bss_conf.beacon_int : 0;
1511 if (value > IL_PASSIVE_DWELL_BASE || !value)
1512 value = IL_PASSIVE_DWELL_BASE;
1513 value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
1514 passive = min(value, passive);
1515 }
1516
1517 return passive;
1518}
1519EXPORT_SYMBOL(il_get_passive_dwell_time);
1520
1521void
1522il_init_scan_params(struct il_priv *il)
1523{
1524 u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
1525 if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
1526 il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
1527 if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
1528 il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
1529}
1530EXPORT_SYMBOL(il_init_scan_params);
1531
1532static int
1533il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
1534{
1535 int ret;
1536
1537 lockdep_assert_held(&il->mutex);
1538
1539 cancel_delayed_work(&il->scan_check);
1540
1541 if (!il_is_ready_rf(il)) {
1542 IL_WARN("Request scan called when driver not ready.\n");
1543 return -EIO;
1544 }
1545
1546 if (test_bit(S_SCAN_HW, &il->status)) {
1547 D_SCAN("Multiple concurrent scan requests in parallel.\n");
1548 return -EBUSY;
1549 }
1550
1551 if (test_bit(S_SCAN_ABORTING, &il->status)) {
1552 D_SCAN("Scan request while abort pending.\n");
1553 return -EBUSY;
1554 }
1555
1556 D_SCAN("Starting scan...\n");
1557
1558 set_bit(S_SCANNING, &il->status);
1559 il->scan_start = jiffies;
1560
1561 ret = il->ops->request_scan(il, vif);
1562 if (ret) {
1563 clear_bit(S_SCANNING, &il->status);
1564 return ret;
1565 }
1566
1567 queue_delayed_work(il->workqueue, &il->scan_check,
1568 IL_SCAN_CHECK_WATCHDOG);
1569
1570 return 0;
1571}
1572
1573int
1574il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1575 struct cfg80211_scan_request *req)
1576{
1577 struct il_priv *il = hw->priv;
1578 int ret;
1579
1580 if (req->n_channels == 0) {
1581 IL_ERR("Can not scan on no channels.\n");
1582 return -EINVAL;
1583 }
1584
1585 mutex_lock(&il->mutex);
1586 D_MAC80211("enter\n");
1587
1588 if (test_bit(S_SCANNING, &il->status)) {
1589 D_SCAN("Scan already in progress.\n");
1590 ret = -EAGAIN;
1591 goto out_unlock;
1592 }
1593
1594 /* mac80211 will only ask for one band at a time */
1595 il->scan_request = req;
1596 il->scan_vif = vif;
1597 il->scan_band = req->channels[0]->band;
1598
1599 ret = il_scan_initiate(il, vif);
1600
1601out_unlock:
1602 D_MAC80211("leave ret %d\n", ret);
1603 mutex_unlock(&il->mutex);
1604
1605 return ret;
1606}
1607EXPORT_SYMBOL(il_mac_hw_scan);
1608
1609static void
1610il_bg_scan_check(struct work_struct *data)
1611{
1612 struct il_priv *il =
1613 container_of(data, struct il_priv, scan_check.work);
1614
1615 D_SCAN("Scan check work\n");
1616
1617 /* Since we are here firmware does not finish scan and
1618 * most likely is in bad shape, so we don't bother to
1619 * send abort command, just force scan complete to mac80211 */
1620 mutex_lock(&il->mutex);
1621 il_force_scan_end(il);
1622 mutex_unlock(&il->mutex);
1623}
1624
1625/**
1626 * il_fill_probe_req - fill in all required fields and IE for probe request
1627 */
1628
1629u16
1630il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1631 const u8 *ta, const u8 *ies, int ie_len, int left)
1632{
1633 int len = 0;
1634 u8 *pos = NULL;
1635
1636 /* Make sure there is enough space for the probe request,
1637 * two mandatory IEs and the data */
1638 left -= 24;
1639 if (left < 0)
1640 return 0;
1641
1642 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
1643 eth_broadcast_addr(frame->da);
1644 memcpy(frame->sa, ta, ETH_ALEN);
1645 eth_broadcast_addr(frame->bssid);
1646 frame->seq_ctrl = 0;
1647
1648 len += 24;
1649
1650 /* ...next IE... */
1651 pos = &frame->u.probe_req.variable[0];
1652
1653 /* fill in our indirect SSID IE */
1654 left -= 2;
1655 if (left < 0)
1656 return 0;
1657 *pos++ = WLAN_EID_SSID;
1658 *pos++ = 0;
1659
1660 len += 2;
1661
1662 if (WARN_ON(left < ie_len))
1663 return len;
1664
1665 if (ies && ie_len) {
1666 memcpy(pos, ies, ie_len);
1667 len += ie_len;
1668 }
1669
1670 return (u16) len;
1671}
1672EXPORT_SYMBOL(il_fill_probe_req);
1673
1674static void
1675il_bg_abort_scan(struct work_struct *work)
1676{
1677 struct il_priv *il = container_of(work, struct il_priv, abort_scan);
1678
1679 D_SCAN("Abort scan work\n");
1680
1681 /* We keep scan_check work queued in case when firmware will not
1682 * report back scan completed notification */
1683 mutex_lock(&il->mutex);
1684 il_scan_cancel_timeout(il, 200);
1685 mutex_unlock(&il->mutex);
1686}
1687
1688static void
1689il_bg_scan_completed(struct work_struct *work)
1690{
1691 struct il_priv *il = container_of(work, struct il_priv, scan_completed);
1692 bool aborted;
1693
1694 D_SCAN("Completed scan.\n");
1695
1696 cancel_delayed_work(&il->scan_check);
1697
1698 mutex_lock(&il->mutex);
1699
1700 aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
1701 if (aborted)
1702 D_SCAN("Aborted scan completed.\n");
1703
1704 if (!test_and_clear_bit(S_SCANNING, &il->status)) {
1705 D_SCAN("Scan already completed.\n");
1706 goto out_settings;
1707 }
1708
1709 il_complete_scan(il, aborted);
1710
1711out_settings:
1712 /* Can we still talk to firmware ? */
1713 if (!il_is_ready_rf(il))
1714 goto out;
1715
1716 /*
1717 * We do not commit power settings while scan is pending,
1718 * do it now if the settings changed.
1719 */
1720 il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
1721 il_set_tx_power(il, il->tx_power_next, false);
1722
1723 il->ops->post_scan(il);
1724
1725out:
1726 mutex_unlock(&il->mutex);
1727}
1728
1729void
1730il_setup_scan_deferred_work(struct il_priv *il)
1731{
1732 INIT_WORK(&il->scan_completed, il_bg_scan_completed);
1733 INIT_WORK(&il->abort_scan, il_bg_abort_scan);
1734 INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
1735}
1736EXPORT_SYMBOL(il_setup_scan_deferred_work);
1737
1738void
1739il_cancel_scan_deferred_work(struct il_priv *il)
1740{
1741 cancel_work_sync(&il->abort_scan);
1742 cancel_work_sync(&il->scan_completed);
1743
1744 if (cancel_delayed_work_sync(&il->scan_check)) {
1745 mutex_lock(&il->mutex);
1746 il_force_scan_end(il);
1747 mutex_unlock(&il->mutex);
1748 }
1749}
1750EXPORT_SYMBOL(il_cancel_scan_deferred_work);
1751
1752/* il->sta_lock must be held */
1753static void
1754il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
1755{
1756
1757 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
1758 IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
1759 sta_id, il->stations[sta_id].sta.sta.addr);
1760
1761 if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
1762 D_ASSOC("STA id %u addr %pM already present"
1763 " in uCode (according to driver)\n", sta_id,
1764 il->stations[sta_id].sta.sta.addr);
1765 } else {
1766 il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
1767 D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
1768 il->stations[sta_id].sta.sta.addr);
1769 }
1770}
1771
1772static int
1773il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
1774 struct il_rx_pkt *pkt, bool sync)
1775{
1776 u8 sta_id = addsta->sta.sta_id;
1777 unsigned long flags;
1778 int ret = -EIO;
1779
1780 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
1781 IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
1782 return ret;
1783 }
1784
1785 D_INFO("Processing response for adding station %u\n", sta_id);
1786
1787 spin_lock_irqsave(&il->sta_lock, flags);
1788
1789 switch (pkt->u.add_sta.status) {
1790 case ADD_STA_SUCCESS_MSK:
1791 D_INFO("C_ADD_STA PASSED\n");
1792 il_sta_ucode_activate(il, sta_id);
1793 ret = 0;
1794 break;
1795 case ADD_STA_NO_ROOM_IN_TBL:
1796 IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
1797 break;
1798 case ADD_STA_NO_BLOCK_ACK_RESOURCE:
1799 IL_ERR("Adding station %d failed, no block ack resource.\n",
1800 sta_id);
1801 break;
1802 case ADD_STA_MODIFY_NON_EXIST_STA:
1803 IL_ERR("Attempting to modify non-existing station %d\n",
1804 sta_id);
1805 break;
1806 default:
1807 D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
1808 break;
1809 }
1810
1811 D_INFO("%s station id %u addr %pM\n",
1812 il->stations[sta_id].sta.mode ==
1813 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
1814 il->stations[sta_id].sta.sta.addr);
1815
1816 /*
1817 * XXX: The MAC address in the command buffer is often changed from
1818 * the original sent to the device. That is, the MAC address
1819 * written to the command buffer often is not the same MAC address
1820 * read from the command buffer when the command returns. This
1821 * issue has not yet been resolved and this debugging is left to
1822 * observe the problem.
1823 */
1824 D_INFO("%s station according to cmd buffer %pM\n",
1825 il->stations[sta_id].sta.mode ==
1826 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
1827 spin_unlock_irqrestore(&il->sta_lock, flags);
1828
1829 return ret;
1830}
1831
1832static void
1833il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
1834 struct il_rx_pkt *pkt)
1835{
1836 struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
1837
1838 il_process_add_sta_resp(il, addsta, pkt, false);
1839
1840}
1841
1842int
1843il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
1844{
1845 struct il_rx_pkt *pkt = NULL;
1846 int ret = 0;
1847 u8 data[sizeof(*sta)];
1848 struct il_host_cmd cmd = {
1849 .id = C_ADD_STA,
1850 .flags = flags,
1851 .data = data,
1852 };
1853 u8 sta_id __maybe_unused = sta->sta.sta_id;
1854
1855 D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
1856 flags & CMD_ASYNC ? "a" : "");
1857
1858 if (flags & CMD_ASYNC)
1859 cmd.callback = il_add_sta_callback;
1860 else {
1861 cmd.flags |= CMD_WANT_SKB;
1862 might_sleep();
1863 }
1864
1865 cmd.len = il->ops->build_addsta_hcmd(sta, data);
1866 ret = il_send_cmd(il, &cmd);
1867
1868 if (ret || (flags & CMD_ASYNC))
1869 return ret;
1870
1871 if (ret == 0) {
1872 pkt = (struct il_rx_pkt *)cmd.reply_page;
1873 ret = il_process_add_sta_resp(il, sta, pkt, true);
1874 }
1875 il_free_pages(il, cmd.reply_page);
1876
1877 return ret;
1878}
1879EXPORT_SYMBOL(il_send_add_sta);
1880
1881static void
1882il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta)
1883{
1884 struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
1885 __le32 sta_flags;
1886
1887 if (!sta || !sta_ht_inf->ht_supported)
1888 goto done;
1889
1890 D_ASSOC("spatial multiplexing power save mode: %s\n",
1891 (sta->smps_mode == IEEE80211_SMPS_STATIC) ? "static" :
1892 (sta->smps_mode == IEEE80211_SMPS_DYNAMIC) ? "dynamic" :
1893 "disabled");
1894
1895 sta_flags = il->stations[idx].sta.station_flags;
1896
1897 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
1898
1899 switch (sta->smps_mode) {
1900 case IEEE80211_SMPS_STATIC:
1901 sta_flags |= STA_FLG_MIMO_DIS_MSK;
1902 break;
1903 case IEEE80211_SMPS_DYNAMIC:
1904 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
1905 break;
1906 case IEEE80211_SMPS_OFF:
1907 break;
1908 default:
1909 IL_WARN("Invalid MIMO PS mode %d\n", sta->smps_mode);
1910 break;
1911 }
1912
1913 sta_flags |=
1914 cpu_to_le32((u32) sta_ht_inf->
1915 ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
1916
1917 sta_flags |=
1918 cpu_to_le32((u32) sta_ht_inf->
1919 ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
1920
1921 if (il_is_ht40_tx_allowed(il, &sta->ht_cap))
1922 sta_flags |= STA_FLG_HT40_EN_MSK;
1923 else
1924 sta_flags &= ~STA_FLG_HT40_EN_MSK;
1925
1926 il->stations[idx].sta.station_flags = sta_flags;
1927done:
1928 return;
1929}
1930
1931/**
1932 * il_prep_station - Prepare station information for addition
1933 *
1934 * should be called with sta_lock held
1935 */
1936u8
1937il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
1938 struct ieee80211_sta *sta)
1939{
1940 struct il_station_entry *station;
1941 int i;
1942 u8 sta_id = IL_INVALID_STATION;
1943 u16 rate;
1944
1945 if (is_ap)
1946 sta_id = IL_AP_ID;
1947 else if (is_broadcast_ether_addr(addr))
1948 sta_id = il->hw_params.bcast_id;
1949 else
1950 for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
1951 if (ether_addr_equal(il->stations[i].sta.sta.addr,
1952 addr)) {
1953 sta_id = i;
1954 break;
1955 }
1956
1957 if (!il->stations[i].used &&
1958 sta_id == IL_INVALID_STATION)
1959 sta_id = i;
1960 }
1961
1962 /*
1963 * These two conditions have the same outcome, but keep them
1964 * separate
1965 */
1966 if (unlikely(sta_id == IL_INVALID_STATION))
1967 return sta_id;
1968
1969 /*
1970 * uCode is not able to deal with multiple requests to add a
1971 * station. Keep track if one is in progress so that we do not send
1972 * another.
1973 */
1974 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
1975 D_INFO("STA %d already in process of being added.\n", sta_id);
1976 return sta_id;
1977 }
1978
1979 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
1980 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
1981 ether_addr_equal(il->stations[sta_id].sta.sta.addr, addr)) {
1982 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
1983 sta_id, addr);
1984 return sta_id;
1985 }
1986
1987 station = &il->stations[sta_id];
1988 station->used = IL_STA_DRIVER_ACTIVE;
1989 D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
1990 il->num_stations++;
1991
1992 /* Set up the C_ADD_STA command to send to device */
1993 memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
1994 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
1995 station->sta.mode = 0;
1996 station->sta.sta.sta_id = sta_id;
1997 station->sta.station_flags = 0;
1998
1999 /*
2000 * OK to call unconditionally, since local stations (IBSS BSSID
2001 * STA and broadcast STA) pass in a NULL sta, and mac80211
2002 * doesn't allow HT IBSS.
2003 */
2004 il_set_ht_add_station(il, sta_id, sta);
2005
2006 /* 3945 only */
2007 rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
2008 /* Turn on both antennas for the station... */
2009 station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
2010
2011 return sta_id;
2012
2013}
2014EXPORT_SYMBOL_GPL(il_prep_station);
2015
2016#define STA_WAIT_TIMEOUT (HZ/2)
2017
2018/**
2019 * il_add_station_common -
2020 */
2021int
2022il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
2023 struct ieee80211_sta *sta, u8 *sta_id_r)
2024{
2025 unsigned long flags_spin;
2026 int ret = 0;
2027 u8 sta_id;
2028 struct il_addsta_cmd sta_cmd;
2029
2030 *sta_id_r = 0;
2031 spin_lock_irqsave(&il->sta_lock, flags_spin);
2032 sta_id = il_prep_station(il, addr, is_ap, sta);
2033 if (sta_id == IL_INVALID_STATION) {
2034 IL_ERR("Unable to prepare station %pM for addition\n", addr);
2035 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2036 return -EINVAL;
2037 }
2038
2039 /*
2040 * uCode is not able to deal with multiple requests to add a
2041 * station. Keep track if one is in progress so that we do not send
2042 * another.
2043 */
2044 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
2045 D_INFO("STA %d already in process of being added.\n", sta_id);
2046 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2047 return -EEXIST;
2048 }
2049
2050 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
2051 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
2052 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
2053 sta_id, addr);
2054 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2055 return -EEXIST;
2056 }
2057
2058 il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
2059 memcpy(&sta_cmd, &il->stations[sta_id].sta,
2060 sizeof(struct il_addsta_cmd));
2061 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2062
2063 /* Add station to device's station table */
2064 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2065 if (ret) {
2066 spin_lock_irqsave(&il->sta_lock, flags_spin);
2067 IL_ERR("Adding station %pM failed.\n",
2068 il->stations[sta_id].sta.sta.addr);
2069 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2070 il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2071 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2072 }
2073 *sta_id_r = sta_id;
2074 return ret;
2075}
2076EXPORT_SYMBOL(il_add_station_common);
2077
2078/**
2079 * il_sta_ucode_deactivate - deactivate ucode status for a station
2080 *
2081 * il->sta_lock must be held
2082 */
2083static void
2084il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
2085{
2086 /* Ucode must be active and driver must be non active */
2087 if ((il->stations[sta_id].
2088 used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
2089 IL_STA_UCODE_ACTIVE)
2090 IL_ERR("removed non active STA %u\n", sta_id);
2091
2092 il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
2093
2094 memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
2095 D_ASSOC("Removed STA %u\n", sta_id);
2096}
2097
2098static int
2099il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
2100 bool temporary)
2101{
2102 struct il_rx_pkt *pkt;
2103 int ret;
2104
2105 unsigned long flags_spin;
2106 struct il_rem_sta_cmd rm_sta_cmd;
2107
2108 struct il_host_cmd cmd = {
2109 .id = C_REM_STA,
2110 .len = sizeof(struct il_rem_sta_cmd),
2111 .flags = CMD_SYNC,
2112 .data = &rm_sta_cmd,
2113 };
2114
2115 memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
2116 rm_sta_cmd.num_sta = 1;
2117 memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
2118
2119 cmd.flags |= CMD_WANT_SKB;
2120
2121 ret = il_send_cmd(il, &cmd);
2122
2123 if (ret)
2124 return ret;
2125
2126 pkt = (struct il_rx_pkt *)cmd.reply_page;
2127 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
2128 IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
2129 ret = -EIO;
2130 }
2131
2132 if (!ret) {
2133 switch (pkt->u.rem_sta.status) {
2134 case REM_STA_SUCCESS_MSK:
2135 if (!temporary) {
2136 spin_lock_irqsave(&il->sta_lock, flags_spin);
2137 il_sta_ucode_deactivate(il, sta_id);
2138 spin_unlock_irqrestore(&il->sta_lock,
2139 flags_spin);
2140 }
2141 D_ASSOC("C_REM_STA PASSED\n");
2142 break;
2143 default:
2144 ret = -EIO;
2145 IL_ERR("C_REM_STA failed\n");
2146 break;
2147 }
2148 }
2149 il_free_pages(il, cmd.reply_page);
2150
2151 return ret;
2152}
2153
2154/**
2155 * il_remove_station - Remove driver's knowledge of station.
2156 */
2157int
2158il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
2159{
2160 unsigned long flags;
2161
2162 if (!il_is_ready(il)) {
2163 D_INFO("Unable to remove station %pM, device not ready.\n",
2164 addr);
2165 /*
2166 * It is typical for stations to be removed when we are
2167 * going down. Return success since device will be down
2168 * soon anyway
2169 */
2170 return 0;
2171 }
2172
2173 D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
2174
2175 if (WARN_ON(sta_id == IL_INVALID_STATION))
2176 return -EINVAL;
2177
2178 spin_lock_irqsave(&il->sta_lock, flags);
2179
2180 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
2181 D_INFO("Removing %pM but non DRIVER active\n", addr);
2182 goto out_err;
2183 }
2184
2185 if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
2186 D_INFO("Removing %pM but non UCODE active\n", addr);
2187 goto out_err;
2188 }
2189
2190 if (il->stations[sta_id].used & IL_STA_LOCAL) {
2191 kfree(il->stations[sta_id].lq);
2192 il->stations[sta_id].lq = NULL;
2193 }
2194
2195 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2196
2197 il->num_stations--;
2198
2199 BUG_ON(il->num_stations < 0);
2200
2201 spin_unlock_irqrestore(&il->sta_lock, flags);
2202
2203 return il_send_remove_station(il, addr, sta_id, false);
2204out_err:
2205 spin_unlock_irqrestore(&il->sta_lock, flags);
2206 return -EINVAL;
2207}
2208EXPORT_SYMBOL_GPL(il_remove_station);
2209
2210/**
2211 * il_clear_ucode_stations - clear ucode station table bits
2212 *
2213 * This function clears all the bits in the driver indicating
2214 * which stations are active in the ucode. Call when something
2215 * other than explicit station management would cause this in
2216 * the ucode, e.g. unassociated RXON.
2217 */
2218void
2219il_clear_ucode_stations(struct il_priv *il)
2220{
2221 int i;
2222 unsigned long flags_spin;
2223 bool cleared = false;
2224
2225 D_INFO("Clearing ucode stations in driver\n");
2226
2227 spin_lock_irqsave(&il->sta_lock, flags_spin);
2228 for (i = 0; i < il->hw_params.max_stations; i++) {
2229 if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
2230 D_INFO("Clearing ucode active for station %d\n", i);
2231 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2232 cleared = true;
2233 }
2234 }
2235 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2236
2237 if (!cleared)
2238 D_INFO("No active stations found to be cleared\n");
2239}
2240EXPORT_SYMBOL(il_clear_ucode_stations);
2241
2242/**
2243 * il_restore_stations() - Restore driver known stations to device
2244 *
2245 * All stations considered active by driver, but not present in ucode, is
2246 * restored.
2247 *
2248 * Function sleeps.
2249 */
2250void
2251il_restore_stations(struct il_priv *il)
2252{
2253 struct il_addsta_cmd sta_cmd;
2254 struct il_link_quality_cmd lq;
2255 unsigned long flags_spin;
2256 int i;
2257 bool found = false;
2258 int ret;
2259 bool send_lq;
2260
2261 if (!il_is_ready(il)) {
2262 D_INFO("Not ready yet, not restoring any stations.\n");
2263 return;
2264 }
2265
2266 D_ASSOC("Restoring all known stations ... start.\n");
2267 spin_lock_irqsave(&il->sta_lock, flags_spin);
2268 for (i = 0; i < il->hw_params.max_stations; i++) {
2269 if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
2270 !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
2271 D_ASSOC("Restoring sta %pM\n",
2272 il->stations[i].sta.sta.addr);
2273 il->stations[i].sta.mode = 0;
2274 il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
2275 found = true;
2276 }
2277 }
2278
2279 for (i = 0; i < il->hw_params.max_stations; i++) {
2280 if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
2281 memcpy(&sta_cmd, &il->stations[i].sta,
2282 sizeof(struct il_addsta_cmd));
2283 send_lq = false;
2284 if (il->stations[i].lq) {
2285 memcpy(&lq, il->stations[i].lq,
2286 sizeof(struct il_link_quality_cmd));
2287 send_lq = true;
2288 }
2289 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2290 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2291 if (ret) {
2292 spin_lock_irqsave(&il->sta_lock, flags_spin);
2293 IL_ERR("Adding station %pM failed.\n",
2294 il->stations[i].sta.sta.addr);
2295 il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
2296 il->stations[i].used &=
2297 ~IL_STA_UCODE_INPROGRESS;
2298 spin_unlock_irqrestore(&il->sta_lock,
2299 flags_spin);
2300 }
2301 /*
2302 * Rate scaling has already been initialized, send
2303 * current LQ command
2304 */
2305 if (send_lq)
2306 il_send_lq_cmd(il, &lq, CMD_SYNC, true);
2307 spin_lock_irqsave(&il->sta_lock, flags_spin);
2308 il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
2309 }
2310 }
2311
2312 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2313 if (!found)
2314 D_INFO("Restoring all known stations"
2315 " .... no stations to be restored.\n");
2316 else
2317 D_INFO("Restoring all known stations" " .... complete.\n");
2318}
2319EXPORT_SYMBOL(il_restore_stations);
2320
2321int
2322il_get_free_ucode_key_idx(struct il_priv *il)
2323{
2324 int i;
2325
2326 for (i = 0; i < il->sta_key_max_num; i++)
2327 if (!test_and_set_bit(i, &il->ucode_key_table))
2328 return i;
2329
2330 return WEP_INVALID_OFFSET;
2331}
2332EXPORT_SYMBOL(il_get_free_ucode_key_idx);
2333
2334void
2335il_dealloc_bcast_stations(struct il_priv *il)
2336{
2337 unsigned long flags;
2338 int i;
2339
2340 spin_lock_irqsave(&il->sta_lock, flags);
2341 for (i = 0; i < il->hw_params.max_stations; i++) {
2342 if (!(il->stations[i].used & IL_STA_BCAST))
2343 continue;
2344
2345 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2346 il->num_stations--;
2347 BUG_ON(il->num_stations < 0);
2348 kfree(il->stations[i].lq);
2349 il->stations[i].lq = NULL;
2350 }
2351 spin_unlock_irqrestore(&il->sta_lock, flags);
2352}
2353EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
2354
2355#ifdef CONFIG_IWLEGACY_DEBUG
2356static void
2357il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
2358{
2359 int i;
2360 D_RATE("lq station id 0x%x\n", lq->sta_id);
2361 D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
2362 lq->general_params.dual_stream_ant_msk);
2363
2364 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
2365 D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
2366}
2367#else
2368static inline void
2369il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
2370{
2371}
2372#endif
2373
2374/**
2375 * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
2376 *
2377 * It sometimes happens when a HT rate has been in use and we
2378 * loose connectivity with AP then mac80211 will first tell us that the
2379 * current channel is not HT anymore before removing the station. In such a
2380 * scenario the RXON flags will be updated to indicate we are not
2381 * communicating HT anymore, but the LQ command may still contain HT rates.
2382 * Test for this to prevent driver from sending LQ command between the time
2383 * RXON flags are updated and when LQ command is updated.
2384 */
2385static bool
2386il_is_lq_table_valid(struct il_priv *il, struct il_link_quality_cmd *lq)
2387{
2388 int i;
2389
2390 if (il->ht.enabled)
2391 return true;
2392
2393 D_INFO("Channel %u is not an HT channel\n", il->active.channel);
2394 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
2395 if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
2396 D_INFO("idx %d of LQ expects HT channel\n", i);
2397 return false;
2398 }
2399 }
2400 return true;
2401}
2402
2403/**
2404 * il_send_lq_cmd() - Send link quality command
2405 * @init: This command is sent as part of station initialization right
2406 * after station has been added.
2407 *
2408 * The link quality command is sent as the last step of station creation.
2409 * This is the special case in which init is set and we call a callback in
2410 * this case to clear the state indicating that station creation is in
2411 * progress.
2412 */
2413int
2414il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2415 u8 flags, bool init)
2416{
2417 int ret = 0;
2418 unsigned long flags_spin;
2419
2420 struct il_host_cmd cmd = {
2421 .id = C_TX_LINK_QUALITY_CMD,
2422 .len = sizeof(struct il_link_quality_cmd),
2423 .flags = flags,
2424 .data = lq,
2425 };
2426
2427 if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
2428 return -EINVAL;
2429
2430 spin_lock_irqsave(&il->sta_lock, flags_spin);
2431 if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
2432 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2433 return -EINVAL;
2434 }
2435 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2436
2437 il_dump_lq_cmd(il, lq);
2438 BUG_ON(init && (cmd.flags & CMD_ASYNC));
2439
2440 if (il_is_lq_table_valid(il, lq))
2441 ret = il_send_cmd(il, &cmd);
2442 else
2443 ret = -EINVAL;
2444
2445 if (cmd.flags & CMD_ASYNC)
2446 return ret;
2447
2448 if (init) {
2449 D_INFO("init LQ command complete,"
2450 " clearing sta addition status for sta %d\n",
2451 lq->sta_id);
2452 spin_lock_irqsave(&il->sta_lock, flags_spin);
2453 il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2454 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2455 }
2456 return ret;
2457}
2458EXPORT_SYMBOL(il_send_lq_cmd);
2459
2460int
2461il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2462 struct ieee80211_sta *sta)
2463{
2464 struct il_priv *il = hw->priv;
2465 struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
2466 int ret;
2467
2468 mutex_lock(&il->mutex);
2469 D_MAC80211("enter station %pM\n", sta->addr);
2470
2471 ret = il_remove_station(il, sta_common->sta_id, sta->addr);
2472 if (ret)
2473 IL_ERR("Error removing station %pM\n", sta->addr);
2474
2475 D_MAC80211("leave ret %d\n", ret);
2476 mutex_unlock(&il->mutex);
2477
2478 return ret;
2479}
2480EXPORT_SYMBOL(il_mac_sta_remove);
2481
2482/************************** RX-FUNCTIONS ****************************/
2483/*
2484 * Rx theory of operation
2485 *
2486 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
2487 * each of which point to Receive Buffers to be filled by the NIC. These get
2488 * used not only for Rx frames, but for any command response or notification
2489 * from the NIC. The driver and NIC manage the Rx buffers by means
2490 * of idxes into the circular buffer.
2491 *
2492 * Rx Queue Indexes
2493 * The host/firmware share two idx registers for managing the Rx buffers.
2494 *
2495 * The READ idx maps to the first position that the firmware may be writing
2496 * to -- the driver can read up to (but not including) this position and get
2497 * good data.
2498 * The READ idx is managed by the firmware once the card is enabled.
2499 *
2500 * The WRITE idx maps to the last position the driver has read from -- the
2501 * position preceding WRITE is the last slot the firmware can place a packet.
2502 *
2503 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
2504 * WRITE = READ.
2505 *
2506 * During initialization, the host sets up the READ queue position to the first
2507 * IDX position, and WRITE to the last (READ - 1 wrapped)
2508 *
2509 * When the firmware places a packet in a buffer, it will advance the READ idx
2510 * and fire the RX interrupt. The driver can then query the READ idx and
2511 * process as many packets as possible, moving the WRITE idx forward as it
2512 * resets the Rx queue buffers with new memory.
2513 *
2514 * The management in the driver is as follows:
2515 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
2516 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
2517 * to replenish the iwl->rxq->rx_free.
2518 * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
2519 * iwl->rxq is replenished and the READ IDX is updated (updating the
2520 * 'processed' and 'read' driver idxes as well)
2521 * + A received packet is processed and handed to the kernel network stack,
2522 * detached from the iwl->rxq. The driver 'processed' idx is updated.
2523 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
2524 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2525 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
2526 * were enough free buffers and RX_STALLED is set it is cleared.
2527 *
2528 *
2529 * Driver sequence:
2530 *
2531 * il_rx_queue_alloc() Allocates rx_free
2532 * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
2533 * il_rx_queue_restock
2534 * il_rx_queue_restock() Moves available buffers from rx_free into Rx
2535 * queue, updates firmware pointers, and updates
2536 * the WRITE idx. If insufficient rx_free buffers
2537 * are available, schedules il_rx_replenish
2538 *
2539 * -- enable interrupts --
2540 * ISR - il_rx() Detach il_rx_bufs from pool up to the
2541 * READ IDX, detaching the SKB from the pool.
2542 * Moves the packet buffer from queue to rx_used.
2543 * Calls il_rx_queue_restock to refill any empty
2544 * slots.
2545 * ...
2546 *
2547 */
2548
2549/**
2550 * il_rx_queue_space - Return number of free slots available in queue.
2551 */
2552int
2553il_rx_queue_space(const struct il_rx_queue *q)
2554{
2555 int s = q->read - q->write;
2556 if (s <= 0)
2557 s += RX_QUEUE_SIZE;
2558 /* keep some buffer to not confuse full and empty queue */
2559 s -= 2;
2560 if (s < 0)
2561 s = 0;
2562 return s;
2563}
2564EXPORT_SYMBOL(il_rx_queue_space);
2565
2566/**
2567 * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
2568 */
2569void
2570il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
2571{
2572 unsigned long flags;
2573 u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
2574 u32 reg;
2575
2576 spin_lock_irqsave(&q->lock, flags);
2577
2578 if (q->need_update == 0)
2579 goto exit_unlock;
2580
2581 /* If power-saving is in use, make sure device is awake */
2582 if (test_bit(S_POWER_PMI, &il->status)) {
2583 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2584
2585 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
2586 D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
2587 reg);
2588 il_set_bit(il, CSR_GP_CNTRL,
2589 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2590 goto exit_unlock;
2591 }
2592
2593 q->write_actual = (q->write & ~0x7);
2594 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
2595
2596 /* Else device is assumed to be awake */
2597 } else {
2598 /* Device expects a multiple of 8 */
2599 q->write_actual = (q->write & ~0x7);
2600 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
2601 }
2602
2603 q->need_update = 0;
2604
2605exit_unlock:
2606 spin_unlock_irqrestore(&q->lock, flags);
2607}
2608EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
2609
2610int
2611il_rx_queue_alloc(struct il_priv *il)
2612{
2613 struct il_rx_queue *rxq = &il->rxq;
2614 struct device *dev = &il->pci_dev->dev;
2615 int i;
2616
2617 spin_lock_init(&rxq->lock);
2618 INIT_LIST_HEAD(&rxq->rx_free);
2619 INIT_LIST_HEAD(&rxq->rx_used);
2620
2621 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
2622 rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
2623 GFP_KERNEL);
2624 if (!rxq->bd)
2625 goto err_bd;
2626
2627 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(struct il_rb_status),
2628 &rxq->rb_stts_dma, GFP_KERNEL);
2629 if (!rxq->rb_stts)
2630 goto err_rb;
2631
2632 /* Fill the rx_used queue with _all_ of the Rx buffers */
2633 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
2634 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
2635
2636 /* Set us so that we have processed and used all buffers, but have
2637 * not restocked the Rx queue with fresh buffers */
2638 rxq->read = rxq->write = 0;
2639 rxq->write_actual = 0;
2640 rxq->free_count = 0;
2641 rxq->need_update = 0;
2642 return 0;
2643
2644err_rb:
2645 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
2646 rxq->bd_dma);
2647err_bd:
2648 return -ENOMEM;
2649}
2650EXPORT_SYMBOL(il_rx_queue_alloc);
2651
2652void
2653il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
2654{
2655 struct il_rx_pkt *pkt = rxb_addr(rxb);
2656 struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
2657
2658 if (!report->state) {
2659 D_11H("Spectrum Measure Notification: Start\n");
2660 return;
2661 }
2662
2663 memcpy(&il->measure_report, report, sizeof(*report));
2664 il->measurement_status |= MEASUREMENT_READY;
2665}
2666EXPORT_SYMBOL(il_hdl_spectrum_measurement);
2667
2668/*
2669 * returns non-zero if packet should be dropped
2670 */
2671int
2672il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
2673 u32 decrypt_res, struct ieee80211_rx_status *stats)
2674{
2675 u16 fc = le16_to_cpu(hdr->frame_control);
2676
2677 /*
2678 * All contexts have the same setting here due to it being
2679 * a module parameter, so OK to check any context.
2680 */
2681 if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
2682 return 0;
2683
2684 if (!(fc & IEEE80211_FCTL_PROTECTED))
2685 return 0;
2686
2687 D_RX("decrypt_res:0x%x\n", decrypt_res);
2688 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2689 case RX_RES_STATUS_SEC_TYPE_TKIP:
2690 /* The uCode has got a bad phase 1 Key, pushes the packet.
2691 * Decryption will be done in SW. */
2692 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2693 RX_RES_STATUS_BAD_KEY_TTAK)
2694 break;
2695
2696 case RX_RES_STATUS_SEC_TYPE_WEP:
2697 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2698 RX_RES_STATUS_BAD_ICV_MIC) {
2699 /* bad ICV, the packet is destroyed since the
2700 * decryption is inplace, drop it */
2701 D_RX("Packet destroyed\n");
2702 return -1;
2703 }
2704 case RX_RES_STATUS_SEC_TYPE_CCMP:
2705 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2706 RX_RES_STATUS_DECRYPT_OK) {
2707 D_RX("hw decrypt successfully!!!\n");
2708 stats->flag |= RX_FLAG_DECRYPTED;
2709 }
2710 break;
2711
2712 default:
2713 break;
2714 }
2715 return 0;
2716}
2717EXPORT_SYMBOL(il_set_decrypted_flag);
2718
2719/**
2720 * il_txq_update_write_ptr - Send new write idx to hardware
2721 */
2722void
2723il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
2724{
2725 u32 reg = 0;
2726 int txq_id = txq->q.id;
2727
2728 if (txq->need_update == 0)
2729 return;
2730
2731 /* if we're trying to save power */
2732 if (test_bit(S_POWER_PMI, &il->status)) {
2733 /* wake up nic if it's powered down ...
2734 * uCode will wake up, and interrupt us again, so next
2735 * time we'll skip this part. */
2736 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2737
2738 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
2739 D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
2740 txq_id, reg);
2741 il_set_bit(il, CSR_GP_CNTRL,
2742 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2743 return;
2744 }
2745
2746 il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
2747
2748 /*
2749 * else not in power-save mode,
2750 * uCode will never sleep when we're
2751 * trying to tx (during RFKILL, we're not trying to tx).
2752 */
2753 } else
2754 _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
2755 txq->need_update = 0;
2756}
2757EXPORT_SYMBOL(il_txq_update_write_ptr);
2758
2759/**
2760 * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
2761 */
2762void
2763il_tx_queue_unmap(struct il_priv *il, int txq_id)
2764{
2765 struct il_tx_queue *txq = &il->txq[txq_id];
2766 struct il_queue *q = &txq->q;
2767
2768 if (q->n_bd == 0)
2769 return;
2770
2771 while (q->write_ptr != q->read_ptr) {
2772 il->ops->txq_free_tfd(il, txq);
2773 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2774 }
2775}
2776EXPORT_SYMBOL(il_tx_queue_unmap);
2777
2778/**
2779 * il_tx_queue_free - Deallocate DMA queue.
2780 * @txq: Transmit queue to deallocate.
2781 *
2782 * Empty queue by removing and destroying all BD's.
2783 * Free all buffers.
2784 * 0-fill, but do not free "txq" descriptor structure.
2785 */
2786void
2787il_tx_queue_free(struct il_priv *il, int txq_id)
2788{
2789 struct il_tx_queue *txq = &il->txq[txq_id];
2790 struct device *dev = &il->pci_dev->dev;
2791 int i;
2792
2793 il_tx_queue_unmap(il, txq_id);
2794
2795 /* De-alloc array of command/tx buffers */
2796 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
2797 kfree(txq->cmd[i]);
2798
2799 /* De-alloc circular buffer of TFDs */
2800 if (txq->q.n_bd)
2801 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2802 txq->tfds, txq->q.dma_addr);
2803
2804 /* De-alloc array of per-TFD driver data */
2805 kfree(txq->skbs);
2806 txq->skbs = NULL;
2807
2808 /* deallocate arrays */
2809 kfree(txq->cmd);
2810 kfree(txq->meta);
2811 txq->cmd = NULL;
2812 txq->meta = NULL;
2813
2814 /* 0-fill queue descriptor structure */
2815 memset(txq, 0, sizeof(*txq));
2816}
2817EXPORT_SYMBOL(il_tx_queue_free);
2818
2819/**
2820 * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
2821 */
2822void
2823il_cmd_queue_unmap(struct il_priv *il)
2824{
2825 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2826 struct il_queue *q = &txq->q;
2827 int i;
2828
2829 if (q->n_bd == 0)
2830 return;
2831
2832 while (q->read_ptr != q->write_ptr) {
2833 i = il_get_cmd_idx(q, q->read_ptr, 0);
2834
2835 if (txq->meta[i].flags & CMD_MAPPED) {
2836 pci_unmap_single(il->pci_dev,
2837 dma_unmap_addr(&txq->meta[i], mapping),
2838 dma_unmap_len(&txq->meta[i], len),
2839 PCI_DMA_BIDIRECTIONAL);
2840 txq->meta[i].flags = 0;
2841 }
2842
2843 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2844 }
2845
2846 i = q->n_win;
2847 if (txq->meta[i].flags & CMD_MAPPED) {
2848 pci_unmap_single(il->pci_dev,
2849 dma_unmap_addr(&txq->meta[i], mapping),
2850 dma_unmap_len(&txq->meta[i], len),
2851 PCI_DMA_BIDIRECTIONAL);
2852 txq->meta[i].flags = 0;
2853 }
2854}
2855EXPORT_SYMBOL(il_cmd_queue_unmap);
2856
2857/**
2858 * il_cmd_queue_free - Deallocate DMA queue.
2859 * @txq: Transmit queue to deallocate.
2860 *
2861 * Empty queue by removing and destroying all BD's.
2862 * Free all buffers.
2863 * 0-fill, but do not free "txq" descriptor structure.
2864 */
2865void
2866il_cmd_queue_free(struct il_priv *il)
2867{
2868 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2869 struct device *dev = &il->pci_dev->dev;
2870 int i;
2871
2872 il_cmd_queue_unmap(il);
2873
2874 /* De-alloc array of command/tx buffers */
2875 for (i = 0; i <= TFD_CMD_SLOTS; i++)
2876 kfree(txq->cmd[i]);
2877
2878 /* De-alloc circular buffer of TFDs */
2879 if (txq->q.n_bd)
2880 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2881 txq->tfds, txq->q.dma_addr);
2882
2883 /* deallocate arrays */
2884 kfree(txq->cmd);
2885 kfree(txq->meta);
2886 txq->cmd = NULL;
2887 txq->meta = NULL;
2888
2889 /* 0-fill queue descriptor structure */
2890 memset(txq, 0, sizeof(*txq));
2891}
2892EXPORT_SYMBOL(il_cmd_queue_free);
2893
2894/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
2895 * DMA services
2896 *
2897 * Theory of operation
2898 *
2899 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
2900 * of buffer descriptors, each of which points to one or more data buffers for
2901 * the device to read from or fill. Driver and device exchange status of each
2902 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
2903 * entries in each circular buffer, to protect against confusing empty and full
2904 * queue states.
2905 *
2906 * The device reads or writes the data in the queues via the device's several
2907 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
2908 *
2909 * For Tx queue, there are low mark and high mark limits. If, after queuing
2910 * the packet for Tx, free space become < low mark, Tx queue stopped. When
2911 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
2912 * Tx queue resumed.
2913 *
2914 * See more detailed info in 4965.h.
2915 ***************************************************/
2916
2917int
2918il_queue_space(const struct il_queue *q)
2919{
2920 int s = q->read_ptr - q->write_ptr;
2921
2922 if (q->read_ptr > q->write_ptr)
2923 s -= q->n_bd;
2924
2925 if (s <= 0)
2926 s += q->n_win;
2927 /* keep some reserve to not confuse empty and full situations */
2928 s -= 2;
2929 if (s < 0)
2930 s = 0;
2931 return s;
2932}
2933EXPORT_SYMBOL(il_queue_space);
2934
2935
2936/**
2937 * il_queue_init - Initialize queue's high/low-water and read/write idxes
2938 */
2939static int
2940il_queue_init(struct il_priv *il, struct il_queue *q, int slots, u32 id)
2941{
2942 /*
2943 * TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
2944 * il_queue_inc_wrap and il_queue_dec_wrap are broken.
2945 */
2946 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
2947 /* FIXME: remove q->n_bd */
2948 q->n_bd = TFD_QUEUE_SIZE_MAX;
2949
2950 q->n_win = slots;
2951 q->id = id;
2952
2953 /* slots_must be power-of-two size, otherwise
2954 * il_get_cmd_idx is broken. */
2955 BUG_ON(!is_power_of_2(slots));
2956
2957 q->low_mark = q->n_win / 4;
2958 if (q->low_mark < 4)
2959 q->low_mark = 4;
2960
2961 q->high_mark = q->n_win / 8;
2962 if (q->high_mark < 2)
2963 q->high_mark = 2;
2964
2965 q->write_ptr = q->read_ptr = 0;
2966
2967 return 0;
2968}
2969
2970/**
2971 * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
2972 */
2973static int
2974il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
2975{
2976 struct device *dev = &il->pci_dev->dev;
2977 size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
2978
2979 /* Driver ilate data, only for Tx (not command) queues,
2980 * not shared with device. */
2981 if (id != il->cmd_queue) {
2982 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(struct skb *),
2983 GFP_KERNEL);
2984 if (!txq->skbs) {
2985 IL_ERR("Fail to alloc skbs\n");
2986 goto error;
2987 }
2988 } else
2989 txq->skbs = NULL;
2990
2991 /* Circular buffer of transmit frame descriptors (TFDs),
2992 * shared with device */
2993 txq->tfds =
2994 dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
2995 if (!txq->tfds)
2996 goto error;
2997
2998 txq->q.id = id;
2999
3000 return 0;
3001
3002error:
3003 kfree(txq->skbs);
3004 txq->skbs = NULL;
3005
3006 return -ENOMEM;
3007}
3008
3009/**
3010 * il_tx_queue_init - Allocate and initialize one tx/cmd queue
3011 */
3012int
3013il_tx_queue_init(struct il_priv *il, u32 txq_id)
3014{
3015 int i, len, ret;
3016 int slots, actual_slots;
3017 struct il_tx_queue *txq = &il->txq[txq_id];
3018
3019 /*
3020 * Alloc buffer array for commands (Tx or other types of commands).
3021 * For the command queue (#4/#9), allocate command space + one big
3022 * command for scan, since scan command is very huge; the system will
3023 * not have two scans at the same time, so only one is needed.
3024 * For normal Tx queues (all other queues), no super-size command
3025 * space is needed.
3026 */
3027 if (txq_id == il->cmd_queue) {
3028 slots = TFD_CMD_SLOTS;
3029 actual_slots = slots + 1;
3030 } else {
3031 slots = TFD_TX_CMD_SLOTS;
3032 actual_slots = slots;
3033 }
3034
3035 txq->meta =
3036 kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL);
3037 txq->cmd =
3038 kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL);
3039
3040 if (!txq->meta || !txq->cmd)
3041 goto out_free_arrays;
3042
3043 len = sizeof(struct il_device_cmd);
3044 for (i = 0; i < actual_slots; i++) {
3045 /* only happens for cmd queue */
3046 if (i == slots)
3047 len = IL_MAX_CMD_SIZE;
3048
3049 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
3050 if (!txq->cmd[i])
3051 goto err;
3052 }
3053
3054 /* Alloc driver data array and TFD circular buffer */
3055 ret = il_tx_queue_alloc(il, txq, txq_id);
3056 if (ret)
3057 goto err;
3058
3059 txq->need_update = 0;
3060
3061 /*
3062 * For the default queues 0-3, set up the swq_id
3063 * already -- all others need to get one later
3064 * (if they need one at all).
3065 */
3066 if (txq_id < 4)
3067 il_set_swq_id(txq, txq_id, txq_id);
3068
3069 /* Initialize queue's high/low-water marks, and head/tail idxes */
3070 il_queue_init(il, &txq->q, slots, txq_id);
3071
3072 /* Tell device where to find queue */
3073 il->ops->txq_init(il, txq);
3074
3075 return 0;
3076err:
3077 for (i = 0; i < actual_slots; i++)
3078 kfree(txq->cmd[i]);
3079out_free_arrays:
3080 kfree(txq->meta);
3081 kfree(txq->cmd);
3082
3083 return -ENOMEM;
3084}
3085EXPORT_SYMBOL(il_tx_queue_init);
3086
3087void
3088il_tx_queue_reset(struct il_priv *il, u32 txq_id)
3089{
3090 int slots, actual_slots;
3091 struct il_tx_queue *txq = &il->txq[txq_id];
3092
3093 if (txq_id == il->cmd_queue) {
3094 slots = TFD_CMD_SLOTS;
3095 actual_slots = TFD_CMD_SLOTS + 1;
3096 } else {
3097 slots = TFD_TX_CMD_SLOTS;
3098 actual_slots = TFD_TX_CMD_SLOTS;
3099 }
3100
3101 memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
3102 txq->need_update = 0;
3103
3104 /* Initialize queue's high/low-water marks, and head/tail idxes */
3105 il_queue_init(il, &txq->q, slots, txq_id);
3106
3107 /* Tell device where to find queue */
3108 il->ops->txq_init(il, txq);
3109}
3110EXPORT_SYMBOL(il_tx_queue_reset);
3111
3112/*************** HOST COMMAND QUEUE FUNCTIONS *****/
3113
3114/**
3115 * il_enqueue_hcmd - enqueue a uCode command
3116 * @il: device ilate data point
3117 * @cmd: a point to the ucode command structure
3118 *
3119 * The function returns < 0 values to indicate the operation is
3120 * failed. On success, it turns the idx (> 0) of command in the
3121 * command queue.
3122 */
3123int
3124il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
3125{
3126 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3127 struct il_queue *q = &txq->q;
3128 struct il_device_cmd *out_cmd;
3129 struct il_cmd_meta *out_meta;
3130 dma_addr_t phys_addr;
3131 unsigned long flags;
3132 int len;
3133 u32 idx;
3134 u16 fix_size;
3135
3136 cmd->len = il->ops->get_hcmd_size(cmd->id, cmd->len);
3137 fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
3138
3139 /* If any of the command structures end up being larger than
3140 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
3141 * we will need to increase the size of the TFD entries
3142 * Also, check to see if command buffer should not exceed the size
3143 * of device_cmd and max_cmd_size. */
3144 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
3145 !(cmd->flags & CMD_SIZE_HUGE));
3146 BUG_ON(fix_size > IL_MAX_CMD_SIZE);
3147
3148 if (il_is_rfkill(il) || il_is_ctkill(il)) {
3149 IL_WARN("Not sending command - %s KILL\n",
3150 il_is_rfkill(il) ? "RF" : "CT");
3151 return -EIO;
3152 }
3153
3154 spin_lock_irqsave(&il->hcmd_lock, flags);
3155
3156 if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
3157 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3158
3159 IL_ERR("Restarting adapter due to command queue full\n");
3160 queue_work(il->workqueue, &il->restart);
3161 return -ENOSPC;
3162 }
3163
3164 idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
3165 out_cmd = txq->cmd[idx];
3166 out_meta = &txq->meta[idx];
3167
3168 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
3169 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3170 return -ENOSPC;
3171 }
3172
3173 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
3174 out_meta->flags = cmd->flags | CMD_MAPPED;
3175 if (cmd->flags & CMD_WANT_SKB)
3176 out_meta->source = cmd;
3177 if (cmd->flags & CMD_ASYNC)
3178 out_meta->callback = cmd->callback;
3179
3180 out_cmd->hdr.cmd = cmd->id;
3181 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
3182
3183 /* At this point, the out_cmd now has all of the incoming cmd
3184 * information */
3185
3186 out_cmd->hdr.flags = 0;
3187 out_cmd->hdr.sequence =
3188 cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
3189 if (cmd->flags & CMD_SIZE_HUGE)
3190 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
3191 len = sizeof(struct il_device_cmd);
3192 if (idx == TFD_CMD_SLOTS)
3193 len = IL_MAX_CMD_SIZE;
3194
3195#ifdef CONFIG_IWLEGACY_DEBUG
3196 switch (out_cmd->hdr.cmd) {
3197 case C_TX_LINK_QUALITY_CMD:
3198 case C_SENSITIVITY:
3199 D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
3200 "%d bytes at %d[%d]:%d\n",
3201 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3202 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
3203 q->write_ptr, idx, il->cmd_queue);
3204 break;
3205 default:
3206 D_HC("Sending command %s (#%x), seq: 0x%04X, "
3207 "%d bytes at %d[%d]:%d\n",
3208 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3209 le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
3210 idx, il->cmd_queue);
3211 }
3212#endif
3213
3214 phys_addr =
3215 pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size,
3216 PCI_DMA_BIDIRECTIONAL);
3217 if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr))) {
3218 idx = -ENOMEM;
3219 goto out;
3220 }
3221 dma_unmap_addr_set(out_meta, mapping, phys_addr);
3222 dma_unmap_len_set(out_meta, len, fix_size);
3223
3224 txq->need_update = 1;
3225
3226 if (il->ops->txq_update_byte_cnt_tbl)
3227 /* Set up entry in queue's byte count circular buffer */
3228 il->ops->txq_update_byte_cnt_tbl(il, txq, 0);
3229
3230 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size, 1,
3231 U32_PAD(cmd->len));
3232
3233 /* Increment and update queue's write idx */
3234 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
3235 il_txq_update_write_ptr(il, txq);
3236
3237out:
3238 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3239 return idx;
3240}
3241
3242/**
3243 * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
3244 *
3245 * When FW advances 'R' idx, all entries between old and new 'R' idx
3246 * need to be reclaimed. As result, some free space forms. If there is
3247 * enough free space (> low mark), wake the stack that feeds us.
3248 */
3249static void
3250il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
3251{
3252 struct il_tx_queue *txq = &il->txq[txq_id];
3253 struct il_queue *q = &txq->q;
3254 int nfreed = 0;
3255
3256 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
3257 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
3258 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
3259 q->write_ptr, q->read_ptr);
3260 return;
3261 }
3262
3263 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
3264 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3265
3266 if (nfreed++ > 0) {
3267 IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
3268 q->write_ptr, q->read_ptr);
3269 queue_work(il->workqueue, &il->restart);
3270 }
3271
3272 }
3273}
3274
3275/**
3276 * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
3277 * @rxb: Rx buffer to reclaim
3278 *
3279 * If an Rx buffer has an async callback associated with it the callback
3280 * will be executed. The attached skb (if present) will only be freed
3281 * if the callback returns 1
3282 */
3283void
3284il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
3285{
3286 struct il_rx_pkt *pkt = rxb_addr(rxb);
3287 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3288 int txq_id = SEQ_TO_QUEUE(sequence);
3289 int idx = SEQ_TO_IDX(sequence);
3290 int cmd_idx;
3291 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
3292 struct il_device_cmd *cmd;
3293 struct il_cmd_meta *meta;
3294 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3295 unsigned long flags;
3296
3297 /* If a Tx command is being handled and it isn't in the actual
3298 * command queue then there a command routing bug has been introduced
3299 * in the queue management code. */
3300 if (WARN
3301 (txq_id != il->cmd_queue,
3302 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
3303 txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
3304 il->txq[il->cmd_queue].q.write_ptr)) {
3305 il_print_hex_error(il, pkt, 32);
3306 return;
3307 }
3308
3309 cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
3310 cmd = txq->cmd[cmd_idx];
3311 meta = &txq->meta[cmd_idx];
3312
3313 txq->time_stamp = jiffies;
3314
3315 pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping),
3316 dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL);
3317
3318 /* Input error checking is done when commands are added to queue. */
3319 if (meta->flags & CMD_WANT_SKB) {
3320 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
3321 rxb->page = NULL;
3322 } else if (meta->callback)
3323 meta->callback(il, cmd, pkt);
3324
3325 spin_lock_irqsave(&il->hcmd_lock, flags);
3326
3327 il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
3328
3329 if (!(meta->flags & CMD_ASYNC)) {
3330 clear_bit(S_HCMD_ACTIVE, &il->status);
3331 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
3332 il_get_cmd_string(cmd->hdr.cmd));
3333 wake_up(&il->wait_command_queue);
3334 }
3335
3336 /* Mark as unmapped */
3337 meta->flags = 0;
3338
3339 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3340}
3341EXPORT_SYMBOL(il_tx_cmd_complete);
3342
3343MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
3344MODULE_VERSION(IWLWIFI_VERSION);
3345MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
3346MODULE_LICENSE("GPL");
3347
3348/*
3349 * set bt_coex_active to true, uCode will do kill/defer
3350 * every time the priority line is asserted (BT is sending signals on the
3351 * priority line in the PCIx).
3352 * set bt_coex_active to false, uCode will ignore the BT activity and
3353 * perform the normal operation
3354 *
3355 * User might experience transmit issue on some platform due to WiFi/BT
3356 * co-exist problem. The possible behaviors are:
3357 * Able to scan and finding all the available AP
3358 * Not able to associate with any AP
3359 * On those platforms, WiFi communication can be restored by set
3360 * "bt_coex_active" module parameter to "false"
3361 *
3362 * default: bt_coex_active = true (BT_COEX_ENABLE)
3363 */
3364static bool bt_coex_active = true;
3365module_param(bt_coex_active, bool, S_IRUGO);
3366MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
3367
3368u32 il_debug_level;
3369EXPORT_SYMBOL(il_debug_level);
3370
3371const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3372EXPORT_SYMBOL(il_bcast_addr);
3373
3374#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
3375#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
3376static void
3377il_init_ht_hw_capab(const struct il_priv *il,
3378 struct ieee80211_sta_ht_cap *ht_info,
3379 enum ieee80211_band band)
3380{
3381 u16 max_bit_rate = 0;
3382 u8 rx_chains_num = il->hw_params.rx_chains_num;
3383 u8 tx_chains_num = il->hw_params.tx_chains_num;
3384
3385 ht_info->cap = 0;
3386 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
3387
3388 ht_info->ht_supported = true;
3389
3390 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
3391 max_bit_rate = MAX_BIT_RATE_20_MHZ;
3392 if (il->hw_params.ht40_channel & BIT(band)) {
3393 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
3394 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
3395 ht_info->mcs.rx_mask[4] = 0x01;
3396 max_bit_rate = MAX_BIT_RATE_40_MHZ;
3397 }
3398
3399 if (il->cfg->mod_params->amsdu_size_8K)
3400 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
3401
3402 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3403 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3404
3405 ht_info->mcs.rx_mask[0] = 0xFF;
3406 if (rx_chains_num >= 2)
3407 ht_info->mcs.rx_mask[1] = 0xFF;
3408 if (rx_chains_num >= 3)
3409 ht_info->mcs.rx_mask[2] = 0xFF;
3410
3411 /* Highest supported Rx data rate */
3412 max_bit_rate *= rx_chains_num;
3413 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
3414 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
3415
3416 /* Tx MCS capabilities */
3417 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3418 if (tx_chains_num != rx_chains_num) {
3419 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
3420 ht_info->mcs.tx_params |=
3421 ((tx_chains_num -
3422 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
3423 }
3424}
3425
3426/**
3427 * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
3428 */
3429int
3430il_init_geos(struct il_priv *il)
3431{
3432 struct il_channel_info *ch;
3433 struct ieee80211_supported_band *sband;
3434 struct ieee80211_channel *channels;
3435 struct ieee80211_channel *geo_ch;
3436 struct ieee80211_rate *rates;
3437 int i = 0;
3438 s8 max_tx_power = 0;
3439
3440 if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
3441 il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
3442 D_INFO("Geography modes already initialized.\n");
3443 set_bit(S_GEO_CONFIGURED, &il->status);
3444 return 0;
3445 }
3446
3447 channels =
3448 kzalloc(sizeof(struct ieee80211_channel) * il->channel_count,
3449 GFP_KERNEL);
3450 if (!channels)
3451 return -ENOMEM;
3452
3453 rates =
3454 kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
3455 GFP_KERNEL);
3456 if (!rates) {
3457 kfree(channels);
3458 return -ENOMEM;
3459 }
3460
3461 /* 5.2GHz channels start after the 2.4GHz channels */
3462 sband = &il->bands[IEEE80211_BAND_5GHZ];
3463 sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
3464 /* just OFDM */
3465 sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
3466 sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
3467
3468 if (il->cfg->sku & IL_SKU_N)
3469 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ);
3470
3471 sband = &il->bands[IEEE80211_BAND_2GHZ];
3472 sband->channels = channels;
3473 /* OFDM & CCK */
3474 sband->bitrates = rates;
3475 sband->n_bitrates = RATE_COUNT_LEGACY;
3476
3477 if (il->cfg->sku & IL_SKU_N)
3478 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ);
3479
3480 il->ieee_channels = channels;
3481 il->ieee_rates = rates;
3482
3483 for (i = 0; i < il->channel_count; i++) {
3484 ch = &il->channel_info[i];
3485
3486 if (!il_is_channel_valid(ch))
3487 continue;
3488
3489 sband = &il->bands[ch->band];
3490
3491 geo_ch = &sband->channels[sband->n_channels++];
3492
3493 geo_ch->center_freq =
3494 ieee80211_channel_to_frequency(ch->channel, ch->band);
3495 geo_ch->max_power = ch->max_power_avg;
3496 geo_ch->max_antenna_gain = 0xff;
3497 geo_ch->hw_value = ch->channel;
3498
3499 if (il_is_channel_valid(ch)) {
3500 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
3501 geo_ch->flags |= IEEE80211_CHAN_NO_IR;
3502
3503 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
3504 geo_ch->flags |= IEEE80211_CHAN_NO_IR;
3505
3506 if (ch->flags & EEPROM_CHANNEL_RADAR)
3507 geo_ch->flags |= IEEE80211_CHAN_RADAR;
3508
3509 geo_ch->flags |= ch->ht40_extension_channel;
3510
3511 if (ch->max_power_avg > max_tx_power)
3512 max_tx_power = ch->max_power_avg;
3513 } else {
3514 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
3515 }
3516
3517 D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
3518 geo_ch->center_freq,
3519 il_is_channel_a_band(ch) ? "5.2" : "2.4",
3520 geo_ch->
3521 flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
3522 geo_ch->flags);
3523 }
3524
3525 il->tx_power_device_lmt = max_tx_power;
3526 il->tx_power_user_lmt = max_tx_power;
3527 il->tx_power_next = max_tx_power;
3528
3529 if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
3530 (il->cfg->sku & IL_SKU_A)) {
3531 IL_INFO("Incorrectly detected BG card as ABG. "
3532 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
3533 il->pci_dev->device, il->pci_dev->subsystem_device);
3534 il->cfg->sku &= ~IL_SKU_A;
3535 }
3536
3537 IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
3538 il->bands[IEEE80211_BAND_2GHZ].n_channels,
3539 il->bands[IEEE80211_BAND_5GHZ].n_channels);
3540
3541 set_bit(S_GEO_CONFIGURED, &il->status);
3542
3543 return 0;
3544}
3545EXPORT_SYMBOL(il_init_geos);
3546
3547/*
3548 * il_free_geos - undo allocations in il_init_geos
3549 */
3550void
3551il_free_geos(struct il_priv *il)
3552{
3553 kfree(il->ieee_channels);
3554 kfree(il->ieee_rates);
3555 clear_bit(S_GEO_CONFIGURED, &il->status);
3556}
3557EXPORT_SYMBOL(il_free_geos);
3558
3559static bool
3560il_is_channel_extension(struct il_priv *il, enum ieee80211_band band,
3561 u16 channel, u8 extension_chan_offset)
3562{
3563 const struct il_channel_info *ch_info;
3564
3565 ch_info = il_get_channel_info(il, band, channel);
3566 if (!il_is_channel_valid(ch_info))
3567 return false;
3568
3569 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
3570 return !(ch_info->
3571 ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
3572 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
3573 return !(ch_info->
3574 ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
3575
3576 return false;
3577}
3578
3579bool
3580il_is_ht40_tx_allowed(struct il_priv *il, struct ieee80211_sta_ht_cap *ht_cap)
3581{
3582 if (!il->ht.enabled || !il->ht.is_40mhz)
3583 return false;
3584
3585 /*
3586 * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
3587 * the bit will not set if it is pure 40MHz case
3588 */
3589 if (ht_cap && !ht_cap->ht_supported)
3590 return false;
3591
3592#ifdef CONFIG_IWLEGACY_DEBUGFS
3593 if (il->disable_ht40)
3594 return false;
3595#endif
3596
3597 return il_is_channel_extension(il, il->band,
3598 le16_to_cpu(il->staging.channel),
3599 il->ht.extension_chan_offset);
3600}
3601EXPORT_SYMBOL(il_is_ht40_tx_allowed);
3602
3603static u16
3604il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
3605{
3606 u16 new_val;
3607 u16 beacon_factor;
3608
3609 /*
3610 * If mac80211 hasn't given us a beacon interval, program
3611 * the default into the device.
3612 */
3613 if (!beacon_val)
3614 return DEFAULT_BEACON_INTERVAL;
3615
3616 /*
3617 * If the beacon interval we obtained from the peer
3618 * is too large, we'll have to wake up more often
3619 * (and in IBSS case, we'll beacon too much)
3620 *
3621 * For example, if max_beacon_val is 4096, and the
3622 * requested beacon interval is 7000, we'll have to
3623 * use 3500 to be able to wake up on the beacons.
3624 *
3625 * This could badly influence beacon detection stats.
3626 */
3627
3628 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
3629 new_val = beacon_val / beacon_factor;
3630
3631 if (!new_val)
3632 new_val = max_beacon_val;
3633
3634 return new_val;
3635}
3636
3637int
3638il_send_rxon_timing(struct il_priv *il)
3639{
3640 u64 tsf;
3641 s32 interval_tm, rem;
3642 struct ieee80211_conf *conf = NULL;
3643 u16 beacon_int;
3644 struct ieee80211_vif *vif = il->vif;
3645
3646 conf = &il->hw->conf;
3647
3648 lockdep_assert_held(&il->mutex);
3649
3650 memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
3651
3652 il->timing.timestamp = cpu_to_le64(il->timestamp);
3653 il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
3654
3655 beacon_int = vif ? vif->bss_conf.beacon_int : 0;
3656
3657 /*
3658 * TODO: For IBSS we need to get atim_win from mac80211,
3659 * for now just always use 0
3660 */
3661 il->timing.atim_win = 0;
3662
3663 beacon_int =
3664 il_adjust_beacon_interval(beacon_int,
3665 il->hw_params.max_beacon_itrvl *
3666 TIME_UNIT);
3667 il->timing.beacon_interval = cpu_to_le16(beacon_int);
3668
3669 tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
3670 interval_tm = beacon_int * TIME_UNIT;
3671 rem = do_div(tsf, interval_tm);
3672 il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
3673
3674 il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
3675
3676 D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
3677 le16_to_cpu(il->timing.beacon_interval),
3678 le32_to_cpu(il->timing.beacon_init_val),
3679 le16_to_cpu(il->timing.atim_win));
3680
3681 return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
3682 &il->timing);
3683}
3684EXPORT_SYMBOL(il_send_rxon_timing);
3685
3686void
3687il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt)
3688{
3689 struct il_rxon_cmd *rxon = &il->staging;
3690
3691 if (hw_decrypt)
3692 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
3693 else
3694 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
3695
3696}
3697EXPORT_SYMBOL(il_set_rxon_hwcrypto);
3698
3699/* validate RXON structure is valid */
3700int
3701il_check_rxon_cmd(struct il_priv *il)
3702{
3703 struct il_rxon_cmd *rxon = &il->staging;
3704 bool error = false;
3705
3706 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
3707 if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
3708 IL_WARN("check 2.4G: wrong narrow\n");
3709 error = true;
3710 }
3711 if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
3712 IL_WARN("check 2.4G: wrong radar\n");
3713 error = true;
3714 }
3715 } else {
3716 if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
3717 IL_WARN("check 5.2G: not short slot!\n");
3718 error = true;
3719 }
3720 if (rxon->flags & RXON_FLG_CCK_MSK) {
3721 IL_WARN("check 5.2G: CCK!\n");
3722 error = true;
3723 }
3724 }
3725 if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
3726 IL_WARN("mac/bssid mcast!\n");
3727 error = true;
3728 }
3729
3730 /* make sure basic rates 6Mbps and 1Mbps are supported */
3731 if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
3732 (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
3733 IL_WARN("neither 1 nor 6 are basic\n");
3734 error = true;
3735 }
3736
3737 if (le16_to_cpu(rxon->assoc_id) > 2007) {
3738 IL_WARN("aid > 2007\n");
3739 error = true;
3740 }
3741
3742 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
3743 (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
3744 IL_WARN("CCK and short slot\n");
3745 error = true;
3746 }
3747
3748 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
3749 (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
3750 IL_WARN("CCK and auto detect");
3751 error = true;
3752 }
3753
3754 if ((rxon->
3755 flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
3756 RXON_FLG_TGG_PROTECT_MSK) {
3757 IL_WARN("TGg but no auto-detect\n");
3758 error = true;
3759 }
3760
3761 if (error)
3762 IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
3763
3764 if (error) {
3765 IL_ERR("Invalid RXON\n");
3766 return -EINVAL;
3767 }
3768 return 0;
3769}
3770EXPORT_SYMBOL(il_check_rxon_cmd);
3771
3772/**
3773 * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
3774 * @il: staging_rxon is compared to active_rxon
3775 *
3776 * If the RXON structure is changing enough to require a new tune,
3777 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
3778 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
3779 */
3780int
3781il_full_rxon_required(struct il_priv *il)
3782{
3783 const struct il_rxon_cmd *staging = &il->staging;
3784 const struct il_rxon_cmd *active = &il->active;
3785
3786#define CHK(cond) \
3787 if ((cond)) { \
3788 D_INFO("need full RXON - " #cond "\n"); \
3789 return 1; \
3790 }
3791
3792#define CHK_NEQ(c1, c2) \
3793 if ((c1) != (c2)) { \
3794 D_INFO("need full RXON - " \
3795 #c1 " != " #c2 " - %d != %d\n", \
3796 (c1), (c2)); \
3797 return 1; \
3798 }
3799
3800 /* These items are only settable from the full RXON command */
3801 CHK(!il_is_associated(il));
3802 CHK(!ether_addr_equal_64bits(staging->bssid_addr, active->bssid_addr));
3803 CHK(!ether_addr_equal_64bits(staging->node_addr, active->node_addr));
3804 CHK(!ether_addr_equal_64bits(staging->wlap_bssid_addr,
3805 active->wlap_bssid_addr));
3806 CHK_NEQ(staging->dev_type, active->dev_type);
3807 CHK_NEQ(staging->channel, active->channel);
3808 CHK_NEQ(staging->air_propagation, active->air_propagation);
3809 CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
3810 active->ofdm_ht_single_stream_basic_rates);
3811 CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
3812 active->ofdm_ht_dual_stream_basic_rates);
3813 CHK_NEQ(staging->assoc_id, active->assoc_id);
3814
3815 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
3816 * be updated with the RXON_ASSOC command -- however only some
3817 * flag transitions are allowed using RXON_ASSOC */
3818
3819 /* Check if we are not switching bands */
3820 CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
3821 active->flags & RXON_FLG_BAND_24G_MSK);
3822
3823 /* Check if we are switching association toggle */
3824 CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
3825 active->filter_flags & RXON_FILTER_ASSOC_MSK);
3826
3827#undef CHK
3828#undef CHK_NEQ
3829
3830 return 0;
3831}
3832EXPORT_SYMBOL(il_full_rxon_required);
3833
3834u8
3835il_get_lowest_plcp(struct il_priv *il)
3836{
3837 /*
3838 * Assign the lowest rate -- should really get this from
3839 * the beacon skb from mac80211.
3840 */
3841 if (il->staging.flags & RXON_FLG_BAND_24G_MSK)
3842 return RATE_1M_PLCP;
3843 else
3844 return RATE_6M_PLCP;
3845}
3846EXPORT_SYMBOL(il_get_lowest_plcp);
3847
3848static void
3849_il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
3850{
3851 struct il_rxon_cmd *rxon = &il->staging;
3852
3853 if (!il->ht.enabled) {
3854 rxon->flags &=
3855 ~(RXON_FLG_CHANNEL_MODE_MSK |
3856 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
3857 | RXON_FLG_HT_PROT_MSK);
3858 return;
3859 }
3860
3861 rxon->flags |=
3862 cpu_to_le32(il->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
3863
3864 /* Set up channel bandwidth:
3865 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
3866 /* clear the HT channel mode before set the mode */
3867 rxon->flags &=
3868 ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
3869 if (il_is_ht40_tx_allowed(il, NULL)) {
3870 /* pure ht40 */
3871 if (il->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
3872 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
3873 /* Note: control channel is opposite of extension channel */
3874 switch (il->ht.extension_chan_offset) {
3875 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3876 rxon->flags &=
3877 ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
3878 break;
3879 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
3880 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
3881 break;
3882 }
3883 } else {
3884 /* Note: control channel is opposite of extension channel */
3885 switch (il->ht.extension_chan_offset) {
3886 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3887 rxon->flags &=
3888 ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
3889 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3890 break;
3891 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
3892 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
3893 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3894 break;
3895 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
3896 default:
3897 /* channel location only valid if in Mixed mode */
3898 IL_ERR("invalid extension channel offset\n");
3899 break;
3900 }
3901 }
3902 } else {
3903 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
3904 }
3905
3906 if (il->ops->set_rxon_chain)
3907 il->ops->set_rxon_chain(il);
3908
3909 D_ASSOC("rxon flags 0x%X operation mode :0x%X "
3910 "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
3911 il->ht.protection, il->ht.extension_chan_offset);
3912}
3913
3914void
3915il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
3916{
3917 _il_set_rxon_ht(il, ht_conf);
3918}
3919EXPORT_SYMBOL(il_set_rxon_ht);
3920
3921/* Return valid, unused, channel for a passive scan to reset the RF */
3922u8
3923il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band)
3924{
3925 const struct il_channel_info *ch_info;
3926 int i;
3927 u8 channel = 0;
3928 u8 min, max;
3929
3930 if (band == IEEE80211_BAND_5GHZ) {
3931 min = 14;
3932 max = il->channel_count;
3933 } else {
3934 min = 0;
3935 max = 14;
3936 }
3937
3938 for (i = min; i < max; i++) {
3939 channel = il->channel_info[i].channel;
3940 if (channel == le16_to_cpu(il->staging.channel))
3941 continue;
3942
3943 ch_info = il_get_channel_info(il, band, channel);
3944 if (il_is_channel_valid(ch_info))
3945 break;
3946 }
3947
3948 return channel;
3949}
3950EXPORT_SYMBOL(il_get_single_channel_number);
3951
3952/**
3953 * il_set_rxon_channel - Set the band and channel values in staging RXON
3954 * @ch: requested channel as a pointer to struct ieee80211_channel
3955
3956 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
3957 * in the staging RXON flag structure based on the ch->band
3958 */
3959int
3960il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch)
3961{
3962 enum ieee80211_band band = ch->band;
3963 u16 channel = ch->hw_value;
3964
3965 if (le16_to_cpu(il->staging.channel) == channel && il->band == band)
3966 return 0;
3967
3968 il->staging.channel = cpu_to_le16(channel);
3969 if (band == IEEE80211_BAND_5GHZ)
3970 il->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
3971 else
3972 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
3973
3974 il->band = band;
3975
3976 D_INFO("Staging channel set to %d [%d]\n", channel, band);
3977
3978 return 0;
3979}
3980EXPORT_SYMBOL(il_set_rxon_channel);
3981
3982void
3983il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
3984 struct ieee80211_vif *vif)
3985{
3986 if (band == IEEE80211_BAND_5GHZ) {
3987 il->staging.flags &=
3988 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
3989 RXON_FLG_CCK_MSK);
3990 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
3991 } else {
3992 /* Copied from il_post_associate() */
3993 if (vif && vif->bss_conf.use_short_slot)
3994 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
3995 else
3996 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
3997
3998 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
3999 il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
4000 il->staging.flags &= ~RXON_FLG_CCK_MSK;
4001 }
4002}
4003EXPORT_SYMBOL(il_set_flags_for_band);
4004
4005/*
4006 * initialize rxon structure with default values from eeprom
4007 */
4008void
4009il_connection_init_rx_config(struct il_priv *il)
4010{
4011 const struct il_channel_info *ch_info;
4012
4013 memset(&il->staging, 0, sizeof(il->staging));
4014
4015 switch (il->iw_mode) {
4016 case NL80211_IFTYPE_UNSPECIFIED:
4017 il->staging.dev_type = RXON_DEV_TYPE_ESS;
4018 break;
4019 case NL80211_IFTYPE_STATION:
4020 il->staging.dev_type = RXON_DEV_TYPE_ESS;
4021 il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
4022 break;
4023 case NL80211_IFTYPE_ADHOC:
4024 il->staging.dev_type = RXON_DEV_TYPE_IBSS;
4025 il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
4026 il->staging.filter_flags =
4027 RXON_FILTER_BCON_AWARE_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
4028 break;
4029 default:
4030 IL_ERR("Unsupported interface type %d\n", il->vif->type);
4031 return;
4032 }
4033
4034#if 0
4035 /* TODO: Figure out when short_preamble would be set and cache from
4036 * that */
4037 if (!hw_to_local(il->hw)->short_preamble)
4038 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
4039 else
4040 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
4041#endif
4042
4043 ch_info =
4044 il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel));
4045
4046 if (!ch_info)
4047 ch_info = &il->channel_info[0];
4048
4049 il->staging.channel = cpu_to_le16(ch_info->channel);
4050 il->band = ch_info->band;
4051
4052 il_set_flags_for_band(il, il->band, il->vif);
4053
4054 il->staging.ofdm_basic_rates =
4055 (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
4056 il->staging.cck_basic_rates =
4057 (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
4058
4059 /* clear both MIX and PURE40 mode flag */
4060 il->staging.flags &=
4061 ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
4062 if (il->vif)
4063 memcpy(il->staging.node_addr, il->vif->addr, ETH_ALEN);
4064
4065 il->staging.ofdm_ht_single_stream_basic_rates = 0xff;
4066 il->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
4067}
4068EXPORT_SYMBOL(il_connection_init_rx_config);
4069
4070void
4071il_set_rate(struct il_priv *il)
4072{
4073 const struct ieee80211_supported_band *hw = NULL;
4074 struct ieee80211_rate *rate;
4075 int i;
4076
4077 hw = il_get_hw_mode(il, il->band);
4078 if (!hw) {
4079 IL_ERR("Failed to set rate: unable to get hw mode\n");
4080 return;
4081 }
4082
4083 il->active_rate = 0;
4084
4085 for (i = 0; i < hw->n_bitrates; i++) {
4086 rate = &(hw->bitrates[i]);
4087 if (rate->hw_value < RATE_COUNT_LEGACY)
4088 il->active_rate |= (1 << rate->hw_value);
4089 }
4090
4091 D_RATE("Set active_rate = %0x\n", il->active_rate);
4092
4093 il->staging.cck_basic_rates =
4094 (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
4095
4096 il->staging.ofdm_basic_rates =
4097 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
4098}
4099EXPORT_SYMBOL(il_set_rate);
4100
4101void
4102il_chswitch_done(struct il_priv *il, bool is_success)
4103{
4104 if (test_bit(S_EXIT_PENDING, &il->status))
4105 return;
4106
4107 if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
4108 ieee80211_chswitch_done(il->vif, is_success);
4109}
4110EXPORT_SYMBOL(il_chswitch_done);
4111
4112void
4113il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
4114{
4115 struct il_rx_pkt *pkt = rxb_addr(rxb);
4116 struct il_csa_notification *csa = &(pkt->u.csa_notif);
4117 struct il_rxon_cmd *rxon = (void *)&il->active;
4118
4119 if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
4120 return;
4121
4122 if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
4123 rxon->channel = csa->channel;
4124 il->staging.channel = csa->channel;
4125 D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
4126 il_chswitch_done(il, true);
4127 } else {
4128 IL_ERR("CSA notif (fail) : channel %d\n",
4129 le16_to_cpu(csa->channel));
4130 il_chswitch_done(il, false);
4131 }
4132}
4133EXPORT_SYMBOL(il_hdl_csa);
4134
4135#ifdef CONFIG_IWLEGACY_DEBUG
4136void
4137il_print_rx_config_cmd(struct il_priv *il)
4138{
4139 struct il_rxon_cmd *rxon = &il->staging;
4140
4141 D_RADIO("RX CONFIG:\n");
4142 il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
4143 D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
4144 D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
4145 D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
4146 D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
4147 D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
4148 D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
4149 D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
4150 D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
4151 D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
4152}
4153EXPORT_SYMBOL(il_print_rx_config_cmd);
4154#endif
4155/**
4156 * il_irq_handle_error - called for HW or SW error interrupt from card
4157 */
4158void
4159il_irq_handle_error(struct il_priv *il)
4160{
4161 /* Set the FW error flag -- cleared on il_down */
4162 set_bit(S_FW_ERROR, &il->status);
4163
4164 /* Cancel currently queued command. */
4165 clear_bit(S_HCMD_ACTIVE, &il->status);
4166
4167 IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
4168
4169 il->ops->dump_nic_error_log(il);
4170 if (il->ops->dump_fh)
4171 il->ops->dump_fh(il, NULL, false);
4172#ifdef CONFIG_IWLEGACY_DEBUG
4173 if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
4174 il_print_rx_config_cmd(il);
4175#endif
4176
4177 wake_up(&il->wait_command_queue);
4178
4179 /* Keep the restart process from trying to send host
4180 * commands by clearing the INIT status bit */
4181 clear_bit(S_READY, &il->status);
4182
4183 if (!test_bit(S_EXIT_PENDING, &il->status)) {
4184 IL_DBG(IL_DL_FW_ERRORS,
4185 "Restarting adapter due to uCode error.\n");
4186
4187 if (il->cfg->mod_params->restart_fw)
4188 queue_work(il->workqueue, &il->restart);
4189 }
4190}
4191EXPORT_SYMBOL(il_irq_handle_error);
4192
4193static int
4194_il_apm_stop_master(struct il_priv *il)
4195{
4196 int ret = 0;
4197
4198 /* stop device's busmaster DMA activity */
4199 _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
4200
4201 ret =
4202 _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
4203 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
4204 if (ret < 0)
4205 IL_WARN("Master Disable Timed Out, 100 usec\n");
4206
4207 D_INFO("stop master\n");
4208
4209 return ret;
4210}
4211
4212void
4213_il_apm_stop(struct il_priv *il)
4214{
4215 lockdep_assert_held(&il->reg_lock);
4216
4217 D_INFO("Stop card, put in low power state\n");
4218
4219 /* Stop device's DMA activity */
4220 _il_apm_stop_master(il);
4221
4222 /* Reset the entire device */
4223 _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
4224
4225 udelay(10);
4226
4227 /*
4228 * Clear "initialization complete" bit to move adapter from
4229 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
4230 */
4231 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
4232}
4233EXPORT_SYMBOL(_il_apm_stop);
4234
4235void
4236il_apm_stop(struct il_priv *il)
4237{
4238 unsigned long flags;
4239
4240 spin_lock_irqsave(&il->reg_lock, flags);
4241 _il_apm_stop(il);
4242 spin_unlock_irqrestore(&il->reg_lock, flags);
4243}
4244EXPORT_SYMBOL(il_apm_stop);
4245
4246/*
4247 * Start up NIC's basic functionality after it has been reset
4248 * (e.g. after platform boot, or shutdown via il_apm_stop())
4249 * NOTE: This does not load uCode nor start the embedded processor
4250 */
4251int
4252il_apm_init(struct il_priv *il)
4253{
4254 int ret = 0;
4255 u16 lctl;
4256
4257 D_INFO("Init card's basic functions\n");
4258
4259 /*
4260 * Use "set_bit" below rather than "write", to preserve any hardware
4261 * bits already set by default after reset.
4262 */
4263
4264 /* Disable L0S exit timer (platform NMI Work/Around) */
4265 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
4266 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
4267
4268 /*
4269 * Disable L0s without affecting L1;
4270 * don't wait for ICH L0s (ICH bug W/A)
4271 */
4272 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
4273 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
4274
4275 /* Set FH wait threshold to maximum (HW error during stress W/A) */
4276 il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
4277
4278 /*
4279 * Enable HAP INTA (interrupt from management bus) to
4280 * wake device's PCI Express link L1a -> L0s
4281 * NOTE: This is no-op for 3945 (non-existent bit)
4282 */
4283 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
4284 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
4285
4286 /*
4287 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
4288 * Check if BIOS (or OS) enabled L1-ASPM on this device.
4289 * If so (likely), disable L0S, so device moves directly L0->L1;
4290 * costs negligible amount of power savings.
4291 * If not (unlikely), enable L0S, so there is at least some
4292 * power savings, even without L1.
4293 */
4294 if (il->cfg->set_l0s) {
4295 pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
4296 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
4297 /* L1-ASPM enabled; disable(!) L0S */
4298 il_set_bit(il, CSR_GIO_REG,
4299 CSR_GIO_REG_VAL_L0S_ENABLED);
4300 D_POWER("L1 Enabled; Disabling L0S\n");
4301 } else {
4302 /* L1-ASPM disabled; enable(!) L0S */
4303 il_clear_bit(il, CSR_GIO_REG,
4304 CSR_GIO_REG_VAL_L0S_ENABLED);
4305 D_POWER("L1 Disabled; Enabling L0S\n");
4306 }
4307 }
4308
4309 /* Configure analog phase-lock-loop before activating to D0A */
4310 if (il->cfg->pll_cfg_val)
4311 il_set_bit(il, CSR_ANA_PLL_CFG,
4312 il->cfg->pll_cfg_val);
4313
4314 /*
4315 * Set "initialization complete" bit to move adapter from
4316 * D0U* --> D0A* (powered-up active) state.
4317 */
4318 il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
4319
4320 /*
4321 * Wait for clock stabilization; once stabilized, access to
4322 * device-internal resources is supported, e.g. il_wr_prph()
4323 * and accesses to uCode SRAM.
4324 */
4325 ret =
4326 _il_poll_bit(il, CSR_GP_CNTRL,
4327 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
4328 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
4329 if (ret < 0) {
4330 D_INFO("Failed to init the card\n");
4331 goto out;
4332 }
4333
4334 /*
4335 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
4336 * BSM (Boostrap State Machine) is only in 3945 and 4965.
4337 *
4338 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
4339 * do not disable clocks. This preserves any hardware bits already
4340 * set by default in "CLK_CTRL_REG" after reset.
4341 */
4342 if (il->cfg->use_bsm)
4343 il_wr_prph(il, APMG_CLK_EN_REG,
4344 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
4345 else
4346 il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
4347 udelay(20);
4348
4349 /* Disable L1-Active */
4350 il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
4351 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
4352
4353out:
4354 return ret;
4355}
4356EXPORT_SYMBOL(il_apm_init);
4357
4358int
4359il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
4360{
4361 int ret;
4362 s8 prev_tx_power;
4363 bool defer;
4364
4365 lockdep_assert_held(&il->mutex);
4366
4367 if (il->tx_power_user_lmt == tx_power && !force)
4368 return 0;
4369
4370 if (!il->ops->send_tx_power)
4371 return -EOPNOTSUPP;
4372
4373 /* 0 dBm mean 1 milliwatt */
4374 if (tx_power < 0) {
4375 IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
4376 return -EINVAL;
4377 }
4378
4379 if (tx_power > il->tx_power_device_lmt) {
4380 IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
4381 tx_power, il->tx_power_device_lmt);
4382 return -EINVAL;
4383 }
4384
4385 if (!il_is_ready_rf(il))
4386 return -EIO;
4387
4388 /* scan complete and commit_rxon use tx_power_next value,
4389 * it always need to be updated for newest request */
4390 il->tx_power_next = tx_power;
4391
4392 /* do not set tx power when scanning or channel changing */
4393 defer = test_bit(S_SCANNING, &il->status) ||
4394 memcmp(&il->active, &il->staging, sizeof(il->staging));
4395 if (defer && !force) {
4396 D_INFO("Deferring tx power set\n");
4397 return 0;
4398 }
4399
4400 prev_tx_power = il->tx_power_user_lmt;
4401 il->tx_power_user_lmt = tx_power;
4402
4403 ret = il->ops->send_tx_power(il);
4404
4405 /* if fail to set tx_power, restore the orig. tx power */
4406 if (ret) {
4407 il->tx_power_user_lmt = prev_tx_power;
4408 il->tx_power_next = prev_tx_power;
4409 }
4410 return ret;
4411}
4412EXPORT_SYMBOL(il_set_tx_power);
4413
4414void
4415il_send_bt_config(struct il_priv *il)
4416{
4417 struct il_bt_cmd bt_cmd = {
4418 .lead_time = BT_LEAD_TIME_DEF,
4419 .max_kill = BT_MAX_KILL_DEF,
4420 .kill_ack_mask = 0,
4421 .kill_cts_mask = 0,
4422 };
4423
4424 if (!bt_coex_active)
4425 bt_cmd.flags = BT_COEX_DISABLE;
4426 else
4427 bt_cmd.flags = BT_COEX_ENABLE;
4428
4429 D_INFO("BT coex %s\n",
4430 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
4431
4432 if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
4433 IL_ERR("failed to send BT Coex Config\n");
4434}
4435EXPORT_SYMBOL(il_send_bt_config);
4436
4437int
4438il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
4439{
4440 struct il_stats_cmd stats_cmd = {
4441 .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
4442 };
4443
4444 if (flags & CMD_ASYNC)
4445 return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
4446 &stats_cmd, NULL);
4447 else
4448 return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
4449 &stats_cmd);
4450}
4451EXPORT_SYMBOL(il_send_stats_request);
4452
4453void
4454il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
4455{
4456#ifdef CONFIG_IWLEGACY_DEBUG
4457 struct il_rx_pkt *pkt = rxb_addr(rxb);
4458 struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
4459 D_RX("sleep mode: %d, src: %d\n",
4460 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
4461#endif
4462}
4463EXPORT_SYMBOL(il_hdl_pm_sleep);
4464
4465void
4466il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
4467{
4468 struct il_rx_pkt *pkt = rxb_addr(rxb);
4469 u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
4470 D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
4471 il_get_cmd_string(pkt->hdr.cmd));
4472 il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
4473}
4474EXPORT_SYMBOL(il_hdl_pm_debug_stats);
4475
4476void
4477il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
4478{
4479 struct il_rx_pkt *pkt = rxb_addr(rxb);
4480
4481 IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
4482 "seq 0x%04X ser 0x%08X\n",
4483 le32_to_cpu(pkt->u.err_resp.error_type),
4484 il_get_cmd_string(pkt->u.err_resp.cmd_id),
4485 pkt->u.err_resp.cmd_id,
4486 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
4487 le32_to_cpu(pkt->u.err_resp.error_info));
4488}
4489EXPORT_SYMBOL(il_hdl_error);
4490
4491void
4492il_clear_isr_stats(struct il_priv *il)
4493{
4494 memset(&il->isr_stats, 0, sizeof(il->isr_stats));
4495}
4496
4497int
4498il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
4499 const struct ieee80211_tx_queue_params *params)
4500{
4501 struct il_priv *il = hw->priv;
4502 unsigned long flags;
4503 int q;
4504
4505 D_MAC80211("enter\n");
4506
4507 if (!il_is_ready_rf(il)) {
4508 D_MAC80211("leave - RF not ready\n");
4509 return -EIO;
4510 }
4511
4512 if (queue >= AC_NUM) {
4513 D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
4514 return 0;
4515 }
4516
4517 q = AC_NUM - 1 - queue;
4518
4519 spin_lock_irqsave(&il->lock, flags);
4520
4521 il->qos_data.def_qos_parm.ac[q].cw_min =
4522 cpu_to_le16(params->cw_min);
4523 il->qos_data.def_qos_parm.ac[q].cw_max =
4524 cpu_to_le16(params->cw_max);
4525 il->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
4526 il->qos_data.def_qos_parm.ac[q].edca_txop =
4527 cpu_to_le16((params->txop * 32));
4528
4529 il->qos_data.def_qos_parm.ac[q].reserved1 = 0;
4530
4531 spin_unlock_irqrestore(&il->lock, flags);
4532
4533 D_MAC80211("leave\n");
4534 return 0;
4535}
4536EXPORT_SYMBOL(il_mac_conf_tx);
4537
4538int
4539il_mac_tx_last_beacon(struct ieee80211_hw *hw)
4540{
4541 struct il_priv *il = hw->priv;
4542 int ret;
4543
4544 D_MAC80211("enter\n");
4545
4546 ret = (il->ibss_manager == IL_IBSS_MANAGER);
4547
4548 D_MAC80211("leave ret %d\n", ret);
4549 return ret;
4550}
4551EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
4552
4553static int
4554il_set_mode(struct il_priv *il)
4555{
4556 il_connection_init_rx_config(il);
4557
4558 if (il->ops->set_rxon_chain)
4559 il->ops->set_rxon_chain(il);
4560
4561 return il_commit_rxon(il);
4562}
4563
4564int
4565il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
4566{
4567 struct il_priv *il = hw->priv;
4568 int err;
4569 bool reset;
4570
4571 mutex_lock(&il->mutex);
4572 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
4573
4574 if (!il_is_ready_rf(il)) {
4575 IL_WARN("Try to add interface when device not ready\n");
4576 err = -EINVAL;
4577 goto out;
4578 }
4579
4580 /*
4581 * We do not support multiple virtual interfaces, but on hardware reset
4582 * we have to add the same interface again.
4583 */
4584 reset = (il->vif == vif);
4585 if (il->vif && !reset) {
4586 err = -EOPNOTSUPP;
4587 goto out;
4588 }
4589
4590 il->vif = vif;
4591 il->iw_mode = vif->type;
4592
4593 err = il_set_mode(il);
4594 if (err) {
4595 IL_WARN("Fail to set mode %d\n", vif->type);
4596 if (!reset) {
4597 il->vif = NULL;
4598 il->iw_mode = NL80211_IFTYPE_STATION;
4599 }
4600 }
4601
4602out:
4603 D_MAC80211("leave err %d\n", err);
4604 mutex_unlock(&il->mutex);
4605
4606 return err;
4607}
4608EXPORT_SYMBOL(il_mac_add_interface);
4609
4610static void
4611il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif)
4612{
4613 lockdep_assert_held(&il->mutex);
4614
4615 if (il->scan_vif == vif) {
4616 il_scan_cancel_timeout(il, 200);
4617 il_force_scan_end(il);
4618 }
4619
4620 il_set_mode(il);
4621}
4622
4623void
4624il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
4625{
4626 struct il_priv *il = hw->priv;
4627
4628 mutex_lock(&il->mutex);
4629 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
4630
4631 WARN_ON(il->vif != vif);
4632 il->vif = NULL;
4633 il->iw_mode = NL80211_IFTYPE_UNSPECIFIED;
4634 il_teardown_interface(il, vif);
4635 memset(il->bssid, 0, ETH_ALEN);
4636
4637 D_MAC80211("leave\n");
4638 mutex_unlock(&il->mutex);
4639}
4640EXPORT_SYMBOL(il_mac_remove_interface);
4641
4642int
4643il_alloc_txq_mem(struct il_priv *il)
4644{
4645 if (!il->txq)
4646 il->txq =
4647 kzalloc(sizeof(struct il_tx_queue) *
4648 il->cfg->num_of_queues, GFP_KERNEL);
4649 if (!il->txq) {
4650 IL_ERR("Not enough memory for txq\n");
4651 return -ENOMEM;
4652 }
4653 return 0;
4654}
4655EXPORT_SYMBOL(il_alloc_txq_mem);
4656
4657void
4658il_free_txq_mem(struct il_priv *il)
4659{
4660 kfree(il->txq);
4661 il->txq = NULL;
4662}
4663EXPORT_SYMBOL(il_free_txq_mem);
4664
4665int
4666il_force_reset(struct il_priv *il, bool external)
4667{
4668 struct il_force_reset *force_reset;
4669
4670 if (test_bit(S_EXIT_PENDING, &il->status))
4671 return -EINVAL;
4672
4673 force_reset = &il->force_reset;
4674 force_reset->reset_request_count++;
4675 if (!external) {
4676 if (force_reset->last_force_reset_jiffies &&
4677 time_after(force_reset->last_force_reset_jiffies +
4678 force_reset->reset_duration, jiffies)) {
4679 D_INFO("force reset rejected\n");
4680 force_reset->reset_reject_count++;
4681 return -EAGAIN;
4682 }
4683 }
4684 force_reset->reset_success_count++;
4685 force_reset->last_force_reset_jiffies = jiffies;
4686
4687 /*
4688 * if the request is from external(ex: debugfs),
4689 * then always perform the request in regardless the module
4690 * parameter setting
4691 * if the request is from internal (uCode error or driver
4692 * detect failure), then fw_restart module parameter
4693 * need to be check before performing firmware reload
4694 */
4695
4696 if (!external && !il->cfg->mod_params->restart_fw) {
4697 D_INFO("Cancel firmware reload based on "
4698 "module parameter setting\n");
4699 return 0;
4700 }
4701
4702 IL_ERR("On demand firmware reload\n");
4703
4704 /* Set the FW error flag -- cleared on il_down */
4705 set_bit(S_FW_ERROR, &il->status);
4706 wake_up(&il->wait_command_queue);
4707 /*
4708 * Keep the restart process from trying to send host
4709 * commands by clearing the INIT status bit
4710 */
4711 clear_bit(S_READY, &il->status);
4712 queue_work(il->workqueue, &il->restart);
4713
4714 return 0;
4715}
4716EXPORT_SYMBOL(il_force_reset);
4717
4718int
4719il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4720 enum nl80211_iftype newtype, bool newp2p)
4721{
4722 struct il_priv *il = hw->priv;
4723 int err;
4724
4725 mutex_lock(&il->mutex);
4726 D_MAC80211("enter: type %d, addr %pM newtype %d newp2p %d\n",
4727 vif->type, vif->addr, newtype, newp2p);
4728
4729 if (newp2p) {
4730 err = -EOPNOTSUPP;
4731 goto out;
4732 }
4733
4734 if (!il->vif || !il_is_ready_rf(il)) {
4735 /*
4736 * Huh? But wait ... this can maybe happen when
4737 * we're in the middle of a firmware restart!
4738 */
4739 err = -EBUSY;
4740 goto out;
4741 }
4742
4743 /* success */
4744 vif->type = newtype;
4745 vif->p2p = false;
4746 il->iw_mode = newtype;
4747 il_teardown_interface(il, vif);
4748 err = 0;
4749
4750out:
4751 D_MAC80211("leave err %d\n", err);
4752 mutex_unlock(&il->mutex);
4753
4754 return err;
4755}
4756EXPORT_SYMBOL(il_mac_change_interface);
4757
4758void il_mac_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
4759{
4760 struct il_priv *il = hw->priv;
4761 unsigned long timeout = jiffies + msecs_to_jiffies(500);
4762 int i;
4763
4764 mutex_lock(&il->mutex);
4765 D_MAC80211("enter\n");
4766
4767 if (il->txq == NULL)
4768 goto out;
4769
4770 for (i = 0; i < il->hw_params.max_txq_num; i++) {
4771 struct il_queue *q;
4772
4773 if (i == il->cmd_queue)
4774 continue;
4775
4776 q = &il->txq[i].q;
4777 if (q->read_ptr == q->write_ptr)
4778 continue;
4779
4780 if (time_after(jiffies, timeout)) {
4781 IL_ERR("Failed to flush queue %d\n", q->id);
4782 break;
4783 }
4784
4785 msleep(20);
4786 }
4787out:
4788 D_MAC80211("leave\n");
4789 mutex_unlock(&il->mutex);
4790}
4791EXPORT_SYMBOL(il_mac_flush);
4792
4793/*
4794 * On every watchdog tick we check (latest) time stamp. If it does not
4795 * change during timeout period and queue is not empty we reset firmware.
4796 */
4797static int
4798il_check_stuck_queue(struct il_priv *il, int cnt)
4799{
4800 struct il_tx_queue *txq = &il->txq[cnt];
4801 struct il_queue *q = &txq->q;
4802 unsigned long timeout;
4803 unsigned long now = jiffies;
4804 int ret;
4805
4806 if (q->read_ptr == q->write_ptr) {
4807 txq->time_stamp = now;
4808 return 0;
4809 }
4810
4811 timeout =
4812 txq->time_stamp +
4813 msecs_to_jiffies(il->cfg->wd_timeout);
4814
4815 if (time_after(now, timeout)) {
4816 IL_ERR("Queue %d stuck for %u ms.\n", q->id,
4817 jiffies_to_msecs(now - txq->time_stamp));
4818 ret = il_force_reset(il, false);
4819 return (ret == -EAGAIN) ? 0 : 1;
4820 }
4821
4822 return 0;
4823}
4824
4825/*
4826 * Making watchdog tick be a quarter of timeout assure we will
4827 * discover the queue hung between timeout and 1.25*timeout
4828 */
4829#define IL_WD_TICK(timeout) ((timeout) / 4)
4830
4831/*
4832 * Watchdog timer callback, we check each tx queue for stuck, if if hung
4833 * we reset the firmware. If everything is fine just rearm the timer.
4834 */
4835void
4836il_bg_watchdog(unsigned long data)
4837{
4838 struct il_priv *il = (struct il_priv *)data;
4839 int cnt;
4840 unsigned long timeout;
4841
4842 if (test_bit(S_EXIT_PENDING, &il->status))
4843 return;
4844
4845 timeout = il->cfg->wd_timeout;
4846 if (timeout == 0)
4847 return;
4848
4849 /* monitor and check for stuck cmd queue */
4850 if (il_check_stuck_queue(il, il->cmd_queue))
4851 return;
4852
4853 /* monitor and check for other stuck queues */
4854 for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
4855 /* skip as we already checked the command queue */
4856 if (cnt == il->cmd_queue)
4857 continue;
4858 if (il_check_stuck_queue(il, cnt))
4859 return;
4860 }
4861
4862 mod_timer(&il->watchdog,
4863 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
4864}
4865EXPORT_SYMBOL(il_bg_watchdog);
4866
4867void
4868il_setup_watchdog(struct il_priv *il)
4869{
4870 unsigned int timeout = il->cfg->wd_timeout;
4871
4872 if (timeout)
4873 mod_timer(&il->watchdog,
4874 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
4875 else
4876 del_timer(&il->watchdog);
4877}
4878EXPORT_SYMBOL(il_setup_watchdog);
4879
4880/*
4881 * extended beacon time format
4882 * time in usec will be changed into a 32-bit value in extended:internal format
4883 * the extended part is the beacon counts
4884 * the internal part is the time in usec within one beacon interval
4885 */
4886u32
4887il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
4888{
4889 u32 quot;
4890 u32 rem;
4891 u32 interval = beacon_interval * TIME_UNIT;
4892
4893 if (!interval || !usec)
4894 return 0;
4895
4896 quot =
4897 (usec /
4898 interval) & (il_beacon_time_mask_high(il,
4899 il->hw_params.
4900 beacon_time_tsf_bits) >> il->
4901 hw_params.beacon_time_tsf_bits);
4902 rem =
4903 (usec % interval) & il_beacon_time_mask_low(il,
4904 il->hw_params.
4905 beacon_time_tsf_bits);
4906
4907 return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
4908}
4909EXPORT_SYMBOL(il_usecs_to_beacons);
4910
4911/* base is usually what we get from ucode with each received frame,
4912 * the same as HW timer counter counting down
4913 */
4914__le32
4915il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
4916 u32 beacon_interval)
4917{
4918 u32 base_low = base & il_beacon_time_mask_low(il,
4919 il->hw_params.
4920 beacon_time_tsf_bits);
4921 u32 addon_low = addon & il_beacon_time_mask_low(il,
4922 il->hw_params.
4923 beacon_time_tsf_bits);
4924 u32 interval = beacon_interval * TIME_UNIT;
4925 u32 res = (base & il_beacon_time_mask_high(il,
4926 il->hw_params.
4927 beacon_time_tsf_bits)) +
4928 (addon & il_beacon_time_mask_high(il,
4929 il->hw_params.
4930 beacon_time_tsf_bits));
4931
4932 if (base_low > addon_low)
4933 res += base_low - addon_low;
4934 else if (base_low < addon_low) {
4935 res += interval + base_low - addon_low;
4936 res += (1 << il->hw_params.beacon_time_tsf_bits);
4937 } else
4938 res += (1 << il->hw_params.beacon_time_tsf_bits);
4939
4940 return cpu_to_le32(res);
4941}
4942EXPORT_SYMBOL(il_add_beacon_time);
4943
4944#ifdef CONFIG_PM_SLEEP
4945
4946static int
4947il_pci_suspend(struct device *device)
4948{
4949 struct pci_dev *pdev = to_pci_dev(device);
4950 struct il_priv *il = pci_get_drvdata(pdev);
4951
4952 /*
4953 * This function is called when system goes into suspend state
4954 * mac80211 will call il_mac_stop() from the mac80211 suspend function
4955 * first but since il_mac_stop() has no knowledge of who the caller is,
4956 * it will not call apm_ops.stop() to stop the DMA operation.
4957 * Calling apm_ops.stop here to make sure we stop the DMA.
4958 */
4959 il_apm_stop(il);
4960
4961 return 0;
4962}
4963
4964static int
4965il_pci_resume(struct device *device)
4966{
4967 struct pci_dev *pdev = to_pci_dev(device);
4968 struct il_priv *il = pci_get_drvdata(pdev);
4969 bool hw_rfkill = false;
4970
4971 /*
4972 * We disable the RETRY_TIMEOUT register (0x41) to keep
4973 * PCI Tx retries from interfering with C3 CPU state.
4974 */
4975 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4976
4977 il_enable_interrupts(il);
4978
4979 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
4980 hw_rfkill = true;
4981
4982 if (hw_rfkill)
4983 set_bit(S_RFKILL, &il->status);
4984 else
4985 clear_bit(S_RFKILL, &il->status);
4986
4987 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
4988
4989 return 0;
4990}
4991
4992SIMPLE_DEV_PM_OPS(il_pm_ops, il_pci_suspend, il_pci_resume);
4993EXPORT_SYMBOL(il_pm_ops);
4994
4995#endif /* CONFIG_PM_SLEEP */
4996
4997static void
4998il_update_qos(struct il_priv *il)
4999{
5000 if (test_bit(S_EXIT_PENDING, &il->status))
5001 return;
5002
5003 il->qos_data.def_qos_parm.qos_flags = 0;
5004
5005 if (il->qos_data.qos_active)
5006 il->qos_data.def_qos_parm.qos_flags |=
5007 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
5008
5009 if (il->ht.enabled)
5010 il->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
5011
5012 D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
5013 il->qos_data.qos_active, il->qos_data.def_qos_parm.qos_flags);
5014
5015 il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd),
5016 &il->qos_data.def_qos_parm, NULL);
5017}
5018
5019/**
5020 * il_mac_config - mac80211 config callback
5021 */
5022int
5023il_mac_config(struct ieee80211_hw *hw, u32 changed)
5024{
5025 struct il_priv *il = hw->priv;
5026 const struct il_channel_info *ch_info;
5027 struct ieee80211_conf *conf = &hw->conf;
5028 struct ieee80211_channel *channel = conf->chandef.chan;
5029 struct il_ht_config *ht_conf = &il->current_ht_config;
5030 unsigned long flags = 0;
5031 int ret = 0;
5032 u16 ch;
5033 int scan_active = 0;
5034 bool ht_changed = false;
5035
5036 mutex_lock(&il->mutex);
5037 D_MAC80211("enter: channel %d changed 0x%X\n", channel->hw_value,
5038 changed);
5039
5040 if (unlikely(test_bit(S_SCANNING, &il->status))) {
5041 scan_active = 1;
5042 D_MAC80211("scan active\n");
5043 }
5044
5045 if (changed &
5046 (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
5047 /* mac80211 uses static for non-HT which is what we want */
5048 il->current_ht_config.smps = conf->smps_mode;
5049
5050 /*
5051 * Recalculate chain counts.
5052 *
5053 * If monitor mode is enabled then mac80211 will
5054 * set up the SM PS mode to OFF if an HT channel is
5055 * configured.
5056 */
5057 if (il->ops->set_rxon_chain)
5058 il->ops->set_rxon_chain(il);
5059 }
5060
5061 /* during scanning mac80211 will delay channel setting until
5062 * scan finish with changed = 0
5063 */
5064 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
5065
5066 if (scan_active)
5067 goto set_ch_out;
5068
5069 ch = channel->hw_value;
5070 ch_info = il_get_channel_info(il, channel->band, ch);
5071 if (!il_is_channel_valid(ch_info)) {
5072 D_MAC80211("leave - invalid channel\n");
5073 ret = -EINVAL;
5074 goto set_ch_out;
5075 }
5076
5077 if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
5078 !il_is_channel_ibss(ch_info)) {
5079 D_MAC80211("leave - not IBSS channel\n");
5080 ret = -EINVAL;
5081 goto set_ch_out;
5082 }
5083
5084 spin_lock_irqsave(&il->lock, flags);
5085
5086 /* Configure HT40 channels */
5087 if (il->ht.enabled != conf_is_ht(conf)) {
5088 il->ht.enabled = conf_is_ht(conf);
5089 ht_changed = true;
5090 }
5091 if (il->ht.enabled) {
5092 if (conf_is_ht40_minus(conf)) {
5093 il->ht.extension_chan_offset =
5094 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
5095 il->ht.is_40mhz = true;
5096 } else if (conf_is_ht40_plus(conf)) {
5097 il->ht.extension_chan_offset =
5098 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
5099 il->ht.is_40mhz = true;
5100 } else {
5101 il->ht.extension_chan_offset =
5102 IEEE80211_HT_PARAM_CHA_SEC_NONE;
5103 il->ht.is_40mhz = false;
5104 }
5105 } else
5106 il->ht.is_40mhz = false;
5107
5108 /*
5109 * Default to no protection. Protection mode will
5110 * later be set from BSS config in il_ht_conf
5111 */
5112 il->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
5113
5114 /* if we are switching from ht to 2.4 clear flags
5115 * from any ht related info since 2.4 does not
5116 * support ht */
5117 if ((le16_to_cpu(il->staging.channel) != ch))
5118 il->staging.flags = 0;
5119
5120 il_set_rxon_channel(il, channel);
5121 il_set_rxon_ht(il, ht_conf);
5122
5123 il_set_flags_for_band(il, channel->band, il->vif);
5124
5125 spin_unlock_irqrestore(&il->lock, flags);
5126
5127 if (il->ops->update_bcast_stations)
5128 ret = il->ops->update_bcast_stations(il);
5129
5130set_ch_out:
5131 /* The list of supported rates and rate mask can be different
5132 * for each band; since the band may have changed, reset
5133 * the rate mask to what mac80211 lists */
5134 il_set_rate(il);
5135 }
5136
5137 if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
5138 il->power_data.ps_disabled = !(conf->flags & IEEE80211_CONF_PS);
5139 ret = il_power_update_mode(il, false);
5140 if (ret)
5141 D_MAC80211("Error setting sleep level\n");
5142 }
5143
5144 if (changed & IEEE80211_CONF_CHANGE_POWER) {
5145 D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
5146 conf->power_level);
5147
5148 il_set_tx_power(il, conf->power_level, false);
5149 }
5150
5151 if (!il_is_ready(il)) {
5152 D_MAC80211("leave - not ready\n");
5153 goto out;
5154 }
5155
5156 if (scan_active)
5157 goto out;
5158
5159 if (memcmp(&il->active, &il->staging, sizeof(il->staging)))
5160 il_commit_rxon(il);
5161 else
5162 D_INFO("Not re-sending same RXON configuration.\n");
5163 if (ht_changed)
5164 il_update_qos(il);
5165
5166out:
5167 D_MAC80211("leave ret %d\n", ret);
5168 mutex_unlock(&il->mutex);
5169
5170 return ret;
5171}
5172EXPORT_SYMBOL(il_mac_config);
5173
5174void
5175il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
5176{
5177 struct il_priv *il = hw->priv;
5178 unsigned long flags;
5179
5180 mutex_lock(&il->mutex);
5181 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
5182
5183 spin_lock_irqsave(&il->lock, flags);
5184
5185 memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
5186
5187 /* new association get rid of ibss beacon skb */
5188 if (il->beacon_skb)
5189 dev_kfree_skb(il->beacon_skb);
5190 il->beacon_skb = NULL;
5191 il->timestamp = 0;
5192
5193 spin_unlock_irqrestore(&il->lock, flags);
5194
5195 il_scan_cancel_timeout(il, 100);
5196 if (!il_is_ready_rf(il)) {
5197 D_MAC80211("leave - not ready\n");
5198 mutex_unlock(&il->mutex);
5199 return;
5200 }
5201
5202 /* we are restarting association process */
5203 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5204 il_commit_rxon(il);
5205
5206 il_set_rate(il);
5207
5208 D_MAC80211("leave\n");
5209 mutex_unlock(&il->mutex);
5210}
5211EXPORT_SYMBOL(il_mac_reset_tsf);
5212
5213static void
5214il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
5215{
5216 struct il_ht_config *ht_conf = &il->current_ht_config;
5217 struct ieee80211_sta *sta;
5218 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
5219
5220 D_ASSOC("enter:\n");
5221
5222 if (!il->ht.enabled)
5223 return;
5224
5225 il->ht.protection =
5226 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
5227 il->ht.non_gf_sta_present =
5228 !!(bss_conf->
5229 ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
5230
5231 ht_conf->single_chain_sufficient = false;
5232
5233 switch (vif->type) {
5234 case NL80211_IFTYPE_STATION:
5235 rcu_read_lock();
5236 sta = ieee80211_find_sta(vif, bss_conf->bssid);
5237 if (sta) {
5238 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
5239 int maxstreams;
5240
5241 maxstreams =
5242 (ht_cap->mcs.
5243 tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
5244 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
5245 maxstreams += 1;
5246
5247 if (ht_cap->mcs.rx_mask[1] == 0 &&
5248 ht_cap->mcs.rx_mask[2] == 0)
5249 ht_conf->single_chain_sufficient = true;
5250 if (maxstreams <= 1)
5251 ht_conf->single_chain_sufficient = true;
5252 } else {
5253 /*
5254 * If at all, this can only happen through a race
5255 * when the AP disconnects us while we're still
5256 * setting up the connection, in that case mac80211
5257 * will soon tell us about that.
5258 */
5259 ht_conf->single_chain_sufficient = true;
5260 }
5261 rcu_read_unlock();
5262 break;
5263 case NL80211_IFTYPE_ADHOC:
5264 ht_conf->single_chain_sufficient = true;
5265 break;
5266 default:
5267 break;
5268 }
5269
5270 D_ASSOC("leave\n");
5271}
5272
5273static inline void
5274il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
5275{
5276 /*
5277 * inform the ucode that there is no longer an
5278 * association and that no more packets should be
5279 * sent
5280 */
5281 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5282 il->staging.assoc_id = 0;
5283 il_commit_rxon(il);
5284}
5285
5286static void
5287il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
5288{
5289 struct il_priv *il = hw->priv;
5290 unsigned long flags;
5291 __le64 timestamp;
5292 struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
5293
5294 if (!skb)
5295 return;
5296
5297 D_MAC80211("enter\n");
5298
5299 lockdep_assert_held(&il->mutex);
5300
5301 if (!il->beacon_enabled) {
5302 IL_ERR("update beacon with no beaconing enabled\n");
5303 dev_kfree_skb(skb);
5304 return;
5305 }
5306
5307 spin_lock_irqsave(&il->lock, flags);
5308
5309 if (il->beacon_skb)
5310 dev_kfree_skb(il->beacon_skb);
5311
5312 il->beacon_skb = skb;
5313
5314 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
5315 il->timestamp = le64_to_cpu(timestamp);
5316
5317 D_MAC80211("leave\n");
5318 spin_unlock_irqrestore(&il->lock, flags);
5319
5320 if (!il_is_ready_rf(il)) {
5321 D_MAC80211("leave - RF not ready\n");
5322 return;
5323 }
5324
5325 il->ops->post_associate(il);
5326}
5327
5328void
5329il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5330 struct ieee80211_bss_conf *bss_conf, u32 changes)
5331{
5332 struct il_priv *il = hw->priv;
5333 int ret;
5334
5335 mutex_lock(&il->mutex);
5336 D_MAC80211("enter: changes 0x%x\n", changes);
5337
5338 if (!il_is_alive(il)) {
5339 D_MAC80211("leave - not alive\n");
5340 mutex_unlock(&il->mutex);
5341 return;
5342 }
5343
5344 if (changes & BSS_CHANGED_QOS) {
5345 unsigned long flags;
5346
5347 spin_lock_irqsave(&il->lock, flags);
5348 il->qos_data.qos_active = bss_conf->qos;
5349 il_update_qos(il);
5350 spin_unlock_irqrestore(&il->lock, flags);
5351 }
5352
5353 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5354 /* FIXME: can we remove beacon_enabled ? */
5355 if (vif->bss_conf.enable_beacon)
5356 il->beacon_enabled = true;
5357 else
5358 il->beacon_enabled = false;
5359 }
5360
5361 if (changes & BSS_CHANGED_BSSID) {
5362 D_MAC80211("BSSID %pM\n", bss_conf->bssid);
5363
5364 /*
5365 * On passive channel we wait with blocked queues to see if
5366 * there is traffic on that channel. If no frame will be
5367 * received (what is very unlikely since scan detects AP on
5368 * that channel, but theoretically possible), mac80211 associate
5369 * procedure will time out and mac80211 will call us with NULL
5370 * bssid. We have to unblock queues on such condition.
5371 */
5372 if (is_zero_ether_addr(bss_conf->bssid))
5373 il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
5374
5375 /*
5376 * If there is currently a HW scan going on in the background,
5377 * then we need to cancel it, otherwise sometimes we are not
5378 * able to authenticate (FIXME: why ?)
5379 */
5380 if (il_scan_cancel_timeout(il, 100)) {
5381 D_MAC80211("leave - scan abort failed\n");
5382 mutex_unlock(&il->mutex);
5383 return;
5384 }
5385
5386 /* mac80211 only sets assoc when in STATION mode */
5387 memcpy(il->staging.bssid_addr, bss_conf->bssid, ETH_ALEN);
5388
5389 /* FIXME: currently needed in a few places */
5390 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
5391 }
5392
5393 /*
5394 * This needs to be after setting the BSSID in case
5395 * mac80211 decides to do both changes at once because
5396 * it will invoke post_associate.
5397 */
5398 if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
5399 il_beacon_update(hw, vif);
5400
5401 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
5402 D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
5403 if (bss_conf->use_short_preamble)
5404 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
5405 else
5406 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
5407 }
5408
5409 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
5410 D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
5411 if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
5412 il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
5413 else
5414 il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
5415 if (bss_conf->use_cts_prot)
5416 il->staging.flags |= RXON_FLG_SELF_CTS_EN;
5417 else
5418 il->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
5419 }
5420
5421 if (changes & BSS_CHANGED_BASIC_RATES) {
5422 /* XXX use this information
5423 *
5424 * To do that, remove code from il_set_rate() and put something
5425 * like this here:
5426 *
5427 if (A-band)
5428 il->staging.ofdm_basic_rates =
5429 bss_conf->basic_rates;
5430 else
5431 il->staging.ofdm_basic_rates =
5432 bss_conf->basic_rates >> 4;
5433 il->staging.cck_basic_rates =
5434 bss_conf->basic_rates & 0xF;
5435 */
5436 }
5437
5438 if (changes & BSS_CHANGED_HT) {
5439 il_ht_conf(il, vif);
5440
5441 if (il->ops->set_rxon_chain)
5442 il->ops->set_rxon_chain(il);
5443 }
5444
5445 if (changes & BSS_CHANGED_ASSOC) {
5446 D_MAC80211("ASSOC %d\n", bss_conf->assoc);
5447 if (bss_conf->assoc) {
5448 il->timestamp = bss_conf->sync_tsf;
5449
5450 if (!il_is_rfkill(il))
5451 il->ops->post_associate(il);
5452 } else
5453 il_set_no_assoc(il, vif);
5454 }
5455
5456 if (changes && il_is_associated(il) && bss_conf->aid) {
5457 D_MAC80211("Changes (%#x) while associated\n", changes);
5458 ret = il_send_rxon_assoc(il);
5459 if (!ret) {
5460 /* Sync active_rxon with latest change. */
5461 memcpy((void *)&il->active, &il->staging,
5462 sizeof(struct il_rxon_cmd));
5463 }
5464 }
5465
5466 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5467 if (vif->bss_conf.enable_beacon) {
5468 memcpy(il->staging.bssid_addr, bss_conf->bssid,
5469 ETH_ALEN);
5470 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
5471 il->ops->config_ap(il);
5472 } else
5473 il_set_no_assoc(il, vif);
5474 }
5475
5476 if (changes & BSS_CHANGED_IBSS) {
5477 ret = il->ops->manage_ibss_station(il, vif,
5478 bss_conf->ibss_joined);
5479 if (ret)
5480 IL_ERR("failed to %s IBSS station %pM\n",
5481 bss_conf->ibss_joined ? "add" : "remove",
5482 bss_conf->bssid);
5483 }
5484
5485 D_MAC80211("leave\n");
5486 mutex_unlock(&il->mutex);
5487}
5488EXPORT_SYMBOL(il_mac_bss_info_changed);
5489
5490irqreturn_t
5491il_isr(int irq, void *data)
5492{
5493 struct il_priv *il = data;
5494 u32 inta, inta_mask;
5495 u32 inta_fh;
5496 unsigned long flags;
5497 if (!il)
5498 return IRQ_NONE;
5499
5500 spin_lock_irqsave(&il->lock, flags);
5501
5502 /* Disable (but don't clear!) interrupts here to avoid
5503 * back-to-back ISRs and sporadic interrupts from our NIC.
5504 * If we have something to service, the tasklet will re-enable ints.
5505 * If we *don't* have something, we'll re-enable before leaving here. */
5506 inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
5507 _il_wr(il, CSR_INT_MASK, 0x00000000);
5508
5509 /* Discover which interrupts are active/pending */
5510 inta = _il_rd(il, CSR_INT);
5511 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
5512
5513 /* Ignore interrupt if there's nothing in NIC to service.
5514 * This may be due to IRQ shared with another device,
5515 * or due to sporadic interrupts thrown from our NIC. */
5516 if (!inta && !inta_fh) {
5517 D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
5518 goto none;
5519 }
5520
5521 if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
5522 /* Hardware disappeared. It might have already raised
5523 * an interrupt */
5524 IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
5525 goto unplugged;
5526 }
5527
5528 D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
5529 inta_fh);
5530
5531 inta &= ~CSR_INT_BIT_SCD;
5532
5533 /* il_irq_tasklet() will service interrupts and re-enable them */
5534 if (likely(inta || inta_fh))
5535 tasklet_schedule(&il->irq_tasklet);
5536
5537unplugged:
5538 spin_unlock_irqrestore(&il->lock, flags);
5539 return IRQ_HANDLED;
5540
5541none:
5542 /* re-enable interrupts here since we don't have anything to service. */
5543 /* only Re-enable if disabled by irq */
5544 if (test_bit(S_INT_ENABLED, &il->status))
5545 il_enable_interrupts(il);
5546 spin_unlock_irqrestore(&il->lock, flags);
5547 return IRQ_NONE;
5548}
5549EXPORT_SYMBOL(il_isr);
5550
5551/*
5552 * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
5553 * function.
5554 */
5555void
5556il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
5557 __le16 fc, __le32 *tx_flags)
5558{
5559 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
5560 *tx_flags |= TX_CMD_FLG_RTS_MSK;
5561 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
5562 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5563
5564 if (!ieee80211_is_mgmt(fc))
5565 return;
5566
5567 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
5568 case cpu_to_le16(IEEE80211_STYPE_AUTH):
5569 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
5570 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
5571 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
5572 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5573 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5574 break;
5575 }
5576 } else if (info->control.rates[0].
5577 flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
5578 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5579 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5580 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5581 }
5582}
5583EXPORT_SYMBOL(il_tx_cmd_protection);